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Fixes BSR and BSF 32bit op when source is zero

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BSR/BSF needs to not write to destination when source is zero
This ensures it doesn't clear the upper 32bits of the register in this
case.
This commit is contained in:
Ryan Houdek committed 2020-03-08 22:05:47 -07:00
1 parent 30b2f019b4
commit c11ac417ce
1 file changed
+6 -4
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External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
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+6 -4
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@@ -2164,7 +2164,8 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) {
}
void OpDispatchBuilder::BSFOp(OpcodeArgs) {
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
uint8_t DstSize = GetDstSize(Op) == 2 ? 2 : 8;
OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, DstSize, Op->Flags, -1);
OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
// Find the LSB of this source
@@ -2183,12 +2184,13 @@ void OpDispatchBuilder::BSFOp(OpcodeArgs) {
Src, ZeroConst,
OneConst, ZeroConst);
StoreResult(GPRClass, Op, SelectOp, -1);
StoreResult_WithOpSize(GPRClass, Op, Op->Dest, SelectOp, DstSize, -1);
SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(ZFSelectOp);
}
void OpDispatchBuilder::BSROp(OpcodeArgs) {
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
uint8_t DstSize = GetDstSize(Op) == 2 ? 2 : 8;
OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, DstSize, Op->Flags, -1);
OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
// Find the MSB of this source
@@ -2207,7 +2209,7 @@ void OpDispatchBuilder::BSROp(OpcodeArgs) {
Src, ZeroConst,
OneConst, ZeroConst);
StoreResult(GPRClass, Op, SelectOp, -1);
StoreResult_WithOpSize(GPRClass, Op, Op->Dest, SelectOp, DstSize, -1);
SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(ZFSelectOp);
}