Merge pull request #2137 from Sonicadvance1/pclmul_disable

OpcodeDispatcher: Disable PCLMUL if not supported on host

External/FEXCore/Source/Interface/Core/CPUID.cpp

@@ -421,7 +421,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
 
   Res.ecx =
     (1 <<  0) | // SSE3
-    (1 <<  1) | // PCLMULQDQ
+    (CTX->HostFeatures.SupportsPMULL_128Bit <<  1) | // PCLMULQDQ
     (1 <<  2) | // DS area supports 64bit layout
     (1 <<  3) | // MWait
     (0 <<  4) | // DS-CPL

External/FEXCore/Source/Interface/Core/HostFeatures.cpp

@@ -65,6 +65,7 @@ HostFeatures::HostFeatures() {
   SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
   SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
   SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
+  SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
 
   Supports3DNow = true;
   SupportsSSE4A = true;
@@ -127,6 +128,7 @@ HostFeatures::HostFeatures() {
   SupportsSHA = Features.has(Xbyak::util::Cpu::tSHA);
   SupportsBMI1 = Features.has(Xbyak::util::Cpu::tBMI1);
   SupportsBMI2 = Features.has(Xbyak::util::Cpu::tBMI2);
+  SupportsPMULL_128Bit = Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
 
   // xbyak doesn't know how to check for CLZero
   uint32_t eax, ebx, ecx, edx;

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -5655,10 +5655,20 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
   constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> H0F3A_AES[] = {
     {OPD(0, PF_3A_66,   0xDF), 1, &OpDispatchBuilder::AESKeyGenAssist},
   };
+  constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> H0F3A_PCLMUL[] = {
+    {OPD(0, PF_3A_66,   0x44), 1, &OpDispatchBuilder::PCLMULQDQOp},
+  };
+
 #undef PF_3A_NONE
 #undef PF_3A_66
 #undef OPD
 
+#define OPD(map_select, pp, opcode) (((map_select - 1) << 10) | (pp << 8) | (opcode))
+  constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> VEX_PCLMUL[] = {
+    {OPD(3, 0b01, 0x44), 1, &OpDispatchBuilder::VPCLMULQDQOp},
+  };
+#undef OPD
+
 #define OPD(group, prefix, Reg) (((group - FEXCore::X86Tables::TYPE_GROUP_6) << 5) | (prefix) << 3 | (Reg))
   constexpr uint16_t PF_NONE = 0;
   constexpr uint16_t PF_66 = 2;
@@ -5706,6 +5716,11 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
   if (CTX->HostFeatures.SupportsRAND) {
     InstallToTable(FEXCore::X86Tables::SecondInstGroupOps, SecondaryExtensionOp_RDRAND);
   }
+
+  if (CTX->HostFeatures.SupportsPMULL_128Bit) {
+    InstallToTable(FEXCore::X86Tables::H0F3ATableOps, H0F3A_PCLMUL);
+    InstallToTable(FEXCore::X86Tables::VEXTableOps, VEX_PCLMUL);
+  }
   Initialized = true;
 }
 
@@ -6922,7 +6937,6 @@ constexpr uint16_t PF_F2 = 3;
     {OPD(0, PF_3A_66,   0x40), 1, &OpDispatchBuilder::DPPOp<4>},
     {OPD(0, PF_3A_66,   0x41), 1, &OpDispatchBuilder::DPPOp<8>},
     {OPD(0, PF_3A_66,   0x42), 1, &OpDispatchBuilder::MPSADBWOp},
-    {OPD(0, PF_3A_66,   0x44), 1, &OpDispatchBuilder::PCLMULQDQOp},
 
     {OPD(0, PF_3A_NONE, 0xCC), 1, &OpDispatchBuilder::SHA1RNDS4Op},
   };
@@ -7006,8 +7020,6 @@ constexpr uint16_t PF_F2 = 3;
     {OPD(2, 0b10, 0xF7), 1, &OpDispatchBuilder::BMI2Shift},
     {OPD(2, 0b11, 0xF7), 1, &OpDispatchBuilder::BMI2Shift},
 
-    {OPD(3, 0b01, 0x44), 1, &OpDispatchBuilder::VPCLMULQDQOp},
-
     {OPD(3, 0b11, 0xF0), 1, &OpDispatchBuilder::RORX},
   };
 #undef OPD

External/FEXCore/include/FEXCore/Core/HostFeatures.h

@@ -27,6 +27,7 @@ class HostFeatures final {
     bool SupportsSHA{};
     bool SupportsBMI1{};
     bool SupportsBMI2{};
+    bool SupportsPMULL_128Bit{};
 
     // Float exception behaviour
     bool SupportsFlushInputsToZero{};