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Merge pull request #1549 from Sonicadvance1/implement_pcmpgtq

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OpcodeDispatcher: Implements PCMPGTQ
This commit is contained in:
Mai M authored and GitHub committed 2022-02-03 21:46:13 -05:00
2 parents 5978143141 594c70b5e0
commit caffad8562
4 files changed
+67
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External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+1
View File
@@ -6176,6 +6176,7 @@ constexpr uint16_t PF_F2 = 3;
{OPD(PF_38_66, 0x33), 1, &OpDispatchBuilder::ExtendVectorElements<2, 4, false>},
{OPD(PF_38_66, 0x34), 1, &OpDispatchBuilder::ExtendVectorElements<2, 8, false>},
{OPD(PF_38_66, 0x35), 1, &OpDispatchBuilder::ExtendVectorElements<4, 8, false>},
{OPD(PF_38_66, 0x37), 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VCMPGT, 8>},
{OPD(PF_38_66, 0x38), 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VSMIN, 1>},
{OPD(PF_38_66, 0x39), 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VSMIN, 4>},
{OPD(PF_38_66, 0x3A), 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUMIN, 2>},
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
Vendored
+2
View File
@@ -241,6 +241,8 @@ void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPGT, 2>(OpcodeArgs);
template
void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPGT, 4>(OpcodeArgs);
template
void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPGT, 8>(OpcodeArgs);
template
void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPEQ, 1>(OpcodeArgs);
template
void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPEQ, 2>(OpcodeArgs);
External/FEXCore/Source/Interface/Core/X86Tables/H0F38Tables.cpp
Vendored
+1
View File
@@ -74,6 +74,7 @@ void InitializeH0F38Tables() {
{OPD(PF_38_66, 0x33), 1, X86InstInfo{"PMOVZXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(PF_38_66, 0x34), 1, X86InstInfo{"PMOVZXWQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(PF_38_66, 0x35), 1, X86InstInfo{"PMOVZXDQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(PF_38_66, 0x37), 1, X86InstInfo{"PCMPGTQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(PF_38_66, 0x38), 1, X86InstInfo{"PMINSB", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(PF_38_66, 0x39), 1, X86InstInfo{"PMINSD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(PF_38_66, 0x3A), 1, X86InstInfo{"PMINUW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
unittests/ASM/H0F38/66_37.asm
+63
View File
@@ -0,0 +1,63 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x0000000000000000", "0xFFFFFFFFFFFFFFFF"],
"XMM1": ["0x0000000000000000", "0x0000000000000000"],
"XMM2": ["0x0000000000000000", "0x0000000000000000"],
"XMM3": ["0x0000000000000000", "0xFFFFFFFFFFFFFFFF"],
"XMM4": ["0xFFFFFFFFFFFFFFFF", "0x0000000000000000"],
"XMM5": ["0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF"],
"XMM6": ["0x0000000000000000", "0x0000000000000000"],
"XMM7": ["0xFFFFFFFFFFFFFFFF", "0x0000000000000000"],
"XMM8": ["0x0000000000000000", "0xFFFFFFFFFFFFFFFF"],
"XMM9": ["0xFFFFFFFFFFFFFFFF", "0x0000000000000000"]
}
}
%endif
movaps xmm0, [rel .data0]
movaps xmm1, [rel .data1]
movaps xmm2, [rel .data2]
movaps xmm3, [rel .data3]
movaps xmm4, [rel .data4]
movaps xmm5, [rel .data0]
movaps xmm6, [rel .data1]
movaps xmm7, [rel .data2]
movaps xmm8, [rel .data3]
movaps xmm9, [rel .data4]
pcmpgtq xmm0, [rel .data4]
pcmpgtq xmm1, [rel .data3]
pcmpgtq xmm2, [rel .data2]
pcmpgtq xmm3, [rel .data1]
pcmpgtq xmm4, [rel .data0]
pcmpgtq xmm5, [rel .data1]
pcmpgtq xmm6, [rel .data2]
pcmpgtq xmm7, [rel .data3]
pcmpgtq xmm8, [rel .data4]
pcmpgtq xmm9, [rel .data0]
hlt
align 16
.data0:
dq 0
dq 0
.data1:
dq -1
dq -1
.data2:
dq 1
dq 1
.data3:
dq -1
dq 1
.data4:
dq 1
dq -1