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Fixes Zext on FPR->GPR conversion for AArch64

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The 32bit and lower sizes were making vixl asserts fire.
Wouldn't actually change emitted code
This commit is contained in:
Ryan Houdek committed 2020-07-11 06:20:50 +01:00
1 parent d281e9f7ff
commit cb74beadb4
1 file changed
+3 -3
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External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
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+3 -3
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@@ -745,13 +745,13 @@ DEF_OP(Zext) {
// FPR -> GPR transfer with free truncation
switch (Op->SrcSize) {
case 8:
mov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V16B(), 0);
mov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V16B(), 0);
break;
case 16:
mov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V8H(), 0);
mov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V8H(), 0);
break;
case 32:
mov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V4S(), 0);
mov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V4S(), 0);
break;
case 64:
mov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V2D(), 0);