Revert "Cache predicate register generation from pattern"

This reverts commit 72a4063651.

Caused #4264

FEXCore/Scripts/json_ir_generator.py

@@ -223,7 +223,7 @@ def parse_ops(ops):
                         (OpArg.Type == "GPR" or
                         OpArg.Type == "GPRPair" or
                         OpArg.Type == "FPR" or
-                        OpArg.Type == "PRED")):
+                        OpArg.Type == "PR")):
                         OpDef.EmitValidation.append(f"GetOpRegClass({ArgName}) == InvalidClass || WalkFindRegClass({ArgName}) == {OpArg.Type}Class")
 
                     OpArg.Name = ArgName

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -4314,7 +4314,7 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T
       Ref MemSrc = LoadEffectiveAddress(A, true);
       if (CTX->HostFeatures.SupportsSVE128 || CTX->HostFeatures.SupportsSVE256) {
         // Using SVE we can load this with a single instruction.
-        auto PReg = InitPredicateCached(OpSize::i16Bit, ARMEmitter::PredicatePattern::SVE_VL5);
+        auto PReg = _InitPredicate(OpSize::i16Bit, FEXCore::ToUnderlying(ARMEmitter::PredicatePattern::SVE_VL5));
         return _LoadMemPredicate(OpSize::i128Bit, OpSize::i16Bit, PReg, MemSrc);
       } else {
         // For X87 extended doubles, Split the load.
@@ -4448,7 +4448,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
   if (OpSize == OpSize::f80Bit) {
     Ref MemStoreDst = LoadEffectiveAddress(A, true);
     if (CTX->HostFeatures.SupportsSVE128 || CTX->HostFeatures.SupportsSVE256) {
-      auto PReg = InitPredicateCached(OpSize::i16Bit, ARMEmitter::PredicatePattern::SVE_VL5);
+      auto PReg = _InitPredicate(OpSize::i16Bit, FEXCore::ToUnderlying(ARMEmitter::PredicatePattern::SVE_VL5));
       _StoreMemPredicate(OpSize::i128Bit, OpSize::i16Bit, Src, PReg, MemStoreDst);
     } else {
       // For X87 extended doubles, split before storing

FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -125,9 +125,6 @@ public:
 
     // Need to clear any named constants that were cached.
     ClearCachedNamedConstants();
-
-    // Clear predicate cache for x87 ldst
-    ResetInitPredicateCache();
   }
 
   IRPair<IROp_Jump> Jump() {

FEXCore/Source/Interface/IR/IREmitter.cpp

@@ -41,7 +41,6 @@ FEXCore::IR::RegisterClassType IREmitter::WalkFindRegClass(Ref Node) {
   case FPRClass:
   case GPRFixedClass:
   case FPRFixedClass:
-  case PREDClass:
   case InvalidClass: return Class;
   default: break;
   }

FEXCore/Source/Interface/IR/IREmitter.h

@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: MIT
 #pragma once
 
-#include "CodeEmitter/Emitter.h"
 #include "Interface/IR/IR.h"
 #include "Interface/IR/IntrusiveIRList.h"
 
@@ -10,9 +9,9 @@
 
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/fextl/vector.h>
-#include <FEXCore/fextl/unordered_map.h>
 
 #include <algorithm>
+#include <new>
 #include <stdint.h>
 #include <string.h>
 
@@ -46,37 +45,6 @@ public:
   }
   void ResetWorkingList();
 
-  // Predicate Cache Implementation
-  // This lives here rather than OpcodeDispatcher because x87StackOptimization Pass
-  // also needs it.
-  struct PredicateKey {
-    ARMEmitter::PredicatePattern Pattern;
-    OpSize Size;
-    bool operator==(const PredicateKey& rhs) const = default;
-  };
-
-  struct PredicateKeyHash {
-    size_t operator()(const PredicateKey& key) const {
-      return FEXCore::ToUnderlying(key.Pattern) + (FEXCore::ToUnderlying(key.Size) * FEXCore::ToUnderlying(OpSize::iInvalid));
-    }
-  };
-  fextl::unordered_map<PredicateKey, Ref, PredicateKeyHash> InitPredicateCache;
-
-  Ref InitPredicateCached(OpSize Size, ARMEmitter::PredicatePattern Pattern) {
-    PredicateKey Key {Pattern, Size};
-    auto ValIt = InitPredicateCache.find(Key);
-    if (ValIt == InitPredicateCache.end()) {
-      auto Predicate = _InitPredicate(Size, static_cast<uint8_t>(FEXCore::ToUnderlying(Pattern)));
-      InitPredicateCache[Key] = Predicate;
-      return Predicate;
-    }
-    return ValIt->second;
-  }
-
-  void ResetInitPredicateCache() {
-    InitPredicateCache.clear();
-  }
-
   /**
    * @name IR allocation routines
    *

FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp

@@ -824,7 +824,7 @@ void X87StackOptimization::Run(IREmitter* Emit) {
             }
             if (Op->StoreSize == OpSize::f80Bit) { // Part of code from StoreResult_WithOpSize()
               if (Features.SupportsSVE128 || Features.SupportsSVE256) {
-                auto PReg = IREmit->InitPredicateCached(OpSize::i16Bit, ARMEmitter::PredicatePattern::SVE_VL5);
+                auto PReg = IREmit->_InitPredicate(OpSize::i16Bit, FEXCore::ToUnderlying(ARMEmitter::PredicatePattern::SVE_VL5));
                 IREmit->_StoreMemPredicate(OpSize::i128Bit, OpSize::i16Bit, StackNode, PReg, AddrNode);
               } else {
                 // For X87 extended doubles, split before storing