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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2025-03-17 16:49:05 -04:00
1 parent bc87c3d494
commit cd3518d99d
9 files changed
+1639 -2194
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unittests/InstructionCountCI/AVX128/VEX_map1.json
+481 -687
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unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
+4 -6
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@@ -12,15 +12,14 @@
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ext v2.16b, v18.16b, v18.16b, #8",
"fcadd v16.2d, v17.2d, v2.2d, #90",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vaddsubpd ymm0, ymm0, ymm2": {
@@ -71,15 +70,14 @@
]
},
"vaddsubps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"rev64 v2.4s, v18.4s",
"fcadd v16.4s, v17.4s, v2.4s, #90",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vaddsubps ymm0, ymm1, ymm0": {
unittests/InstructionCountCI/AVX128/VEX_map2.json
+356 -480
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File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
+48 -72
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@@ -11,283 +11,259 @@
},
"Instructions": {
"vfmadd132ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x99 128-bit"
],
"ExpectedArm64ASM": [
"fmadd s0, s16, s18, s17",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmadd132sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x99 128-bit"
],
"ExpectedArm64ASM": [
"fmadd d0, d16, d18, d17",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmsub132ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9b 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub s0, s16, s18, s17",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmsub132sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9b 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub d0, d16, d18, d17",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmadd132ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9d 128-bit"
],
"ExpectedArm64ASM": [
"fmsub s0, s16, s18, s17",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmadd132sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9d 128-bit"
],
"ExpectedArm64ASM": [
"fmsub d0, d16, d18, d17",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmsub132ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9f 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd s0, s16, s18, s17",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmsub132sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9f 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd d0, d16, d18, d17",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmadd213ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xa9 128-bit"
],
"ExpectedArm64ASM": [
"fmadd s0, s17, s16, s18",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmadd213sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xa9 128-bit"
],
"ExpectedArm64ASM": [
"fmadd d0, d17, d16, d18",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmsub213ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xab 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub s0, s17, s16, s18",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmsub213sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xab 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub d0, d17, d16, d18",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmadd213ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xad 128-bit"
],
"ExpectedArm64ASM": [
"fmsub s0, s17, s16, s18",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmadd213sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xad 128-bit"
],
"ExpectedArm64ASM": [
"fmsub d0, d17, d16, d18",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmsub213ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xaf 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd s0, s17, s16, s18",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmsub213sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xaf 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd d0, d17, d16, d18",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmadd231ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xb9 128-bit"
],
"ExpectedArm64ASM": [
"fmadd s16, s17, s18, s16",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmadd231sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xb9 128-bit"
],
"ExpectedArm64ASM": [
"fmadd d16, d17, d18, d16",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmsub231ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbb 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub s16, s17, s18, s16",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfmsub231sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbb 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub d16, d17, d18, d16",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmadd231ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbd 128-bit"
],
"ExpectedArm64ASM": [
"fmsub s16, s17, s18, s16",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmadd231sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbd 128-bit"
],
"ExpectedArm64ASM": [
"fmsub d16, d17, d18, d16",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmsub231ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbf 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd s16, s17, s18, s16",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vfnmsub231sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbf 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd d16, d17, d18, d16",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
}
}
unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+332 -395
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unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+8 -12
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@@ -168,7 +168,7 @@
]
},
"vmaskmovps xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"Map 2 0b01 0x2c 128-bit"
],
@@ -190,8 +190,7 @@
"tbz w0, #31, #+0x8",
"ld1 {v0.s}[3], [x1]",
"mov v16.16b, v0.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vmaskmovps ymm0, ymm1, [rax]": {
@@ -240,7 +239,7 @@
]
},
"vmaskmovpd xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"Map 2 0b01 0x2d 128-bit"
],
@@ -254,8 +253,7 @@
"tbz x0, #63, #+0x8",
"ld1 {v0.d}[1], [x1]",
"mov v16.16b, v0.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vmaskmovpd ymm0, ymm1, [rax]": {
@@ -392,7 +390,7 @@
]
},
"vpmaskmovd xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"Map 2 0b01 0x8c 128-bit"
],
@@ -414,8 +412,7 @@
"tbz w0, #31, #+0x8",
"ld1 {v0.s}[3], [x1]",
"mov v16.16b, v0.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpmaskmovd ymm0, ymm1, [rax]": {
@@ -464,7 +461,7 @@
]
},
"vpmaskmovq xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"Map 2 0b01 0x8c 128-bit"
],
@@ -478,8 +475,7 @@
"tbz x0, #63, #+0x8",
"ld1 {v0.d}[1], [x1]",
"mov v16.16b, v0.16b",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpmaskmovq ymm0, ymm1, [rax]": {
unittests/InstructionCountCI/AVX128/VEX_map3.json
+346 -449
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unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
+6 -9
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@@ -11,7 +11,7 @@
},
"Instructions": {
"vblendvps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x4a 128-bit"
],
@@ -19,8 +19,7 @@
"sshr v2.4s, v19.4s, #31",
"movprfx z16, z18",
"bsl z16.d, z16.d, z17.d, z2.d",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vblendvps ymm0, ymm1, ymm2, ymm3": {
@@ -41,7 +40,7 @@
]
},
"vblendvpd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x4b 128-bit"
],
@@ -49,8 +48,7 @@
"sshr v2.2d, v19.2d, #63",
"movprfx z16, z18",
"bsl z16.d, z16.d, z17.d, z2.d",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vblendvpd ymm0, ymm1, ymm2, ymm3": {
@@ -71,7 +69,7 @@
]
},
"vpblendvb xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x4c 128-bit"
],
@@ -79,8 +77,7 @@
"sshr v2.16b, v19.16b, #7",
"movprfx z16, z18",
"bsl z16.d, z16.d, z17.d, z2.d",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpblendvb ymm0, ymm1, ymm2, ymm3": {
unittests/InstructionCountCI/AVX128/VEX_map_group.json
+58 -84
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@@ -12,36 +12,33 @@
},
"Instructions": {
"vpsrlw xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
"vpsrlw xmm0, xmm1, 15": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"ushr v16.8h, v17.8h, #15",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrlw xmm0, xmm1, 16": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrlw ymm0, ymm1, 0": {
@@ -80,36 +77,33 @@
]
},
"vpsraw xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
"vpsraw xmm0, xmm1, 15": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"sshr v16.8h, v17.8h, #15",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsraw xmm0, xmm1, 16": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"sshr v16.8h, v17.8h, #15",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsraw ymm0, ymm1, 0": {
@@ -148,36 +142,33 @@
]
},
"vpsllw xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
"vpsllw xmm0, xmm1, 15": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"shl v16.8h, v17.8h, #15",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsllw xmm0, xmm1, 16": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsllw ymm0, ymm1, 0": {
@@ -216,36 +207,33 @@
]
},
"vpsrld xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
"vpsrld xmm0, xmm1, 31": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"ushr v16.4s, v17.4s, #31",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrld xmm0, xmm1, 32": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrld ymm0, ymm1, 0": {
@@ -284,36 +272,33 @@
]
},
"vpsrad xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
"vpsrad xmm0, xmm1, 31": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"sshr v16.4s, v17.4s, #31",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrad xmm0, xmm1, 32": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"sshr v16.4s, v17.4s, #31",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrad ymm0, ymm1, 0": {
@@ -352,36 +337,33 @@
]
},
"vpslld xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
"vpslld xmm0, xmm1, 31": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"shl v16.4s, v17.4s, #31",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpslld xmm0, xmm1, 32": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpslld ymm0, ymm1, 0": {
@@ -420,36 +402,33 @@
]
},
"vpsrlq xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
"vpsrlq xmm0, xmm1, 63": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"ushr v16.2d, v17.2d, #63",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrlq xmm0, xmm1, 64": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrlq ymm0, ymm1, 0": {
@@ -488,13 +467,12 @@
]
},
"vpsrldq xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
@@ -506,7 +484,7 @@
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ext v16.16b, v17.16b, v2.16b, #15",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrldq xmm0, xmm1, 16": {
@@ -516,7 +494,7 @@
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"str q16, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsrldq ymm0, ymm1, 0": {
@@ -550,40 +528,37 @@
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"str q16, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsllq xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
"vpsllq xmm0, xmm1, 63": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"shl v16.2d, v17.2d, #63",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsllq xmm0, xmm1, 64": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"movi v2.2d, #0x0",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpsllq ymm0, ymm1, 0": {
@@ -622,13 +597,12 @@
]
},
"vpslldq xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Comment": [
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"stp xzr, xzr, [x28, #16]",
"mov v16.16b, v17.16b"
]
},
@@ -640,7 +614,7 @@
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ext v16.16b, v2.16b, v17.16b, #1",
"str q2, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpslldq xmm0, xmm1, 16": {
@@ -650,7 +624,7 @@
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"str q16, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
},
"vpslldq ymm0, ymm1, 0": {
@@ -684,7 +658,7 @@
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"str q16, [x28, #16]"
"stp xzr, xzr, [x28, #16]"
]
}
}