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Arm64/VectorOps: Remove redundant moves in SVE VExtr when possible

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We don't need to do any moves here is the destination aliases the
lower bits.
This commit is contained in:
Lioncache committed 2023-08-23 19:56:10 -04:00
1 parent 926b8c2c97
commit d0d94adabe
2 files changed
+10 -7
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FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+8 -3
View File
@@ -2752,9 +2752,14 @@ DEF_OP(VExtr) {
const auto CopyFromByte = Index * ElementSize;
if (HostSupportsSVE256 && Is256Bit) {
movprfx(VTMP2.Z(), LowerBits.Z());
ext<FEXCore::ARMEmitter::OpType::Destructive>(VTMP2.Z(), VTMP2.Z(), UpperBits.Z(), CopyFromByte);
mov(Dst.Z(), VTMP2.Z());
if (Dst == LowerBits) {
// Trivial case where we don't need to do any moves
ext<FEXCore::ARMEmitter::OpType::Destructive>(Dst.Z(), Dst.Z(), UpperBits.Z(), CopyFromByte);
} else {
movprfx(VTMP2.Z(), LowerBits.Z());
ext<FEXCore::ARMEmitter::OpType::Destructive>(VTMP2.Z(), VTMP2.Z(), UpperBits.Z(), CopyFromByte);
mov(Dst.Z(), VTMP2.Z());
}
} else {
if (OpSize == 8) {
ext(Dst.D(), LowerBits.D(), UpperBits.D(), CopyFromByte);
unittests/InstructionCountCI/VEX_map_group.json
+2 -4
View File
@@ -568,7 +568,7 @@
]
},
"vpsrldq ymm0, ymm1, 15": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": [
"Map group 14 0b011 256-bit"
@@ -577,9 +577,7 @@
"mov z4.d, p7/m, z17.d",
"mov z5.d, #0",
"ext v6.16b, v4.16b, v5.16b, #15",
"movprfx z1, z4",
"ext z1.b, z1.b, z5.b, #31",
"mov z4.d, z1.d",
"ext z4.b, z4.b, z5.b, #31",
"mov z1.q, q4",
"mov z4.d, z6.d",
"not p0.b, p7/z, p6.b",