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Fill/SpillRegister: Spill based on register class

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Stefanos Kornilios Mitsis Poiitidis committed 2020-11-06 01:42:04 +02:00
1 parent 462cb39043
commit d6fa850b68
2 files changed
+152 -84
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External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
Vendored
+78 -44
View File
@@ -300,28 +300,45 @@ DEF_OP(SpillRegister) {
auto Op = IROp->C<IR::IROp_SpillRegister>();
uint8_t OpSize = IROp->Size;
uint32_t SlotOffset = Op->Slot * 16 + 16;
switch (OpSize) {
case 1: {
strb(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
case 2: {
strh(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
case 4: {
str(GetReg<RA_32>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
case 8: {
str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
case 16: {
str(GetSrc(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
if (Op->Class == FEXCore::IR::GPRClass) {
switch (OpSize) {
case 1: {
strb(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
case 2: {
strh(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
case 4: {
str(GetReg<RA_32>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
case 8: {
str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
}
} else if (Op->Class == FEXCore::IR::FPRClass) {
switch (OpSize) {
case 4: {
str(GetSrc(Op->Header.Args[0].ID()).S(), MemOperand(sp, SlotOffset));
break;
}
case 8: {
str(GetSrc(Op->Header.Args[0].ID()).D(), MemOperand(sp, SlotOffset));
break;
}
case 16: {
str(GetSrc(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
}
} else {
LogMan::Msg::A("Unhandled SpillRegister class: %d", Op->Class.Val);
}
}
@@ -329,28 +346,45 @@ DEF_OP(FillRegister) {
auto Op = IROp->C<IR::IROp_FillRegister>();
uint8_t OpSize = IROp->Size;
uint32_t SlotOffset = Op->Slot * 16 + 16;
switch (OpSize) {
case 1: {
ldrb(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
break;
}
case 2: {
ldrh(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
break;
}
case 4: {
ldr(GetReg<RA_32>(Node), MemOperand(sp, SlotOffset));
break;
}
case 8: {
ldr(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
break;
}
case 16: {
ldr(GetDst(Node), MemOperand(sp, SlotOffset));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
if (Op->Class == FEXCore::IR::GPRClass) {
switch (OpSize) {
case 1: {
ldrb(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
break;
}
case 2: {
ldrh(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
break;
}
case 4: {
ldr(GetReg<RA_32>(Node), MemOperand(sp, SlotOffset));
break;
}
case 8: {
ldr(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
}
} else if (Op->Class == FEXCore::IR::FPRClass) {
switch (OpSize) {
case 4: {
ldr(GetDst(Node).S(), MemOperand(sp, SlotOffset));
break;
}
case 8: {
ldr(GetDst(Node).D(), MemOperand(sp, SlotOffset));
break;
}
case 16: {
ldr(GetDst(Node), MemOperand(sp, SlotOffset));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
}
} else {
LogMan::Msg::A("Unhandled FillRegister class: %d", Op->Class.Val);
}
}
External/FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp
Vendored
+74 -40
View File
@@ -350,29 +350,47 @@ DEF_OP(SpillRegister) {
uint8_t OpSize = IROp->Size;
uint32_t SlotOffset = Op->Slot * 16;
switch (OpSize) {
case 1: {
mov(byte [rsp + SlotOffset], GetSrc<RA_8>(Op->Header.Args[0].ID()));
break;
if (Op->Class == FEXCore::IR::GPRClass) {
switch (OpSize) {
case 1: {
mov(byte [rsp + SlotOffset], GetSrc<RA_8>(Op->Header.Args[0].ID()));
break;
}
case 2: {
mov(word [rsp + SlotOffset], GetSrc<RA_16>(Op->Header.Args[0].ID()));
break;
}
case 4: {
mov(dword [rsp + SlotOffset], GetSrc<RA_32>(Op->Header.Args[0].ID()));
break;
}
case 8: {
mov(qword [rsp + SlotOffset], GetSrc<RA_64>(Op->Header.Args[0].ID()));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
}
case 2: {
mov(word [rsp + SlotOffset], GetSrc<RA_16>(Op->Header.Args[0].ID()));
break;
} else if (Op->Class == FEXCore::IR::FPRClass) {
switch (OpSize) {
case 4: {
movss(dword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
break;
}
case 8: {
movsd(qword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
break;
}
case 16: {
movaps(xword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
}
case 4: {
mov(dword [rsp + SlotOffset], GetSrc<RA_32>(Op->Header.Args[0].ID()));
break;
}
case 8: {
mov(qword [rsp + SlotOffset], GetSrc<RA_64>(Op->Header.Args[0].ID()));
break;
}
case 16: {
movaps(xword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
break;
}
default: LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
} else {
LogMan::Msg::A("Unhandled SpillRegister class: %d", Op->Class.Val);
}
}
DEF_OP(FillRegister) {
@@ -380,28 +398,44 @@ DEF_OP(FillRegister) {
uint8_t OpSize = IROp->Size;
uint32_t SlotOffset = Op->Slot * 16;
switch (OpSize) {
case 1: {
movzx(GetDst<RA_32>(Node), byte [rsp + SlotOffset]);
break;
if (Op->Class == FEXCore::IR::GPRClass) {
switch (OpSize) {
case 1: {
movzx(GetDst<RA_32>(Node), byte [rsp + SlotOffset]);
break;
}
case 2: {
movzx(GetDst<RA_32>(Node), word [rsp + SlotOffset]);
break;
}
case 4: {
mov(GetDst<RA_32>(Node), dword [rsp + SlotOffset]);
break;
}
case 8: {
mov(GetDst<RA_64>(Node), qword [rsp + SlotOffset]);
break;
}
default: LogMan::Msg::A("Unhandled FillRegister size: %d", OpSize);
}
case 2: {
movzx(GetDst<RA_32>(Node), word [rsp + SlotOffset]);
break;
} else if (Op->Class == FEXCore::IR::FPRClass) {
switch (OpSize) {
case 4: {
movss(GetDst(Node), dword [rsp + SlotOffset]);
break;
}
case 8: {
movsd(GetDst(Node), qword [rsp + SlotOffset]);
break;
}
case 16: {
movaps(GetDst(Node), xword [rsp + SlotOffset]);
break;
}
default: LogMan::Msg::A("Unhandled FillRegister size: %d", OpSize);
}
case 4: {
mov(GetDst<RA_32>(Node), dword [rsp + SlotOffset]);
break;
}
case 8: {
mov(GetDst<RA_64>(Node), qword [rsp + SlotOffset]);
break;
}
case 16: {
movaps(GetDst(Node), xword [rsp + SlotOffset]);
break;
}
default: LogMan::Msg::A("Unhandled FillRegister size: %d", OpSize);
} else {
LogMan::Msg::A("Unhandled FillRegister class: %d", Op->Class.Val);
}
}