mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-29 04:01:27 +01:00
JIT-inline F64ATAN and F64FYL2X for reduced precision x87 path
This commit is contained in:
Paulo Matos committed
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59755ec115
commit
db50b04663
5 files changed
+359
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@@ -551,6 +551,8 @@ void Dispatcher::EmitDispatcher() {
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EmitF64Tan();
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EmitF64F2XM1();
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EmitF64Scale();
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EmitF64Atan();
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EmitF64FYL2X();
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// Interpreter fallbacks
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{
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@@ -1421,6 +1423,322 @@ void Dispatcher::EmitF64F2XM1() {
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dc64(0x3D78'1619'3166'D0F5ULL);
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}
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// JIT-inlined double-precision atan2 for the F64 reduced precision x87 path.
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// Input: VTMP1 = y, VTMP2 = x. Output: VTMP1 = atan2(y, x).
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// Algorithm: 20-term Horner polynomial from ARM optimized-routines atan_data.c.
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// atan(z) = z + z^3 * P(z^2), with range reduction to [0,1] and quadrant adjustment.
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void Dispatcher::EmitF64Atan() {
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F64AtanHandlerAddress = GetCursorAddress<uint64_t>();
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constexpr auto Accum = ARMEmitter::VReg::v2;
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ARMEmitter::ForwardLabel Fallback;
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ARMEmitter::ForwardLabel NoSwap, PosX, NegY;
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ARMEmitter::ForwardLabel PiOver2Label, PiLabel;
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ARMEmitter::ForwardLabel C0Label, C1Label, C2Label, C3Label, C4Label, C5Label, C6Label;
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ARMEmitter::ForwardLabel C7Label, C8Label, C9Label, C10Label, C11Label, C12Label, C13Label;
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ARMEmitter::ForwardLabel C14Label, C15Label, C16Label, C17Label, C18Label, C19Label;
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// Stack layout: [sp] = q2 (16B), [sp+16] = y bits (8B), [sp+24] = x bits (8B).
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str<ARMEmitter::IndexType::PRE>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, -32);
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mrs(TMP1, ARMEmitter::SystemRegister::NZCV);
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str(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
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fmov(ARMEmitter::Size::i64Bit, TMP1, VTMP2.D());
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fmov(ARMEmitter::Size::i64Bit, TMP2, VTMP1.D());
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str(TMP2, ARMEmitter::Reg::rsp, 16);
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str(TMP1, ARMEmitter::Reg::rsp, 24);
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// Compute |x|, |y|, pack sign/swap flags into TMP1 = (sign_x<<2)|(sign_y<<1)|swap.
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fabs(Accum.D(), VTMP2.D());
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fabs(VTMP2.D(), VTMP1.D());
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fcmp(VTMP2.D(), Accum.D());
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lsr(ARMEmitter::Size::i64Bit, TMP1, TMP1, 63);
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lsr(ARMEmitter::Size::i64Bit, TMP2, TMP2, 63);
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cset(ARMEmitter::Size::i64Bit, TMP3, ARMEmitter::Condition::CC_HI);
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lsl(ARMEmitter::Size::i64Bit, TMP1, TMP1, 2);
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orr(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP2, ARMEmitter::ShiftType::LSL, 1);
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orr(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP3);
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// z = min(|y|,|x|) / max(|y|,|x|); NaN guard catches 0/0, inf/inf, NaN inputs.
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fcsel(ARMEmitter::ScalarRegSize::i64Bit, VTMP1, Accum, VTMP2, ARMEmitter::Condition::CC_HI);
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fcsel(ARMEmitter::ScalarRegSize::i64Bit, Accum, VTMP2, Accum, ARMEmitter::Condition::CC_HI);
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fdiv(VTMP2.D(), VTMP1.D(), Accum.D());
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fcmp(VTMP2.D(), VTMP2.D());
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(void)b(ARMEmitter::Condition::CC_VS, &Fallback);
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// P(z^2) via 20-term Horner.
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fmul(Accum.D(), VTMP2.D(), VTMP2.D());
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fmov(ARMEmitter::Size::i64Bit, TMP3, VTMP2.D());
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ldr(VTMP1.D(), &C19Label);
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ldr(VTMP2.D(), &C18Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C17Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C16Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C15Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C14Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C13Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C12Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C11Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C10Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C9Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C8Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C7Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C6Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C5Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C4Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C3Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C2Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C1Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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ldr(VTMP2.D(), &C0Label);
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fmadd(VTMP1.D(), Accum.D(), VTMP1.D(), VTMP2.D());
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// atan_abs = z + z^3 * P(z^2).
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fmov(ARMEmitter::Size::i64Bit, VTMP2.D(), TMP3);
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fmul(VTMP1.D(), Accum.D(), VTMP1.D());
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fmadd(VTMP1.D(), VTMP2.D(), VTMP1.D(), VTMP2.D());
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// Quadrant adjustment driven by packed flags in TMP1.
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(void)tbz(TMP1, 0, &NoSwap);
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ldr(VTMP2.D(), &PiOver2Label);
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fsub(VTMP1.D(), VTMP2.D(), VTMP1.D());
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(void)Bind(&NoSwap);
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(void)tbz(TMP1, 2, &PosX);
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ldr(VTMP2.D(), &PiLabel);
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fsub(VTMP1.D(), VTMP2.D(), VTMP1.D());
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(void)Bind(&PosX);
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(void)tbz(TMP1, 1, &NegY);
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fneg(VTMP1.D(), VTMP1.D());
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(void)Bind(&NegY);
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ldr(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
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msr(ARMEmitter::SystemRegister::NZCV, TMP1);
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ldr<ARMEmitter::IndexType::POST>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, 32);
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ret();
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// Fallback path: restore original inputs from stack stash and dispatch the ABI handler.
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(void)Bind(&Fallback);
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ldr(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
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msr(ARMEmitter::SystemRegister::NZCV, TMP1);
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ldr(TMP2, ARMEmitter::Reg::rsp, 16);
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ldr(TMP1, ARMEmitter::Reg::rsp, 24);
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ldr<ARMEmitter::IndexType::POST>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, 32);
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fmov(ARMEmitter::Size::i64Bit, VTMP1.D(), TMP2);
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fmov(ARMEmitter::Size::i64Bit, VTMP2.D(), TMP1);
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str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
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ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[FEXCore::Core::OPINDEX_F64ATAN].ABIHandler));
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ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[FEXCore::Core::OPINDEX_F64ATAN].Func));
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blr(TMP1);
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ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
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ret();
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Align(16);
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(void)Bind(&C19Label);
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dc64(0x3EF3'5885'1160'A528ULL);
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(void)Bind(&C18Label);
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dc64(0xBF2A'B24D'A7BE'7402ULL);
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(void)Bind(&C17Label);
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dc64(0x3F51'7739'E210'171AULL);
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(void)Bind(&C16Label);
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dc64(0xBF6D'0062'B42F'E3BFULL);
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(void)Bind(&C15Label);
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dc64(0x3F81'4E9D'C19A'4A4EULL);
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(void)Bind(&C14Label);
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dc64(0xBF90'0513'8172'2A59ULL);
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(void)Bind(&C13Label);
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dc64(0x3F98'6089'7B29'E5EFULL);
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(void)Bind(&C12Label);
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dc64(0xBFA0'0E6E'ECE7'DE80ULL);
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(void)Bind(&C11Label);
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dc64(0x3FA3'38E3'1EB2'FBBCULL);
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(void)Bind(&C10Label);
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dc64(0xBFA5'D301'40AE'5E99ULL);
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(void)Bind(&C9Label);
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dc64(0x3FA8'42DB'E9B0'D916ULL);
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(void)Bind(&C8Label);
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dc64(0xBFAA'EBFE'7B41'8581ULL);
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(void)Bind(&C7Label);
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dc64(0x3FAE'1D0F'9696'F63BULL);
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(void)Bind(&C6Label);
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dc64(0xBFB1'1100'EE08'4227ULL);
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(void)Bind(&C5Label);
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dc64(0x3FB3'B139'B6A8'8BA1ULL);
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(void)Bind(&C4Label);
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dc64(0xBFB7'45D1'60A7'E368ULL);
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(void)Bind(&C3Label);
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dc64(0x3FBC'71C7'1BC3'951CULL);
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(void)Bind(&C2Label);
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dc64(0xBFC2'4924'9247'8F88ULL);
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(void)Bind(&C1Label);
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dc64(0x3FC9'9999'9999'96C1ULL);
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(void)Bind(&C0Label);
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dc64(0xBFD5'5555'5555'5555ULL);
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(void)Bind(&PiOver2Label);
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dc64(0x3FF9'21FB'5444'2D18ULL);
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(void)Bind(&PiLabel);
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dc64(0x4009'21FB'5444'2D18ULL);
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}
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// JIT-inlined double-precision y * log2(x) for the F64 reduced precision x87 path.
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// Input: VTMP1 = x, VTMP2 = y. Output: VTMP1 = y * log2(x).
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// Algorithm: atanh-based log via s = f/(2+f) with 9-term polynomial, scaled by 1/ln(2),
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// then multiplied by y.
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void Dispatcher::EmitF64FYL2X() {
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F64FYL2XHandlerAddress = GetCursorAddress<uint64_t>();
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constexpr auto Accum = ARMEmitter::VReg::v2;
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ARMEmitter::ForwardLabel Fallback;
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ARMEmitter::ForwardLabel NoNorm;
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ARMEmitter::ForwardLabel Sqrt2Label, Log2eLabel;
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ARMEmitter::ForwardLabel BiasLabel;
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ARMEmitter::ForwardLabel P0Label, P1Label, P2Label, P3Label, P4Label, P5Label, P6Label, P7Label, P8Label;
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str<ARMEmitter::IndexType::PRE>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, -16);
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mrs(TMP1, ARMEmitter::SystemRegister::NZCV);
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str(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
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// Reject x <= 0, subnormal, inf and NaN before any FPR is clobbered,
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// so VTMP1/VTMP2 still hold the original inputs at the fallback.
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fmov(ARMEmitter::Size::i64Bit, TMP1, VTMP1.D());
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(void)tbnz(TMP1, 63, &Fallback);
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lsr(ARMEmitter::Size::i64Bit, TMP2, TMP1, 52);
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(void)cbz(ARMEmitter::Size::i64Bit, TMP2, &Fallback);
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cmp(ARMEmitter::Size::i64Bit, TMP2, 0x7FF);
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(void)b(ARMEmitter::Condition::CC_EQ, &Fallback);
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fmov(ARMEmitter::Size::i64Bit, TMP3, VTMP2.D());
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// Extract k and normalize mantissa m into [1.0, 2.0).
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sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, 1023);
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ubfx(ARMEmitter::Size::i64Bit, TMP1, TMP1, 0, 52);
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ldr(TMP4, &BiasLabel);
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orr(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP4);
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fmov(ARMEmitter::Size::i64Bit, VTMP1.D(), TMP1);
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// If m > sqrt(2), halve m and increment k.
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ldr(VTMP2.D(), &Sqrt2Label);
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fcmp(VTMP1.D(), VTMP2.D());
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(void)b(ARMEmitter::Condition::CC_LE, &NoNorm);
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fmov(ARMEmitter::ScalarRegSize::i64Bit, VTMP2, 0.5f);
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fmul(VTMP1.D(), VTMP1.D(), VTMP2.D());
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add(ARMEmitter::Size::i64Bit, TMP2, TMP2, 1);
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(void)Bind(&NoNorm);
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// f = m - 1; s = f / (2 + f); TMP1 stashes s, VTMP1 holds s^2.
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fmov(ARMEmitter::ScalarRegSize::i64Bit, VTMP2, 1.0f);
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fsub(VTMP1.D(), VTMP1.D(), VTMP2.D());
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fmov(ARMEmitter::ScalarRegSize::i64Bit, VTMP2, 2.0f);
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fadd(VTMP2.D(), VTMP1.D(), VTMP2.D());
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fdiv(Accum.D(), VTMP1.D(), VTMP2.D());
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fmul(VTMP1.D(), Accum.D(), Accum.D());
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fmov(ARMEmitter::Size::i64Bit, TMP1, Accum.D());
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// 9-term Horner from 1/19 down to 1/3.
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ldr(Accum.D(), &P8Label);
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ldr(VTMP2.D(), &P7Label);
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fmadd(Accum.D(), VTMP1.D(), Accum.D(), VTMP2.D());
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ldr(VTMP2.D(), &P6Label);
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fmadd(Accum.D(), VTMP1.D(), Accum.D(), VTMP2.D());
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ldr(VTMP2.D(), &P5Label);
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fmadd(Accum.D(), VTMP1.D(), Accum.D(), VTMP2.D());
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ldr(VTMP2.D(), &P4Label);
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fmadd(Accum.D(), VTMP1.D(), Accum.D(), VTMP2.D());
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ldr(VTMP2.D(), &P3Label);
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fmadd(Accum.D(), VTMP1.D(), Accum.D(), VTMP2.D());
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ldr(VTMP2.D(), &P2Label);
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fmadd(Accum.D(), VTMP1.D(), Accum.D(), VTMP2.D());
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ldr(VTMP2.D(), &P1Label);
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fmadd(Accum.D(), VTMP1.D(), Accum.D(), VTMP2.D());
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ldr(VTMP2.D(), &P0Label);
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fmadd(Accum.D(), VTMP1.D(), Accum.D(), VTMP2.D());
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// ln(1+f) = 2 * s * (1 + s^2 * P(s^2)).
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fmul(Accum.D(), VTMP1.D(), Accum.D());
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fmov(ARMEmitter::ScalarRegSize::i64Bit, VTMP2, 1.0f);
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fadd(Accum.D(), Accum.D(), VTMP2.D());
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fmov(ARMEmitter::Size::i64Bit, VTMP2.D(), TMP1);
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fmul(Accum.D(), VTMP2.D(), Accum.D());
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fadd(Accum.D(), Accum.D(), Accum.D());
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// log2(x) = k + ln(1+f)/ln(2); multiply by y.
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ldr(VTMP1.D(), &Log2eLabel);
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fmul(VTMP1.D(), Accum.D(), VTMP1.D());
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scvtf(ARMEmitter::Size::i64Bit, VTMP2.D(), TMP2);
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fadd(VTMP1.D(), VTMP1.D(), VTMP2.D());
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fmov(ARMEmitter::Size::i64Bit, VTMP2.D(), TMP3);
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fmul(VTMP1.D(), VTMP1.D(), VTMP2.D());
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ldr(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
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msr(ARMEmitter::SystemRegister::NZCV, TMP1);
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ldr<ARMEmitter::IndexType::POST>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, 16);
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ret();
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// Fallback path: VTMP1/VTMP2 still hold the original x/y.
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(void)Bind(&Fallback);
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ldr(TMP1.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
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msr(ARMEmitter::SystemRegister::NZCV, TMP1);
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ldr<ARMEmitter::IndexType::POST>(ARMEmitter::QReg::q2, ARMEmitter::Reg::rsp, 16);
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str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
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ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[FEXCore::Core::OPINDEX_F64FYL2X].ABIHandler));
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ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[FEXCore::Core::OPINDEX_F64FYL2X].Func));
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blr(TMP1);
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ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
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ret();
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// Constant pool: bias=1.0, sqrt(2), log2(e)=1/ln(2), P8..P0 = 1/19, 1/17, 1/15, ..., 1/3.
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Align(16);
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(void)Bind(&BiasLabel);
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dc64(0x3FF0'0000'0000'0000ULL);
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(void)Bind(&Sqrt2Label);
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dc64(0x3FF6'A09E'667F'3BCDULL);
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(void)Bind(&Log2eLabel);
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dc64(0x3FF7'1547'652B'82FEULL);
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(void)Bind(&P8Label);
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dc64(0x3FAA'F286'BCA1'AF28ULL);
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(void)Bind(&P7Label);
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dc64(0x3FAE'1E1E'1E1E'1E1EULL);
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(void)Bind(&P6Label);
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||||
dc64(0x3FB1'1111'1111'1111ULL);
|
||||
(void)Bind(&P5Label);
|
||||
dc64(0x3FB3'B13B'13B1'3B14ULL);
|
||||
(void)Bind(&P4Label);
|
||||
dc64(0x3FB7'45D1'745D'1746ULL);
|
||||
(void)Bind(&P3Label);
|
||||
dc64(0x3FBC'71C7'1C71'C71CULL);
|
||||
(void)Bind(&P2Label);
|
||||
dc64(0x3FC2'4924'9249'2492ULL);
|
||||
(void)Bind(&P1Label);
|
||||
dc64(0x3FC9'9999'9999'999AULL);
|
||||
(void)Bind(&P0Label);
|
||||
dc64(0x3FD5'5555'5555'5555ULL);
|
||||
}
|
||||
|
||||
uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
|
||||
auto Address = GetCursorAddress<uint64_t>();
|
||||
constexpr static auto FallbackPointerReg = TMP4;
|
||||
@@ -1870,6 +2188,8 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread)
|
||||
Ptrs.F64TanHandler = F64TanHandlerAddress;
|
||||
Ptrs.F64F2XM1Handler = F64F2XM1HandlerAddress;
|
||||
Ptrs.F64ScaleHandler = F64ScaleHandlerAddress;
|
||||
Ptrs.F64AtanHandler = F64AtanHandlerAddress;
|
||||
Ptrs.F64FYL2XHandler = F64FYL2XHandlerAddress;
|
||||
|
||||
// Fill in the fallback handlers
|
||||
InterpreterOps::FillFallbackIndexPointers(Ptrs.FallbackHandlerPointers, &ABIPointers[0]);
|
||||
|
||||
@@ -105,6 +105,8 @@ private:
|
||||
uint64_t F64TanHandlerAddress {};
|
||||
uint64_t F64F2XM1HandlerAddress {};
|
||||
uint64_t F64ScaleHandlerAddress {};
|
||||
uint64_t F64AtanHandlerAddress {};
|
||||
uint64_t F64FYL2XHandlerAddress {};
|
||||
|
||||
void EmitDispatcher();
|
||||
uint64_t GenerateABICall(FallbackABI ABI);
|
||||
@@ -121,6 +123,8 @@ private:
|
||||
void EmitF64Tan();
|
||||
void EmitF64F2XM1();
|
||||
void EmitF64Scale();
|
||||
void EmitF64Atan();
|
||||
void EmitF64FYL2X();
|
||||
|
||||
FEX_CONFIG_OPT(DisableL2Cache, DISABLEL2CACHE);
|
||||
};
|
||||
|
||||
@@ -4650,6 +4650,37 @@ DEF_OP(F64TAN) {
|
||||
fmov(Dst.D(), VTMP1.D());
|
||||
}
|
||||
|
||||
// Src1=y(ST1), Src2=x(ST0). Marshal into VTMP1/VTMP2 and dispatch the shared handler.
|
||||
DEF_OP(F64ATAN) {
|
||||
const auto Op = IROp->C<IR::IROp_F64ATAN>();
|
||||
const auto Src1 = GetVReg(Op->Src1);
|
||||
const auto Src2 = GetVReg(Op->Src2);
|
||||
const auto Dst = GetVReg(Node);
|
||||
|
||||
fmov(VTMP1.D(), Src1.D());
|
||||
fmov(VTMP2.D(), Src2.D());
|
||||
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.F64AtanHandler));
|
||||
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
|
||||
blr(TMP1);
|
||||
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
|
||||
fmov(Dst.D(), VTMP1.D());
|
||||
}
|
||||
|
||||
// Src=x(ST0), Src2=y(ST1). Marshal into VTMP1/VTMP2 and dispatch the shared handler.
|
||||
DEF_OP(F64FYL2X) {
|
||||
const auto Op = IROp->C<IR::IROp_F64FYL2X>();
|
||||
const auto Src = GetVReg(Op->Src);
|
||||
const auto Src2 = GetVReg(Op->Src2);
|
||||
const auto Dst = GetVReg(Node);
|
||||
|
||||
fmov(VTMP1.D(), Src.D());
|
||||
fmov(VTMP2.D(), Src2.D());
|
||||
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.F64FYL2XHandler));
|
||||
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
|
||||
blr(TMP1);
|
||||
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
|
||||
fmov(Dst.D(), VTMP1.D());
|
||||
}
|
||||
|
||||
DEF_OP(F64SCALE) {
|
||||
const auto Op = IROp->C<IR::IROp_F64SCALE>();
|
||||
|
||||
@@ -2758,7 +2758,7 @@
|
||||
"F64": {
|
||||
"FPR = F64ATAN FPR:$Src1, FPR:$Src2": {
|
||||
"DestSize": "OpSize::i64Bit",
|
||||
"JITDispatch": false
|
||||
"JITDispatch": true
|
||||
},
|
||||
"FPR = F64FPREM FPR:$Src1, FPR:$Src2": {
|
||||
"DestSize": "OpSize::i64Bit",
|
||||
@@ -2778,7 +2778,7 @@
|
||||
},
|
||||
"FPR = F64FYL2X FPR:$Src, FPR:$Src2": {
|
||||
"DestSize": "OpSize::i64Bit",
|
||||
"JITDispatch": false
|
||||
"JITDispatch": true
|
||||
},
|
||||
"FPR = F64TAN FPR:$Src": {
|
||||
"DestSize": "OpSize::i64Bit",
|
||||
|
||||
@@ -381,6 +381,8 @@ struct JITPointers {
|
||||
uint64_t F64TanHandler {};
|
||||
uint64_t F64F2XM1Handler {};
|
||||
uint64_t F64ScaleHandler {};
|
||||
uint64_t F64AtanHandler {};
|
||||
uint64_t F64FYL2XHandler {};
|
||||
/** @} */
|
||||
|
||||
// Copy of process-wide named vector constants data.
|
||||
|
||||
Reference in new issue
Block a user