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Merge pull request #9 from Sonicadvance1/unittests/stos
Adds unit tests for the STOS instruction family
This commit is contained in:
Stefanos Kornilios Mitsis Poiitidis authored and GitHub committed
commit
e2e9e1eb41
13 files changed
+483
-46
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+73
-46
@@ -1748,71 +1748,98 @@ void OpDispatchBuilder::DECOp(OpcodeArgs) {
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}
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void OpDispatchBuilder::STOSOp(OpcodeArgs) {
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LogMan::Throw::A(Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_REP_PREFIX, "Can't handle REP not existing on STOS\n");
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LogMan::Throw::A(!(Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_REPNE_PREFIX), "Invalid REPNE on STOS");
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auto Size = GetSrcSize(Op);
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// Create all our blocks
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auto LoopHead = CreateNewCodeBlock();
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auto LoopTail = CreateNewCodeBlock();
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auto LoopEnd = CreateNewCodeBlock();
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// At the time this was written, our RA can't handle accessing nodes across blocks.
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// So we need to re-load and re-calculate essential values each iteration of the loop.
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bool Repeat = Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_REP_PREFIX;
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// First thing we need to do is finish this block and jump to the start of the loop.
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_Jump(LoopHead);
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if (!Repeat) {
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OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), GPRClass);
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SetCurrentCodeBlock(LoopHead);
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{
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OrderedNode *Counter = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RCX]), GPRClass);
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auto ZeroConst = _Constant(0);
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// Store to memory where RDI points
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_StoreMem(GPRClass, Size, Dest, Src, Size);
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// Can we end the block?
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auto CanLeaveCond = _Select(FEXCore::IR::COND_EQ,
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Counter, ZeroConst,
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_Constant(1), ZeroConst);
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auto SizeConst = _Constant(Size);
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auto NegSizeConst = _Constant(-Size);
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_CondJump(CanLeaveCond, LoopEnd, LoopTail);
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}
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// Calculate direction.
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auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC);
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auto PtrDir = _Select(FEXCore::IR::COND_EQ,
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DF, _Constant(0),
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SizeConst, NegSizeConst);
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SetCurrentCodeBlock(LoopTail);
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{
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OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), GPRClass);
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// Offset the pointer
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OrderedNode *TailDest = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), GPRClass);
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TailDest = _Add(TailDest, PtrDir);
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_StoreContext(GPRClass, 8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), TailDest);
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// Store to memory where RDI points
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_StoreMem(GPRClass, Size, Dest, Src, Size);
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}
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else {
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// Create all our blocks
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auto LoopHead = CreateNewCodeBlock();
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auto LoopTail = CreateNewCodeBlock();
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auto LoopEnd = CreateNewCodeBlock();
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OrderedNode *TailCounter = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RCX]), GPRClass);
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OrderedNode *TailDest = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), GPRClass);
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// At the time this was written, our RA can't handle accessing nodes across blocks.
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// So we need to re-load and re-calculate essential values each iteration of the loop.
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// Decrement counter
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TailCounter = _Sub(TailCounter, _Constant(1));
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// First thing we need to do is finish this block and jump to the start of the loop.
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_Jump(LoopHead);
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// Store the counter so we don't have to deal with PHI here
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_StoreContext(GPRClass, 8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RCX]), TailCounter);
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SetCurrentCodeBlock(LoopHead);
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{
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OrderedNode *Counter = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RCX]), GPRClass);
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auto ZeroConst = _Constant(0);
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auto SizeConst = _Constant(Size);
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auto NegSizeConst = _Constant(-Size);
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// Can we end the block?
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auto CanLeaveCond = _Select(FEXCore::IR::COND_EQ,
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Counter, ZeroConst,
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_Constant(1), ZeroConst);
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// Calculate direction.
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auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC);
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auto PtrDir = _Select(FEXCore::IR::COND_EQ,
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DF, _Constant(0),
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SizeConst, NegSizeConst);
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_CondJump(CanLeaveCond, LoopEnd, LoopTail);
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}
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// Offset the pointer
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TailDest = _Add(TailDest, PtrDir);
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_StoreContext(GPRClass, 8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), TailDest);
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SetCurrentCodeBlock(LoopTail);
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{
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OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), GPRClass);
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// Jump back to the start, we have more work to do
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_Jump(LoopHead);
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}
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// Store to memory where RDI points
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_StoreMem(GPRClass, Size, Dest, Src, Size);
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// Make sure to start a new block after ending this one
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OrderedNode *TailCounter = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RCX]), GPRClass);
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OrderedNode *TailDest = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), GPRClass);
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SetCurrentCodeBlock(LoopEnd);
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// Decrement counter
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TailCounter = _Sub(TailCounter, _Constant(1));
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// Store the counter so we don't have to deal with PHI here
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_StoreContext(GPRClass, 8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RCX]), TailCounter);
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auto SizeConst = _Constant(Size);
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auto NegSizeConst = _Constant(-Size);
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// Calculate direction.
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auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC);
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auto PtrDir = _Select(FEXCore::IR::COND_EQ,
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DF, _Constant(0),
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SizeConst, NegSizeConst);
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// Offset the pointer
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TailDest = _Add(TailDest, PtrDir);
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_StoreContext(GPRClass, 8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), TailDest);
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// Jump back to the start, we have more work to do
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_Jump(LoopHead);
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}
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// Make sure to start a new block after ending this one
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SetCurrentCodeBlock(LoopEnd);
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}
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}
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void OpDispatchBuilder::MOVSOp(OpcodeArgs) {
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@@ -0,0 +1,40 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF2F2F2F2F2F2F2F2",
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"RDX": "0x0",
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"RDI": "0xE0000018"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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lea rdi, [rdx + 8 * 2]
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cld
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mov rax, 0xF2
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stosb ; rdi <- al
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stosb
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stosb
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stosb
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stosb
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stosb
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stosb
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stosb
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mov rax, [rdx + 8 * 2]
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mov rdx, [rdx + 8 * 3]
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hlt
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@@ -0,0 +1,33 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF2F2F2F2F2F2F2F2",
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"RDX": "0x0",
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"RDI": "0xE0000018"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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lea rdi, [rdx + 8 * 2]
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cld
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mov rcx, 8
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mov rax, 0xF2
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rep stosb ; rdi <- rsi
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mov rax, [rdx + 8 * 2]
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mov rdx, [rdx + 8 * 3]
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hlt
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@@ -0,0 +1,33 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF2F2F2F2F2F2F2F2",
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"RDX": "0x0",
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"RDI": "0xE000000F"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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lea rdi, [rdx + 8 * 2 + 7]
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std
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mov rcx, 8
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mov rax, 0xF2
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rep stosb ; rdi <- rsi
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mov rax, [rdx + 8 * 2]
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mov rdx, [rdx + 8 * 3]
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hlt
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@@ -0,0 +1,33 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF1F2F3F4F1F2F3F4",
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"RDX": "0x0",
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"RDI": "0xE0000018"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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lea rdi, [rdx + 8 * 2]
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cld
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mov rax, 0xF1F2F3F4
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stosd ; rdi <- eax
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stosd
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mov rax, [rdx + 8 * 2]
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mov rdx, [rdx + 8 * 3]
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hlt
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@@ -0,0 +1,33 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF1F2F3F4F1F2F3F4",
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"RDX": "0x0",
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"RDI": "0xE0000018"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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lea rdi, [rdx + 8 * 2]
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cld
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mov rax, 0xF1F2F3F4
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mov rcx, 2
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rep stosd ; rdi <- eax
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mov rax, [rdx + 8 * 2]
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mov rdx, [rdx + 8 * 3]
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hlt
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@@ -0,0 +1,33 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF1F2F3F4F1F2F3F4",
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"RDX": "0x0",
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"RDI": "0xE000000C"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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lea rdi, [rdx + 8 * 2 + 4]
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std
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mov rax, 0xF1F2F3F4
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mov rcx, 2
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rep stosd ; rdi <- eax
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mov rax, [rdx + 8 * 2]
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mov rdx, [rdx + 8 * 3]
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hlt
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@@ -0,0 +1,32 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF1F2F3F4F5F6F7F8",
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"RDX": "0x0",
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"RDI": "0xE0000018"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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lea rdi, [rdx + 8 * 2]
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cld
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mov rax, 0xF1F2F3F4F5F6F7F8
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stosq ; rdi <- rax
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mov rax, [rdx + 8 * 2]
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mov rdx, [rdx + 8 * 3]
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hlt
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@@ -0,0 +1,36 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF1F2F3F4F5F6F7F8",
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"RDX": "0xF1F2F3F4F5F6F7F8",
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"RSI": "0x0",
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"RDI": "0xE0000020"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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mov [rdx + 8 * 4], rax
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lea rdi, [rdx + 8 * 2]
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cld
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mov rax, 0xF1F2F3F4F5F6F7F8
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mov rcx, 2
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rep stosq ; rdi <- rax
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mov rax, [rdx + 8 * 2]
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mov rsi, [rdx + 8 * 4]
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mov rdx, [rdx + 8 * 3]
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hlt
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@@ -0,0 +1,36 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0xF1F2F3F4F5F6F7F8",
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"RDX": "0xF1F2F3F4F5F6F7F8",
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"RSI": "0x0",
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"RDI": "0xE0000008"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x0
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mov [rdx + 8 * 2], rax
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mov [rdx + 8 * 3], rax
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mov [rdx + 8 * 4], rax
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lea rdi, [rdx + 8 * 3]
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std
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mov rax, 0xF1F2F3F4F5F6F7F8
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mov rcx, 2
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rep stosq ; rdi <- rax
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mov rax, [rdx + 8 * 2]
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mov rsi, [rdx + 8 * 4]
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mov rdx, [rdx + 8 * 3]
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hlt
|
||||
@@ -0,0 +1,35 @@
|
||||
%ifdef CONFIG
|
||||
{
|
||||
"RegData": {
|
||||
"RAX": "0xF1F2F1F2F1F2F1F2",
|
||||
"RDX": "0x0",
|
||||
"RDI": "0xE0000018"
|
||||
},
|
||||
"MemoryRegions": {
|
||||
"0x100000000": "4096"
|
||||
}
|
||||
}
|
||||
%endif
|
||||
|
||||
mov rdx, 0xe0000000
|
||||
|
||||
mov rax, 0x4142434445464748
|
||||
mov [rdx + 8 * 0], rax
|
||||
mov rax, 0x5152535455565758
|
||||
mov [rdx + 8 * 1], rax
|
||||
mov rax, 0x0
|
||||
mov [rdx + 8 * 2], rax
|
||||
mov [rdx + 8 * 3], rax
|
||||
|
||||
lea rdi, [rdx + 8 * 2]
|
||||
|
||||
cld
|
||||
mov rax, 0xF1F2
|
||||
stosw ; rdi <- ax
|
||||
stosw
|
||||
stosw
|
||||
stosw
|
||||
|
||||
mov rax, [rdx + 8 * 2]
|
||||
mov rdx, [rdx + 8 * 3]
|
||||
hlt
|
||||
@@ -0,0 +1,33 @@
|
||||
%ifdef CONFIG
|
||||
{
|
||||
"RegData": {
|
||||
"RAX": "0xF1F2F1F2F1F2F1F2",
|
||||
"RDX": "0x0",
|
||||
"RDI": "0xE0000018"
|
||||
},
|
||||
"MemoryRegions": {
|
||||
"0x100000000": "4096"
|
||||
}
|
||||
}
|
||||
%endif
|
||||
|
||||
mov rdx, 0xe0000000
|
||||
|
||||
mov rax, 0x4142434445464748
|
||||
mov [rdx + 8 * 0], rax
|
||||
mov rax, 0x5152535455565758
|
||||
mov [rdx + 8 * 1], rax
|
||||
mov rax, 0x0
|
||||
mov [rdx + 8 * 2], rax
|
||||
mov [rdx + 8 * 3], rax
|
||||
|
||||
lea rdi, [rdx + 8 * 2]
|
||||
|
||||
cld
|
||||
mov rcx, 0x4
|
||||
mov rax, 0xF1F2
|
||||
rep stosw ; rdi <- ax
|
||||
|
||||
mov rax, [rdx + 8 * 2]
|
||||
mov rdx, [rdx + 8 * 3]
|
||||
hlt
|
||||
@@ -0,0 +1,33 @@
|
||||
%ifdef CONFIG
|
||||
{
|
||||
"RegData": {
|
||||
"RAX": "0xF1F2F1F2F1F2F1F2",
|
||||
"RDX": "0x0",
|
||||
"RDI": "0xE000000E"
|
||||
},
|
||||
"MemoryRegions": {
|
||||
"0x100000000": "4096"
|
||||
}
|
||||
}
|
||||
%endif
|
||||
|
||||
mov rdx, 0xe0000000
|
||||
|
||||
mov rax, 0x4142434445464748
|
||||
mov [rdx + 8 * 0], rax
|
||||
mov rax, 0x5152535455565758
|
||||
mov [rdx + 8 * 1], rax
|
||||
mov rax, 0x0
|
||||
mov [rdx + 8 * 2], rax
|
||||
mov [rdx + 8 * 3], rax
|
||||
|
||||
lea rdi, [rdx + 8 * 2 + 6]
|
||||
|
||||
std
|
||||
mov rcx, 0x4
|
||||
mov rax, 0xF1F2
|
||||
rep stosw ; rdi <- ax
|
||||
|
||||
mov rax, [rdx + 8 * 2]
|
||||
mov rdx, [rdx + 8 * 3]
|
||||
hlt
|
||||
Reference in new issue
Block a user