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Merge pull request #4330 from Sonicadvance1/hotblock_tso_32bit
InstcountCI: Adds a hotblock for 32-bit TSO testing
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1 file changed
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{
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"Features": {
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"Bitness": 32,
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"EnabledHostFeatures": [
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"TSO",
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"LRCPC",
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"LRCPC2",
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"FLAGM",
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"FLAGM2"
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"AFP"
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]
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},
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"Instructions": {
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"The Sims 1 hot block": {
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"x86InstructionCount": 47,
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"ExpectedInstructionCount": 106,
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"Comment": [
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"Hottest in-game block from The Sims 1, Legacy Collection",
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"Consumed 6.13% of a CPU core on Oryon-1",
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"Some interesting problems in this block:",
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" - LRCPC2 small immediate loadstores aren't getting used",
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" - Memory stores of zero aren't using wzr register",
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" - Vector loadstores are using large negative numbers which Arm64 can't optimize",
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" - Would need to generate a temporary and convert negative offsets to positive (Or close enough for simm9)",
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" - LRCPC3 isn't used for vector loadstores at all",
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" - Where the excessive dmb comes from",
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" - No hardware ships with LRCPC3 yet anyway"
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],
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"x86Insts": [
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"push ebp",
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"mov ebp, esp",
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"sub esp, 0x1c4",
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"mov eax, dword [0xa37400]",
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"xor eax, ebp",
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"mov dword [ebp-0x4], eax",
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"mov edx, dword [ebp+0x8]",
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"push ebx",
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"push esi",
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"mov esi, dword [ebp+0x18]",
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"push edi",
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"mov edi, ecx",
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"mov dword [ebp-0x184], edx",
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"mov dword [ebp-0x180], 0x0",
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"lea ecx, [ebp-0x16c]",
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"add esi, 0x28",
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"mov edx, 0x6",
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"mov eax, dword [edi+0x3190]",
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"mov dword [ebp-0x188], eax",
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"mov eax, dword [ebp+0xc]",
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"mov dword [ebp-0x178], eax",
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"mov eax, dword [ebp+0x10]",
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"mov dword [ebp-0x170], eax",
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"movzx eax, byte [ebp+0x14]",
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"mov dword [ebp-0x17c], eax",
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"movq xmm0, qword [esi-0x28]",
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"xorps xmm1, xmm1",
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"mov eax, dword [esi-0x20]",
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"lea esi, [esi+0x4c]",
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"movq qword [ebp-0x1c4], xmm0",
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"lea ecx, [ecx+0x3c]",
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"mov dword [ebp-0x1bc], eax",
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"movups xmm0, [esi-0x58]",
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"movups [ebp-0x1a8], xmm1",
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"movups [ebp-0x1b8], xmm0",
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"movups xmm0, [ebp-0x1c4]",
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"movups [ebp-0x198], xmm1",
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"psrldq xmm1, 0xc",
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"movups [ecx-0x3c], xmm0",
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"movups xmm0, [ebp-0x1b4]",
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"movups [ecx-0x2c], xmm0",
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"movups xmm0, [ebp-0x1a4]",
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"movups [ecx-0x1c], xmm0",
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"movq xmm0, qword [ebp-0x194]",
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"movq qword [ecx-0xc], xmm0",
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"movd dword [ecx-0x4], xmm1",
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"sub edx, 0x1"
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],
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"ExpectedArm64ASM": [
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"str w9, [x8, #-4]!",
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"mov x9, x8",
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"sub w8, w8, #0x1c4 (452)",
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"mov w20, #0x7400",
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"movk w20, #0xa3, lsl #16",
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"ldapur w4, [x20]",
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"nop",
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"eor w4, w4, w9",
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"mov w20, #0x0",
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"sub w21, w9, #0x4 (4)",
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"nop",
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"stlur w4, [x21]",
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"add w21, w9, #0x8 (8)",
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"ldapur w5, [x21]",
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"nop",
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"str w6, [x8, #-4]!",
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"str w10, [x8, #-4]!",
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"add w21, w9, #0x18 (24)",
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"ldapur w10, [x21]",
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"nop",
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"str w11, [x8, #-4]!",
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"mov x11, x7",
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"sub w21, w9, #0x184 (388)",
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"nop",
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"stlur w5, [x21]",
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"sub w21, w9, #0x180 (384)",
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"nop",
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"stlur w20, [x21]",
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"sub w7, w9, #0x16c (364)",
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"add w10, w10, #0x28 (40)",
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"mov w5, #0x6",
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"mov w20, #0x3190",
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"add w20, w11, w20",
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"ldapur w4, [x20]",
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"nop",
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"sub w20, w9, #0x188 (392)",
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"nop",
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"stlur w4, [x20]",
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"add w20, w9, #0xc (12)",
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"ldapur w4, [x20]",
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"nop",
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"sub w20, w9, #0x178 (376)",
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"nop",
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"stlur w4, [x20]",
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"add w20, w9, #0x10 (16)",
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"ldapur w4, [x20]",
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"nop",
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"sub w20, w9, #0x170 (368)",
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"nop",
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"stlur w4, [x20]",
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"add w20, w9, #0x14 (20)",
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"ldapurb w4, [x20]",
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"sub w20, w9, #0x17c (380)",
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"nop",
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"stlur w4, [x20]",
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"ldur d16, [x10, #-40]",
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"dmb ishld",
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"movi v17.2d, #0x0",
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"sub w20, w10, #0x20 (32)",
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"ldapur w4, [x20]",
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"nop",
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"add w10, w10, #0x4c (76)",
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"mov x20, #0xfffffffffffffe3c",
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"dmb ish",
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"str d16, [x9, x20, sxtx]",
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"add w7, w7, #0x3c (60)",
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"sub w21, w9, #0x1bc (444)",
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"nop",
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"stlur w4, [x21]",
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"ldur q16, [x10, #-88]",
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"dmb ishld",
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"mov v2.16b, v17.16b",
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"mov x21, #0xfffffffffffffe58",
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"dmb ish",
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"str q17, [x9, x21, sxtx]",
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"mov x21, #0xfffffffffffffe48",
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"dmb ish",
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"str q16, [x9, x21, sxtx]",
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"ldr q16, [x9, x20, sxtx]",
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"dmb ishld",
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"mov x20, #0xfffffffffffffe68",
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"dmb ish",
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"str q17, [x9, x20, sxtx]",
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"ext v17.16b, v17.16b, v2.16b, #12",
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"dmb ish",
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"stur q16, [x7, #-60]",
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"mov x20, #0xfffffffffffffe4c",
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"ldr q16, [x9, x20, sxtx]",
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"dmb ishld",
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"dmb ish",
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"stur q16, [x7, #-44]",
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"mov x20, #0xfffffffffffffe5c",
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"ldr q16, [x9, x20, sxtx]",
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"dmb ishld",
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"dmb ish",
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"stur q16, [x7, #-28]",
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"mov x20, #0xfffffffffffffe6c",
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"ldr d16, [x9, x20, sxtx]",
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"dmb ishld",
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"dmb ish",
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"stur d16, [x7, #-12]",
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"sub w20, w7, #0x4 (4)",
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"str s17, [x20]",
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"subs w26, w5, #0x1 (1)",
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"mov x27, x5",
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"mov x5, x26"
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]
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}
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}
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}
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