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Arm64/VectorOps: Eliminate unnecessary EOR and MOV in VCMP{EQ,GT}

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We can use the zeroing version of MOVPRFX to perform the same behavior.
This commit is contained in:
Lioncache committed 2023-03-27 15:38:03 -04:00
1 parent 9183cf144f
commit eecd016ba8
1 file changed
+4 -12
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External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
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+4 -12
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@@ -1531,17 +1531,13 @@ DEF_OP(VCMPEQ) {
const auto Mask = PRED_TMP_32B.Zeroing();
const auto ComparePred = ARMEmitter::PReg::p0;
// Ensure no junk is in the temp (important for ensuring
// non-equal entries remain as zero during the final bitwise OR).
eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
// General idea is to compare for equality, not the equal vals
// from one of the registers, then or both together to make the
// relevant equal entries all 1s.
cmpeq(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
mov(Dst.Z(), VTMP1.Z());
movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
} else {
if (IsScalar) {
cmeq(SubRegSize.Scalar, Dst, Vector1, Vector2);
@@ -1615,17 +1611,13 @@ DEF_OP(VCMPGT) {
const auto Mask = PRED_TMP_32B.Zeroing();
const auto ComparePred = ARMEmitter::PReg::p0;
// Ensure no junk is in the temp (important for ensuring
// non greater-than values remain as zero).
eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
// General idea is to compare for greater-than, bitwise NOT
// the valid values, then ORR the NOTed values with the original
// values to form entries that are all 1s.
cmpgt(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
mov(Dst.Z(), VTMP1.Z());
movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
} else {
if (IsScalar) {
cmgt(SubRegSize.Scalar, Dst, Vector1, Vector2);