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IR: Change LoadNamedVectorIndexedConstant to use IR::OpSize

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Ryan Houdek committed 2024-10-27 22:08:27 -07:00
1 parent 886db4ffca
commit efd5c51110
3 files changed
+12 -11
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FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+4 -4
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@@ -445,7 +445,7 @@ public:
void PUNPCKLOp(OpcodeArgs, size_t ElementSize);
void PUNPCKHOp(OpcodeArgs, size_t ElementSize);
void PSHUFBOp(OpcodeArgs);
Ref PShufWLane(size_t Size, FEXCore::IR::IndexNamedVectorConstant IndexConstant, bool LowLane, Ref IncomingLane, uint8_t Shuffle);
Ref PShufWLane(IR::OpSize Size, FEXCore::IR::IndexNamedVectorConstant IndexConstant, bool LowLane, Ref IncomingLane, uint8_t Shuffle);
void PSHUFWOp(OpcodeArgs, bool Low);
void PSHUFW8ByteOp(OpcodeArgs);
void PSHUFDOp(OpcodeArgs);
@@ -1422,7 +1422,7 @@ private:
Ref PSRLDOpImpl(OpcodeArgs, size_t ElementSize, Ref Src, Ref ShiftVec);
Ref SHUFOpImpl(OpcodeArgs, size_t DstSize, size_t ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle);
Ref SHUFOpImpl(OpcodeArgs, IR::OpSize DstSize, size_t ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle);
void VMASKMOVOpImpl(OpcodeArgs, IR::OpSize ElementSize, IR::OpSize DataSize, bool IsStore, const X86Tables::DecodedOperand& MaskOp,
const X86Tables::DecodedOperand& DataOp);
@@ -2196,11 +2196,11 @@ private:
CachedNamedVectorConstants[NamedConstant][log2_size_bytes] = Constant;
return Constant;
}
Ref LoadAndCacheIndexedNamedVectorConstant(uint8_t Size, FEXCore::IR::IndexNamedVectorConstant NamedIndexedConstant, uint32_t Index) {
Ref LoadAndCacheIndexedNamedVectorConstant(IR::OpSize Size, FEXCore::IR::IndexNamedVectorConstant NamedIndexedConstant, uint32_t Index) {
IndexNamedVectorMapKey Key {
.Index = Index,
.NamedIndexedConstant = NamedIndexedConstant,
.log2_size_in_bytes = FEXCore::ilog2(Size),
.log2_size_in_bytes = FEXCore::ilog2(IR::OpSizeToSize(Size)),
};
auto it = CachedIndexedNamedVectorConstants.find(Key);
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+7 -6
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@@ -888,7 +888,8 @@ void OpDispatchBuilder::VPSHUFBOp(OpcodeArgs) {
StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
}
Ref OpDispatchBuilder::PShufWLane(size_t Size, FEXCore::IR::IndexNamedVectorConstant IndexConstant, bool LowLane, Ref IncomingLane, uint8_t Shuffle) {
Ref OpDispatchBuilder::PShufWLane(IR::OpSize Size, FEXCore::IR::IndexNamedVectorConstant IndexConstant, bool LowLane, Ref IncomingLane,
uint8_t Shuffle) {
constexpr auto IdentityCopy = 0b11'10'01'00;
const bool Is128BitLane = Size == OpSize::i128Bit;
@@ -933,7 +934,7 @@ Ref OpDispatchBuilder::PShufWLane(size_t Size, FEXCore::IR::IndexNamedVectorCons
void OpDispatchBuilder::PSHUFW8ByteOp(OpcodeArgs) {
uint16_t Shuffle = Op->Src[1].Data.Literal.Value;
const auto Size = GetSrcSize(Op);
const auto Size = OpSizeFromSrc(Op);
Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
Ref Dest = PShufWLane(Size, FEXCore::IR::INDEXED_NAMED_VECTOR_PSHUFLW, true, Src, Shuffle);
StoreResult(FPRClass, Op, Dest, OpSize::iInvalid);
@@ -941,7 +942,7 @@ void OpDispatchBuilder::PSHUFW8ByteOp(OpcodeArgs) {
void OpDispatchBuilder::PSHUFWOp(OpcodeArgs, bool Low) {
uint16_t Shuffle = Op->Src[1].Data.Literal.Value;
const auto Size = GetSrcSize(Op);
const auto Size = OpSizeFromSrc(Op);
Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
const auto IndexedVectorConstant = Low ? FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW :
FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW;
@@ -1219,7 +1220,7 @@ void OpDispatchBuilder::VPSHUFWOp(OpcodeArgs, size_t ElementSize, bool Low) {
StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
}
Ref OpDispatchBuilder::SHUFOpImpl(OpcodeArgs, size_t DstSize, size_t ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle) {
Ref OpDispatchBuilder::SHUFOpImpl(OpcodeArgs, IR::OpSize DstSize, size_t ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle) {
// Since 256-bit variants and up don't lane cross, we can construct
// everything in terms of the 128-variant, as each lane is essentially
// its own 128-bit segment.
@@ -1415,7 +1416,7 @@ void OpDispatchBuilder::SHUFOp(OpcodeArgs, size_t ElementSize) {
Ref Src2Node = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
uint8_t Shuffle = Op->Src[1].Literal();
Ref Result = SHUFOpImpl(Op, GetDstSize(Op), ElementSize, Src1Node, Src2Node, Shuffle);
Ref Result = SHUFOpImpl(Op, OpSizeFromDst(Op), ElementSize, Src1Node, Src2Node, Shuffle);
StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
}
@@ -1424,7 +1425,7 @@ void OpDispatchBuilder::VSHUFOp(OpcodeArgs, size_t ElementSize) {
Ref Src2Node = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags);
uint8_t Shuffle = Op->Src[2].Literal();
Ref Result = SHUFOpImpl(Op, GetDstSize(Op), ElementSize, Src1Node, Src2Node, Shuffle);
Ref Result = SHUFOpImpl(Op, OpSizeFromDst(Op), ElementSize, Src1Node, Src2Node, Shuffle);
StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
}
FEXCore/Source/Interface/IR/IR.json
+1 -1
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@@ -1892,7 +1892,7 @@
],
"DestSize": "RegisterSize"
},
"FPR = LoadNamedVectorIndexedConstant u8:#RegisterSize, IndexNamedVectorConstant:$Constant, u32:$Index": {
"FPR = LoadNamedVectorIndexedConstant OpSize:#RegisterSize, IndexNamedVectorConstant:$Constant, u32:$Index": {
"Desc": ["Load a named vector constant from Indexable table.",
"Index needs to be aligned register size.",
"The list of indexable vector constants can be found in <FEXCore/IR/IR.h>"