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OpcodeDispatcher: Optimize AddSubP{S,D}

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Use a named constant for loading the sign inversion, then EOR the second
source and just FAdd it all.
In a vacuum it isn't a significant improvement, but as soon as more than
one instruction is in a block it will eventually get optimized with
named constant caching and be a significant win.

Thanks to @rygorous for the idea!
This commit is contained in:
Ryan Houdek committed 2023-08-23 20:32:51 -07:00
1 parent c5f358b47a
commit f300196d90
4 files changed
+33 -11
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FEXCore/Source/Interface/Core/CPUBackend.cpp
+10 -2
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@@ -8,8 +8,12 @@ namespace FEXCore {
namespace CPU {
constexpr static uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_MAX][2] = {
{0x0003'0002'0001'0000, 0x0007'0006'0005'0004},
{0x000B'000A'0009'0008, 0x000F'000E'000D'000C},
{0x0003'0002'0001'0000, 0x0007'0006'0005'0004}, // NAMED_VECTOR_INCREMENTAL_U16_INDEX
{0x000B'000A'0009'0008, 0x000F'000E'000D'000C}, // NAMED_VECTOR_INCREMENTAL_U16_INDEX_UPPER
{0x0000'0000'8000'0000, 0x0000'0000'8000'0000}, // NAMED_VECTOR_PADDSUBPS_INVERT
{0x0000'0000'8000'0000, 0x0000'0000'8000'0000}, // NAMED_VECTOR_PADDSUBPS_INVERT_UPPER
{0x8000'0000'0000'0000, 0x0000'0000'0000'0000}, // NAMED_VECTOR_PADDSUBPD_INVERT
{0x8000'0000'0000'0000, 0x0000'0000'0000'0000}, // NAMED_VECTOR_PADDSUBPD_INVERT_UPPER
};
CPUBackend::CPUBackend(FEXCore::Core::InternalThreadState *ThreadState, size_t InitialCodeSize, size_t MaxCodeSize)
@@ -20,6 +24,10 @@ CPUBackend::CPUBackend(FEXCore::Core::InternalThreadState *ThreadState, size_t I
// Initialize named vector constants.
Common.NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_INCREMENTAL_U16_INDEX] = reinterpret_cast<uint64_t>(NamedVectorConstants[0]);
Common.NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_INCREMENTAL_U16_INDEX_UPPER] = reinterpret_cast<uint64_t>(NamedVectorConstants[1]);
Common.NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_PADDSUBPS_INVERT] = reinterpret_cast<uint64_t>(NamedVectorConstants[2]);
Common.NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_PADDSUBPS_INVERT_UPPER] = reinterpret_cast<uint64_t>(NamedVectorConstants[3]);
Common.NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_PADDSUBPD_INVERT] = reinterpret_cast<uint64_t>(NamedVectorConstants[4]);
Common.NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_PADDSUBPD_INVERT_UPPER] = reinterpret_cast<uint64_t>(NamedVectorConstants[5]);
#ifndef FEX_DISABLE_TELEMETRY
// Fill in telemetry values
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+3 -9
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@@ -2962,15 +2962,9 @@ OrderedNode* OpDispatchBuilder::ADDSUBPOpImpl(OpcodeArgs, size_t ElementSize,
OrderedNode *Src1, OrderedNode *Src2) {
const auto Size = GetSrcSize(Op);
OrderedNode *ResAdd = _VFAdd(Size, ElementSize, Src1, Src2);
OrderedNode *ResSub = _VFSub(Size, ElementSize, Src1, Src2);
// Even elements are the sub result
// Odd elements are the add results
OrderedNode *UnzipSub = _VUnZip(Size, ElementSize, ResSub, ResSub);
OrderedNode *UnzipAdd = _VUnZip2(Size, ElementSize, ResAdd, ResAdd);
return _VZip(Size, ElementSize, UnzipSub, UnzipAdd);
auto ConstantEOR = _LoadNamedVectorConstant(Size, ElementSize == 4 ? NAMED_VECTOR_PADDSUBPS_INVERT : NAMED_VECTOR_PADDSUBPD_INVERT);
auto InvertedSource = _VXor(Size, ElementSize, Src2, ConstantEOR);
return _VFAdd(Size, ElementSize, Src1, InvertedSource);
}
template<size_t ElementSize>
FEXCore/Source/Interface/IR/IRDumper.cpp
+16
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@@ -193,6 +193,22 @@ static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const
*out << "u16_incremental_index_upper";
break;
}
case FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_PADDSUBPS_INVERT: {
*out << "addsubps_invert";
break;
}
case FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_PADDSUBPS_INVERT_UPPER: {
*out << "addsubps_invert_upper";
break;
}
case FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_PADDSUBPD_INVERT: {
*out << "addsubpd_invert";
break;
}
case FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_PADDSUBPD_INVERT_UPPER: {
*out << "addsubpd_invert_upper";
break;
}
default: *out << "<Unknown Named Vector Constant>"; break;
}
}
FEXCore/include/FEXCore/IR/IR.h
+4
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@@ -519,6 +519,10 @@ FEX_DEF_NUM_OPS(SyscallFlags)
enum NamedVectorConstant : uint8_t {
NAMED_VECTOR_INCREMENTAL_U16_INDEX = 0,
NAMED_VECTOR_INCREMENTAL_U16_INDEX_UPPER,
NAMED_VECTOR_PADDSUBPS_INVERT,
NAMED_VECTOR_PADDSUBPS_INVERT_UPPER,
NAMED_VECTOR_PADDSUBPD_INVERT,
NAMED_VECTOR_PADDSUBPD_INVERT_UPPER,
NAMED_VECTOR_MAX,
};