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InstCountCI: Update for instruction changes.
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@@ -1861,7 +1861,7 @@
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"Comment": "0x69",
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"ExpectedArm64ASM": [
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"mov w20, #0x101",
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"mul x21, x7, x20",
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"smull x21, w7, w20",
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"asr x21, x21, #32",
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"mul w4, w7, w20",
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"sbfx x20, x4, #31, #1",
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@@ -1900,7 +1900,7 @@
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"Comment": "0x6b",
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"ExpectedArm64ASM": [
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"mov w20, #0x3",
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"mul x21, x7, x20",
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"smull x21, w7, w20",
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"asr x21, x21, #32",
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"mul w4, w7, w20",
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"sbfx x20, x4, #31, #1",
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@@ -1006,7 +1006,7 @@
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"ExpectedInstructionCount": 6,
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"Comment": "0x0f 0xaf",
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"ExpectedArm64ASM": [
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"mul x20, x4, x7",
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"smull x20, w4, w7",
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"asr x20, x20, #32",
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"mul w4, w4, w7",
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"sbfx x21, x4, #31, #1",
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@@ -2091,7 +2091,7 @@
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"Comment": "0x69",
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"ExpectedArm64ASM": [
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"mov w20, #0x101",
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"mul x21, x7, x20",
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"smull x21, w7, w20",
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"asr x21, x21, #32",
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"mul w4, w7, w20",
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"sbfx x20, x4, #31, #1",
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@@ -2154,7 +2154,7 @@
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"Comment": "0x6b",
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"ExpectedArm64ASM": [
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"mov w20, #0x3",
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"mul x21, x7, x20",
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"smull x21, w7, w20",
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"asr x21, x21, #32",
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"mul w4, w7, w20",
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"sbfx x20, x4, #31, #1",
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@@ -1867,7 +1867,7 @@
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"ExpectedInstructionCount": 6,
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"Comment": "0x0f 0xaf",
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"ExpectedArm64ASM": [
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"mul x20, x4, x7",
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"smull x20, w4, w7",
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"asr x20, x20, #32",
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"mul w4, w4, w7",
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"sbfx x21, x4, #31, #1",
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