Ryan Houdek
c17340547c
Merge pull request #1789 from lioncash/avx-impl
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AVX initial groundwork
2022-07-13 14:12:53 -07:00
lioncash
82a6ce63b4
Dispatcher: Make use of AVX confix to determine stack sizes
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Now that we have the AVX config option in place, we can use it to
determine how to set up the stack for storing and loading all of the
necessary state we need.
2022-07-13 14:55:04 -04:00
Ryan Houdek
3ac6ba0fe2
Merge pull request #1846 from lioncash/x86ir
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x86_64: Migrate args over to named IR arguments
2022-07-13 11:39:51 -07:00
lioncash
8b0fb4fa19
HostFeatures: Add querying for AVX support
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If we have SVE2 support and a vector length of at least 256, then we can
adequately handle AVX.
However we also add in the ability for application profiles to disable
AVX if necessary for any reason.
Not currently used, but will be in subsequent changes.
2022-07-13 14:30:31 -04:00
lioncash
9d437b8863
CoreState: Expand xmm registers
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Expands them to add the high lanes added in AVX
2022-07-13 14:29:48 -04:00
lioncash
f72469c80a
Dispatcher: Handle restoring ymm high lanes
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On Linux the bottom 12 bytes of the legacy FXSAVE context are used to
encode information about any extension blocks that may follow it.
We can use the same approach to encode our high lanes of the AVX
YMM registers into memory and vice-versa.
2022-07-13 14:29:48 -04:00
Lioncache
fc9343e7a4
x86_64/VectorOps: Correct VRev64 op cast
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This was using the structure for VDupElement, but happened
to work because the layouts are the same.
2022-07-13 13:46:16 -04:00
Lioncache
be8e353d12
x86_64/VectorOps: Move args names over to IR names
2022-07-13 13:45:45 -04:00
Lioncache
53217acdd0
x86_64/MoveOps: Move args names over to IR names
2022-07-13 13:16:37 -04:00
Lioncache
c1e0ea5e0a
x86_64/MiscOps: Move args names over to IR names
2022-07-13 13:15:16 -04:00
Lioncache
467afc7248
x86_64/FlagOps: Move args names over to IR names
2022-07-13 13:13:37 -04:00
Lioncache
62753071f4
x86_64/EncryptionOps: Move args names over to IR names
2022-07-13 13:13:08 -04:00
Lioncache
de32de9edd
x86_64/ConversionOps: Move args names over to IR names
2022-07-13 13:10:18 -04:00
Lioncache
aa7d2c3f7e
x86_64/BranchOps: Move args names over to IR names
2022-07-13 13:07:48 -04:00
Lioncache
2a1dd68583
x86_64/ALUOps: Move args names over to IR names
2022-07-13 13:06:30 -04:00
Ryan Houdek
8d7b8729f1
FEXCore: Support synchronizing RIP on block entry through config
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If an application is doing long jumps on exceptions then we need to
ensure that RIP is synchronized at least to block entry for some amount
of safety.
Due to our block linking which doesn't ensure that RIP is synchronized
on block entry, our exception handling wouldn't see a RIP change, thus
not going down the path that we jump to Dispatcher loop top on RIP
change.
Burn a couple of instructions on block entry to ensure that RIP
synchronized but only on config.
2022-07-13 08:49:13 -07:00
Ryan Houdek
3f9a1c3751
Merge pull request #1844 from lioncash/interp
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Interpreter: Move argument names over to IR names
2022-07-12 10:10:25 -07:00
Ryan Houdek
235ad441b4
Dispatcher: Fix SRA enabled check in signal delegator handlers
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When some SRA code was being shuffled around, this config variable was
never being set. This caused the guest signal handlers to never expect
SRA to be enabled.
Moves the Dispatcher config object to the actual dispatcher rather than
having it in the arch specific dispatcher class. Then have the signal
delegator check the config directly instead of having this secondary
config value.
Fixes vc_redist_x64 and vc_redist_x86. Probably also fixes a bunch of
other random Proton/Wine things that rely on signal long jump.
2022-07-10 11:39:25 -07:00
Stefanos Kornilios Misis Poiitidis
9af3bc1864
Dispatcher/Arm64: Fix vixl assert
2022-06-29 10:41:24 +03:00
Stefanos Kornilios Misis Poiitidis
4139332ad9
GDBSymbols: Cleanups
2022-06-27 14:44:07 +03:00
Stefanos Kornilios Misis Poiitidis
3871646611
GDBSymbols: Add gdb reader for fex, GDBSymbols option to enable
2022-06-24 16:27:16 +03:00
Stefanos Kornilios Misis Poiitidis
9ce94266e1
IR: Remove GuestCallDirect, GuestCallIndirect
2022-06-23 19:46:25 +03:00
Tony Wasserka
f27830bf41
Fix inconsistent allocation schemes used for RegisterAllocationData
2022-06-23 17:16:44 +02:00
Stefanos Kornilios Misis Poiitidis
835155021d
Dispatchers: Use thread local emitters for backend callbacks
2022-06-23 13:33:56 +03:00
Stefanos Kornilios Misis Poiitidis
e2c5c2292d
Dispatchers: Use thread local emitters for backend callbacks
2022-06-23 13:20:03 +03:00
Stefanos Kornilios Mitsis Poiitidis
072690a191
Merge pull request #1782 from FEX-Emu/skmp/ipr-unified-dispatch
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Backends: Unified dispatch, interface rework, cleanups
2022-06-23 07:03:14 +00:00
Stefanos Kornilios Misis Poiitidis
4dbcd34548
Backends: Rework some of the interfaces, unified backend dispatch
2022-06-22 22:24:42 +03:00
lioncash
5cd0f6e7e7
Interpreter/VectorOps: Move argument names over to IR names
2022-06-17 15:31:10 -04:00
lioncash
2627ed3193
Interpreter/MoveOps: Move argument names over to IR names
2022-06-17 14:31:01 -04:00
lioncash
e3bb8b43ab
Interpreter/MiscOps: Move argument names over to IR names
2022-06-17 14:30:00 -04:00
lioncash
8ba6a3bda9
Interpreter/MemoryOps: Move argument names over to IR names
2022-06-17 14:28:44 -04:00
lioncash
d288249609
Interpreter/FlagOps: Move argument names over to IR names
2022-06-17 14:25:39 -04:00
lioncash
33d7c6be9e
Interpreter/F80Ops: Move argument names over to IR names
2022-06-17 14:25:09 -04:00
lioncash
c13acc5b60
Interpreter/EncryptionOps: Move argument names over to IR names
2022-06-17 14:14:46 -04:00
lioncash
fc9be28d51
Interpreter/ConversionOps: Move argument names over to IR names
2022-06-17 14:12:09 -04:00
lioncash
944f400d19
Interpreter/BranchOps: Move argument names over to IR names
2022-06-17 14:08:43 -04:00
lioncash
5aee30a7b5
Interpreter/ALUOps: Move argument names over to IR names
2022-06-17 14:06:18 -04:00
lioncash
58ae49372c
CoreState: Add register size constants
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Gets rid of some magic numbers and reduces the number of things that
need to manually change (e.g. when supporting AVX and needing to
increase the xmm size).
2022-06-17 10:55:07 -04:00
Stefanos Kornilios Mitsis Poiitidis
0a62a4c571
Merge pull request #1775 from FEX-Emu/skmp/dispatcher-per-context
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Make Dispatcher per Context from per Thread, Simplify TestHarnessRunner
2022-06-16 21:08:32 +00:00
Stefanos Kornilios Misis Poiitidis
525266e482
Core: Move common signal handling setup to context
2022-06-16 19:41:42 +00:00
Stefanos Kornilios Misis Poiitidis
503881f5df
Jit/Arm64: Fix ubuntu 20.04 include
2022-06-16 19:41:42 +00:00
Stefanos Kornilios Misis Poiitidis
04fd4f2bb4
Arm64Dispatcher: Add missing ExitFunctionLinker Pointer
2022-06-16 19:41:42 +00:00
Stefanos Kornilios Misis Poiitidis
472ce7c1e4
Context: Add DipsatcherConfig to class, minor header massaging
2022-06-16 19:41:42 +00:00
Stefanos Kornilios Misis Poiitidis
39f3406fba
Backends+Context: Make Dispatcher per Context from per Thread
2022-06-16 19:41:42 +00:00
Ryan Houdek
19b0a9cd7d
Merge pull request #1779 from lioncash/irname
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Arm64/JIT: Use IR names in opcode implementations
2022-06-16 12:37:18 -07:00
Stefanos Kornilios Mitsis Poiitidis
eac579f714
Merge pull request #1778 from FEX-Emu/skmp/fix-thread-creation-race
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Context: Fix CreateThread partial initialization issue
2022-06-16 18:17:34 +00:00
Stefanos Kornilios Mitsis Poiitidis
b0a31f7105
Merge pull request #1770 from FEX-Emu/skmp/custom-ir-handlers-2
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Context: Decouple from CodeLoader, introduce generic CustomIREntrypoints
2022-06-16 18:04:18 +00:00
Stefanos Kornilios Misis Poiitidis
29163cfd07
Context: Fix CreateThread partial initialization issue
2022-06-16 17:51:49 +00:00
Stefanos Kornilios Mitsis Poiitidis
f05b24636f
OpDisp: Re add ShouldDump
2022-06-16 17:38:44 +00:00
lioncash
39466a3a8f
Arm64/VectorOps: Move arguments over to IR names
2022-06-16 12:03:33 -04:00
Ryan Houdek