lioncash
232c2fe87f
x86_64/VectorOps: Separate 128-bit VCMPEQZ path
2022-11-16 19:06:54 +00:00
lioncash
661112cfd4
x86_64/VectorOps: Separate 128-bit VCMPEQ path
2022-11-16 19:01:31 +00:00
lioncash
d4a84eaa9a
x86_64/VectorOps: Separate 128-bit VBSL path
2022-11-16 18:59:40 +00:00
lioncash
99f8af64d0
x86_64/VectorOps: Separate 128-bit VSMax path
2022-11-16 18:57:16 +00:00
lioncash
1541ea9ffc
x86_64/VectorOps: Separate 128-bit VUMax path
2022-11-16 18:55:23 +00:00
lioncash
ced86e693c
x86_64/VectorOps: Separate 128-bit VSMin path
2022-11-16 18:53:46 +00:00
lioncash
53920d5bd3
x86_64/VectorOps: Separate 128-bit VUMin path
2022-11-16 18:51:56 +00:00
lioncash
15c5a9dac0
x86_64/VectorOps: Separate 128-bit VNot path
2022-11-16 18:49:13 +00:00
lioncash
d63cfdbe7d
x86_64/VectorOps: Separate 128-bit VFNeg path
2022-11-16 18:46:35 +00:00
lioncash
569461a01c
x86_64/VectorOps: Separate 128-bit VNeg path
2022-11-16 18:41:16 +00:00
lioncash
37c7dee236
x86_64/VectorOps: Separate 128-bit VFRSqrt path
2022-11-16 18:35:43 +00:00
lioncash
cc230091c8
x86_64/VectorOps: Separate 128-bit VFSqrt path
2022-11-16 18:33:14 +00:00
lioncash
bac33cf246
x86_64/VectorOps: Separate 128-bit VFRecp path
2022-11-16 18:31:38 +00:00
lioncash
7a9c0506b4
x86_64/VectorOps: Separate 128-bit VFMax path
2022-11-16 18:28:31 +00:00
lioncash
fbd7c15a4b
x86_64/VectorOps: Separate 128-bit VFMin path
2022-11-16 18:27:00 +00:00
lioncash
64edf24bc7
x86_64/VectorOps: Separate 128-bit VFDiv path
2022-11-16 18:25:00 +00:00
lioncash
3f456d683f
x86_64/VectorOps: Separate 128-bit VFMul path
2022-11-16 18:23:21 +00:00
lioncash
aac0824fd3
x86_64/VectorOps: Separate 128-bit VFSub path
2022-11-16 18:21:29 +00:00
lioncash
1b32ca0b93
x86_64/VectorOps: Separate 128-bit VFAddP path
2022-11-16 18:19:13 +00:00
lioncash
c29456aac9
x86_64/VectorOps: Separate 128-bit VFAdd path
2022-11-16 18:17:23 +00:00
lioncash
715f25d059
x86_64/VectorOps: Separate 128-bit VAbs path
2022-11-16 18:13:51 +00:00
lioncash
c85e31ec7a
x86_64/VectorOps: Separate 128-bit VURAvg path
2022-11-16 18:10:53 +00:00
lioncash
0d6bfc4fa4
x86_64/VectorOps: Separate 128-bit VSQSub path
2022-11-16 18:07:59 +00:00
lioncash
106917add2
x86_64/VectorOps: Separate 128-bit VSQAdd path
2022-11-16 18:06:17 +00:00
lioncash
1e10a2bac3
x86_64/VectorOps: Separate 128-bit VUQSub path
2022-11-16 18:02:09 +00:00
lioncash
63dd09cd6f
x86_64/VectorOps: Separate 128-bit VUQAdd path
2022-11-16 17:56:37 +00:00
lioncash
c7e6935f42
x86_64/VectorOps: Separate 128-bit VSub path
2022-11-16 17:54:57 +00:00
lioncash
1be5054e86
x86_64/VectorOps: Separate 128-bit VAdd path
2022-11-16 17:51:57 +00:00
lioncash
f40755aca7
x86_64/VectorOps: Separate 128-bit VXor path
2022-11-16 17:49:25 +00:00
lioncash
d49b78cf34
x86_64/VectorOps: Separate 128-bit VOr path
2022-11-16 17:46:49 +00:00
lioncash
10e80ae064
x86_64/VectorOps: Separate 128-bit VBic path
2022-11-16 17:44:10 +00:00
lioncash
f3ebb214aa
x86_64/VectorOps: Separate 128-bit VAnd path
2022-11-16 17:40:25 +00:00
lioncash
dc41c3bd9f
x86_64/VectorOps: Separate 128-bit VectorImm path
2022-11-16 17:40:14 +00:00
lioncash
1707b27d14
OpcodeDecoder: Only install AVX ops if host supports it
2022-11-15 19:57:08 +00:00
lioncash
7c92963eca
x86_64/MemoryOps: Use unaligned loads/stores for 256-bit cases
...
Alignment will always be a little finicky in this case, so let's just
use unaligned variants to make behavior always consistent.
2022-11-15 19:57:08 +00:00
lioncash
ecf82c90ee
OpcodeDispatcher: Handle VMOVAPS
2022-11-15 19:57:05 +00:00
lioncash
580f06fe00
Frontend: Handle 256-bit vectors
2022-11-15 03:11:34 +00:00
lioncash
f7367e56af
IR: Handle 256-bit VExtr
...
Extends VExtr to handle 256-bit vectors.
2022-11-14 22:26:52 +00:00
Ryan Houdek
24696e6b98
IR: Removes the only uses of VSLI and VSRI
...
We use these two IR ops for PSRLQ and PSLLQ respectively, Which is
actually implemented in a quite inefficient way.
Instead switch the ops over to using VExtr which maps directly to one
instruction and can emulate both.
2022-11-13 19:51:31 -08:00
lioncash
c713602d56
IR: Remove VLoadMemElement and VStoreMemElement
...
These are unused, so we can get rid of them.
2022-11-11 19:06:38 +00:00
Mai
c8293cbbda
Merge pull request #2137 from Sonicadvance1/pclmul_disable
...
OpcodeDispatcher: Disable PCLMUL if not supported on host
2022-11-10 22:23:48 +00:00
lioncash
ad1d65e91a
IR: Handle 256-bit LoadRegister
...
Extends LoadRegister to handle 256-bit vectors.
2022-11-09 03:19:38 +00:00
lioncash
3a6c7803e8
IR: Handle 256-bit StoreRegister
...
Extends StoreRegister to handle 256-bit vectors.
2022-11-09 03:19:34 +00:00
lioncash
1eae07f1b8
IR: Handle 256-bit VAddV
...
Extends VAddV to handle 256-bit vectors.
2022-11-08 18:21:30 +00:00
Ryan Houdek
1ac7cd5835
OpcodeDispatcher: Disable PCLMUL if not supported on host
...
Might fix Steam on Pi4
2022-11-05 12:11:45 -07:00
Ryan Houdek
b1d98f4e58
Merge pull request #2134 from lioncash/temp
...
Arm64/ConversionOps: Eliminate use of temporary in Vector_FToF
2022-11-02 19:18:40 -07:00
Ryan Houdek
9e7daf61d0
Merge pull request #2133 from lioncash/inselem
...
IR: Handle 256-bit VInsElement
2022-11-02 18:59:18 -07:00
lioncash
6fbe25753b
IR: Handle 256-bit VInsElement
...
Extends VInsElem to handle 256-bit vectors.
2022-11-03 01:43:42 +00:00
lioncash
5536f1e835
Arm64/ConversionOps: Eliminate use of temporary in Vector_FToF
...
We can just use the destination register in this case.
2022-11-02 23:50:28 +00:00
lioncash
17722dad6d
IR: Handle 256-bit LoadContextIndexed
...
Extends LoadContextIndexed to handle 256-bit vectors.
2022-11-02 16:16:58 +00:00
lioncash