Stefanos Kornilios Mitsis Poiitidis
bf130e28a5
Merge pull request #114 from Sonicadvance1/cvtsd2si
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Implements CVTSD2SI
2020-04-13 09:57:13 +03:00
Ryan Houdek
b79083e510
Implements CVTSD2SI
2020-04-12 17:46:42 -07:00
Ryan Houdek
f74bca4fdb
Fixes a race condition in WaitForIdle
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This is something that TSAN caught was happening.
Grabs the thread creation mutex when checking for idle and extends the
sleep time for WaitForIdle to something that is still below unit test
run time
2020-04-12 17:31:11 -07:00
Stefanos Kornilios Mitsis Poiitidis
fec93ea573
Merge pull request #95 from FEX-Emu/skmp/block-cache-hotfix
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BlockCache: Remove MemoryBase logic, check full address for match
2020-04-10 13:58:04 +03:00
Stefanos Kornilios Mitsis Poiitidis
937dbd811c
BlockCache: Remove MemoryBase logic, check full address on aliased lookup
2020-04-10 13:50:09 +03:00
Ryan Houdek
30bce2468d
Remove magic numbers for invalid register class definition
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Consolidates usage of register class to the one that is defined in the
IR Json file.
Every magic number is replaced with InvalidClass and instead uses the
enums directly
Another bug fix is that the GetHostFlags IR ops was being declared as
using the flags register class, which isn't a real thing yet.
This would most likely have ended up with host flag usage being
scheduled to a GPR that was already scheduled and overwrite it.
Once this IR op ends up in host flags this will be changed as well
2020-04-10 01:02:29 -07:00
Ryan Houdek
2340e35c5b
Fixes unordered flag FCMP result on AArch64 JIT
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Was using the wrong enum
2020-04-10 01:02:20 -07:00
Ryan Houdek
17ebe1b77a
Removes ShouldDump from CMPXCHG
2020-04-10 01:02:16 -07:00
Ryan Houdek
1ee5e87275
Fixes COMIS instruction table definitions
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These instructions are always in xmm1, xmm2/mem format.
Incoming size needs to be 32bit or 64bit to be correct
2020-04-10 01:02:02 -07:00
Ryan Houdek
0766de70dd
Merge pull request #89 from Sonicadvance1/wip_pair
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CMPXCHG8B and CMPXCHG16B support
2020-04-10 00:56:26 -07:00
Ryan Houdek
eed4ff8b69
Implements support for CMPXCHG8B and CMPXCHG16B
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There are still some extraneous moves generated around the instruction,
but we need RA instruction constraints in order to safely (and cleanly)
remove them
2020-04-10 00:50:35 -07:00
Ryan Houdek
79255c2c12
Adds LLVM support for the new pair IR ops
2020-04-10 00:50:35 -07:00
Ryan Houdek
f73d82353c
Adds AArch64 support for the new pair IR ops
2020-04-10 00:50:35 -07:00
Stefanos Kornilios Mitsis Poiitidis
43ffdbdc2a
Merge pull request #96 from Sonicadvance1/remove_aes
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Remove CPUID flag saying that we support AES
2020-04-10 08:27:54 +03:00
Ryan Houdek
fdf521ff46
Remove CPUID flag saying that we support AES
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Node was found using it and we don't yet support it
All of the instructions directly map to AArch64 instructions aside from
AESKEYGENASSIST
2020-04-09 13:40:36 -07:00
Ryan Houdek
436d988168
Adds x86-64 support for the new pair IR ops
2020-04-08 00:18:36 -07:00
Ryan Houdek
980448bcf9
Adds interpreter support for the new pair IR ops
2020-04-08 00:17:54 -07:00
Ryan Houdek
88576f187c
Fixes VBitCast IR op in the x86 JIT
2020-04-06 12:25:58 -07:00
Stefanos Kornilios Mitsis Poiitidis
ba3ed680a8
Merge pull request #81 from Sonicadvance1/cvttps2dq
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Implements CVTTPS2DQ x86 instruction
2020-04-06 18:12:15 +03:00
Stefanos Kornilios Mitsis Poiitidis
e356c6d9b4
Merge pull request #84 from Sonicadvance1/fix_x86_abi
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Fixes stack alignment in x86_64 JIT
2020-04-06 18:11:28 +03:00
Stefanos Kornilios Mitsis Poiitidis
4049b30e57
Merge pull request #76 from Sonicadvance1/syscall_cleanup
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Syscall cleanup
2020-04-06 18:10:05 +03:00
Ryan Houdek
75ab768a8f
Let the AArch64 JIT support unified memory address space
2020-04-05 14:00:22 -07:00
Ryan Houdek
8c2beba584
Cleans up x86-64 syscall implementation
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Splits out to a jump table approach and loosely classifies and groups
the syscalls.
Also defines syscalls by number of arguments so it can be optimized
2020-04-05 14:00:13 -07:00
Ryan Houdek
ea4476f687
Fixes stack alignment in x86_64 JIT
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SystemV ABI mandates that the stack frame is aligned to 16bytes.
Once the call instruction happens then it is offset by 8bytes, so it is
on the callee's hands to realign the stack pointer to 16bytes.
We rely on the assumption that the stack is aligned to 16bytes for spill
slots and other function calls
2020-04-05 13:45:14 -07:00
Stefanos Kornilios Mitsis Poiitidis
227d6dc8c1
Merge pull request #83 from Sonicadvance1/unordered_ordered_compare
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Implements unordered and ordered compare IR op
2020-04-05 13:02:44 +03:00
Stefanos Kornilios Mitsis Poiitidis
133aa604a2
Merge pull request #79 from Sonicadvance1/fix_sign_extend
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Fixes bug in CBW op
2020-04-05 12:58:14 +03:00
Stefanos Kornilios Mitsis Poiitidis
aa073d9190
Merge pull request #78 from Sonicadvance1/fix_x86_fcmp
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Fixes FCMP in x86-64
2020-04-05 12:56:51 +03:00
Stefanos Kornilios Mitsis Poiitidis
234799ebde
Merge pull request #77 from Sonicadvance1/fix_x86_vector_cvt
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Use the correct float vector op for Vector_FToZS on x86
2020-04-05 12:55:11 +03:00
Ryan Houdek
840fee77b4
Implements unordered and ordered compare IR op
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Implements the remaining missed comparisons for x86's compare ops
2020-04-04 23:19:22 -07:00
Ryan Houdek
6f2726379c
Implements CVTTPS2DQ x86 instruction
2020-04-04 23:16:53 -07:00
Ryan Houdek
1e9badadd0
Fixes bug in CBW op
2020-04-04 23:11:35 -07:00
Ryan Houdek
85b75b3f12
Fixes FCMP in x86-64
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We were overwriting flags while reading from them.
Keep the flags in AX with LAHF/SAHF to be easy
2020-04-04 23:10:53 -07:00
Ryan Houdek
05fa263653
Use the correct float vector op for Vector_FToZS on x86
2020-04-04 23:09:34 -07:00
Ryan Houdek
3e398a1b9b
Pass Context to the OpDispatcher
2020-04-04 23:05:03 -07:00
Ryan Houdek
fd4fb37056
Adds a new VMOV IR op
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Both AArch64 and x86 don't have optimal paths to move <64bit FPRs to
another with ZEXT.
So this is optimal for 128bit and 64bit while smaller ops have have the
expected overhead when using it
2020-04-01 20:04:05 -07:00
Ryan Houdek
f06d6c8274
Makes MMX PMULUDQ more efficent and fixes unit test on LLVM+AArch64
2020-04-01 20:04:05 -07:00
Ryan Houdek
1a5cf0b8a3
Implements 80 new MMX instructiosn in the OpDispatcher
2020-04-01 20:04:05 -07:00
Ryan Houdek
f8b7df00b9
Fill out MMX instructions in the x86 tables
2020-04-01 20:04:05 -07:00
Ryan Houdek
7f0a98673d
Make the MMX frontend register selection use InvalidReg
2020-04-01 20:04:05 -07:00
Ryan Houdek
94c10e3518
Implement MMX register loadstores in generic helper
2020-04-01 19:53:21 -07:00
Stefanos Kornilios Mitsis Poiitidis
e6bcecf2d5
Merge pull request #73 from Sonicadvance1/push_pop_flags
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Implements push and pop flags instruction
2020-03-29 14:16:26 +03:00
Stefanos Kornilios Mitsis Poiitidis
66924cc37f
Merge pull request #72 from Sonicadvance1/new_ir_ops
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Adds new IR ops
2020-03-29 14:15:13 +03:00
Ryan Houdek
5d55f73cd2
Adds new IR ops to the LLVM JIT
2020-03-27 20:56:56 -07:00
Ryan Houdek
6f14607a82
Adds the new IR ops to the x86 JIT
2020-03-27 20:56:56 -07:00
Ryan Houdek
7c4b5c3be8
Adds to IR ops to the AArch64 JIT
2020-03-27 20:56:56 -07:00
Ryan Houdek
3cd1e0ee8f
Adds new vector ops to the interpreter
2020-03-27 20:56:56 -07:00
Ryan Houdek
a8d4d0d3c3
Adds new IR ops
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vector pairwise add
vector unsigned shift right with narrowing
vector unsigned and signed extend with lengthening from upper bits
vector unsigned and signed multiply with lengthening from upper bits
2020-03-27 20:56:56 -07:00
Ryan Houdek
65219ba4e4
Implements push and pop flags instruction
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This allows applications to push the eflags to and from the stack.
Noticed when running some GL games
2020-03-27 18:28:23 -07:00
Ryan Houdek
a97c2c8bb3
Adds MMX decoding support to the frontend
2020-03-27 18:07:57 -07:00
Stefanos Kornilios Mitsis Poiitidis
84743796a5
Merge pull request #67 from Sonicadvance1/more_cvt
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Implements two more CVT instructions
2020-03-23 00:39:59 +02:00