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Author SHA1 Message Date
Ryan Houdek 2d8b70bbd5 Merge pull request #710 from Sonicadvance1/brk_improvements 
More improvements to BRK handling
 2021-01-27 10:49:07 -08:00
Stefanos Kornilios Mitsis Poiitidis cc1000751a Merge pull request #719 from Sonicadvance1/ioctl32 
Implements ioctl32 for x86-64
 2021-01-27 20:18:11 +02:00
Stefanos Kornilios Mitsis Poiitidis f872e178ac Merge pull request #718 from Sonicadvance1/32bit_sigret_handler 
Forces SIGRET handler to the lower 32bits VA on 32bit processes
 2021-01-27 20:16:51 +02:00
Ryan Houdek a5d9e62cc6 More improvements to BRK handling 
Base size is now only one page in size. We will then increment that BRK
size by 8MB alignments. 256MB for 32bit applications was causing some
applications on the edge to run out of virtual memory
I was hitting some 32bit applications that were being fairly mean with
BRK. They were allocating all of BRK space then running out of virtual
memory space with its mmap handler fallback after freeing BRK space.

This means we now munmap BRK pages on release for the guest, similar to
behaviour that Linux does.

Additionally I had an application that was getting very upset that BRK
wasn't actually at the end of program space. So allocate at the end of
program space like expected.

brk test now passes from gvisor
 2021-01-27 10:12:25 -08:00
Stefanos Kornilios Mitsis Poiitidis ec31dc0872 Merge pull request #716 from Sonicadvance1/describe_tag 
Puts the FEX describe tag in CPUID
 2021-01-27 20:10:46 +02:00
Stefanos Kornilios Mitsis Poiitidis 4c4b797f51 Merge pull request #715 from Sonicadvance1/fix_vixl_asserts 
Fixes some asserts from vixl and a bug in ExitSpillSRA
 2021-01-27 20:09:33 +02:00
Ryan Houdek 15df787710 Implements ioctl32 for x86-64 
If you have the COMPAT feature enabled then this just works there.
AArch64 not implemented currently since changes aren't upstream
 2021-01-27 08:02:49 -08:00
Ryan Houdek 2437b89c7b Forces SIGRET handler to the lower 32bits VA on 32bit processes 
This is visible to the guest process so for 32bit it needs to be in the
lower 32bits.
 2021-01-27 07:54:30 -08:00
Ryan Houdek 5673a0e213 Puts the FEX describe tag in CPUID 
This is what shows up in /proc/cpuinfo

example on tagged release:   'model name      : FEX-2101'
example on untagged release: 'model name      : FEX-2101-64-g536be23f'

Fixes #661
 2021-01-27 07:20:14 -08:00
Ryan Houdek 3df344a78d Fixes some asserts from vixl and a bug in ExitSpillSRA 
Assembler by default doesn't allow you to use the assembler. Needs a
CodeBufferCheckScope.

Labels with binds and not links will throw an assert.
ExitSpillSRA was using b instead of bind incorrectly.
Thus branching to a invalid location
 2021-01-27 00:53:27 -08:00
Ryan Houdek f58d018934 Enables vixl asserts when in debug mode globally 
Fixes an issue where some header asserts were missed
 2021-01-27 00:52:37 -08:00
Ryan Houdek 536be23f68 Merge pull request #704 from FEX-Emu/skmp/add-gcc-target-tests 
Add gcc target tests
 2021-01-26 15:45:12 -08:00
Stefanos Kornilios Mitsis Poiitidis 8ff0b870b1 Merge pull request #712 from Sonicadvance1/fix_timers 
Fixes timer syscall API
 2021-01-26 15:33:00 +02:00
Ryan Houdek 3679156dd7 Fixes timer syscall API 
The glibc and kernel timer interfaces are sufficiently different enough
that unwrapping this through glibc is impossible.
Pass it directly through to the kernel.
 2021-01-26 05:02:44 -08:00
Stefanos Kornilios Mitsis Poiitidis 10e398a540 Merge pull request #711 from Sonicadvance1/implement_vbsl_aarch64 
Implements VBSL on AArch64
 2021-01-26 14:56:22 +02:00
Stefanos Kornilios Mitsis Poiitidis b453ede9ce Tests: Disable gcc target tests that fail only on arm 2021-01-26 14:55:35 +02:00
Ryan Houdek 6bca290611 Implements VBSL on AArch64 
This isn't quite optimal without RA constraints
 2021-01-26 03:01:48 -08:00
Stefanos Kornilios Mitsis Poiitidis dbfbfe5f0e Merge pull request #709 from Sonicadvance1/remove_boost 
Removes all references to Boost
 2021-01-26 12:40:43 +02:00
Stefanos Kornilios Mitsis Poiitidis 25bfab25da CI: Disable gcc target tests for x86-32 2021-01-26 12:37:07 +02:00
Ryan Houdek cab317e2f0 Removes all references to Boost 
We don't require this
Fixes #699
 2021-01-26 02:34:26 -08:00
Ryan Houdek 4d98c890e7 Merge pull request #708 from Sonicadvance1/decode_tsx 
Add TSX names to decode tables so we know what they are
 2021-01-26 02:24:47 -08:00
Ryan Houdek 513cb27825 Add TSX names to decode tables so we know what they are 
Rather than just stating UND

We can't support this until we have an ARM CPU that supports TME and
more robust multiblock.
 2021-01-26 02:03:42 -08:00
Stefanos Kornilios Mitsis Poiitidis 29a8fd0a4a Tests: Add gcc-target-tests for 32 and 64 bit 2021-01-26 12:00:45 +02:00
Stefanos Kornilios Mitsis Poiitidis e466dfb480 Merge pull request #707 from Sonicadvance1/update_gvisor_tests 
Updates gvisor test results that have changed due to OS update
 2021-01-26 11:59:38 +02:00
Ryan Houdek 8cbfef2e74 Updates gvisor test results that have changed due to OS update 2021-01-26 01:11:40 -08:00
Stefanos Kornilios Mitsis Poiitidis 53582fdf47 Merge pull request #701 from FEX-Emu/skmp/opdisp-32-bit-fixes 
OpDisp: Address most 32-bit rip size issues
 2021-01-25 15:31:55 +02:00
Stefanos Kornilios Mitsis Poiitidis b0365871b6 OpDisp: Address most 32-bit rip size issues 2021-01-25 15:04:12 +02:00
Ryan Houdek 2721418fb7 Merge pull request #698 from phire/better_defaults 
Better Default Configuration
 2021-01-22 16:56:29 -08:00
Scott Mansell 3cae0a0932 Better Default Configuration 
Make FEX have good performance out of the box

resolves #685
 2021-01-23 13:47:53 +13:00
Ryan Houdek d4ffea5c31 Merge pull request #670 from FEX-Emu/skmp/faster-ra 
IR: Optimize runtime of optimization passes
 2021-01-22 04:54:08 -08:00
Stefanos Kornilios Mitsis Poiitidis 0546da7a75 Address review feedback 2021-01-22 11:01:36 +02:00
Ryan Houdek ce1b9fcdc9 Merge pull request #674 from FEX-Emu/skmp/split-irparser 
IR: Split parser from IRLoader, add IR::Parse(), Fixes, Tests
 2021-01-21 23:09:53 -08:00
Stefanos Kornilios Mitsis Poiitidis 8b025d4c26 IRLoader: Actually set EntryRIP if the IR was parsed 2021-01-21 22:19:16 +02:00
Stefanos Kornilios Mitsis Poiitidis e7f2a650b5 Fix compilation 2021-01-21 22:18:48 +02:00
Stefanos Kornilios Mitsis Poiitidis 3bd8731b26 IR: Add CONFIG_VALIDATE_IR_PARSER, enable it on TestHarnessRunner 2021-01-21 21:38:41 +02:00
Stefanos Kornilios Mitsis Poiitidis 13613c6de1 IR: Change ValidateCode to use two uint64_t instead of __uint128_t 2021-01-21 21:37:58 +02:00
Stefanos Kornilios Mitsis Poiitidis 1177c375ff IR: Further parser cleanups, add fence types 2021-01-21 21:17:27 +02:00
Stefanos Kornilios Mitsis Poiitidis fb57e5183a IR: Fix TypeDefinition to actually fit used vector sizes 2021-01-21 21:10:11 +02:00
Stefanos Kornilios Mitsis Poiitidis 74160f38c4 IR: Fix IREmitter::Copy 2021-01-21 21:01:27 +02:00
Stefanos Kornilios Mitsis Poiitidis 072067b5fd IR: Split parser from IRLoader, add IR::Parse() 2021-01-21 19:17:51 +02:00
Stefanos Kornilios Mitsis Poiitidis 773e5866b4 Merge pull request #666 from Sonicadvance1/handle_unaligned_caspal32 
Handle unaligned cmpxchg and cmpxchg8b on ARMv8.1+
 2021-01-21 13:30:18 +02:00
Stefanos Kornilios Mitsis Poiitidis 00ca576644 IRCompaction: Only memset in debug 2021-01-21 13:06:43 +02:00
Ryan Houdek 5226f779c3 Merge pull request #673 from FEX-Emu/skmp/fix-ir-printing 
IR: Fix Printing and Parsing for float conds
 2021-01-21 00:28:50 -08:00
Stefanos Kornilios Mitsis Poiitidis 036771d825 IR: Fix Printing and Parsing for float conds 2021-01-21 10:16:08 +02:00
Ryan Houdek 633ea045e5 Handles unaligned cmpxchg/cmpxchg8b in SIGBUS handler 
cmpxchg/cmpxchg8b doesn't have alignment requirements on x86, which means
applications rely on unaligned behaviour support with it.

Steam relies on this to work for a linked list array of jobs in some
internal job queueing system. It will end up always aligning by offsets
of 4 since it stores a couple of pointers.

Doesn't currently support the case of unaligned cmpxchg8b crossing a
cacheline, which ends up being semi-broken depending on which x86
behaviour the application is expected.
Intel CPUs do the "Big ring lock" or "split locks". Which means accesses
across cachelines are atomic.
AMD CPUs will tear the value across the cacheline, which is expected x86
behaviour by spec.

If they are expecting Intel behaviour, then that application is just
broken on non-Intel platforms unless they are fine with a tear.
 2021-01-20 16:07:50 -08:00
Stefanos Kornilios Mitsis Poiitidis 0e7db64ac7 RA: Run compation after spilling, not before 2021-01-21 01:01:02 +02:00
Stefanos Kornilios Mitsis Poiitidis ac1036ac92 IR: Sync Invalid class with RA 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 9c462eb400 ConsProp: Revert to ordered set for identical codegen 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 8aef9cb6a7 RA: Exit after first spill per iteration is found 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis d3fc85e18d RA: Make spans at least 1 offset long 2021-01-20 04:26:06 +02:00