steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-25 17:00:46 +01:00
Code Issues Packages Projects Releases 67 Wiki Activity
547 Commits 11 Branches 71 Tags
39b11cfc2ef0e686bae99b1e171c14babbfe191d
Commit Graph
159 Commits
Author SHA1 Message Date
Ryan Houdek eed4ff8b69 Implements support for CMPXCHG8B and CMPXCHG16B 
There are still some extraneous moves generated around the instruction,
but we need RA instruction constraints in order to safely (and cleanly)
remove them
 2020-04-10 00:50:35 -07:00
Ryan Houdek 79255c2c12 Adds LLVM support for the new pair IR ops 2020-04-10 00:50:35 -07:00
Ryan Houdek f73d82353c Adds AArch64 support for the new pair IR ops 2020-04-10 00:50:35 -07:00
Ryan Houdek 436d988168 Adds x86-64 support for the new pair IR ops 2020-04-08 00:18:36 -07:00
Ryan Houdek 980448bcf9 Adds interpreter support for the new pair IR ops 2020-04-08 00:17:54 -07:00
Stefanos Kornilios Mitsis Poiitidis ba3ed680a8 Merge pull request #81 from Sonicadvance1/cvttps2dq 
Implements CVTTPS2DQ x86 instruction
 2020-04-06 18:12:15 +03:00
Stefanos Kornilios Mitsis Poiitidis e356c6d9b4 Merge pull request #84 from Sonicadvance1/fix_x86_abi 
Fixes stack alignment in x86_64 JIT
 2020-04-06 18:11:28 +03:00
Stefanos Kornilios Mitsis Poiitidis 4049b30e57 Merge pull request #76 from Sonicadvance1/syscall_cleanup 
Syscall cleanup
 2020-04-06 18:10:05 +03:00
Ryan Houdek 75ab768a8f Let the AArch64 JIT support unified memory address space 2020-04-05 14:00:22 -07:00
Ryan Houdek 8c2beba584 Cleans up x86-64 syscall implementation 
Splits out to a jump table approach and loosely classifies and groups
the syscalls.

Also defines syscalls by number of arguments so it can be optimized
 2020-04-05 14:00:13 -07:00
Ryan Houdek ea4476f687 Fixes stack alignment in x86_64 JIT 
SystemV ABI mandates that the stack frame is aligned to 16bytes.
Once the call instruction happens then it is offset by 8bytes, so it is
on the callee's hands to realign the stack pointer to 16bytes.
We rely on the assumption that the stack is aligned to 16bytes for spill
slots and other function calls
 2020-04-05 13:45:14 -07:00
Stefanos Kornilios Mitsis Poiitidis 227d6dc8c1 Merge pull request #83 from Sonicadvance1/unordered_ordered_compare 
Implements unordered and ordered compare IR op
 2020-04-05 13:02:44 +03:00
Stefanos Kornilios Mitsis Poiitidis 133aa604a2 Merge pull request #79 from Sonicadvance1/fix_sign_extend 
Fixes bug in CBW op
 2020-04-05 12:58:14 +03:00
Stefanos Kornilios Mitsis Poiitidis aa073d9190 Merge pull request #78 from Sonicadvance1/fix_x86_fcmp 
Fixes FCMP in x86-64
 2020-04-05 12:56:51 +03:00
Stefanos Kornilios Mitsis Poiitidis 234799ebde Merge pull request #77 from Sonicadvance1/fix_x86_vector_cvt 
Use the correct float vector op for Vector_FToZS on x86
 2020-04-05 12:55:11 +03:00
Ryan Houdek 840fee77b4 Implements unordered and ordered compare IR op 
Implements the remaining missed comparisons for x86's compare ops
 2020-04-04 23:19:22 -07:00
Ryan Houdek 6f2726379c Implements CVTTPS2DQ x86 instruction 2020-04-04 23:16:53 -07:00
Ryan Houdek 1e9badadd0 Fixes bug in CBW op 2020-04-04 23:11:35 -07:00
Ryan Houdek 85b75b3f12 Fixes FCMP in x86-64 
We were overwriting flags while reading from them.
Keep the flags in AX with LAHF/SAHF to be easy
 2020-04-04 23:10:53 -07:00
Ryan Houdek 05fa263653 Use the correct float vector op for Vector_FToZS on x86 2020-04-04 23:09:34 -07:00
Ryan Houdek 3e398a1b9b Pass Context to the OpDispatcher 2020-04-04 23:05:03 -07:00
Ryan Houdek fd4fb37056 Adds a new VMOV IR op 
Both AArch64 and x86 don't have optimal paths to move <64bit FPRs to
another with ZEXT.
So this is optimal for 128bit and 64bit while smaller ops have have the
expected overhead when using it
 2020-04-01 20:04:05 -07:00
Ryan Houdek f06d6c8274 Makes MMX PMULUDQ more efficent and fixes unit test on LLVM+AArch64 2020-04-01 20:04:05 -07:00
Ryan Houdek 1a5cf0b8a3 Implements 80 new MMX instructiosn in the OpDispatcher 2020-04-01 20:04:05 -07:00
Ryan Houdek f8b7df00b9 Fill out MMX instructions in the x86 tables 2020-04-01 20:04:05 -07:00
Ryan Houdek 7f0a98673d Make the MMX frontend register selection use InvalidReg 2020-04-01 20:04:05 -07:00
Ryan Houdek 94c10e3518 Implement MMX register loadstores in generic helper 2020-04-01 19:53:21 -07:00
Stefanos Kornilios Mitsis Poiitidis e6bcecf2d5 Merge pull request #73 from Sonicadvance1/push_pop_flags 
Implements push and pop flags instruction
 2020-03-29 14:16:26 +03:00
Stefanos Kornilios Mitsis Poiitidis 66924cc37f Merge pull request #72 from Sonicadvance1/new_ir_ops 
Adds new IR ops
 2020-03-29 14:15:13 +03:00
Ryan Houdek 5d55f73cd2 Adds new IR ops to the LLVM JIT 2020-03-27 20:56:56 -07:00
Ryan Houdek 6f14607a82 Adds the new IR ops to the x86 JIT 2020-03-27 20:56:56 -07:00
Ryan Houdek 7c4b5c3be8 Adds to IR ops to the AArch64 JIT 2020-03-27 20:56:56 -07:00
Ryan Houdek 3cd1e0ee8f Adds new vector ops to the interpreter 2020-03-27 20:56:56 -07:00
Ryan Houdek a8d4d0d3c3 Adds new IR ops 
vector pairwise add
vector unsigned shift right with narrowing
vector unsigned and signed extend with lengthening from upper bits
vector unsigned and signed multiply with lengthening from upper bits
 2020-03-27 20:56:56 -07:00
Ryan Houdek 65219ba4e4 Implements push and pop flags instruction 
This allows applications to push the eflags to and from the stack.
Noticed when running some GL games
 2020-03-27 18:28:23 -07:00
Ryan Houdek a97c2c8bb3 Adds MMX decoding support to the frontend 2020-03-27 18:07:57 -07:00
Stefanos Kornilios Mitsis Poiitidis 84743796a5 Merge pull request #67 from Sonicadvance1/more_cvt 
Implements two more CVT instructions
 2020-03-23 00:39:59 +02:00
Stefanos Kornilios Mitsis Poiitidis d0667452e6 Merge pull request #66 from Sonicadvance1/pmul 
Implements PMULLW
 2020-03-23 00:39:49 +02:00
Ryan Houdek 33e68cf0c4 Implements PADDB in OpDispatcher 2020-03-22 13:07:25 -07:00
Ryan Houdek eeebfeaec1 Implements two more CVT instructions 
CCVTSS2SI and CVTTPD2DQ
 2020-03-22 13:03:34 -07:00
Ryan Houdek ad71b4de94 Implements PMULLW in OpDispatcher 
Renames the PMULL function that does PMUL to larger element to have the distinction between the two
 2020-03-22 13:00:36 -07:00
Ryan Houdek f4dc6ee1ce Adds vector multiply op to LLVM JIT 2020-03-22 13:00:36 -07:00
Stefanos Kornilios Mitsis Poiitidis 013ac22744 Merge pull request #62 from Sonicadvance1/vector_mul 
Implement vector integer multiply IR ops
 2020-03-22 09:01:35 +02:00
Stefanos Kornilios Mitsis Poiitidis 7930712ef2 Merge pull request #63 from Sonicadvance1/vector_ftozs 
Implements Vector_FTOZS op in x86 JIT
 2020-03-22 09:01:21 +02:00
Stefanos Kornilios Mitsis Poiitidis 7989a22802 Merge pull request #53 from Sonicadvance1/fix_flag_setting 
Implements and fixes flag setting in a few instructions
 2020-03-22 09:01:08 +02:00
Ryan Houdek f89ef01578 Implements the COMISS instructions 
These are fairly popular so not having them around is causing headaches.
We will really want these in the future to use the host register, btu
that is more time consuming than I want to dedicate to at the moment.

So the FCMP instruction must be told which flags to generate up front,
then it generates the flags in to a GPR which are then tracked and
pulled out with a specific IR op.

This can be augmented in the future to more easily RA the host flag
register
 2020-03-21 22:52:46 -07:00
Ryan Houdek c94102051c Implements Vector_FTOZS op in x86 JIT 2020-03-21 20:58:53 -07:00
Ryan Houdek 2133a1755d Implement vector integer multiply IR ops 2020-03-21 20:56:54 -07:00
Ryan Houdek b93848c343 Removes sarx usage in the x86 JIT 2020-03-21 12:44:27 -07:00
Stefanos Kornilios Mitsis Poiitidis f9b7eff7c6 Merge pull request #58 from Sonicadvance1/instruction_fixes 
Fixes for SQRTPD, SQRTPS, RSQRTPS
 2020-03-21 09:31:00 +02:00