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5,853 Commits 11 Branches 71 Tags
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Commit Graph
2243 Commits
Author SHA1 Message Date
Lioncache 6eeafd0724 ARMEmitter: Handle predicated wide shifts 2023-02-09 01:58:23 -05:00
Ryan Houdek e6fc159d88 Merge pull request #2390 from lioncash/ext 
OpcodeDispatcher: Handle VEXTRACTF128/VEXTRACTI128
 2023-02-08 22:04:22 -08:00
Ryan Houdek 5fd68b6f07 Merge pull request #2392 from lioncash/wide 
ARMEmitter: Handle unpredicated wide shifts and unpredicated shifts by immediates
 2023-02-08 21:52:23 -08:00
Lioncache 5f80702cf1 ARMEmitter: Handle unpredicated bitwise shift by immediate 2023-02-09 00:15:35 -05:00
Lioncache b45b980b3a ARMEmitter: Handle unpredicated shifts by wide elements 2023-02-09 00:00:17 -05:00
Mai 143ef57141 Merge pull request #2345 from Sonicadvance1/user_sigreturn 
Support user supplied signal restorer.
 2023-02-08 20:11:47 -05:00
Lioncache 0218c966bd IR: Allow specifying register size for PCLMUL 
This will allow us to support 256-bit vector operation in the future.
 2023-02-08 16:35:20 -05:00
Lioncache ec5bc9cf3e IR: Allow specifying register sizes for AES enc/dec ops 
This will allow us to support operating on 256-bit vectors.

Currently only sets up the bits and pieces on the x86-64 side, since
facilities for testing the 256-bit operations on ARM isn't set up yet.
 2023-02-08 16:25:19 -05:00
Lioncache 63bf0d5826 OpcodeDispatcher: Handle VEXTRACTI128 2023-02-08 15:46:27 -05:00
Lioncache 2526fa8b6f OpcodeDispatcher: Handle VEXTRACTF128 2023-02-08 15:40:36 -05:00
Lioncache d7c6ed842d Arm64/VectorOps: Use movprfx with VBSL 
We can use movprfx here to allow compressing the move and bsl operation
together on cpus that can handle it.
 2023-02-07 00:44:08 -05:00
Lioncache 7a75e43125 VectorOps: Only use VBSL 256-bit path if SVE is present 
With this in place, a _VMov isn't necessary for variable blends anymore,
since the vector upper lanes are guaranteed to be zeroed out in the 128-bit case.
 2023-02-07 00:13:04 -05:00
Lioncache 88fee019a1 OpcodeDispatcher: Handle VPBLENDVB 2023-02-06 23:04:26 -05:00
Lioncache 5d3141dffc OpcodeDispatcher: Handle VBLENDVPD 2023-02-06 23:04:26 -05:00
Lioncache 94e91565b1 OpcodeDispatcher: Handle VBLENDVPS 2023-02-06 23:04:26 -05:00
Lioncache acbfee55b4 IR: Allow provising register size for VBSL 
Necessary, since this will now be used with both 256-bit and 128-bit
registers, rather than just 128-bit.
 2023-02-06 23:04:26 -05:00
Lioncache a2481d6892 OpcodeDispatcher: Add helper for AVX variable blends 
These will be used by following instruction implementations.
 2023-02-06 23:04:26 -05:00
Ryan Houdek e255f1cdef Merge pull request #2383 from lioncash/blend 
OpcodeDispatcher: Handle VBLENDPD/VPBLENDW
 2023-02-06 18:55:31 -08:00
Ryan Houdek cb3cfed9c2 Merge pull request #2384 from lioncash/sqadd 
ARMEmitter: Handle SVE2 saturating add/subtract category
 2023-02-06 18:55:23 -08:00
Lioncache 2b12a46d2d ARMEmitter: Handle UQSUBR 2023-02-06 21:29:10 -05:00
Lioncache 8f50109501 ARMEmitter: Handle SQSUBR 2023-02-06 21:29:10 -05:00
Lioncache 1d451b8df1 ARMEmitter: Handle USQADD 2023-02-06 21:29:10 -05:00
Lioncache 49772c6826 ARMEmitter: Handle SUQADD 2023-02-06 21:29:10 -05:00
Lioncache 535a2ab2ba ARMEmitter: Handle UQSUB (vectors, predicated) 2023-02-06 21:29:10 -05:00
Lioncache b8b212719f ARMEmitter: Handle SQSUB (vectors, predicated) 2023-02-06 21:29:10 -05:00
Lioncache be593d43ce ARMEmitter: Handle UQADD (vectors, predicated) 2023-02-06 21:29:10 -05:00
Lioncache a89b7c5dbb ARMEmitter: Handle SQADD (vectors, predicated) 2023-02-06 21:29:07 -05:00
Lioncache c682f51811 OpcodeDispatcher: Handle VPBLENDW 2023-02-06 21:23:30 -05:00
Lioncache 2c7562c54c OpcodeDispatcher: Handle VBLENDPD 2023-02-06 21:03:54 -05:00
Lioncache 8f5ec20cb7 OpcodeDispatcher: Add helper for AVX vector blends 2023-02-06 20:38:35 -05:00
Lioncache 79abe2aa64 ARMEmitter: Simplify bitwise shift by immediate (predicated) category 
Centralizes the immediate handling in the encoding helper function.

Lets us move all the asserts there as well.
 2023-02-06 20:03:21 -05:00
Lioncache 9f3857b3b0 ARMEmitter: Simplify saturating extract narrow category 
Centralizes the immediate handling in the encoding function.
 2023-02-06 19:21:42 -05:00
Lioncache 9521638910 ARMEmitter: Simplify bitwise shift right narrow category 
Centralizes the immediate handling in one place, making everything much
shorter.
 2023-02-06 19:21:39 -05:00
Mai 60b76f53cf Merge pull request #2381 from Sonicadvance1/code_data_header 
JIT: Adds a JIT data header and tail.
 2023-02-06 18:07:20 -05:00
Mai 5da90aac46 Merge pull request #2378 from Sonicadvance1/fix_emitter_warnings 
ARMEmitter: Fixes some warnings that cropped up.
 2023-02-06 18:05:56 -05:00
Ryan Houdek ba5ad72ca2 JIT: Adds a JIT data header and tail. 
This will be used to store various bits of data about the code going
forward.

Currently unused but that will change as we move forward.
 2023-02-06 14:06:37 -08:00
Mai c7c47a827a Merge pull request #2377 from Sonicadvance1/code_data_support 
Core: Support Data in JIT buffer header
 2023-02-06 16:54:01 -05:00
Ryan Houdek 37421d36e6 ARMEmitter: Fixes some warnings that cropped up. 2023-02-05 18:06:29 -08:00
Ryan Houdek bd86deb9ba Core: Support Data in JIT buffer header 
Currently unused (The full data gets thrown away after CompileCode is
called), but allows us to separate code and data in what `CompileCode`
returns.

This will allow us put a header on JIT blocks which will fix a long
outstanding bug where RIP isn't always synchronized on block entry, but
since it only needs to synchronize on signal we can rebuild in the
handler. This future task will remove the `86dec_SynchronizeRIPOnAllBlocks`
config option, but the data will also end up being used for more things
in the future.
 2023-02-05 17:55:31 -08:00
Ryan Houdek 2e701fc9e6 Dispatcher: Minor flags optimization 
SelectCC shift wasn't necessary since we just need to ensure the final
result is zero when or'd together.

Also operations calculating SF can just use a BFE instead of a shifts
with a constant. BFE by immediate is more efficiently encoded in our IR.
 2023-02-04 17:50:36 -08:00
Ryan Houdek 844e27e9ad X86HelperGen: Support fallback sigreturn helpers 
For the case that the 32-bit VDSO thunk library isn't available, have a
fallback that can work as well.
Otherwise 32-bit applications will just straight up crash on signal
return.
 2023-02-04 10:54:30 -08:00
Ryan Houdek c58e7a732e X86HelperGen: Remove now unused sigret codegen 
This is no longer used so doesn't need to exist.
 2023-02-04 10:35:07 -08:00
Ryan Houdek 0538574dd0 Dispatcher: Supports user provided signal restorer 
This is required for backtrace to work correctly.
If we are using our custom instruction for returning from a signal, then
backtrace tries to read PC for the sigreturn code and finds our code,
breaking it.

Instead we now /correctly/ support using rt_sigreturn/sigreturn and the
restorer provided from the user.
To facilitate this, we now store a single 64-bit value on the stack to
return our host stack pointer to the correct location from before the
signal.
With cookie checking in place, we can know if an application betrays our
expectations and tries to pass its own signal frames.
If an application in the future /does/ try to pass its own signal
frames, that's unsafe and we cna deal with it then.
 2023-02-04 10:35:07 -08:00
Ryan Houdek abc596c634 IR: Removes SignalReturn op 
This will no longer be used as we are swithing over to using the Linux
system call directly.
 2023-02-04 10:35:06 -08:00
Ryan Houdek d107bc9a24 FEXCore: Adds handlers for signal handler returns 
Lets the frontend syscall handlers for signal return call the JIT return
handlers directly.
 2023-02-04 10:35:06 -08:00
Ryan Houdek a45047bc1e OpDispatcher: Removes SIGRET x86 instruction 
We are switching over to syscalls.
 2023-02-04 10:35:06 -08:00
Lioncache 6522d3d6e4 ARMEmitter: Move 128-bit check into SVE2IntegerMultiplyVectors 
Simplifies the amount of code needed. Also we can remove some
unnecessary namespacing to make these a little faster to grok when
looking at them.
 2023-02-04 05:08:43 -05:00
Lioncache d65fcf7bb8 ARMEmitter: Handle SVE SQRDMULH (vectors) 2023-02-04 05:06:56 -05:00
Lioncache 16e0f628cd ARMEmitter: Handle SVE SQDMULH (vectors) 2023-02-04 05:05:27 -05:00
Lioncache 75bc997ab7 ARMEmitter: Handle RDVL 2023-02-04 01:11:57 -05:00