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ARMEmitter: Handle SVE SQRDMULH (vectors)

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Lioncache committed 2023-02-04 05:06:56 -05:00
1 parent 16e0f628cd
commit d65fcf7bb8
2 files changed
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External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl
Vendored
+3
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@@ -1403,6 +1403,9 @@ public:
void sqdmulh(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
SVE2IntegerMultiplyVectors(0b100, size, zm, zn, zd);
}
void sqrdmulh(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
SVE2IntegerMultiplyVectors(0b101, size, zm, zn, zd);
}
// SVE Bitwise Shift - Unpredicated
// SVE bitwise shift by wide elements (unpredicated)
External/FEXCore/unittests/Emitter/SVE_Tests.cpp
Vendored
+5
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@@ -933,6 +933,11 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 signed saturating doublin
TEST_SINGLE(sqdmulh(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqdmulh z30.h, z29.h, z28.h");
TEST_SINGLE(sqdmulh(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqdmulh z30.s, z29.s, z28.s");
TEST_SINGLE(sqdmulh(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqdmulh z30.d, z29.d, z28.d");
TEST_SINGLE(sqrdmulh(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqrdmulh z30.b, z29.b, z28.b");
TEST_SINGLE(sqrdmulh(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqrdmulh z30.h, z29.h, z28.h");
TEST_SINGLE(sqrdmulh(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqrdmulh z30.s, z29.s, z28.s");
TEST_SINGLE(sqrdmulh(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqrdmulh z30.d, z29.d, z28.d");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise shift by wide elements (unpredicated)") {