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Code Issues Packages Projects Releases 67 Wiki Activity
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Author SHA1 Message Date
Ryan Houdek 91229c8ea2 Implements new VTBL1 IR op in x86 JIT 2020-09-26 12:59:34 -07:00
Ryan Houdek 59bffc7431 Implements new VTBL1 instruction in AArch64 JIT 2020-09-26 12:59:34 -07:00
Ryan Houdek a5f6a5b26e Implements new VTBL1 op in the interpreter 2020-09-26 12:59:34 -07:00
Ryan Houdek 83ac23be21 Implements new VTBL1 IR op 
This perfectly matches the AArch64 variant and almost perfectly matches
x86's pshufb instruction
 2020-09-26 12:59:34 -07:00
Ryan Houdek e1560bd68b Merge pull request #431 from Sonicadvance1/palignr 
Implements MMX register based palignr
 2020-09-26 12:59:10 -07:00
Ryan Houdek 3465021721 Implements a MMX palignr unit test 2020-09-26 12:53:51 -07:00
Ryan Houdek 55077cfa55 Implements MMX register based palignr 
We had already implemented the XMM variant
 2020-09-26 12:53:51 -07:00
Ryan Houdek 9cdd0c4776 Fixes an edge case in our palignr implementation 
When the shift amount is greater than the size of both the registers
then it'll set the resulting register to zero
 2020-09-26 12:53:51 -07:00
Ryan Houdek 12a4dd6d2d Fixes VExtr in the ARM64 JIT for 8byte registers 
We only expected 16byte registers before
 2020-09-26 12:52:26 -07:00
Ryan Houdek bd37d007c9 Fixes 64bit register usage in VExtr on x86_64 
We would need to fall back to MMX if we wanted to handle that cleanly
there.
Just emulate instead of using MMX
 2020-09-26 12:52:26 -07:00
Ryan Houdek a11aed2f47 Removes some undefined behaviour in the interpreter VExtr implementation 2020-09-26 12:52:26 -07:00
Ryan Houdek ddd7b8f406 Adds a mixxing VXor op to the IREmitter helper 2020-09-26 12:52:26 -07:00
Ryan Houdek 5b96dd04f0 Updates XMM PAlignr test to test more cases 
One larger than the first register, then another that would zero
everything
 2020-09-26 12:52:02 -07:00
Ryan Houdek d8d50e8200 Merge pull request #430 from Sonicadvance1/pabs 
Implements support for SSSE3 PABS{B,W,D}
 2020-09-26 12:51:10 -07:00
Ryan Houdek e09a9fb651 Adds XMM register PABS unit tests 
verified with host runner
 2020-09-26 12:47:01 -07:00
Ryan Houdek 854c2f259a Adds MMX register PABS unit tests 
verified with host runner
 2020-09-26 12:47:01 -07:00
Ryan Houdek ec06806244 Implements support for SSSE3 PABS{B,W,D} 
For both MMX and XMM registers
 2020-09-26 12:47:01 -07:00
Stefanos Kornilios Mitsis Poiitidis 83db01f505 Merge pull request #429 from Sonicadvance1/psign 
Implements support for SSSE3 PSIGN{B,W,D}
 2020-09-26 20:20:06 +03:00
Stefanos Kornilios Mitsis Poiitidis de62124b95 Merge pull request #428 from Sonicadvance1/lzcnt 
Implements ABM's LZCNT instruction
 2020-09-26 20:11:47 +03:00
Stefanos Kornilios Mitsis Poiitidis ca676e324d Merge pull request #427 from Sonicadvance1/duplicated_ops 
Implements the couple of duplicated ops
 2020-09-26 20:09:58 +03:00
Stefanos Kornilios Mitsis Poiitidis 5cb3a9df9d Merge pull request #426 from Sonicadvance1/addsub 
Implements ADDSUB{PS, PD}
 2020-09-26 20:09:48 +03:00
Stefanos Kornilios Mitsis Poiitidis cf6b07fc16 Merge pull request #425 from Sonicadvance1/remove_direct_widening_use 
Removes some direct usage of widening flag
 2020-09-26 20:09:35 +03:00
Stefanos Kornilios Mitsis Poiitidis 1f24fefdff Merge pull request #422 from Sonicadvance1/host_runner_enable 
Adds and enables the x86 host runner when building on x86 host!
 2020-09-26 20:09:15 +03:00
Ryan Houdek 42c6eacfc5 Adds and enables the x86 host runner when building on x86 host! 
Disables the thunking unit test on host because obviously it won't work
there

Also disables the SSE4a unit tests on host because Intel doesn't support
SSE4a and technically neither does FEX
 2020-09-25 21:17:54 -07:00
Ryan Houdek 7c14619346 Support disabling ASM and IR tests per runner type 
Allows us to disable specific tests for interpreter, jit, or host.
No architecture specific disabling yet
 2020-09-25 21:17:54 -07:00
Stefanos Kornilios Mitsis Poiitidis 8662fb0db7 Merge pull request #424 from Sonicadvance1/mmx_cvt 
Implements missing mmx conversion ops
 2020-09-25 18:21:16 +03:00
Stefanos Kornilios Mitsis Poiitidis e145876898 Merge pull request #404 from Sonicadvance1/x87_bcd 
Adds support for BCD x87 intructions
 2020-09-25 18:07:49 +03:00
Ryan Houdek f9cf8344e8 Adds MMX register PSIGN unit tests 
verified with host runner
 2020-09-24 19:46:39 -07:00
Ryan Houdek 5c339d605e Adds XMM register PSIGN unit tests 
verified with host runner
 2020-09-24 19:46:15 -07:00
Ryan Houdek faa06771ef Implements support for SSSE3 PSIGN{B,W,D} 
For both MMX and XMM registers
 2020-09-24 19:45:39 -07:00
Ryan Houdek b68832f31b Adds the IR ops to the IREmitter helper 2020-09-24 19:45:17 -07:00
Ryan Houdek 7c73920a2c Implements the new IR ops in the x86-64 JIT 2020-09-24 19:44:55 -07:00
Ryan Houdek 6254d15f02 Implements the new IR ops in the ARM64 JIT 2020-09-24 19:36:15 -07:00
Ryan Houdek 2079e3ca31 Implements the new IR ops in the interpreter 2020-09-24 19:35:18 -07:00
Ryan Houdek c6385093eb Adds a few new IR ops 
VectorZero, useful to generate a zero vector without any previous
dependencies

and comparisons with zero which ARM supports faster versions of
 2020-09-24 19:34:19 -07:00
Ryan Houdek 04d2d70e51 Implements LZCNT unit test 
Verified correct with the hsot unit test runner
 2020-09-23 22:35:32 -07:00
Ryan Houdek 84936e6297 Implements ABM's LZCNT instruction 
This overlaps the previous BSR instruction which is why the table had to
be changed.

We were accidently claiming support for ABM in CPUID before so that
didn't need to be changed.

We now implement both LZCNT and TZCNT so we fully support ABM now.
 2020-09-23 22:35:32 -07:00
Ryan Houdek 697df88314 Implements the new CLZ IR op in the x86 JIT 2020-09-23 22:14:56 -07:00
Ryan Houdek 47c3fdafd7 Implements the new CLZ op in the ARM64 JIT 2020-09-23 22:14:36 -07:00
Ryan Houdek 935deb0167 Implements new CLZ op in the interpreter 2020-09-23 22:14:15 -07:00
Ryan Houdek 479505b069 Implements new CountLeadingZeroes IR op 2020-09-23 22:13:28 -07:00
Ryan Houdek c72d50a9c6 Implements the couple of duplicated ops 
SAL is exactly the same as SHL
TEST is exactly the same as the previous TESTs
Bit silly of encodings since compilers will never actually generate
these

No unit tests on these since getting nasm to emit it is a PITA
 2020-09-23 18:56:26 -07:00
Ryan Houdek 61f1d28077 Implements ADDSUB{PS, PD} unit tests 
Verified with the host runner
 2020-09-23 18:09:02 -07:00
Ryan Houdek ae3c38e9e5 Implements ADDSUB{PS, PD} in the OpDispatcher 2020-09-23 18:08:19 -07:00
Ryan Houdek 09ee71b8c3 Adds missing VFSub IREmitter function 2020-09-23 18:07:53 -07:00
Ryan Houdek e238afe2fb Removes some direct usage of widening flag 
Instead use our helpers to determine the sizes to stay consistent
 2020-09-23 17:30:43 -07:00
Ryan Houdek b0065435e2 Missing MMX conversion ops unit tests 2020-09-23 17:21:01 -07:00
Ryan Houdek 35798c8d9d Implements missing mmx conversion ops 2020-09-23 17:21:01 -07:00
Stefanos Kornilios Mitsis Poiitidis d5d0899d5f Merge pull request #421 from Sonicadvance1/fix_mov_mem_offset 
Fixes move with mem offset
 2020-09-23 21:11:16 +03:00
Ryan Houdek 811e956df5 Fixes move memoffset tests to have address size override prefix 
Required for the 32bit literal offset
 2020-09-23 10:43:20 -07:00