There are a significant number of changes here that I don't really
expect much review on.
Adds a bunch of new features and allows us to support GDB, IDA, and
Binja through their remote GDB debugging facilities.
Ghidra may also work but I haven't tried.
This work isn't quite yet complete to do correct thread stepping yet. We
need to add support for stopping threads using signals since threads may
be stuck inside of a syscall.
I have a hack locally that tries pausing all threads and times out after
a few seconds which works well enough for local testing.
Add and substract were the main culprits here.
We are trying to more towards a state where:
* Every IR op can expect it isn't given extra bits
on it's input
* Every IR op never sets more bits than it's size
* All unnessicary BFEs are never emitted
* ARM doesn't have to implement special 8 and 16bit versions of IR ops
All masking required to implement 8/16bit math on
arm should be explictly generated from Opcode decoder
Any time a guest signal is blocked, add it to the guest signal mask.
This doesn't use a signal queue so repeat signals can end up being lost.
This is expected behaviour
This doesn't help with implementing the problem of unblocking signals
causing the masked signal to be resent
Bunch of templated instructions that didn't need to be templated.
Removes a bunch of duplicate entries.
Saves a couple hundred kilobytes on the final file
When RA made the source address register be the same register as the
destination register then we could have overwritten the address with the
move.
Use a temporary until we get RA constraints in place.
For loadstores to memory, this will use TSO ops to emulate x86
behaviour.
In the case that the source register is the stack pointer then it falls
back down to using regular loadstores. Since it is expected that stack
pointer usage will be thread specific.
With the AArch64 implementation this makes us be quite a bit closer to
being x86 TSO compliant
This patches unaligned LORegion loadstores with DMB wrapped loadstores.
This will ensure full cacheline consistency on loadstores, at the
expense of speed.
The performance can potentially be improved with "Half-barriers"
Described a bit here: https://github.com/dotnet/runtime/issues/8072
We can worry about that path after the initial implementation
This is the base implementation that uses LORegion loadstore
instructions to support the load/store release semantics, which these
instructions use.
Sadly these don't match the alignment requirements of x86 loadstores, so
if it was just used everywhere then it will cause alignment faults.
This means we need to catch the sigbus and backpatch the instruction to
do safe (aka expensive) TSO.
Currently this backpatch just falls back to regular loadstores
surrounded by DMB instructions.
Basically unaligned loadstores will fall back to nearly what we are
doing now, so significantly improved but not perfect.
A follow up PR will change this over to using a helper routine to be
100% safe
It needs to track guest SigAltAction and have its own definitions for
sigaction and sa_mask. sa_mask specifically is defined differently
between the kernel and glibc.
Also fixes some issues with the SignalDelegator that posix tests found
We are rebranding an x86-64 illegal instruction near VIA's old ALTINST
instruction as an instruction to handle returning from guest signals
cleanly.
If this ever collides with a new x86-64 (unlikely) then we will need to
change the instruction.
This ends up looking similar to what we will do for thunk callbacks
Just generates some context level x86 code space for our guest to jump
in to.
This is only currently used for sigret but will become more important as
we come to support vdso.
This was sort of partially worked around.
The issue comes down to REX.W and Operand size prefix ordering on an
instruction.
When an instruction has both prefixes, then the one that has occured
later will overwrite the previous one.
Additionally in the case of 66h being reused as an escape prefix, we
needed to ignore it in this case.
The previous workaround was that if an instruction happened to have both
widening and narrowing, then widening would win(for MODRM args),
but then later on in the instruction decoding the literal constant
decoding would properly check which order the flags came in.
This resulted in literal constants working, but not modrm bytes
Instead replace the "last" flag handling with a two deep stack that we
can push and pop the flags correctly on to it, this ensures that the
flags stay around in the 66h ignoring mode (so widening doesn't get
obliterated).
This effects every instruction that supports REX.W and 66h Operand size
prefix, so it could be fixing some unknown bugs elsewhere.
Very specifically this one was found in OpenSSL, because it looks like
GCC is padding a mov instruction with 66h.
Instruction Examples:
Only difference is the prefix order being swapped
0x00000000 4 66488b1f mov rbx, qword [rdi]
0x00000004 4 48668b1f mov bx, word [rdi]
Stefanos Kornilios Mitsis Poiitidis