Ryan Houdek
a1fed323df
Merge pull request #820 from Sonicadvance1/remove_config_duplication
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Deduplicates some configuration data
2021-03-08 23:20:04 -08:00
Ryan Houdek
0bcd1c7df5
Merge pull request #816 from Sonicadvance1/cpuid_80000005
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Implements CPUID 0x8000'0005 for L1 cacheline information
2021-03-08 23:15:03 -08:00
Ryan Houdek
a3ba1ae199
Deduplicates some configuration data
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Configuration mapping was duplicated between three different tables.
Additionally default configuration values were strewn about. Making it confusing as to what the default value would end up being
Adds a new ConfigValues.inl header that defines a few things right next to each other.
Defines the enum name as usual.
Defines the JSON config option name.
Defines the Environment config option name
Defines the default value that the configuration should be
2021-03-08 22:53:41 -08:00
Scott Mansell
98cb54e3e4
Merge pull request #812 from phire/both_sides
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Allow both ARM64 and X86_64 jits to be compiled at the same time
2021-03-09 14:59:11 +13:00
Scott Mansell
cb17127ccb
Remove last traces of vixl simulator mode
2021-03-08 16:30:25 +13:00
Scott Mansell
93b6dbdc2b
Fix Arm64JitCore instantiation on x86
2021-03-08 16:30:25 +13:00
Scott Mansell
bea0adc3d1
Allow both jitcores to be enabled simultaneously
2021-03-08 16:30:25 +13:00
Scott Mansell
9cf7545f8d
Abstract mcontext out of JITs
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This will help with unification of common code later
2021-03-08 16:30:25 +13:00
Ryan Houdek
c657165e56
Implements CPUID 0x8000'0005 for L1 cacheline information
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@skmp commented about this in the L2 cacheline information PR.
Quickly implement it since it also has cacheline information.
Fairly trivial since every piece of information is just some 8bit variables.
2021-03-06 08:32:47 -08:00
Ryan Houdek
05ae7d3c5e
Merge pull request #814 from Sonicadvance1/cacheline_cpuid
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Implements CPUID 0x8000'0006 for cacheline information
2021-03-06 08:23:03 -08:00
Ryan Houdek
f94529ebb2
Implements CPUID 0x8000'0006 for cacheline information
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This exposes some cache information including cacheline information.
Fills out this data structure as well just incase we hit another cacheline size bug
2021-03-06 07:30:25 -08:00
Ryan Houdek
1adbf66fee
Implements MOVNTDQA
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Found this when running Steamlink under FEX on my laptop.
Turns out the Iris video driver now uses this unconditionally in a couple of locations.
Makes sense there since all the Iris targets are expected to support SSE4.1 atm.
2021-03-06 06:23:18 -08:00
Stefanos Kornilios Mitsis Poiitidis
3978097f15
Merge pull request #705 from FEX-Emu/skmp/mmap-cache-flushing
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Flush IR/Code cache on mmap, mmunmap & mprot
2021-03-03 12:59:29 +02:00
Stefanos Kornilios Mitsis Poiitidis
613e5b66ba
SMC: Expand --smc-checks options to 'none', 'mman', 'full'
2021-03-03 12:49:23 +02:00
Scott Mansell
ec95610587
X64_64 JIt: Remove -fno-operator-names
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Some IDEs didn't recognize this flag and threw
phantom errors when these files were open.
Lets lean towards a smoother developer experience
2021-03-03 15:47:58 +13:00
Stefanos Kornilios Mitsis Poiitidis
e92578817d
SMC: Flush IR/Code cache on mmap, mmunmap & mprot
2021-02-26 13:22:05 +02:00
Stefanos Kornilios Mitsis Poiitidis
aecea294d5
Merge pull request #792 from Sonicadvance1/implemented_unaligned_memory_ops
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Implements unaligned atomic memory ops for ARMv8.1+
2021-02-26 12:50:06 +02:00
Ryan Houdek
6c469c21db
Fixes Zext and flags behaviour of CMPXCHG to register
2021-02-23 23:21:28 -08:00
Ryan Houdek
9798522bc5
Fixes Zext behaviour of CMPXCHG to memory
2021-02-23 23:21:05 -08:00
Ryan Houdek
373f4275f6
Fixes CMPXCHG flags being incorrect aside from ZF
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Almost everything only checks ZF but we had the arguments reversed for
the rest of the comparison flag results.
2021-02-23 22:01:52 -08:00
Scott Mansell
6fee5b9ca2
Merge pull request #789 from FEX-Emu/skmp/add-cacheinfo-cpuid
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CPUID: Add cache information, function 0x2
2021-02-24 03:06:20 +13:00
Stefanos Kornilios Mitsis Poiitidis
075cd423ed
AOTIR: Review feedback
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
8e06966ddc
AOTIR: Make OP_REMOVECODEENTRY relocatable
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
bdcf3ff606
AOTIR: Merge IRLists, RALists and DebugDataLists to LocalIRCache; cleanups and fixups
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
b29121c71a
AOTIR: Rename AOTCache to AOTIRCache
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
a5ee4bdf3c
AOTIR: Fix double free issues
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
56d10dcbbb
IR: Make OP_THUNK use an inline sha256 hash of the thunk name, update thunk scripts
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
1f919949cc
JIT: Fix arm64 build
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
dbc8b8e8e9
AOTIR: Append optimization flags to fileid
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
681deca4eb
IR: Make entrypoint implicit, Add InlineEntrypointOffset, make ValidateCode Entrypoint-relative
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
b3d12fbb7b
AOTIR: Cleanup interface
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
fafc987eab
AOTIR: Rename Generate to Capture
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
d825ed2b03
AOTIR: Reduce map lookup
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
f2f62c5f2c
AOTIR: Implement EntrypointOffset for aarch64
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
3e1e093b24
AOTIR: Store in ~/.fex-emu/aotir, per so
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
71dceb5339
Fix relocation support for FinishOp
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
be40d1604a
Improve aotir format
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
47d4481a75
AOTIR: Support relocations via new ir op
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
fc30efe040
AOTIR: Add hashing of code bytes
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
57680a8614
AOTIR: Add --aotir-generate and --aotir-load to FEXLoader & Config
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
66bdface49
AOTIR: Make copies for insertions, only cache RA'd blocks
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
816c4656df
IR: Add AOT Cache
2021-02-23 12:08:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
8642406b8f
CPUID: Add cache information, function 0x2
2021-02-23 11:01:15 +02:00
Ryan Houdek
bb0850eab8
Adds assert checks on missing LOCK support
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These usually don't get hit, but Geekbench4 DOES manage to hit LOCK on
BTS.
Which we just don't support right now.
2021-02-22 23:20:18 -08:00
Ryan Houdek
232eeff483
Implements BTC, BTR, BTS atomic variants
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BTS specifically is being used for threading related tasks. Which could
be why our threading has been unstable.
2021-02-22 22:27:10 -08:00
Ryan Houdek
55fc47e0b7
Passes SIGBUS handler to unaligned atomic op handler for ARMv8.1
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ARMv8.0 still unsupported here.
This allows us to support unaligned atomic ops for every atomic x86 op
that we support.
2021-02-22 18:22:10 -08:00
Ryan Houdek
4f40166902
Implements unaligned atomic memory ops for ARMv8.1+
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This takes the existing unaligned CAS handling code and makes it more
robust to handle both true unaligned CAS and unaligned atomic memory
ops.
Specifically it inserts some lambda helpers to calculate the Desired and
Expected values inside of the CAS loops to account for CAS and memory
operation.
2021-02-22 18:17:53 -08:00
Stefanos Kornilios Mitsis Poiitidis
9b360e66dc
Threading: Workaround exit_group bug
2021-02-22 14:24:42 +02:00
Stefanos Kornilios Mitsis Poiitidis
3bc12de017
OpDisp: Imm SAR OpSize < 32 needs sign extension
2021-02-17 08:17:20 +02:00
Stefanos Kornilios Mitsis Poiitidis
5ae6a64800
Merge pull request #778 from FEX-Emu/skmp/x87-round-trunc
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x87: Round, Truncate & Precision control
2021-02-17 05:27:56 +02:00
