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Code Issues Packages Projects Releases 67 Wiki Activity
216 Commits 11 Branches 71 Tags
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Commit Graph
61 Commits
Author SHA1 Message Date
Ryan Houdek 2889c860d4 Adds new vector IR ops 2020-03-06 07:56:14 +02:00
Ryan Houdek a272970559 Rewrites the Dead Context Loadstore elimination passes to be more generic 
Accesses are now classified more generically, which allows them to be
optimized away more easily.
XMM still needs a special case but maybe that can be changed in the
future.
 2020-03-06 07:56:13 +02:00
Ryan Houdek 18c5a3d6e5 Fixes a couple of bugs in the RA 2020-03-06 07:56:13 +02:00
Ryan Houdek 03a32ef2aa Disables the redundant context load elimination pass again. Since it is broken once again. 2020-03-06 07:56:13 +02:00
Ryan Houdek 92e4be828f Implements new RA pass that supports PHI nodes 
Has a heuristic that changes from a map lookup and a linear scan
depending on the number of SSA values. Map lookup is faster for larger
blocks while for smaller blocks linear scan is faster.

Block scan is 1.5x - 2x faster for a 30k SSA value block I was looking
at.
 2020-03-06 07:56:13 +02:00
Ryan Houdek 19fa513583 Fixes IRValidation bug 2020-03-06 07:56:13 +02:00
Ryan Houdek 89266c4dce Enables new validation passes in debug build. 2020-03-06 07:56:13 +02:00
Ryan Houdek a25f5eb011 Adds value dominance validation pass 2020-03-06 07:56:08 +02:00
Ryan Houdek 1d9dc9c60f Adds PHI validation pass 2020-03-06 07:56:08 +02:00
Ryan Houdek 88c6b629ce Allows dumping of PHI values 2020-03-06 07:56:08 +02:00
Ryan Houdek dd3c2ced6a Adds PHI IR nodes 2020-03-06 07:56:08 +02:00
Scott Mansell 26141e426a Fix unsigned/signed compare conditions 
Also, rename to match the LLVM naming style, which is less confusing.
 2020-03-06 07:56:07 +02:00
Scott Mansell 4fe10ca130 Add Load/StoreContextIndexted IR instructions 
Useful for things like x87 where instructions can dynamically index
into a resgister file.

This commit includes support for irint and x86 jit.
 2020-03-06 07:56:06 +02:00
Ryan Houdek 86f21c2dbd Adds Atomic Swap/FetchAnd/FetchOr/FetchXor to IR json 2020-03-06 07:56:05 +02:00
Ryan Houdek 79f3d40be1 Fixes IR JSON and RA to fix wrong class RA generation. 
IR Op Print is now the defining split between GPR and FPR class types
 2020-03-06 07:56:05 +02:00
Ryan Houdek c014a0ce3a Adds new atomic IR ops 2020-03-06 07:56:04 +02:00
Ryan Houdek d666ee0d57 Fixes SplatVector IROp size calculation 2020-03-06 07:56:04 +02:00
Ryan Houdek 1ef4bf90a2 Adds new IR Ops 
18 new IR ops for handling things
 2020-03-06 07:56:02 +02:00
Ryan Houdek 3bb9197e6a Adds VAND IR Op 2020-03-06 07:56:02 +02:00
Ryan Houdek e9be5430b9 Adds a couple new IR ops for easy movement of registers between classes. 2020-03-06 07:56:01 +02:00
Ryan Houdek afdbd9ebdc Fixes issues with PSLLDQ and PSRLDQ 
These are whole vector shift instructions and they shift by bytes rather
than bits.
You only get an immediate offset for the instruction.
Implements two new IR ops to account for these instructions

This also doesn't match AArch64 behaviour 100%, requires two
instructions to emulate rather than the single one on the x86-side
 2020-03-06 07:55:59 +02:00
Ryan Houdek 41ed7ca126 Fixes compile failures 
Didn't get caught previously because of my dirty build directory
 2020-03-06 07:55:59 +02:00
Ryan Houdek bc294164e3 Updates project to allow it to be installed 
Installs as both a static library and a shared library
 2020-03-06 07:55:59 +02:00
Ryan Houdek 939e210a68 Updates SonicUtils 
Makes changes to match latest changes
 2020-03-06 07:55:54 +02:00
Ryan Houdek 9e910520c6 Adds placeholder Guest call/ret IROps 
Will be used in the future
 2020-03-06 07:55:46 +02:00
Ryan Houdek 87e6b7108f Adds an unsafe disabled flag elimination pass 
This is a very useful optimization, but may only become "safe" once we
recompile a full function.
 2020-03-06 07:55:45 +02:00
Ryan Houdek 9e132e107a Adds alignment information to the mem loadstore IR ops 
Allows us to not always emit unaligned loadstore ops for these
 2020-03-06 07:55:45 +02:00
Ryan Houdek f697da77b6 Splits up, documents, and extends the RCLE pass 
Splits this pass in to three parts.
First function is to remove StoreContext-LoadContext pairs that are
redundant. Removes the Load that has occured after a store-load pair.

Second function is to remove LoadContext instructions that are redundant
due to no other stores to that location

Third function is to remove StoreContext instructions that are redundant
due to no load happening between them (Relies on previous functions)
 2020-03-06 07:55:45 +02:00
Ryan Houdek 6dc7d2e679 Extends IR Validation to check exit to be correct 
Checks to ensure the last op in a block is EndBlock.
Checks to ensure the last instruction before that one is one of the ops
that exit correctly. So ExitFunction, Jump, CondJump, or Break.
 2020-03-06 07:55:45 +02:00
Ryan Houdek f8b858e7fc Removes the EndFunction IR Op 2020-03-06 07:55:45 +02:00
Ryan Houdek 9218df31c2 Re-enables RCLE pass since it works with the better IR now 2020-03-06 07:55:44 +02:00
Ryan Houdek e2bce88eb0 Adds aligned XMM tracking to RCLE pass 2020-03-06 07:55:44 +02:00
Ryan Houdek db7b3d415d Adds VBitcast IR op 
Casts vector to a integer of the same width as the vector
 2020-03-06 07:55:44 +02:00
Ryan Houdek 704b8f9679 Disables Redundant Context Load Elimination pass. 
It's currently broken (Due to not 100% valid IR?)
 2020-03-06 07:55:37 +02:00
Ryan Houdek b199ce70e9 Changes over IRValidation to the new format. 
We still can't pass this validation pass
 2020-03-06 07:55:37 +02:00
Ryan Houdek b7c7a34cf6 Changes (aggressively) how branching is handled in the frontend. 
This changes over CondJump to have a defined True and False branch path.
Additionally needing to change over everything to handle this.
This now means that a false branch condition will no longer assume
fallthrough past this instruction.
Currently the x86-64 JIT generates an additional jmp instruction on
fallthrough that isn't optimized away.

This is working towards improvements in our IR branching model and
improving IRValidation in doing so.
This is working towards the model that IRBlocks can only have 0-2
successors.
Ret/Exit - 0 successors
Jump - 2 successors
CondJump - 2 successors

TBD:
Syscall/CPUID - Breaking block?
 2020-03-06 07:55:37 +02:00
Scott Mansell 597ee06243 Add ConstProp for Mul 2020-03-06 07:55:36 +02:00
Scott Mansell 5263f94d84 Elimitate loads before const prop 2020-03-06 07:55:36 +02:00
Scott Mansell b148afef4b Add Dead Code Elimitation pass 
Refactor the previous WIP to use NumUses
 2020-03-06 07:55:36 +02:00
Scott Mansell b34465544a Fix Incorrect tracking during Redudent Flag pass 2020-03-06 07:55:36 +02:00
Scott Mansell 8e34a74030 Keep node usage when compacting 2020-03-06 07:55:36 +02:00
Scott Mansell d1f2d85d0c Fix up usage tracking of Args. 
Make sure we keep them up to date when removing
nodes.
 2020-03-06 07:55:36 +02:00
Scott Mansell b054807270 WIP Dead Code Elimitation pass 2020-03-06 07:55:36 +02:00
Ryan Houdek aabc6f6de2 Extends ConstProp pass a bit more. 
Still doesn't cover all the IROps but it hits quite a few more that I
could see.
 2020-03-06 07:55:35 +02:00
Ryan Houdek 0eb86389de Cleans up RA spill slot calculation. 
RA spill slots now have live ranges so we can reuse the spill slot.
This can reduce spill stack usage significantly in code ranges with
large live ranges.
 2020-03-06 07:55:35 +02:00
Ryan Houdek 012805fd72 Fixes multiblock and a few bugs in RA. 
This makes it so multiblock can now be enabled with the JITs.
Results in a decent performance increase by itself.
 2020-03-06 07:55:35 +02:00
Ryan Houdek c105c52d67 Changes IRValidation to use the new IR::GetArgs function. 2020-03-06 07:55:34 +02:00
Ryan Houdek 52b5ac9e19 Changes slightly how IR::IRHeader is represented 2020-03-06 07:55:33 +02:00
Ryan Houdek f27f9485f6 Changes IR::CondJump's condition to dump textually. 2020-03-06 07:55:33 +02:00
Ryan Houdek a8ff6414c1 Fixes indent failure on IR dumping. 
Depending on IR ordering then it could have wrapped around to max
indent.
 2020-03-06 07:55:22 +02:00