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Adds VBitcast IR op

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Casts vector to a integer of the same width as the vector
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Ryan Houdek authored and Stefanos Kornilios Mitsis Poiitidis committed 2020-03-06 07:55:44 +02:00
1 parent 3eb55d5f9f
commit db7b3d415d
3 files changed
+22 -2
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Source/Interface/Core/JIT/x86_64/JIT.cpp
+5
View File
@@ -1434,6 +1434,11 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
vpor(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
break;
}
case IR::OP_VBITCAST: {
auto Op = IROp->C<IR::IROp_VBitcast>();
movaps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
break;
}
case IR::OP_VCMPEQ: {
auto Op = IROp->C<IR::IROp_VCMPEQ>();
LogMan::Throw::A(Op->RegisterSize == 16, "Can't handle register size of: %d", Op->RegisterSize);
Source/Interface/Core/LLVMJIT/LLVMCore.cpp
+11 -2
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@@ -749,7 +749,7 @@ llvm::Value *LLVMJITCore::CastToOpaqueStructure(llvm::Value *Arg, llvm::Type *Ds
Arg = JITState.IRBuilder->CreateBitCast(Arg, NewIntegerType);
}
return JITState.IRBuilder->CreateZExtOrTrunc(Arg, DstType->getPointerElementType());
return JITState.IRBuilder->CreateZExtOrTrunc(Arg, DstType);
}
void LLVMJITCore::SetDest(IR::OrderedNodeWrapper Op, llvm::Value *Val) {
@@ -935,7 +935,7 @@ void LLVMJITCore::HandleIR(FEXCore::IR::IRListView<true> const *IR, IR::NodeWrap
auto Op = IROp->C<IR::IROp_StoreContext>();
auto Src = GetSrc(Op->Header.Args[0]);
auto Value = CreateContextPtr(Op->Offset, Op->Size);
Src = CastToOpaqueStructure(Src, Value->getType());
Src = CastToOpaqueStructure(Src, Value->getType()->getPointerElementType());
if ((Op->Offset % Op->Size) == 0)
JITState.IRBuilder->CreateAlignedStore(Src, Value, Op->Size);
@@ -1472,6 +1472,15 @@ void LLVMJITCore::HandleIR(FEXCore::IR::IRListView<true> const *IR, IR::NodeWrap
SetDest(*WrapperOp, Result);
break;
}
case IR::OP_VBITCAST: {
auto Op = IROp->C<IR::IROp_VBitcast>();
auto Src = GetSrc(Op->Header.Args[0]);
auto Result = CastToOpaqueStructure(Src, Type::getIntNTy(*Con, Src->getType()->getPrimitiveSizeInBits()));
SetDest(*WrapperOp, Result);
break;
}
case IR::OP_VOR: {
auto Op = IROp->C<IR::IROp_Or>();
auto Src1 = GetSrc(Op->Header.Args[0]);
Source/Interface/IR/IR.json
+6
View File
@@ -540,6 +540,12 @@
"uint8_t", "Index"
]
},
"VBitcast": {
"HasDest": true,
"SSAArgs": "1"
},
"Last": {
"Last": true,
"Args": []