These are whole vector shift instructions and they shift by bytes rather
than bits.
You only get an immediate offset for the instruction.
Implements two new IR ops to account for these instructions
This also doesn't match AArch64 behaviour 100%, requires two
instructions to emulate rather than the single one on the x86-side
Splits this pass in to three parts.
First function is to remove StoreContext-LoadContext pairs that are
redundant. Removes the Load that has occured after a store-load pair.
Second function is to remove LoadContext instructions that are redundant
due to no other stores to that location
Third function is to remove StoreContext instructions that are redundant
due to no load happening between them (Relies on previous functions)
Checks to ensure the last op in a block is EndBlock.
Checks to ensure the last instruction before that one is one of the ops
that exit correctly. So ExitFunction, Jump, CondJump, or Break.
This changes over CondJump to have a defined True and False branch path.
Additionally needing to change over everything to handle this.
This now means that a false branch condition will no longer assume
fallthrough past this instruction.
Currently the x86-64 JIT generates an additional jmp instruction on
fallthrough that isn't optimized away.
This is working towards improvements in our IR branching model and
improving IRValidation in doing so.
This is working towards the model that IRBlocks can only have 0-2
successors.
Ret/Exit - 0 successors
Jump - 2 successors
CondJump - 2 successors
TBD:
Syscall/CPUID - Breaking block?
RA spill slots now have live ranges so we can reuse the spill slot.
This can reduce spill stack usage significantly in code ranges with
large live ranges.
I had to change how blocks are represented to make it easier to parse
This required a fairly substantial refactor that makes it so blocks are
represented differently and we can walk them sequentially.
This will make future analysis easier to deal with.
Had to rewrite the passes and core's parsing of the IR afterwards.
Moved RA in to a optimization pass to be shared between the JIT backends
This works because x86-64 and AArch64 RA can be identical.
Still doesn't support PHI nodes or spilling correctly, this is the first
step in the process of getting there.
Ryan Houdek