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FEX-Emu--FEX/FEXCore/Source/Interface/Core/JIT
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Lioncache 678e03b470 VectorOps: Correct benign VFAddV op cast 
This was using the non-float VAddV variant, but had the same behavior,
since the fields were named the same. So this is just a correctness fix.
2025-07-15 11:41:28 -04:00
..
ALUOps.cpp
JIT: fix divisor masking
2025-07-09 15:00:42 -04:00
Arm64Relocations.cpp
Drop use of assume-asserting logging macros
2025-01-21 12:01:33 +01:00
AtomicOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00
BranchOps.cpp
IR: include a fence in CPUID
2025-07-02 13:04:49 -04:00
ConversionOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00
EncryptionOps.cpp
JIT: make almost all the DEF_OPs common
2025-05-19 13:42:59 -04:00
JIT.cpp
FEXCore: Support multiple entrypoints into a multiblock
2025-07-10 16:00:24 +01:00
JITClass.h
FEXCore: Support multiple entrypoints into a multiblock
2025-07-10 16:00:24 +01:00
MemoryOps.cpp
IR: give StoreRegister a precoloured destination
2025-06-19 13:44:23 -04:00
MiscOps.cpp
RegisterAllocationPass: delete trivial instructions
2025-05-26 15:52:23 -04:00
MoveOps.cpp
RegisterAllocationPass: delete trivial instructions
2025-05-26 15:52:23 -04:00
VectorOps.cpp
VectorOps: Correct benign VFAddV op cast
2025-07-15 11:41:28 -04:00