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SpeedBreaker ProjectandClaude Opus 5.5
a6ade41b9f
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
270 lines
10 KiB
Python
270 lines
10 KiB
Python
"""Generate instruction tests (Xenia's .s format) for instructions we added to
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XenonRecomp that Xenia has no tests for, or too few.
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Expected values come from an independent Python model of the PowerPC
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semantics (big-endian element order, as written in the tests), never from the
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recompiler, so a codegen bug can't agree with itself.
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python3 tests/gen_instr_tests.py # writes tests/instr/nfsmw_*.s
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"""
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import os
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import random
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import struct
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OUT = os.path.join(os.path.dirname(__file__), 'instr')
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rng = random.Random(0x360)
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# --- vector helpers: a vector is 4 big-endian words [w0, w1, w2, w3] ---------
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def to_bytes(ws):
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return b''.join(struct.pack('>I', w) for w in ws)
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def from_bytes(b):
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return [struct.unpack('>I', b[i:i + 4])[0] for i in range(0, 16, 4)]
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def elems(ws, size, signed):
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fmt = {1: 'b', 2: 'h', 4: 'i'}[size]
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fmt = fmt if signed else fmt.upper()
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return list(struct.unpack('>' + fmt * (16 // size), to_bytes(ws)))
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def pack(values, size, signed):
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fmt = {1: 'b', 2: 'h', 4: 'i'}[size]
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fmt = fmt if signed else fmt.upper()
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return from_bytes(struct.pack('>' + fmt * (16 // size), *values))
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def sat(x, lo, hi):
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return max(lo, min(hi, x))
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def vec(ws):
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return '[' + ', '.join(f'{w:08X}' for w in ws) + ']'
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def rand_vec(size=None):
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"""Random vector, biased toward edge values for the element size."""
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if size is None or rng.random() < 0.3:
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return [rng.getrandbits(32) for _ in range(4)]
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n, bits = 16 // size, size * 8
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edges = [0, 1, (1 << bits) - 1, 1 << (bits - 1), (1 << (bits - 1)) - 1]
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vals = [rng.choice(edges) if rng.random() < 0.4 else rng.getrandbits(bits) for _ in range(n)]
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return pack(vals, size, False)
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# --- reference models --------------------------------------------------------
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def shift_op(size, kind):
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bits = size * 8
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mask = (1 << bits) - 1
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def f(a, b):
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ua, sa, sh = elems(a, size, False), elems(a, size, True), elems(b, size, False)
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out = []
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for x, sx, s in zip(ua, sa, sh):
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s &= bits - 1
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if kind == 'sl': out.append((x << s) & mask)
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elif kind == 'sr': out.append(x >> s)
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elif kind == 'sra': out.append((sx >> s) & mask)
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elif kind == 'rl': out.append(((x << s) | (x >> (bits - s))) & mask)
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return pack(out, size, False)
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return f
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def sat_arith(size, signed, op):
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bits = size * 8
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lo, hi = (-(1 << (bits - 1)), (1 << (bits - 1)) - 1) if signed else (0, (1 << bits) - 1)
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def f(a, b):
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return pack([sat(op(x, y), lo, hi) for x, y in zip(elems(a, size, signed), elems(b, size, signed))], size, signed)
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return f
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def modular(size, op):
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mask = (1 << (size * 8)) - 1
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def f(a, b):
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return pack([op(x, y) & mask for x, y in zip(elems(a, size, False), elems(b, size, False))], size, False)
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return f
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def elementwise(size, signed, op):
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def f(a, b):
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return pack([op(x, y) for x, y in zip(elems(a, size, signed), elems(b, size, signed))], size, signed)
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return f
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def pack_op(in_size, in_signed, out_signed):
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out_bits = in_size * 4
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lo, hi = (-(1 << (out_bits - 1)), (1 << (out_bits - 1)) - 1) if out_signed else (0, (1 << out_bits) - 1)
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def f(a, b):
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# vD = sat(vA elements) then sat(vB elements), in element order.
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vals = [sat(x, lo, hi) for x in elems(a, in_size, in_signed) + elems(b, in_size, in_signed)]
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return pack(vals, in_size // 2, out_signed)
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return f
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def compare(size, signed, op):
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mask = (1 << (size * 8)) - 1
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def f(a, b):
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return pack([mask if op(x, y) else 0 for x, y in zip(elems(a, size, signed), elems(b, size, signed))], size, False)
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return f
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VECTOR_BINOPS = {
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# name: (model, element size for biased inputs)
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'vslh': (shift_op(2, 'sl'), 2),
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'vsrh': (shift_op(2, 'sr'), 2),
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'vsrah': (shift_op(2, 'sra'), 2),
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'vrlh': (shift_op(2, 'rl'), 2),
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'vsrab': (shift_op(1, 'sra'), 1),
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'vaddsws': (sat_arith(4, True, lambda x, y: x + y), 4),
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'vaddsbs': (sat_arith(1, True, lambda x, y: x + y), 1),
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'vsubshs': (sat_arith(2, True, lambda x, y: x - y), 2),
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'vsububm': (modular(1, lambda x, y: x - y), 1),
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'vmaxsh': (elementwise(2, True, max), 2),
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'vminsh': (elementwise(2, True, min), 2),
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'vavguh': (elementwise(2, False, lambda x, y: (x + y + 1) >> 1), 2),
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'vandc': (lambda a, b: [x & ~y & 0xFFFFFFFF for x, y in zip(a, b)], None),
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'vpkswss': (pack_op(4, True, True), 4),
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'vpkswus': (pack_op(4, True, False), 4),
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'vpkshss': (pack_op(2, True, True), 2),
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'vpkuhus': (pack_op(2, False, False), 2),
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'vcmpgtsh': (compare(2, True, lambda x, y: x > y), 2),
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'vcmpgtsw': (compare(4, True, lambda x, y: x > y), 4),
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'vcmpequh': (compare(2, False, lambda x, y: x == y), 2),
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'vcmpgtuh': (compare(2, False, lambda x, y: x > y), 2),
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}
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RECORD_FORMS = ['vcmpgtsh', 'vcmpgtsw', 'vcmpequh', 'vcmpgtuh']
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def write(name, tests):
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with open(os.path.join(OUT, f'nfsmw_{name}.s'), 'w') as f:
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f.write(f'# Generated by tests/gen_instr_tests.py (independent Python model). Do not edit.\n\n')
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for i, t in enumerate(tests, 1):
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f.write(f'test_nfsmw_{name}_{i}:\n' + t + '\n')
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def main():
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os.makedirs(OUT, exist_ok=True)
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for f in os.listdir(OUT):
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if f.startswith('nfsmw_'):
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os.remove(os.path.join(OUT, f))
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for name, (model, size) in VECTOR_BINOPS.items():
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tests = []
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for _ in range(8):
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a, b = rand_vec(size), rand_vec(size)
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if name == 'vcmpequh' and rng.random() < 0.5:
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b = list(a) # make equality actually happen
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d = model(a, b)
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tests.append(
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f' #_ REGISTER_IN v4 {vec(a)}\n'
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f' #_ REGISTER_IN v5 {vec(b)}\n'
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f' {name} v3, v4, v5\n'
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f' blr\n'
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f' #_ REGISTER_OUT v3 {vec(d)}\n'
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f' #_ REGISTER_OUT v4 {vec(a)}\n'
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f' #_ REGISTER_OUT v5 {vec(b)}\n')
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write(name, tests)
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# Record forms: cr6.lt = all elements true, cr6.eq = none true. The harness
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# can't read CR, so branch on it: r3 bit 0 = all, bit 1 = none.
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for name in RECORD_FORMS:
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model, size = VECTOR_BINOPS[name]
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tests = []
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cases = [(rand_vec(size), rand_vec(size)) for _ in range(4)]
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a = rand_vec(size)
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cases += [(a, a), (pack([0] * (16 // size), size, False), pack([0] * (16 // size), size, False))]
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# all-true for the greater-than forms: a = b + 1 elementwise where possible
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big = pack([(1 << (size * 8 - 1)) - 1] * (16 // size), size, False)
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small = pack([0] * (16 // size), size, False)
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cases += [(big, small), (small, big)]
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for a, b in cases:
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d = model(a, b)
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all_true = all(w == 0xFFFFFFFF for w in d)
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none_true = all(w == 0 for w in d)
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r3 = (1 if all_true else 0) | (2 if none_true else 0)
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tests.append(
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f' #_ REGISTER_IN v4 {vec(a)}\n'
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f' #_ REGISTER_IN v5 {vec(b)}\n'
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f' #_ REGISTER_IN r3 0\n'
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f' {name}. v3, v4, v5\n'
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f' bge cr6, .+8\n'
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f' ori r3, r3, 1\n'
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f' bne cr6, .+8\n'
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f' ori r3, r3, 2\n'
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f' blr\n'
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f' #_ REGISTER_OUT v3 {vec(d)}\n'
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f' #_ REGISTER_OUT r3 {r3}\n')
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write(name + '_rc', tests)
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# vspltish: sign-extended 5-bit immediate splatted to every halfword.
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tests = []
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for imm in (-16, -1, 0, 1, 7, 15):
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d = pack([imm & 0xFFFF] * 8, 2, False)
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tests.append(f' vspltish v3, {imm}\n blr\n #_ REGISTER_OUT v3 {vec(d)}\n')
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write('vspltish', tests)
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# Summary-overflow branches after fcmpu: so = unordered (a NaN operand).
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NAN = '0x7FF8000000000000'
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tests = []
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for mnemonic in ('bso', 'bns'):
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for f2, unordered in (('2.0', False), (NAN, True), ('1.0', False)):
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taken = unordered if mnemonic == 'bso' else not unordered
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tests.append(
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f' #_ REGISTER_IN f1 1.0\n'
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f' #_ REGISTER_IN f2 {f2}\n'
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f' #_ REGISTER_IN r3 1\n'
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f' fcmpu cr1, f1, f2\n'
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f' {mnemonic} cr1, .+8\n'
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f' li r3, 2\n'
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f' blr\n'
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f' #_ REGISTER_OUT r3 {1 if taken else 2}\n')
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for mnemonic in ('bsolr', 'bnslr'):
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for f2, unordered in (('2.0', False), (NAN, True)):
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returns = unordered if mnemonic == 'bsolr' else not unordered
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tests.append(
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f' #_ REGISTER_IN f1 1.0\n'
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f' #_ REGISTER_IN f2 {f2}\n'
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f' #_ REGISTER_IN r3 1\n'
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f' fcmpu cr1, f1, f2\n'
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f' {mnemonic} cr1\n'
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f' li r3, 2\n'
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f' blr\n'
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f' #_ REGISTER_OUT r3 {1 if returns else 2}\n')
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write('bso', tests)
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# cror / crorc: cr7.eq = cr0.lt OR [NOT] cr1.gt (bits 30, 0, 5).
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tests = []
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for mnemonic in ('cror', 'crorc'):
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for x, y in ((-1, 1), (-1, -1), (1, 1), (1, -1)):
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lt0, gt1 = x < 0, y > 0
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result = lt0 or (not gt1 if mnemonic == 'crorc' else gt1)
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tests.append(
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f' #_ REGISTER_IN r4 0x{x & 0xFFFFFFFFFFFFFFFF:X}\n'
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f' #_ REGISTER_IN r5 0x{y & 0xFFFFFFFFFFFFFFFF:X}\n'
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f' #_ REGISTER_IN r3 1\n'
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f' cmpwi cr0, r4, 0\n'
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f' cmpwi cr1, r5, 0\n'
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f' cmpwi cr7, r5, 12345\n'
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f' {mnemonic} 30, 0, 5\n'
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f' beq cr7, .+8\n'
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f' li r3, 2\n'
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f' blr\n'
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f' #_ REGISTER_OUT r3 {1 if result else 2}\n')
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write('cror', tests)
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# stfsu: store single, then update rA with the effective address.
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tests = []
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# Values are written as strings with a '.', which is how the harness tells
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# a float input from an integer one.
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for text, disp in (('1.5', 16), ('-2.25', 0), ('3.0e38', -8)):
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value = float(text)
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bits = struct.pack('>f', value)
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ea = 0x1000 + disp
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tests.append(
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f' #_ REGISTER_IN f1 {text}\n'
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f' #_ REGISTER_IN r4 0x1000\n'
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f' stfsu f1, {disp}(r4)\n'
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f' blr\n'
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f' #_ REGISTER_OUT r4 0x{ea:X}\n'
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f' #_ MEMORY_OUT {ea:08X} ' + ' '.join(f'{c:02X}' for c in bits) + '\n')
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write('stfsu', tests)
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print('wrote', sorted(f for f in os.listdir(OUT) if f.startswith('nfsmw_')))
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if __name__ == '__main__':
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main()
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