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ARMEmitter: Handle SVE inc/dec register by predicate count group

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Lioncache committed 2023-03-21 16:16:13 -04:00
1 parent 0930a10026
commit 392438d70a
2 files changed
+15 -2
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External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl
Vendored
+6 -1
View File
@@ -1732,7 +1732,12 @@ public:
}
// SVE inc/dec register by predicate count
// XXX:
void incp(SubRegSize size, XRegister rdn, PRegister pm) {
SVEIncDecPredicateCountScalar(1, 1, 0b00, 0b00, size, rdn, pm);
}
void decp(SubRegSize size, XRegister rdn, PRegister pm) {
SVEIncDecPredicateCountScalar(1, 1, 0b00, 0b01, size, rdn, pm);
}
// SVE Write FFR
// SVE FFR write from predicate
External/FEXCore/unittests/Emitter/SVE_Tests.cpp
Vendored
+9 -1
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@@ -2093,7 +2093,15 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE inc/dec vector by predicat
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE inc/dec register by predicate count") {
// TODO: Implement in emitter.
TEST_SINGLE(incp(SubRegSize::i8Bit, XReg::x30, PReg::p15), "incp x30, p15.b");
TEST_SINGLE(incp(SubRegSize::i16Bit, XReg::x30, PReg::p15), "incp x30, p15.h");
TEST_SINGLE(incp(SubRegSize::i32Bit, XReg::x30, PReg::p15), "incp x30, p15.s");
TEST_SINGLE(incp(SubRegSize::i64Bit, XReg::x30, PReg::p15), "incp x30, p15.d");
TEST_SINGLE(decp(SubRegSize::i8Bit, XReg::x30, PReg::p15), "decp x30, p15.b");
TEST_SINGLE(decp(SubRegSize::i16Bit, XReg::x30, PReg::p15), "decp x30, p15.h");
TEST_SINGLE(decp(SubRegSize::i32Bit, XReg::x30, PReg::p15), "decp x30, p15.s");
TEST_SINGLE(decp(SubRegSize::i64Bit, XReg::x30, PReg::p15), "decp x30, p15.d");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE FFR write from predicate") {