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https://github.com/FEX-Emu/FEX.git
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DCSE: Rename Node2 to StoreNode
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1 parent
f397bf3349
commit
4e783202bc
1 file changed
+10
-9
+10
-9
@@ -24,7 +24,7 @@ namespace {
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uint32_t AccessOffset;
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uint8_t AccessSize;
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FEXCore::IR::OrderedNode *Node;
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FEXCore::IR::OrderedNode *Node2;
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FEXCore::IR::OrderedNode *StoreNode;
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};
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using ContextInfo = std::vector<ContextMemberInfo>;
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@@ -199,6 +199,7 @@ namespace {
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ContextClassification->at(Offset).Accessed = Access;
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ContextClassification->at(Offset).AccessRegClass = FEXCore::IR::InvalidClass;
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ContextClassification->at(Offset).AccessOffset = 0;
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ContextClassification->at(Offset).StoreNode = nullptr;
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};
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size_t Offset = 0;
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SetAccess(Offset++, DefaultAccess[0]);
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@@ -252,8 +253,8 @@ private:
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std::unordered_map<FEXCore::IR::OrderedNodeWrapper::NodeOffsetType, BlockInfo> OffsetToBlockMap;
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ContextMemberInfo *FindMemberInfo(ContextInfo *ClassifiedInfo, uint32_t Offset, uint8_t Size);
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ContextMemberInfo *RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2 = nullptr);
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ContextMemberInfo *RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2 = nullptr);
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ContextMemberInfo *RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr);
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ContextMemberInfo *RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr);
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void CalculateControlFlowInfo(FEXCore::IR::IREmitter *IREmit);
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// Block local Passes
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@@ -276,7 +277,7 @@ ContextMemberInfo *RCLSE::FindMemberInfo(ContextInfo *ClassifiedInfo, uint32_t O
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return Info;
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}
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ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2) {
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ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode) {
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LogMan::Throw::A((Offset + Size) <= (Info->Class.Offset + Info->Class.Size), "Access to context item went over member size");
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LogMan::Throw::A(Info->Accessed != ACCESS_INVALID, "Tried to access invalid member");
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@@ -293,13 +294,13 @@ ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, FEXCore::IR::Reg
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Info->AccessOffset = Offset;
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Info->AccessSize = Size;
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Info->Node = Node;
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Info->Node2 = Node2;
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Info->StoreNode = StoreNode;
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return Info;
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}
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ContextMemberInfo *RCLSE::RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2) {
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ContextMemberInfo *RCLSE::RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode) {
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ContextMemberInfo *Info = FindMemberInfo(ClassifiedInfo, Offset, Size);
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return RecordAccess(Info, RegClass, Offset, Size, AccessType, Node, Node2);
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return RecordAccess(Info, RegClass, Offset, Size, AccessType, Node, StoreNode);
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}
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void RCLSE::CalculateControlFlowInfo(FEXCore::IR::IREmitter *IREmit) {
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@@ -465,7 +466,7 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
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uint32_t LastOffset = Info->AccessOffset;
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uint8_t LastSize = Info->AccessSize;
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LastAccessType LastAccess = Info->Accessed;
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OrderedNode *LastNode2 = Info->Node2;
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OrderedNode *LastStoreNode = Info->StoreNode;
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RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_WRITE, Op->Header.Args[0].GetNode(ListBegin), CodeNode);
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if (LastAccess == ACCESS_WRITE &&
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@@ -475,7 +476,7 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
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Info->Accessed == ACCESS_WRITE) {
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// Remove the last store because this one overwrites it entirely
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// Happens when we store in to a location then store again
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IREmit->Remove(LastNode2);
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IREmit->Remove(LastStoreNode);
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}
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}
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else if (IROp->Op == OP_LOADCONTEXT) {
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