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Merge pull request #3436 from alyssarosenzweig/ir/af-simplify

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Simplify CalculateAF
This commit is contained in:
Alyssa Rosenzweig authored and GitHub committed 2024-02-22 08:17:07 -04:00
2 parents cc9c80d79f 30ff225e80
commit 5378ae2e76
11 files changed
+72 -76
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FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+1 -1
View File
@@ -1744,7 +1744,7 @@ private:
OrderedNode *LoadAF();
void FixupAF();
void CalculatePF(OrderedNode *Res);
void CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
void CalculateAF(OrderedNode *Src1, OrderedNode *Src2);
void CalculateOF(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool Sub);
void CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp
+6 -10
View File
@@ -282,7 +282,7 @@ void OpDispatchBuilder::CalculatePF(OrderedNode *Res) {
SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(Res);
}
void OpDispatchBuilder::CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
void OpDispatchBuilder::CalculateAF(OrderedNode *Src1, OrderedNode *Src2) {
// We only care about bit 4 in the subsequent XOR. If we'll XOR with 0,
// there's no sense XOR'ing at all. This affects INC.
uint64_t Const;
@@ -294,7 +294,7 @@ void OpDispatchBuilder::CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode
// We store the XOR of the arguments. At read time, we XOR with the
// appropriate bit of the result (available as the PF flag) and extract the
// appropriate bit.
OrderedNode *XorRes = _Xor(OpSize, Src1, Src2);
OrderedNode *XorRes = _Xor(OpSize::i32Bit, Src1, Src2);
SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(XorRes);
}
@@ -491,7 +491,7 @@ void OpDispatchBuilder::CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, Or
auto One = _Constant(1);
auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
CalculateAF(OpSize, Res, Src1, Src2);
CalculateAF(Src1, Src2);
CalculatePF(Res);
if (SrcSize >= 4) {
@@ -520,7 +520,7 @@ void OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, Or
auto One = _Constant(1);
auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
CalculateAF(OpSize, Res, Src1, Src2);
CalculateAF(Src1, Src2);
CalculatePF(Res);
if (SrcSize >= 4) {
@@ -551,9 +551,7 @@ void OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, Or
}
void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
CalculateAF(OpSize, Res, Src1, Src2);
CalculateAF(Src1, Src2);
CalculatePF(Res);
// Stash CF before stomping over it
@@ -571,9 +569,7 @@ void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, Or
}
void OpDispatchBuilder::CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
CalculateAF(OpSize, Res, Src1, Src2);
CalculateAF(Src1, Src2);
CalculatePF(Res);
// Stash CF before stomping over it
unittests/InstructionCountCI/Atomics.json
+2 -2
View File
@@ -322,7 +322,7 @@
"ExpectedArm64ASM": [
"ldaddal x5, x20, [x4]",
"add x26, x20, x5",
"eor x27, x20, x5",
"eor w27, w20, w5",
"cmn x20, x5"
]
},
@@ -404,7 +404,7 @@
"mov x20, x7",
"ldaddal x20, x7, [x4]",
"add x26, x7, x20",
"eor x27, x7, x20",
"eor w27, w7, w20",
"cmn x7, x20"
]
},
unittests/InstructionCountCI/FlagM/Atomics.json
+2 -2
View File
@@ -309,7 +309,7 @@
"ExpectedArm64ASM": [
"ldaddal x5, x20, [x4]",
"add x26, x20, x5",
"eor x27, x20, x5",
"eor w27, w20, w5",
"cmn x20, x5"
]
},
@@ -357,7 +357,7 @@
"mov x20, x7",
"ldaddal x20, x7, [x4]",
"add x26, x7, x20",
"eor x27, x7, x20",
"eor w27, w7, w20",
"cmn x7, x20"
]
},
unittests/InstructionCountCI/FlagM/FlagOpts.json
+2 -2
View File
@@ -44,7 +44,7 @@
"add x20, x6, x20",
"mov x21, x5",
"sub x5, x21, x20",
"eor x27, x21, x6",
"eor w27, w21, w6",
"mov x26, x5",
"cfinv",
"sbcs xzr, x21, x6",
@@ -66,7 +66,7 @@
"add x20, x6, x20",
"mov x21, x5",
"add x5, x21, x20",
"eor x27, x21, x6",
"eor w27, w21, w6",
"mov x26, x5",
"adcs xzr, x21, x6",
"cfinv"
unittests/InstructionCountCI/FlagM/Primary.json
+21 -21
View File
@@ -54,7 +54,7 @@
"ExpectedArm64ASM": [
"mov x20, x7",
"add x7, x20, x5",
"eor x27, x20, x5",
"eor w27, w20, w5",
"mov x26, x7",
"cmn x20, x5"
]
@@ -114,7 +114,7 @@
"ExpectedArm64ASM": [
"mov x20, x5",
"add x5, x20, x7",
"eor x27, x20, x7",
"eor w27, w20, w7",
"mov x26, x5",
"cmn x20, x7"
]
@@ -212,7 +212,7 @@
"mov x20, #0xffffffffffffffff",
"mov x21, x4",
"sub x4, x21, #0x1 (1)",
"eor x27, x21, x20",
"eor w27, w21, w20",
"mov x26, x4",
"cmn x21, x20"
]
@@ -463,7 +463,7 @@
"add x20, x5, x20",
"mov x21, x7",
"add x7, x21, x20",
"eor x27, x21, x5",
"eor w27, w21, w5",
"mov x26, x7",
"adcs xzr, x21, x5"
]
@@ -558,7 +558,7 @@
"add x20, x7, x20",
"mov x21, x5",
"add x5, x21, x20",
"eor x27, x21, x7",
"eor w27, w21, w7",
"mov x26, x5",
"adcs xzr, x21, x7"
]
@@ -714,7 +714,7 @@
"add x21, x20, x21",
"mov x22, x4",
"add x4, x22, x21",
"eor x27, x22, x20",
"eor w27, w22, w20",
"mov x26, x4",
"adcs xzr, x22, x20"
]
@@ -799,7 +799,7 @@
"add x20, x5, x20",
"mov x21, x7",
"sub x7, x21, x20",
"eor x27, x21, x5",
"eor w27, w21, w5",
"mov x26, x7",
"cfinv",
"sbcs xzr, x21, x5",
@@ -898,7 +898,7 @@
"add x20, x7, x20",
"mov x21, x5",
"sub x5, x21, x20",
"eor x27, x21, x7",
"eor w27, w21, w7",
"mov x26, x5",
"cfinv",
"sbcs xzr, x21, x7",
@@ -1062,7 +1062,7 @@
"add x21, x20, x21",
"mov x22, x4",
"sub x4, x22, x21",
"eor x27, x22, x20",
"eor w27, w22, w20",
"mov x26, x4",
"cfinv",
"sbcs xzr, x22, x20",
@@ -1265,7 +1265,7 @@
"ExpectedArm64ASM": [
"mov x20, x7",
"sub x7, x20, x5",
"eor x27, x20, x5",
"eor w27, w20, w5",
"mov x26, x7",
"cmp x20, x5",
"cfinv"
@@ -1329,7 +1329,7 @@
"ExpectedArm64ASM": [
"mov x20, x5",
"sub x5, x20, x7",
"eor x27, x20, x7",
"eor w27, w20, w7",
"mov x26, x5",
"cmp x20, x7",
"cfinv"
@@ -1435,7 +1435,7 @@
"mov x20, #0xffffffffffffffff",
"mov x21, x4",
"sub x4, x21, x20",
"eor x27, x21, x20",
"eor w27, w21, w20",
"mov x26, x4",
"cmp x21, x20",
"cfinv"
@@ -1636,7 +1636,7 @@
"Comment": "0x39",
"ExpectedArm64ASM": [
"sub x26, x7, x5",
"eor x27, x7, x5",
"eor w27, w7, w5",
"cmp x7, x5",
"cfinv"
]
@@ -1690,7 +1690,7 @@
],
"ExpectedArm64ASM": [
"sub x26, x5, x7",
"eor x27, x5, x7",
"eor w27, w5, w7",
"cmp x5, x7",
"cfinv"
]
@@ -1780,7 +1780,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"sub x26, x4, x20",
"eor x27, x4, x20",
"eor w27, w4, w20",
"cmp x4, x20",
"cfinv"
]
@@ -2127,7 +2127,7 @@
"sub x22, x23, x22, lsl #4",
"add x11, x11, x22",
"add x10, x10, x22",
"eor x27, x21, x20",
"eor w27, w21, w20",
"cmp x21, x20",
"cfinv"
]
@@ -2208,7 +2208,7 @@
"ldr x21, [x11]",
"ldr x22, [x10]",
"sub x26, x22, x21",
"eor x27, x22, x21",
"eor w27, w22, w21",
"cmp x22, x21",
"cfinv",
"sub x5, x5, #0x1 (1)",
@@ -2294,7 +2294,7 @@
"ldr x21, [x11]",
"ldr x22, [x10]",
"sub x26, x22, x21",
"eor x27, x22, x21",
"eor w27, w22, w21",
"cmp x22, x21",
"cfinv",
"sub x5, x5, #0x1 (1)",
@@ -2424,7 +2424,7 @@
"mov w22, #0x8",
"sub x21, x22, x21, lsl #4",
"add x11, x11, x21",
"eor x27, x4, x20",
"eor w27, w4, w20",
"cmp x4, x20",
"cfinv"
]
@@ -2501,7 +2501,7 @@
"cbz x5, #+0x28",
"ldr x21, [x11]",
"sub x26, x4, x21",
"eor x27, x4, x21",
"eor w27, w4, w21",
"cmp x4, x21",
"cfinv",
"sub x5, x5, #0x1 (1)",
@@ -2582,7 +2582,7 @@
"cbz x5, #+0x28",
"ldr x21, [x11]",
"sub x26, x4, x21",
"eor x27, x4, x21",
"eor w27, w4, w21",
"cmp x4, x21",
"cfinv",
"sub x5, x5, #0x1 (1)",
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+5 -5
View File
@@ -835,7 +835,7 @@
"mov x20, #0xffffffffffffffff",
"mov x21, x4",
"sub x4, x21, #0x1 (1)",
"eor x27, x21, x20",
"eor w27, w21, w20",
"mov x26, x4",
"cmn x21, x20"
]
@@ -883,7 +883,7 @@
"add x21, x20, x21",
"mov x22, x4",
"add x4, x22, x21",
"eor x27, x22, x20",
"eor w27, w22, w20",
"mov x26, x4",
"adcs xzr, x22, x20"
]
@@ -913,7 +913,7 @@
"add x21, x20, x21",
"mov x22, x4",
"sub x4, x22, x21",
"eor x27, x22, x20",
"eor w27, w22, w20",
"mov x26, x4",
"cfinv",
"sbcs xzr, x22, x20",
@@ -958,7 +958,7 @@
"mov x20, #0xffffffffffffffff",
"mov x21, x4",
"sub x4, x21, x20",
"eor x27, x21, x20",
"eor w27, w21, w20",
"mov x26, x4",
"cmp x21, x20",
"cfinv"
@@ -1001,7 +1001,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"sub x26, x4, x20",
"eor x27, x4, x20",
"eor w27, w4, w20",
"cmp x4, x20",
"cfinv"
]
unittests/InstructionCountCI/FlagM/Secondary.json
+4 -4
View File
@@ -1071,7 +1071,7 @@
"ExpectedArm64ASM": [
"mov x20, x5",
"sub x26, x4, x20",
"eor x27, x4, x20",
"eor w27, w4, w20",
"cmp x4, x20",
"cfinv",
"mov x4, x20",
@@ -1087,7 +1087,7 @@
"casal x1, x7, [x20]",
"mov x4, x1",
"sub x26, x20, x4",
"eor x27, x20, x4",
"eor w27, w20, w4",
"cmp x20, x4",
"cfinv"
]
@@ -1610,7 +1610,7 @@
"mov x21, x7",
"add x4, x20, x21",
"mov x7, x20",
"eor x27, x20, x21",
"eor w27, w20, w21",
"mov x26, x4",
"cmn x20, x21"
]
@@ -1622,7 +1622,7 @@
"mov x20, x7",
"ldaddal x20, x7, [x4]",
"add x26, x7, x20",
"eor x27, x7, x20",
"eor w27, w7, w20",
"cmn x7, x20"
]
},
unittests/InstructionCountCI/Primary.json
+21 -21
View File
@@ -53,7 +53,7 @@
"ExpectedArm64ASM": [
"mov x20, x7",
"add x7, x20, x5",
"eor x27, x20, x5",
"eor w27, w20, w5",
"mov x26, x7",
"cmn x20, x5"
]
@@ -113,7 +113,7 @@
"ExpectedArm64ASM": [
"mov x20, x5",
"add x5, x20, x7",
"eor x27, x20, x7",
"eor w27, w20, w7",
"mov x26, x5",
"cmn x20, x7"
]
@@ -211,7 +211,7 @@
"mov x20, #0xffffffffffffffff",
"mov x21, x4",
"sub x4, x21, #0x1 (1)",
"eor x27, x21, x20",
"eor w27, w21, w20",
"mov x26, x4",
"cmn x21, x20"
]
@@ -464,7 +464,7 @@
"add x20, x5, x20",
"mov x21, x7",
"add x7, x21, x20",
"eor x27, x21, x5",
"eor w27, w21, w5",
"mov x26, x7",
"adcs xzr, x21, x5"
]
@@ -561,7 +561,7 @@
"add x20, x7, x20",
"mov x21, x5",
"add x5, x21, x20",
"eor x27, x21, x7",
"eor w27, w21, w7",
"mov x26, x5",
"adcs xzr, x21, x7"
]
@@ -721,7 +721,7 @@
"add x21, x20, x21",
"mov x22, x4",
"add x4, x22, x21",
"eor x27, x22, x20",
"eor w27, w22, w20",
"mov x26, x4",
"adcs xzr, x22, x20"
]
@@ -812,7 +812,7 @@
"add x20, x5, x20",
"mov x21, x7",
"sub x7, x21, x20",
"eor x27, x21, x5",
"eor w27, w21, w5",
"mov x26, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -921,7 +921,7 @@
"add x20, x7, x20",
"mov x21, x5",
"sub x5, x21, x20",
"eor x27, x21, x7",
"eor w27, w21, w7",
"mov x26, x5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1105,7 +1105,7 @@
"add x21, x20, x21",
"mov x22, x4",
"sub x4, x22, x21",
"eor x27, x22, x20",
"eor w27, w22, w20",
"mov x26, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
@@ -1318,7 +1318,7 @@
"ExpectedArm64ASM": [
"mov x20, x7",
"sub x7, x20, x5",
"eor x27, x20, x5",
"eor w27, w20, w5",
"mov x26, x7",
"cmp x20, x5",
"mrs x20, nzcv",
@@ -1390,7 +1390,7 @@
"ExpectedArm64ASM": [
"mov x20, x5",
"sub x5, x20, x7",
"eor x27, x20, x7",
"eor w27, w20, w7",
"mov x26, x5",
"cmp x20, x7",
"mrs x20, nzcv",
@@ -1512,7 +1512,7 @@
"mov x20, #0xffffffffffffffff",
"mov x21, x4",
"sub x4, x21, x20",
"eor x27, x21, x20",
"eor w27, w21, w20",
"mov x26, x4",
"cmp x21, x20",
"mrs x20, nzcv",
@@ -1721,7 +1721,7 @@
"Comment": "0x39",
"ExpectedArm64ASM": [
"sub x26, x7, x5",
"eor x27, x7, x5",
"eor w27, w7, w5",
"cmp x7, x5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1783,7 +1783,7 @@
],
"ExpectedArm64ASM": [
"sub x26, x5, x7",
"eor x27, x5, x7",
"eor w27, w5, w7",
"cmp x5, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1889,7 +1889,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"sub x26, x4, x20",
"eor x27, x4, x20",
"eor w27, w4, w20",
"cmp x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -3231,7 +3231,7 @@
"sub x22, x23, x22, lsl #4",
"add x11, x11, x22",
"add x10, x10, x22",
"eor x27, x21, x20",
"eor w27, w21, w20",
"cmp x21, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -3320,7 +3320,7 @@
"ldr x21, [x11]",
"ldr x22, [x10]",
"sub x26, x22, x21",
"eor x27, x22, x21",
"eor w27, w22, w21",
"cmp x22, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
@@ -3414,7 +3414,7 @@
"ldr x21, [x11]",
"ldr x22, [x10]",
"sub x26, x22, x21",
"eor x27, x22, x21",
"eor w27, w22, w21",
"cmp x22, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
@@ -3798,7 +3798,7 @@
"mov w22, #0x8",
"sub x21, x22, x21, lsl #4",
"add x11, x11, x21",
"eor x27, x4, x20",
"eor w27, w4, w20",
"cmp x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -3883,7 +3883,7 @@
"cbz x5, #+0x30",
"ldr x21, [x11]",
"sub x26, x4, x21",
"eor x27, x4, x21",
"eor w27, w4, w21",
"cmp x4, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
@@ -3972,7 +3972,7 @@
"cbz x5, #+0x30",
"ldr x21, [x11]",
"sub x26, x4, x21",
"eor x27, x4, x21",
"eor w27, w4, w21",
"cmp x4, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
unittests/InstructionCountCI/PrimaryGroup.json
+5 -5
View File
@@ -898,7 +898,7 @@
"mov x20, #0xffffffffffffffff",
"mov x21, x4",
"sub x4, x21, #0x1 (1)",
"eor x27, x21, x20",
"eor w27, w21, w20",
"mov x26, x4",
"cmn x21, x20"
]
@@ -946,7 +946,7 @@
"add x21, x20, x21",
"mov x22, x4",
"add x4, x22, x21",
"eor x27, x22, x20",
"eor w27, w22, w20",
"mov x26, x4",
"adcs xzr, x22, x20"
]
@@ -980,7 +980,7 @@
"add x21, x20, x21",
"mov x22, x4",
"sub x4, x22, x21",
"eor x27, x22, x20",
"eor w27, w22, w20",
"mov x26, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
@@ -1031,7 +1031,7 @@
"mov x20, #0xffffffffffffffff",
"mov x21, x4",
"sub x4, x21, x20",
"eor x27, x21, x20",
"eor w27, w21, w20",
"mov x26, x4",
"cmp x21, x20",
"mrs x20, nzcv",
@@ -1078,7 +1078,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"sub x26, x4, x20",
"eor x27, x4, x20",
"eor w27, w4, w20",
"cmp x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
unittests/InstructionCountCI/Secondary.json
+3 -3
View File
@@ -2011,7 +2011,7 @@
"casal x1, x7, [x20]",
"mov x4, x1",
"sub x26, x20, x4",
"eor x27, x20, x4",
"eor w27, w20, w4",
"cmp x20, x4",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -2623,7 +2623,7 @@
"mov x21, x7",
"add x4, x20, x21",
"mov x7, x20",
"eor x27, x20, x21",
"eor w27, w20, w21",
"mov x26, x4",
"cmn x20, x21"
]
@@ -2635,7 +2635,7 @@
"mov x20, x7",
"ldaddal x20, x7, [x4]",
"add x26, x7, x20",
"eor x27, x7, x20",
"eor w27, w7, w20",
"cmn x7, x20"
]
},