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Merge pull request #2212 from lioncash/comiss

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OpcodeDispatcher: Handle VCOMISD/VCOMISS/VUCOMISD/VUCOMISS
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Ryan Houdek authored and GitHub committed 2022-12-07 14:38:49 -08:00
2 parents a98920d4e4 4aa0f3d0a4
commit 7ac21e794d
6 files changed
+253 -4
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External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+5
View File
@@ -5821,6 +5821,11 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(1, 0b00, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp},
{OPD(1, 0b01, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp},
{OPD(1, 0b00, 0x2E), 1, &OpDispatchBuilder::UCOMISxOp<4>},
{OPD(1, 0b01, 0x2E), 1, &OpDispatchBuilder::UCOMISxOp<8>},
{OPD(1, 0b00, 0x2F), 1, &OpDispatchBuilder::UCOMISxOp<4>},
{OPD(1, 0b01, 0x2F), 1, &OpDispatchBuilder::UCOMISxOp<8>},
{OPD(1, 0b00, 0x54), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VAND, 16>},
{OPD(1, 0b01, 0x54), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VAND, 16>},
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
Vendored
+4 -4
View File
@@ -130,11 +130,11 @@ void InitializeVEXTables() {
{OPD(1, 0b10, 0x2D), 1, X86InstInfo{"VCVTSS2SI", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b11, 0x2D), 1, X86InstInfo{"VCVTSD2SI", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b00, 0x2E), 1, X86InstInfo{"VUCOMISS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0x2E), 1, X86InstInfo{"VUCOMISD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b00, 0x2E), 1, X86InstInfo{"VUCOMISS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0x2E), 1, X86InstInfo{"VUCOMISD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b00, 0x2F), 1, X86InstInfo{"VUCOMISS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0x2F), 1, X86InstInfo{"VUCOMISD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b00, 0x2F), 1, X86InstInfo{"VCOMISS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0x2F), 1, X86InstInfo{"VCOMISD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b00, 0x58), 1, X86InstInfo{"VADDPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0x58), 1, X86InstInfo{"VADDPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
unittests/ASM/VEX/vcomisd.asm
+61
View File
@@ -0,0 +1,61 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"RAX": "0x4700",
"RBX": "0x0300"
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovaps xmm0, [rdx + 16 * 0]
vcomisd xmm0, [rdx + 16 * 1] ; 1.0 <comp> 4.0
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000100
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 00000000
; 7: SF - 00000000 <- 0
; ================
; 00000111
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
mov rbx, rax
vcomisd xmm0, [rdx + 16 * 2] ; 1.0 <comp> NaN
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000100
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 01000000
; 7: SF - 00000000 <- 0
; ================
; 01000111
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
hlt
align 16
.data:
dq 0x3FF0000000000000
dq 0x4000000000000000
dq 0x4010000000000000
dq 0x4010000000000000
dq 0x7FF8000000000000
dq 0x4010000000000000
unittests/ASM/VEX/vcomiss.asm
+61
View File
@@ -0,0 +1,61 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"RAX": "0x4700",
"RBX": "0x0300"
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovaps xmm0, [rdx + 16 * 0]
vcomiss xmm0, [rdx + 16 * 1]
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000000
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 00000000
; 7: SF - 00000000 <- 0
; ================
; 00000011
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
mov rbx, rax
vcomiss xmm0, [rdx + 16 * 2]
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000100
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 01000000
; 7: SF - 00000000 <- 0
; ================
; 01000111
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
hlt
align 16
.data:
dq 0x515253543F800000
dq 0x5152535440000000
dq 0x5152535440800000
dq 0x5152535440800000
dq 0x515253547FC00000
dq 0x5152535440800000
unittests/ASM/VEX/vucomisd.asm
+61
View File
@@ -0,0 +1,61 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"RAX": "0x4700",
"RBX": "0x0300"
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovaps xmm0, [rdx + 16 * 0]
vucomisd xmm0, [rdx + 16 * 1] ; 1.0 <comp> 4.0
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000000
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 00000000
; 7: SF - 00000000 <- 0
; ================
; 00000011
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
mov rbx, rax
vucomisd xmm0, [rdx + 16 * 2] ; 1.0 <comp> NaN
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000100
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 01000000
; 7: SF - 00000000 <- 0
; ================
; 01000111
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
hlt
align 16
.data:
dq 0x3FF0000000000000
dq 0x4000000000000000
dq 0x4010000000000000
dq 0x4010000000000000
dq 0x7FF8000000000000
dq 0x4010000000000000
unittests/ASM/VEX/vucomiss.asm
+61
View File
@@ -0,0 +1,61 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"RAX": "0x4700",
"RBX": "0x0300"
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovaps xmm0, [rdx + 16 * 0]
vucomiss xmm0, [rdx + 16 * 1]
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000000
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 00000000
; 7: SF - 00000000 <- 0
; ================
; 00000011
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
mov rbx, rax
vucomiss xmm0, [rdx + 16 * 2]
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000100
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 01000000
; 7: SF - 00000000 <- 0
; ================
; 01000111
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
hlt
align 16
.data:
dq 0x515253543F800000
dq 0x5152535440000000
dq 0x5152535440800000
dq 0x5152535440800000
dq 0x515253547FC00000
dq 0x5152535440800000