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instcountci: Add instcountci for fnstsw from fast path
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Paulo Matos committed
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4227e012aa
commit
9a8e7eaace
1 file changed
+166
-2
@@ -11725,7 +11725,7 @@
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]
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},
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"fld and fnstsw": {
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"ExpectedInstructionCount": 19,
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"ExpectedInstructionCount": 163,
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"x86Insts": [
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"fld dword [rax]",
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"fld dword [rax + 4]",
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@@ -11733,7 +11733,171 @@
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"fld dword [rax + 12]",
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"fnstsw [rbx]"
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],
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"ExpectedArm64ASM": []
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"ExpectedArm64ASM": [
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"ldr s2, [x4]",
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"mrs x0, nzcv",
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"str w0, [x28, #1000]",
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"stp x4, x5, [x28, #280]",
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"stp x6, x7, [x28, #296]",
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"str x8, [x28, #312]",
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"stp x16, x17, [x28, #376]",
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"sub sp, sp, #0x70 (112)",
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"mov x0, sp",
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"st1 {v2.2d, v3.2d}, [x0], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
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"str x30, [x0], #16",
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"fmov s0, s2",
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"ldrh w0, [x28, #1296]",
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"ldr x1, [x28, #1424]",
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"blr x1",
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"ldr w4, [x28, #1000]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #280]",
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"ldp x6, x7, [x28, #296]",
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"ldr x8, [x28, #312]",
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"ldp x16, x17, [x28, #376]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ldr x30, [sp], #16",
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"eor v2.16b, v2.16b, v2.16b",
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"mov v2.d[0], x0",
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"mov v2.h[4], w1",
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"ldr s3, [x4, #4]",
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"mrs x0, nzcv",
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"str w0, [x28, #1000]",
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"stp x4, x5, [x28, #280]",
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"stp x6, x7, [x28, #296]",
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"str x8, [x28, #312]",
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"stp x16, x17, [x28, #376]",
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"sub sp, sp, #0x70 (112)",
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"mov x0, sp",
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"st1 {v2.2d, v3.2d}, [x0], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
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"str x30, [x0], #16",
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"fmov s0, s3",
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"ldrh w0, [x28, #1296]",
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"ldr x1, [x28, #1424]",
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"blr x1",
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"ldr w4, [x28, #1000]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #280]",
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"ldp x6, x7, [x28, #296]",
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"ldr x8, [x28, #312]",
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"ldp x16, x17, [x28, #376]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ldr x30, [sp], #16",
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"eor v3.16b, v3.16b, v3.16b",
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"mov v3.d[0], x0",
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"mov v3.h[4], w1",
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"mov w20, #0x8",
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"ldr s4, [x4, #8]",
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"mrs x0, nzcv",
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"str w0, [x28, #1000]",
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"stp x4, x5, [x28, #280]",
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"stp x6, x7, [x28, #296]",
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"str x8, [x28, #312]",
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"stp x16, x17, [x28, #376]",
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"sub sp, sp, #0x70 (112)",
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"mov x0, sp",
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"st1 {v2.2d, v3.2d}, [x0], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
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"str x30, [x0], #16",
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"fmov s0, s4",
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"ldrh w0, [x28, #1296]",
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"ldr x1, [x28, #1424]",
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"blr x1",
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"ldr w4, [x28, #1000]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #280]",
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"ldp x6, x7, [x28, #296]",
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"ldr x8, [x28, #312]",
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"ldp x16, x17, [x28, #376]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ldr x30, [sp], #16",
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"eor v4.16b, v4.16b, v4.16b",
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"mov v4.d[0], x0",
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"mov v4.h[4], w1",
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"ldr s5, [x4, #12]",
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"mrs x0, nzcv",
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"str w0, [x28, #1000]",
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"stp x4, x5, [x28, #280]",
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"stp x6, x7, [x28, #296]",
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"str x8, [x28, #312]",
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"stp x16, x17, [x28, #376]",
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"sub sp, sp, #0x70 (112)",
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"mov x0, sp",
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"st1 {v2.2d, v3.2d}, [x0], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
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"str x30, [x0], #16",
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"fmov s0, s5",
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"ldrh w0, [x28, #1296]",
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"ldr x1, [x28, #1424]",
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"blr x1",
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"ldr w4, [x28, #1000]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #280]",
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"ldp x6, x7, [x28, #296]",
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"ldr x8, [x28, #312]",
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"ldp x16, x17, [x28, #376]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ldr x30, [sp], #16",
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"eor v5.16b, v5.16b, v5.16b",
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"mov v5.d[0], x0",
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"mov v5.h[4], w1",
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"ldrb w21, [x28, #1019]",
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"sub w21, w21, #0x4 (4)",
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"and w21, w21, #0x7",
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"strb w21, [x28, #1019]",
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"add x0, x28, x21, lsl #4",
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"str q5, [x0, #1040]",
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"add w22, w21, #0x1 (1)",
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"and w22, w22, #0x7",
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"add x0, x28, x22, lsl #4",
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"str q4, [x0, #1040]",
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"add w23, w21, #0x2 (2)",
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"and w23, w23, #0x7",
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"add x0, x28, x23, lsl #4",
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"str q3, [x0, #1040]",
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"add w24, w21, #0x3 (3)",
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"and w24, w24, #0x7",
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"add x0, x28, x24, lsl #4",
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"str q2, [x0, #1040]",
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"sub w25, w20, w21",
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"ldrb w30, [x28, #1298]",
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"mov w18, #0xf0f",
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"lsr w25, w18, w25",
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"orr w25, w30, w25",
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"strb w25, [x28, #1298]",
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"ldrb w25, [x28, #1016]",
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"ldrb w30, [x28, #1017]",
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"ldrb w18, [x28, #1018]",
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"ldrb w20, [x28, #1022]",
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"lsl x25, x25, #8",
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"orr x25, x25, x30, lsl #9",
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"orr x25, x25, x18, lsl #10",
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"orr x20, x25, x20, lsl #14",
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"ldrb w25, [x28, #1019]",
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"bfi x20, x25, #11, #3",
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"strh w20, [x7]",
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"add x0, x28, x21, lsl #4",
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"str q5, [x0, #1040]",
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"add x0, x28, x22, lsl #4",
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"str q4, [x0, #1040]",
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"add x0, x28, x23, lsl #4",
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"str q3, [x0, #1040]",
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"add x0, x28, x24, lsl #4",
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"str q2, [x0, #1040]",
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"mov w20, #0x8",
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"sub w20, w20, w21",
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"ldrb w21, [x28, #1298]",
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"mov w22, #0xf0f",
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"lsr w20, w22, w20",
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"orr w20, w21, w20",
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"strb w20, [x28, #1298]"
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]
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},
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"ffree st0": {
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"ExpectedInstructionCount": 6,
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