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InstCountCI: Update for movmskps optimization

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Ryan Houdek committed 2023-08-27 21:07:20 -07:00
1 parent 514a8223d9
commit d6864871ed
7 files changed
+56 -65
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unittests/InstructionCountCI/PrimaryGroup.json
+4 -4
View File
@@ -3603,7 +3603,7 @@
"mov x0, x6",
"mov x1, x20",
"mov x2, x7",
"ldr x3, [x28, #1760]",
"ldr x3, [x28, #1768]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -3614,7 +3614,7 @@
"mov x0, x6",
"mov x1, x20",
"mov x2, x7",
"ldr x3, [x28, #1776]",
"ldr x3, [x28, #1784]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -3678,7 +3678,7 @@
"mov x0, x6",
"mov x1, x20",
"mov x2, x7",
"ldr x3, [x28, #1768]",
"ldr x3, [x28, #1776]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -3691,7 +3691,7 @@
"mov x0, x6",
"mov x1, x20",
"mov x2, x7",
"ldr x3, [x28, #1784]",
"ldr x3, [x28, #1792]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
unittests/InstructionCountCI/Secondary.json
+18 -39
View File
@@ -1000,50 +1000,29 @@
]
},
"movmskps eax, xmm0": {
"ExpectedInstructionCount": 17,
"Optimal": "No",
"ExpectedInstructionCount": 6,
"Optimal": "Yes",
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, v16.s[0]",
"ubfx x21, x21, #31, #1",
"orr x20, x20, x21",
"mov w21, v16.s[1]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #1",
"orr x20, x20, x21",
"mov w21, v16.s[2]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #2",
"orr x20, x20, x21",
"mov w21, v16.s[3]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #3",
"orr x20, x20, x21",
"ubfx x4, x20, #0, #32"
"ushr v4.4s, v16.4s, #31",
"ldr x0, [x28, #1600]",
"ldr q5, [x0]",
"ushl v4.4s, v4.4s, v5.4s",
"addv s4, v4.4s",
"mov w4, v4.s[0]"
]
},
"movmskps rax, xmm0": {
"ExpectedInstructionCount": 16,
"Optimal": "No",
"ExpectedInstructionCount": 6,
"Optimal": "Yes",
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, v16.s[0]",
"ubfx x21, x21, #31, #1",
"orr x20, x20, x21",
"mov w21, v16.s[1]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #1",
"orr x20, x20, x21",
"mov w21, v16.s[2]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #2",
"orr x20, x20, x21",
"mov w21, v16.s[3]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #3",
"orr x4, x20, x21"
"ushr v4.4s, v16.4s, #31",
"ldr x0, [x28, #1600]",
"ldr q5, [x0]",
"ushl v4.4s, v4.4s, v5.4s",
"addv s4, v4.4s",
"mov w4, v4.s[0]"
]
},
"sqrtps xmm0, xmm1": {
@@ -1458,7 +1437,7 @@
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr x0, [x28, #1600]",
"ldr x0, [x28, #1608]",
"ldr d5, [x0, #16]",
"tbl v4.8b, {v4.16b}, v5.8b",
"str d4, [x28, #752]"
@@ -1470,7 +1449,7 @@
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d4, [x4]",
"ldr x0, [x28, #1600]",
"ldr x0, [x28, #1608]",
"ldr d5, [x0, #16]",
"tbl v4.8b, {v4.16b}, v5.8b",
"str d4, [x28, #752]"
unittests/InstructionCountCI/Secondary_OpSize.json
+2 -2
View File
@@ -577,7 +577,7 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1616]",
"ldr x0, [x28, #1624]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b}, v4.16b"
]
@@ -592,7 +592,7 @@
],
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"ldr x0, [x28, #1616]",
"ldr x0, [x28, #1624]",
"ldr q5, [x0, #16]",
"tbl v16.16b, {v4.16b}, v5.16b"
]
unittests/InstructionCountCI/Secondary_REP.json
+1 -1
View File
@@ -390,7 +390,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1608]",
"ldr x0, [x28, #1616]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b}, v4.16b"
]
unittests/InstructionCountCI/Secondary_REPNE.json
+1 -1
View File
@@ -335,7 +335,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1600]",
"ldr x0, [x28, #1608]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b}, v4.16b"
]
unittests/InstructionCountCI/Secondary_SVE128.json
+24
View File
@@ -9,6 +9,30 @@
]
},
"Instructions": {
"movmskps eax, xmm0": {
"ExpectedInstructionCount": 5,
"Optimal": "Yes",
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v4.4s, v16.4s, #31",
"index z5.s, #0, #1",
"ushl v4.4s, v4.4s, v5.4s",
"addv s4, v4.4s",
"mov w4, v4.s[0]"
]
},
"movmskps rax, xmm0": {
"ExpectedInstructionCount": 5,
"Optimal": "Yes",
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v4.4s, v16.4s, #31",
"index z5.s, #0, #1",
"ushl v4.4s, v4.4s, v5.4s",
"addv s4, v4.4s",
"mov w4, v4.s[0]"
]
},
"psrlw mm0, mm1": {
"ExpectedInstructionCount": 6,
"Optimal": "No",
unittests/InstructionCountCI/VEX_map1.json
+6 -18
View File
@@ -522,30 +522,18 @@
]
},
"vmovmskps rax, xmm0": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": [
"Map 1 0b00 0x50 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z16.d",
"mov w20, #0x0",
"mov w21, v4.s[0]",
"ubfx x21, x21, #31, #1",
"orr x20, x20, x21",
"mov w21, v4.s[1]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #1",
"orr x20, x20, x21",
"mov w21, v4.s[2]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #2",
"orr x20, x20, x21",
"mov w21, v4.s[3]",
"ubfx x21, x21, #31, #1",
"lsl w21, w21, #3",
"orr x20, x20, x21",
"ubfx x4, x20, #0, #32"
"ushr v4.4s, v4.4s, #31",
"index z5.s, #0, #1",
"ushl v4.4s, v4.4s, v5.4s",
"addv s4, v4.4s",
"mov w4, v4.s[0]"
]
},
"vmovmskps rax, ymm0": {