steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-28 13:01:01 +01:00
Code Issues Packages Projects Releases 67 Wiki Activity

Removes a couple of unnecessary variables to improve reentrancy chances

Browse Source 
We still aren't 100% reentrant safe in the case that the cores are
interrupted while running, but this is a step in the right direction
This commit is contained in:
Ryan Houdek committed 2020-09-16 22:34:21 -07:00
1 parent 00f0047cff
commit e194aa28e4
4 files changed
+12 -24
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
Vendored
+6 -7
View File
@@ -575,10 +575,9 @@ aarch64::VRegister JITCore::GetDst(uint32_t Node) {
void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData) {
using namespace aarch64;
JumpTargets.clear();
CurrentIR = IR;
uint32_t SSACount = CurrentIR->GetSSACount();
uint32_t SSACount = IR->GetSSACount();
auto HeaderOp = CurrentIR->GetHeader();
auto HeaderOp = IR->GetHeader();
if (HeaderOp->ShouldInterpret) {
return reinterpret_cast<void*>(InterpreterFallbackHelperAddress);
}
@@ -626,13 +625,13 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
stp(TMP1, lr, MemOperand(sp, -16, PreIndex));
}
for (auto [BlockNode, BlockHeader] : CurrentIR->GetBlocks()) {
for (auto [BlockNode, BlockHeader] : IR->GetBlocks()) {
using namespace FEXCore::IR;
auto BlockIROp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
LogMan::Throw::A(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
{
uint32_t Node = CurrentIR->GetID(BlockNode);
uint32_t Node = IR->GetID(BlockNode);
auto IsTarget = JumpTargets.find(Node);
if (IsTarget == JumpTargets.end()) {
IsTarget = JumpTargets.try_emplace(Node).first;
@@ -641,8 +640,8 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
bind(&IsTarget->second);
}
for (auto [CodeNode, IROp] : CurrentIR->GetCode(BlockNode)) {
uint32_t ID = CurrentIR->GetID(CodeNode);
for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
uint32_t ID = IR->GetID(CodeNode);
// Execute handler
OpHandler Handler = OpHandlers[IROp->Op];
External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
Vendored
-1
View File
@@ -103,7 +103,6 @@ public:
private:
FEXCore::Context::Context *CTX;
FEXCore::Core::InternalThreadState *State;
FEXCore::IR::IRListView<true> const *CurrentIR;
std::map<IR::OrderedNodeWrapper::NodeOffsetType, aarch64::Label> JumpTargets;
External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
Vendored
+6 -14
View File
@@ -263,7 +263,6 @@ JITCore::JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadSt
, InitialCodeBuffer {Buffer}
{
CurrentCodeBuffer = &InitialCodeBuffer;
Stack.resize(9000 * 16 * 64);
RAPass = Thread->PassManager->GetRAPass();
@@ -417,10 +416,9 @@ Xbyak::Xmm JITCore::GetDst(uint32_t Node) {
void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData) {
JumpTargets.clear();
CurrentIR = IR;
uint32_t SSACount = CurrentIR->GetSSACount();
uint32_t SSACount = IR->GetSSACount();
auto HeaderOp = CurrentIR->GetHeader();
auto HeaderOp = IR->GetHeader();
if (HeaderOp->ShouldInterpret) {
return InterpreterFallbackHelperAddress;
}
@@ -432,11 +430,6 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
ThreadState->CTX->ClearCodeCache(ThreadState, HeaderOp->Entry);
}
uint64_t ListStackSize = SSACount * 16;
if (ListStackSize > Stack.size()) {
Stack.resize(ListStackSize);
}
void *Entry = getCurr<void*>();
LogMan::Throw::A(RAPass->HasFullRA(), "Needs RA");
@@ -507,14 +500,13 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
ret();
};
for (auto [BlockNode, BlockHeader] : CurrentIR->GetBlocks()) {
for (auto [BlockNode, BlockHeader] : IR->GetBlocks()) {
using namespace FEXCore::IR;
{
auto BlockIROp = BlockHeader->CW<IROp_CodeBlock>();
LogMan::Throw::A(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
uint32_t Node = CurrentIR->GetID(BlockNode);
uint32_t Node = IR->GetID(BlockNode);
auto IsTarget = JumpTargets.find(Node);
if (IsTarget == JumpTargets.end()) {
IsTarget = JumpTargets.try_emplace(Node).first;
@@ -523,9 +515,9 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
L(IsTarget->second);
}
for (auto [CodeNode, IROp] : CurrentIR->GetCode(BlockNode)) {
for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
uint8_t OpSize = IROp->Size;
uint32_t Node = CurrentIR->GetID(CodeNode);
uint32_t Node = IR->GetID(CodeNode);
#ifdef DEBUG_RA
if (IROp->Op != IR::OP_BEGINBLOCK &&
External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h
Vendored
-2
View File
@@ -73,10 +73,8 @@ public:
private:
FEXCore::Context::Context *CTX;
FEXCore::Core::InternalThreadState *ThreadState;
FEXCore::IR::IRListView<true> const *CurrentIR;
std::unordered_map<IR::OrderedNodeWrapper::NodeOffsetType, Label> JumpTargets;
std::vector<uint8_t> Stack;
bool MemoryDebug = false;
/**