Merge pull request #124 from Sonicadvance1/fix_cache_clear_crash

Fixes crashes when code cache is cleared

External/FEXCore/Source/Interface/Core/Core.cpp

@@ -451,6 +451,12 @@ namespace FEXCore::Context {
     auto BlockMapPtr = Thread->BlockCache->AddBlockMapping(Address, Ptr);
     if (BlockMapPtr == 0) {
       Thread->BlockCache->ClearCache();
+
+      // Pull out the current IR we added and store it back after we cleared the rest of the list
+      // Needed in the case the the block mapping has aliased
+      auto IR = Thread->IRLists.find(Address)->second.release();
+      Thread->IRLists.clear();
+      Thread->IRLists.try_emplace(Address, IR);
       BlockMapPtr = Thread->BlockCache->AddBlockMapping(Address, Ptr);
       LogMan::Throw::A(BlockMapPtr, "Couldn't add mapping after clearing mapping cache");
     }
@@ -578,6 +584,10 @@ namespace FEXCore::Context {
     }
     else {
       IRList = IR->second.get();
+      auto Debugit = Thread->DebugData.find(GuestRIP);
+      if (Debugit != Thread->DebugData.end()) {
+        DebugData = &Debugit->second;
+      }
     }
 
     // Attempt to get the CPU backend to compile this code

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -110,7 +110,6 @@ void *InterpreterCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true
 
 void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
   auto IR = Thread->IRLists.find(Thread->State.State.rip);
-  auto DebugData = Thread->DebugData.find(Thread->State.State.rip);
   CurrentIR = IR->second.get();
 
   TmpOffset = 0; // Reset where we are in the temp data range
@@ -3843,7 +3842,10 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
     }
   }
 
-  Thread->Stats.InstructionsExecuted.fetch_add(DebugData->second.GuestInstructionCount);
+  auto DebugData = Thread->DebugData.find(Thread->State.State.rip);
+  if (DebugData != Thread->DebugData.end()) {
+    Thread->Stats.InstructionsExecuted.fetch_add(DebugData->second.GuestInstructionCount);
+  }
 }
 
 FEXCore::CPU::CPUBackend *CreateInterpreterCore(FEXCore::Context::Context *ctx) {

External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp

@@ -4458,7 +4458,9 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
 
   ready();
 
-  DebugData->HostCodeSize = reinterpret_cast<uintptr_t>(Exit) - reinterpret_cast<uintptr_t>(Entry);
+  if (DebugData) {
+    DebugData->HostCodeSize = reinterpret_cast<uintptr_t>(Exit) - reinterpret_cast<uintptr_t>(Entry);
+  }
   return Entry;
 }