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InstCountCI: Update tests with inline asm

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This will result in a decent amount of data churn but it's all
automated so it is a non-issue.
This commit is contained in:
Ryan Houdek committed 2023-08-16 13:38:45 -07:00
1 parent 8706f895d0
commit fd40e058e8
18 files changed
+48780 -1034
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unittests/InstructionCountCI/DDD.json
+195 -19
View File
@@ -21,6 +21,13 @@
"This lowers throughput from 1 IPC to 1/2IPC",
"This instruction implementation might not be correct.",
"0x0f 0x0f 0x0c"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"mov v4.h[1], v4.h[2]",
"sxtl v4.4s, v4.4h",
"scvtf v4.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pi2fd mm0, mm1": {
@@ -30,6 +37,11 @@
"FPConvert instruction using 128-bit conversion instead of 64-bit.",
"This lowers throughput from 1 IPC to 1/2IPC",
"0x0f 0x0f 0x0d"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"scvtf v4.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pf2iw mm0, mm1": {
@@ -40,6 +52,13 @@
"This lowers throughput from 1 IPC to 1/2IPC",
"This instruction implementation might not be correct.",
"0x0f 0x0f 0x1c"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"fcvtzs v4.4s, v4.4s",
"mov v4.h[1], v4.h[2]",
"sxtl v4.4s, v4.4h",
"str d4, [x28, #752]"
]
},
"pf2id mm0, mm1": {
@@ -49,6 +68,11 @@
"FPConvert instruction using 128-bit conversion instead of 64-bit.",
"This lowers throughput from 1 IPC to 1/2IPC",
"0x0f 0x0f 0x1d"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"fcvtzs v4.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pfrcpv mm0, mm1": {
@@ -57,6 +81,12 @@
"Comment": [
"FEAT_FPRES could make this more optimal",
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v4.4s, v0.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pfrsqrtv mm0, mm1": {
@@ -65,27 +95,68 @@
"Comment": [
"FEAT_FPRES could make this more optimal",
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v4.4s",
"fdiv v4.4s, v0.4s, v1.4s",
"str d4, [x28, #752]"
]
},
"pfnacc mm0, mm1": {
"ExpectedInstructionCount": 8,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x8a"
"Comment": "0x0f 0x0f 0x8a",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"dup v6.4s, v4.s[1]",
"dup v7.4s, v5.s[1]",
"fsub s4, s4, s6",
"fsub s5, s5, s7",
"mov v4.s[1], v5.s[0]",
"str d4, [x28, #752]"
]
},
"pfpnacc mm0, mm1": {
"ExpectedInstructionCount": 7,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x8e"
"Comment": "0x0f 0x0f 0x8e",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"dup v6.4s, v4.s[1]",
"fsub s4, s4, s6",
"faddp v5.4s, v5.4s, v5.4s",
"mov v4.s[1], v5.s[0]",
"str d4, [x28, #752]"
]
},
"pfcmpge mm0, mm1": {
"ExpectedInstructionCount": 4,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x90"
"Comment": "0x0f 0x0f 0x90",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmge v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pfmin mm0, mm1": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0x0f 0x0f 0x94"
"Comment": "0x0f 0x0f 0x94",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmgt v0.4s, v4.4s, v5.4s",
"mov v1.16b, v5.16b",
"bif v1.16b, v4.16b, v0.16b",
"mov v4.16b, v1.16b",
"str d4, [x28, #752]"
]
},
"pfrcp mm0, mm1": {
"ExpectedInstructionCount": 5,
@@ -93,6 +164,13 @@
"Comment": [
"FEAT_FPRES could make this more optimal",
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"fmov s0, #0x70 (1.0000)",
"fdiv s4, s0, s4",
"dup v4.4s, v4.s[0]",
"str d4, [x28, #752]"
]
},
"pfrsqrt mm0, mm1": {
@@ -101,72 +179,149 @@
"Comment": [
"FEAT_FPRES could make this more optimal",
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s4",
"fdiv s4, s0, s1",
"dup v4.4s, v4.s[0]",
"str d4, [x28, #752]"
]
},
"pfsub mm0, mm1": {
"ExpectedInstructionCount": 4,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x9a"
"Comment": "0x0f 0x0f 0x9a",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fsub v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pfadd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0x9e"
"Comment": "0x0f 0x0f 0x9e",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fadd v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pfcmpgt mm0, mm1": {
"ExpectedInstructionCount": 4,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa0"
"Comment": "0x0f 0x0f 0xa0",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmgt v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pfmax mm0, mm1": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0x0f 0x0f 0xa4"
"Comment": "0x0f 0x0f 0xa4",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmgt v0.4s, v4.4s, v5.4s",
"mov v1.16b, v5.16b",
"bit v1.16b, v4.16b, v0.16b",
"mov v4.16b, v1.16b",
"str d4, [x28, #752]"
]
},
"pfrcpit1 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa6"
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"str d4, [x28, #752]"
]
},
"pfrcpit1 mm0, mm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0x0f 0x0f 0xa6"
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"str d4, [x28, #752]"
]
},
"pfrsqit1 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xa7"
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"str d4, [x28, #752]"
]
},
"pfrsqit1 mm0, mm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0x0f 0x0f 0xa7"
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"str d4, [x28, #752]"
]
},
"pfsubr mm0, mm1": {
"ExpectedInstructionCount": 4,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xaa"
"Comment": "0x0f 0x0f 0xaa",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fsub v4.4s, v4.4s, v5.4s",
"str d4, [x28, #752]"
]
},
"pfcmpeq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xb0"
"Comment": "0x0f 0x0f 0xb0",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fcmeq v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pfmul mm0, mm1": {
"ExpectedInstructionCount": 4,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xb4"
"Comment": "0x0f 0x0f 0xb4",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"fmul v4.4s, v5.4s, v4.4s",
"str d4, [x28, #752]"
]
},
"pfrcpit2 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xb6"
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"str d4, [x28, #752]"
]
},
"pfrcpit2 mm0, mm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0x0f 0x0f 0xb6"
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"str d4, [x28, #752]"
]
},
"db 0x0f, 0x0f, 0xc1, 0xb7": {
"ExpectedInstructionCount": 8,
@@ -176,17 +331,38 @@
"pmulhrw mm0, mm1",
"Might be able to use sqdmulh",
"0x0f 0x0f 0xb7"
],
"ExpectedArm64ASM": [
"ldr d4, [x28, #752]",
"ldr d5, [x28, #768]",
"smull v4.4s, v4.4h, v5.4h",
"mov x20, #0x800000008000",
"dup v5.2d, x20",
"add v4.4s, v4.4s, v5.4s",
"shrn v4.4h, v4.4s, #16",
"str d4, [x28, #752]"
]
},
"pswapd mm0, mm1": {
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xbb"
"Comment": "0x0f 0x0f 0xbb",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"rev64 v4.2s, v4.2s",
"str d4, [x28, #752]"
]
},
"pavgusb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Optimal": "Yes",
"Comment": "0x0f 0x0f 0xbf"
"Comment": "0x0f 0x0f 0xbf",
"ExpectedArm64ASM": [
"ldr d4, [x28, #768]",
"ldr d5, [x28, #752]",
"urhadd v4.16b, v5.16b, v4.16b",
"str d4, [x28, #752]"
]
}
}
}
unittests/InstructionCountCI/H0F38.json
+753 -1
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unittests/InstructionCountCI/H0F3A.json
+851 -1
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unittests/InstructionCountCI/Primary.json
+4224 -208
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unittests/InstructionCountCI/PrimaryGroup.json
+3320 -172
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unittests/InstructionCountCI/Primary_32Bit.json
+651 -22
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@@ -11,107 +11,658 @@
"push es": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0x06"
"Comment": "0x06",
"ExpectedArm64ASM": [
"mov w20, w8",
"sub x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"ldrh w21, [x28, #136]",
"str w21, [x20]"
]
},
"pop es": {
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x07"
"Comment": "0x07",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #136]",
"ubfx x20, x21, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #152]"
]
},
"push cs": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0x0e"
"Comment": "0x0e",
"ExpectedArm64ASM": [
"mov w20, w8",
"sub x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"ldrh w21, [x28, #138]",
"str w21, [x20]"
]
},
"push ss": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0x16"
"Comment": "0x16",
"ExpectedArm64ASM": [
"mov w20, w8",
"sub x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"ldrh w21, [x28, #140]",
"str w21, [x20]"
]
},
"pop ss": {
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x17"
"Comment": "0x17",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #140]",
"ubfx x20, x21, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #160]"
]
},
"push ds": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0x1e"
"Comment": "0x1e",
"ExpectedArm64ASM": [
"mov w20, w8",
"sub x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"ldrh w21, [x28, #142]",
"str w21, [x20]"
]
},
"pop ds": {
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x1f"
"Comment": "0x1f",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #142]",
"ubfx x20, x21, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #164]"
]
},
"daa": {
"ExpectedInstructionCount": 70,
"Optimal": "No",
"Comment": "0x27"
"Comment": "0x27",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx x21, x20, #29, #1",
"ldrb w22, [x28, #708]",
"mov w23, w4",
"uxtb x23, w23",
"mov w24, #0x0",
"bfi w20, w24, #29, #1",
"str w20, [x28, #728]",
"and x20, x23, #0xf",
"cmp x20, #0x9 (9)",
"cset x20, hi",
"orr x20, x22, x20",
"cbnz x20, #+0x10",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"b #+0x38",
"add x20, x23, #0x6 (6)",
"mov w22, w4",
"mov w0, w22",
"bfxil w0, w20, #0, #8",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"ldr w20, [x28, #728]",
"ubfx x22, x20, #29, #1",
"orr w22, w21, w22",
"bfi w20, w22, #29, #1",
"orr w22, wzr, #0x1",
"strb w22, [x28, #708]",
"str w20, [x28, #728]",
"cmp x23, #0x99 (153)",
"cset x20, hi",
"orr x20, x21, x20",
"cbnz x20, #+0x20",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"lsr w20, w0, #0",
"str w20, [x28, #728]",
"b #+0x3c",
"mov w20, w4",
"uxtb x20, w20",
"add x20, x20, #0x60 (96)",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #8",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"orr w20, wzr, #0x1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"lsr w20, w0, #0",
"str w20, [x28, #728]",
"mov w20, w4",
"uxtb x20, w20",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"lsr w21, w0, #0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"das": {
"ExpectedInstructionCount": 70,
"Optimal": "No",
"Comment": "0x2f"
"Comment": "0x2f",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx x21, x20, #29, #1",
"ldrb w22, [x28, #708]",
"mov w23, w4",
"uxtb x23, w23",
"mov w24, #0x0",
"bfi w20, w24, #29, #1",
"str w20, [x28, #728]",
"and x20, x23, #0xf",
"cmp x20, #0x9 (9)",
"cset x20, hi",
"orr x20, x22, x20",
"cbnz x20, #+0x10",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"b #+0x38",
"sub x20, x23, #0x6 (6)",
"mov w22, w4",
"mov w0, w22",
"bfxil w0, w20, #0, #8",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"ldr w20, [x28, #728]",
"ubfx x22, x20, #29, #1",
"orr w22, w21, w22",
"bfi w20, w22, #29, #1",
"orr w22, wzr, #0x1",
"strb w22, [x28, #708]",
"str w20, [x28, #728]",
"cmp x23, #0x99 (153)",
"cset x20, hi",
"orr x20, x21, x20",
"cbnz x20, #+0x20",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"lsr w20, w0, #0",
"str w20, [x28, #728]",
"b #+0x3c",
"mov w20, w4",
"uxtb x20, w20",
"sub x20, x20, #0x60 (96)",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #8",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"orr w20, wzr, #0x1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"lsr w20, w0, #0",
"str w20, [x28, #728]",
"mov w20, w4",
"uxtb x20, w20",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"lsr w21, w0, #0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"aaa": {
"ExpectedInstructionCount": 36,
"Optimal": "No",
"Comment": "0x37"
"Comment": "0x37",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"mov w21, w4",
"uxtb x21, w21",
"mov w22, w4",
"uxth x22, w22",
"and x21, x21, #0xf",
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x38",
"mov w20, #0xff0f",
"and x20, x22, x20",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"bfi w21, w20, #29, #1",
"strb w20, [x28, #708]",
"str w21, [x28, #728]",
"b #+0x38",
"add x20, x22, #0x106 (262)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"orr w20, wzr, #0x1",
"ldr w21, [x28, #728]",
"bfi w21, w20, #29, #1",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
},
"aas": {
"ExpectedInstructionCount": 37,
"Optimal": "No",
"Comment": "0x3f"
"Comment": "0x3f",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"mov w21, w4",
"uxtb x21, w21",
"mov w22, w4",
"uxth x22, w22",
"and x21, x21, #0xf",
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x38",
"mov w20, #0xff0f",
"and x20, x22, x20",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"bfi w21, w20, #29, #1",
"strb w20, [x28, #708]",
"str w21, [x28, #728]",
"b #+0x3c",
"sub x20, x22, #0x6 (6)",
"sub x20, x20, #0x100 (256)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"orr w20, wzr, #0x1",
"ldr w21, [x28, #728]",
"bfi w21, w20, #29, #1",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
},
"inc ax": {
"ExpectedInstructionCount": 27,
"Optimal": "No",
"Comment": "0x40"
"Comment": "0x40",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxth x20, w20",
"add w21, w20, #0x1 (1)",
"mov w22, w4",
"bfxil w22, w21, #0, #16",
"bfxil x4, x22, #0, #32",
"uxth x21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"ubfx x22, x22, #4, #1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx x22, x22, #29, #1",
"lsl w23, w21, #16",
"and x23, x23, #0x80000000",
"cmp x21, #0x0 (0)",
"cset x24, eq",
"orr x23, x23, x24, lsl #30",
"orr x22, x23, x22, lsl #29",
"eor w23, w20, #0x1",
"eor w20, w21, w20",
"bic w20, w20, w23",
"ubfx x20, x20, #15, #1",
"orr x20, x22, x20, lsl #28",
"str w20, [x28, #728]"
]
},
"inc eax": {
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "0x40"
"Comment": "0x40",
"ExpectedArm64ASM": [
"mov w20, w4",
"add w21, w20, #0x1 (1)",
"bfxil x4, x21, #0, #32",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"ubfx x22, x22, #4, #1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx x22, x22, #29, #1",
"tst w21, w21",
"mrs x23, nzcv",
"orr w22, w23, w22, lsl #29",
"eor w23, w20, #0x1",
"eor w20, w21, w20",
"bic w20, w20, w23",
"ubfx x20, x20, #31, #1",
"orr w20, w22, w20, lsl #28",
"str w20, [x28, #728]"
]
},
"dec ax": {
"ExpectedInstructionCount": 27,
"Optimal": "No",
"Comment": "0x48"
"Comment": "0x48",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxth x20, w20",
"sub w21, w20, #0x1 (1)",
"mov w22, w4",
"bfxil w22, w21, #0, #16",
"bfxil x4, x22, #0, #32",
"uxth x21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"ubfx x22, x22, #4, #1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx x22, x22, #29, #1",
"lsl w23, w21, #16",
"and x23, x23, #0x80000000",
"cmp x21, #0x0 (0)",
"cset x24, eq",
"orr x23, x23, x24, lsl #30",
"orr x22, x23, x22, lsl #29",
"eor w23, w20, #0x1",
"eor w20, w21, w20",
"and w20, w23, w20",
"ubfx x20, x20, #15, #1",
"orr x20, x22, x20, lsl #28",
"str w20, [x28, #728]"
]
},
"dec eax": {
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "0x48"
"Comment": "0x48",
"ExpectedArm64ASM": [
"mov w20, w4",
"sub w21, w20, #0x1 (1)",
"bfxil x4, x21, #0, #32",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"ubfx x22, x22, #4, #1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx x22, x22, #29, #1",
"tst w21, w21",
"mrs x23, nzcv",
"orr w22, w23, w22, lsl #29",
"eor w23, w20, #0x1",
"eor w20, w21, w20",
"and w20, w23, w20",
"ubfx x20, x20, #31, #1",
"orr w20, w22, w20, lsl #28",
"str w20, [x28, #728]"
]
},
"pusha": {
"ExpectedInstructionCount": "25",
"Optimal": "No",
"Comment": "0x60"
"Comment": "0x60",
"ExpectedArm64ASM": [
"mov w20, w8",
"sub x21, x20, #0x4 (4)",
"mov w22, w4",
"str w22, [x21]",
"sub x21, x21, #0x4 (4)",
"mov w22, w5",
"str w22, [x21]",
"sub x21, x21, #0x4 (4)",
"mov w22, w6",
"str w22, [x21]",
"sub x21, x21, #0x4 (4)",
"mov w22, w7",
"str w22, [x21]",
"sub x21, x21, #0x4 (4)",
"str w20, [x21]",
"sub x20, x21, #0x4 (4)",
"mov w21, w9",
"str w21, [x20]",
"sub x20, x20, #0x4 (4)",
"mov w21, w10",
"str w21, [x20]",
"sub x20, x20, #0x4 (4)",
"mov w21, w11",
"str w21, [x20]",
"bfxil x8, x20, #0, #32"
]
},
"pushad": {
"ExpectedInstructionCount": "25",
"Optimal": "No",
"Comment": "0x60"
"Comment": "0x60",
"ExpectedArm64ASM": [
"mov w20, w8",
"sub x21, x20, #0x4 (4)",
"mov w22, w4",
"str w22, [x21]",
"sub x21, x21, #0x4 (4)",
"mov w22, w5",
"str w22, [x21]",
"sub x21, x21, #0x4 (4)",
"mov w22, w6",
"str w22, [x21]",
"sub x21, x21, #0x4 (4)",
"mov w22, w7",
"str w22, [x21]",
"sub x21, x21, #0x4 (4)",
"str w20, [x21]",
"sub x20, x21, #0x4 (4)",
"mov w21, w9",
"str w21, [x20]",
"sub x20, x20, #0x4 (4)",
"mov w21, w10",
"str w21, [x20]",
"sub x20, x20, #0x4 (4)",
"mov w21, w11",
"str w21, [x20]",
"bfxil x8, x20, #0, #32"
]
},
"popa": {
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0x61"
"Comment": "0x61",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"bfxil x11, x21, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w20, [x20, #4]",
"bfxil x10, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x9, x21, #0, #32",
"add x21, x20, #0x8 (8)",
"ldr w20, [x20, #8]",
"bfxil x7, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x6, x21, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w20, [x20, #4]",
"bfxil x5, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x4, x21, #0, #32",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32"
]
},
"popad": {
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0x61"
"Comment": "0x61",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"bfxil x11, x21, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w20, [x20, #4]",
"bfxil x10, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x9, x21, #0, #32",
"add x21, x20, #0x8 (8)",
"ldr w20, [x20, #8]",
"bfxil x7, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x6, x21, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w20, [x20, #4]",
"bfxil x5, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x4, x21, #0, #32",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32"
]
},
"aam": {
"ExpectedInstructionCount": 29,
"Optimal": "No",
"Comment": "0xd4"
"Comment": "0xd4",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"mov w21, #0xa",
"udiv x22, x20, x21",
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"lsl x21, x22, #8",
"add x20, x21, x20",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"mov w20, w4",
"uxtb x20, w20",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"lsr w21, w0, #0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"aad": {
"ExpectedInstructionCount": 30,
"Optimal": "No",
"Comment": "0xd5"
"Comment": "0xd5",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"mov w21, w4",
"uxth x21, w21",
"lsr w21, w21, #8",
"mov w22, #0xa",
"mul x21, x21, x22",
"add x20, x20, x21",
"and x20, x20, #0xff",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"mov w20, w4",
"uxtb x20, w20",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"lsr w21, w0, #0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 29,
@@ -119,6 +670,37 @@
"Comment": [
"aam with a different immediate byte base",
"0xd4"
],
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"orr w21, wzr, #0x40",
"udiv x22, x20, x21",
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"lsl x21, x22, #8",
"add x20, x21, x20",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"mov w20, w4",
"uxtb x20, w20",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"lsr w21, w0, #0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd5, 0x40": {
@@ -127,12 +709,59 @@
"Comment": [
"aad with a different immediate byte base",
"0xd5"
],
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"mov w21, w4",
"uxth x21, w21",
"lsr w21, w21, #8",
"lsl x21, x21, #6",
"add x20, x20, x21",
"and x20, x20, #0xff",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"mov w20, w4",
"uxtb x20, w20",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"lsr w21, w0, #0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"salc": {
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": "0xd6"
"Comment": "0xd6",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"ldr w21, [x28, #728]",
"ubfx x22, x21, #29, #1",
"add w20, w20, w22",
"mov w22, w4",
"uxtb x22, w22",
"sub w20, w22, w20",
"mov w22, w4",
"mov w0, w22",
"bfxil w0, w20, #0, #8",
"lsr w20, w0, #0",
"bfxil x4, x20, #0, #32",
"str w21, [x28, #728]"
]
}
}
}
unittests/InstructionCountCI/Secondary.json
+3302 -304
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/SecondaryGroup.json
+1256 -112
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/SecondaryModRM.json
+71 -3
View File
@@ -13,17 +13,85 @@
"xgetbv": {
"ExpectedInstructionCount": 44,
"Optimal": "No",
"Comment": "0xF 0x01 /2 RM-0"
"Comment": "0xF 0x01 /2 RM-0",
"ExpectedArm64ASM": [
"sub sp, sp, #0xd0 (208)",
"mov x0, sp",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
"str x30, [x0]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"stp x8, x9, [x28, #40]",
"stp x10, x11, [x28, #56]",
"stp x12, x13, [x28, #72]",
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"add x0, x28, #0xc0 (192)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"ldr x0, [x28, #1096]",
"ldr x2, [x28, #1112]",
"mov w1, w5",
"blr x2",
"add x5, x28, #0xc0 (192)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldp x8, x9, [x28, #40]",
"ldp x10, x11, [x28, #56]",
"ldp x12, x13, [x28, #72]",
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov w20, w0",
"lsr x21, x0, #32",
"mov w4, w20",
"mov w6, w21"
]
},
"rdtscp": {
"ExpectedInstructionCount": 17,
"Optimal": "No",
"Comment": "0xF 0x01 /7 RM-1"
"Comment": "0xF 0x01 /7 RM-1",
"ExpectedArm64ASM": [
"dmb ld",
"mrs x20, S3_3_c14_c0_2",
"ubfx x4, x20, #0, #32",
"lsr x6, x20, #32",
"str x8, [x28, #40]",
"orr w0, wzr, #0x100",
"str x0, [x28, #1040]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
"add x1, sp, #0x4 (4)",
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr x8, [x28, #40]",
"str xzr, [x28, #1040]",
"orr x5, x0, x1, lsl #12"
]
},
"clzero rax": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xF 0x01 /7 RM-4"
"Comment": "0xF 0x01 /7 RM-4",
"ExpectedArm64ASM": [
"dc zva, x4"
]
}
}
}
unittests/InstructionCountCI/Secondary_32Bit.json
+41 -5
View File
@@ -11,22 +11,58 @@
"push fs": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0x0f 0xa0"
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"mov w20, w8",
"sub x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"ldrh w21, [x28, #146]",
"str w21, [x20]"
]
},
"pop fs": {
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x0f 0xa1"
"Comment": "0x0f 0xa1",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #146]",
"ubfx x20, x21, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #176]"
]
},
"push gs": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0x0f 0xa8"
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"mov w20, w8",
"sub x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"ldrh w21, [x28, #144]",
"str w21, [x20]"
]
},
"pop gs": {
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x0f 0xa9"
"Comment": "0x0f 0xa9",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #144]",
"ubfx x20, x21, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #168]"
]
}
}
}
}
unittests/InstructionCountCI/Secondary_OpSize.json
+714 -116
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Secondary_REP.json
+451 -41
View File
@@ -11,37 +11,80 @@
"movss xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x10"
"Comment": "0xf3 0x0f 0x10",
"ExpectedArm64ASM": [
"mov v16.s[0], v17.s[0]"
]
},
"movss xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x10"
"Comment": "0xf3 0x0f 0x10",
"ExpectedArm64ASM": [
"ldr s16, [x4]"
]
},
"movss [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x11"
"Comment": "0xf3 0x0f 0x11",
"ExpectedArm64ASM": [
"str s16, [x4]"
]
},
"movsldup xmm0, xmm1": {
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x12"
"Comment": "0xf3 0x0f 0x12",
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"mov v0.s[3], v17.s[2]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v0.s[1], v17.s[0]",
"mov v16.16b, v0.16b"
]
},
"movsldup xmm0, [rax]": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x12"
"Comment": "0xf3 0x0f 0x12",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"mov v0.16b, v4.16b",
"mov v0.s[3], v4.s[2]",
"mov v5.16b, v0.16b",
"mov v0.16b, v5.16b",
"mov v0.s[1], v4.s[0]",
"mov v16.16b, v0.16b"
]
},
"movshdup xmm0, xmm1": {
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x16"
"Comment": "0xf3 0x0f 0x16",
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"mov v0.s[2], v17.s[3]",
"mov v4.16b, v0.16b",
"mov v0.16b, v4.16b",
"mov v0.s[0], v17.s[1]",
"mov v16.16b, v0.16b"
]
},
"movshdup xmm0, [rax]": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x16"
"Comment": "0xf3 0x0f 0x16",
"ExpectedArm64ASM": [
"ldr q4, [x4]",
"mov v0.16b, v4.16b",
"mov v0.s[2], v4.s[3]",
"mov v5.16b, v0.16b",
"mov v0.16b, v5.16b",
"mov v0.s[0], v4.s[1]",
"mov v16.16b, v0.16b"
]
},
"cvtsi2ss xmm0, eax": {
"ExpectedInstructionCount": 3,
@@ -49,6 +92,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"scvtf s4, w20",
"mov v16.s[0], v4.s[0]"
]
},
"cvtsi2ss xmm0, dword [rax]": {
@@ -57,12 +105,21 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"scvtf s4, w20",
"mov v16.s[0], v4.s[0]"
]
},
"cvtsi2ss xmm0, rax": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2a"
"Comment": "0xf3 0x0f 0x2a",
"ExpectedArm64ASM": [
"scvtf s4, x4",
"mov v16.s[0], v4.s[0]"
]
},
"cvtsi2ss xmm0, qword [rax]": {
"ExpectedInstructionCount": 3,
@@ -70,57 +127,115 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr x20, [x4]",
"scvtf s4, x20",
"mov v16.s[0], v4.s[0]"
]
},
"movntss [rax], xmm0": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x2b"
"Comment": "0xf3 0x0f 0x2b",
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v16.s[0]",
"mov v4.16b, v0.16b",
"str s4, [x4]"
]
},
"cvttss2si eax, xmm0": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x2c"
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v16.s[0]",
"mov v4.16b, v0.16b",
"fcvtzs w4, s4"
]
},
"cvttss2si eax, dword [rbx]": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2c"
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr s4, [x7]",
"fcvtzs w4, s4"
]
},
"cvttss2si rax, xmm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x2c"
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"mov v4.8b, v16.8b",
"fcvtzs x4, s4"
]
},
"cvttss2si rax, dword [rbx]": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2c"
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"fcvtzs x4, s4"
]
},
"cvtss2si eax, xmm0": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x2d"
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v16.s[0]",
"mov v4.16b, v0.16b",
"frinti s0, s4",
"fcvtzs w4, s0"
]
},
"cvtss2si eax, dword [rbx]": {
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2d"
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr s4, [x7]",
"frinti s0, s4",
"fcvtzs w4, s0"
]
},
"cvtss2si rax, xmm0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x2d"
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"mov v4.8b, v16.8b",
"frinti s0, s4",
"fcvtzs x4, s0"
]
},
"cvtss2si rax, dword [rbx]": {
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x2d"
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"frinti s0, s4",
"fcvtzs x4, s0"
]
},
"sqrtss xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x51"
"Comment": "0xf3 0x0f 0x51",
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fsqrt s4, s4",
"mov v16.s[0], v4.s[0]"
]
},
"rsqrtss xmm0, xmm1": {
"ExpectedInstructionCount": 7,
@@ -128,6 +243,15 @@
"Comment": [
"FEAT_FPRES could make this more optimal",
"0xf3 0x0f 0x52"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s4",
"fdiv s4, s0, s1",
"mov v16.s[0], v4.s[0]"
]
},
"rcpss xmm0, xmm1": {
@@ -136,6 +260,14 @@
"Comment": [
"FEAT_FPRES could make this more optimal",
"0xf3 0x0f 0x53"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fmov s0, #0x70 (1.0000)",
"fdiv s4, s0, s4",
"mov v16.s[0], v4.s[0]"
]
},
"addss xmm0, xmm1": {
@@ -144,6 +276,10 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x58"
],
"ExpectedArm64ASM": [
"fadd s4, s16, s17",
"mov v16.s[0], v4.s[0]"
]
},
"mulss xmm0, xmm1": {
@@ -152,22 +288,41 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x59"
],
"ExpectedArm64ASM": [
"fmul s4, s16, s17",
"mov v16.s[0], v4.s[0]"
]
},
"cvtss2sd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x5a"
"Comment": "0xf3 0x0f 0x5a",
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcvt d4, s4",
"mov v16.d[0], v4.d[0]"
]
},
"cvtss2sd xmm0, [rax]": {
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x5a"
"Comment": "0xf3 0x0f 0x5a",
"ExpectedArm64ASM": [
"ldr s4, [x4]",
"fcvt d4, s4",
"mov v16.d[0], v4.d[0]"
]
},
"cvttps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x5b"
"Comment": "0xf3 0x0f 0x5b",
"ExpectedArm64ASM": [
"fcvtzs v16.4s, v17.4s"
]
},
"subss xmm0, xmm1": {
"ExpectedInstructionCount": 2,
@@ -175,6 +330,10 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x5c"
],
"ExpectedArm64ASM": [
"fsub s4, s16, s17",
"mov v16.s[0], v4.s[0]"
]
},
"minss xmm0, xmm1": {
@@ -183,6 +342,14 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x5d"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmp s16, s4",
"fcsel s4, s16, s4, mi",
"mov v16.s[0], v4.s[0]"
]
},
"divss xmm0, xmm1": {
@@ -191,6 +358,10 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x5e"
],
"ExpectedArm64ASM": [
"fdiv s4, s16, s17",
"mov v16.s[0], v4.s[0]"
]
},
"maxss xmm0, xmm1": {
@@ -199,92 +370,254 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0x5f"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmp s16, s4",
"fcsel s4, s4, s16, mi",
"mov v16.s[0], v4.s[0]"
]
},
"movdqu xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x6f"
"Comment": "0xf3 0x0f 0x6f",
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"movdqu xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x6f"
"Comment": "0xf3 0x0f 0x6f",
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"pshufhw xmm0, xmm1, 0": {
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x70"
"Comment": "0xf3 0x0f 0x70",
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"mov v0.h[4], v17.h[4]",
"mov v4.16b, v0.16b",
"mov v4.h[5], v17.h[4]",
"mov v4.h[6], v17.h[4]",
"mov v0.16b, v4.16b",
"mov v0.h[7], v17.h[4]",
"mov v16.16b, v0.16b"
]
},
"pshufhw xmm0, xmm1, 1": {
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x70"
"Comment": "0xf3 0x0f 0x70",
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"mov v0.h[4], v17.h[5]",
"mov v4.16b, v0.16b",
"mov v4.h[5], v17.h[4]",
"mov v4.h[6], v17.h[4]",
"mov v0.16b, v4.16b",
"mov v0.h[7], v17.h[4]",
"mov v16.16b, v0.16b"
]
},
"pshufhw xmm0, xmm1, 0xff": {
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x70"
"Comment": "0xf3 0x0f 0x70",
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"mov v0.h[4], v17.h[7]",
"mov v4.16b, v0.16b",
"mov v4.h[5], v17.h[7]",
"mov v4.h[6], v17.h[7]",
"mov v0.16b, v4.16b",
"mov v0.h[7], v17.h[7]",
"mov v16.16b, v0.16b"
]
},
"movq xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0xf3 0x0f 0x7e"
"Comment": "0xf3 0x0f 0x7e",
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"mov v16.16b, v4.16b"
]
},
"movq xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x7e"
"Comment": "0xf3 0x0f 0x7e",
"ExpectedArm64ASM": [
"ldr d16, [x4]"
]
},
"movdqu [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0x7f"
"Comment": "0xf3 0x0f 0x7f",
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"popcnt ax, bx": {
"ExpectedInstructionCount": 13,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xb8"
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth x20, w7",
"fmov s0, w20",
"cnt v0.8b, v0.8b",
"addp v0.8b, v0.8b, v0.8b",
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"mov w21, #0x0",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"strb w21, [x28, #706]",
"strb w21, [x28, #708]",
"str w20, [x28, #728]"
]
},
"popcnt eax, ebx": {
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xb8"
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"fmov s0, w20",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"cmp x4, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #30",
"strb w20, [x28, #706]",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
},
"popcnt rax, rbx": {
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xb8"
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov d0, x7",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"cmp x4, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #30",
"strb w20, [x28, #706]",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
},
"tzcnt ax, bx": {
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbc"
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"uxth x20, w7",
"rbit w20, w20",
"orr w20, w20, #0x8000",
"clz w20, w20",
"bfxil x4, x20, #0, #16",
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx x20, x20, #0, #1",
"orr x20, x21, x20, lsl #30",
"str w20, [x28, #728]"
]
},
"tzcnt eax, ebx": {
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbc"
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"rbit w4, w20",
"clz w4, w4",
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #29",
"ubfx x21, x4, #0, #1",
"orr x20, x20, x21, lsl #30",
"str w20, [x28, #728]"
]
},
"tzcnt rax, rbx": {
"ExpectedInstructionCount": 8,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0xbc"
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x4, x7",
"clz x4, x4",
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #29",
"ubfx x21, x4, #0, #1",
"orr x20, x20, x21, lsl #30",
"str w20, [x28, #728]"
]
},
"lzcnt ax, bx": {
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbd"
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"uxth x20, w7",
"lsl w21, w20, #16",
"orr w21, w21, #0x8000",
"clz w21, w21",
"bfxil x4, x21, #0, #16",
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx x20, x20, #15, #1",
"orr x20, x21, x20, lsl #30",
"str w20, [x28, #728]"
]
},
"lzcnt eax, ebx": {
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbd"
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"clz w4, w20",
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx x20, x20, #31, #1",
"orr x20, x21, x20, lsl #30",
"str w20, [x28, #728]"
]
},
"lzcnt rax, rbx": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbd"
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz x4, x7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #29",
"lsr x21, x7, #63",
"orr x20, x20, x21, lsl #30",
"str w20, [x28, #728]"
]
},
"cmpss xmm0, xmm1, 0": {
"ExpectedInstructionCount": 5,
@@ -292,6 +625,13 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmeq s4, s16, s4",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 1": {
@@ -300,6 +640,13 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmgt s4, s4, s16",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 2": {
@@ -308,6 +655,13 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmge s4, s4, s16",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 3": {
@@ -316,6 +670,16 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmge s0, s16, s4",
"fcmgt s1, s4, s16",
"orr v4.8b, v0.8b, v1.8b",
"mvn v4.8b, v4.8b",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 4": {
@@ -324,6 +688,14 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmeq s4, s16, s4",
"mvn v4.8b, v4.8b",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 5": {
@@ -332,6 +704,14 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmgt s4, s4, s16",
"mvn v4.16b, v4.16b",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 6": {
@@ -340,6 +720,14 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmge s4, s4, s16",
"mvn v4.16b, v4.16b",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 7": {
@@ -348,22 +736,44 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmge s0, s16, s4",
"fcmgt s1, s4, s16",
"orr v4.8b, v0.8b, v1.8b",
"mov v16.s[0], v4.s[0]"
]
},
"movq2dq xmm0, mm0": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0xd6"
"Comment": "0xf3 0x0f 0xd6",
"ExpectedArm64ASM": [
"ldr d16, [x28, #752]"
]
},
"cvtdq2pd xmm0, xmm1": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xe6"
"Comment": "0xf3 0x0f 0xe6",
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"sxtl v4.2d, v4.2s",
"scvtf v16.2d, v4.2d"
]
},
"cvtdq2pd xmm0, [rax]": {
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0xf3 0x0f 0xe6"
"Comment": "0xf3 0x0f 0xe6",
"ExpectedArm64ASM": [
"ldr d4, [x4]",
"sxtl v4.2d, v4.2s",
"scvtf v16.2d, v4.2d"
]
}
}
}
unittests/InstructionCountCI/Secondary_REPNE.json
+259 -24
View File
@@ -11,27 +11,44 @@
"movsd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x10"
"Comment": "0xf2 0x0f 0x10",
"ExpectedArm64ASM": [
"mov v16.d[0], v17.d[0]"
]
},
"movsd xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x10"
"Comment": "0xf2 0x0f 0x10",
"ExpectedArm64ASM": [
"ldr d16, [x4]"
]
},
"movsd [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x11"
"Comment": "0xf2 0x0f 0x11",
"ExpectedArm64ASM": [
"str d16, [x4]"
]
},
"movddup xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x12"
"Comment": "0xf2 0x0f 0x12",
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"dup v16.2d, v4.d[0]"
]
},
"movddup xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x12"
"Comment": "0xf2 0x0f 0x12",
"ExpectedArm64ASM": [
"ldr d4, [x4]",
"dup v16.2d, v4.d[0]"
]
},
"cvtsi2sd xmm0, eax": {
"ExpectedInstructionCount": 3,
@@ -39,6 +56,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"scvtf d4, w20",
"mov v16.d[0], v4.d[0]"
]
},
"cvtsi2sd xmm0, dword [rax]": {
@@ -47,6 +69,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"scvtf d4, w20",
"mov v16.d[0], v4.d[0]"
]
},
"cvtsi2sd xmm0, rax": {
@@ -55,6 +82,10 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"scvtf d4, x4",
"mov v16.d[0], v4.d[0]"
]
},
"cvtsi2sd xmm0, qword [rax]": {
@@ -63,52 +94,97 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr x20, [x4]",
"scvtf d4, x20",
"mov v16.d[0], v4.d[0]"
]
},
"movntsd [rax], xmm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x2b"
"Comment": "0xf2 0x0f 0x2b",
"ExpectedArm64ASM": [
"mov v4.8b, v16.8b",
"str d4, [x4]"
]
},
"cvttsd2si eax, xmm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x2c"
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"mov v4.8b, v16.8b",
"fcvtzs w4, d4"
]
},
"cvttsd2si eax, qword [rbx]": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x2c"
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"fcvtzs w4, d4"
]
},
"cvttsd2si rax, xmm0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x2c"
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"mov v4.8b, v16.8b",
"fcvtzs x4, d4"
]
},
"cvttsd2si rax, qword [rbx]": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x2c"
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"fcvtzs x4, d4"
]
},
"cvtsd2si eax, xmm0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x2d"
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"mov v4.8b, v16.8b",
"frinti d0, d4",
"fcvtzs x4, d0"
]
},
"cvtsd2si eax, qword [rbx]": {
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x2d"
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"frinti d0, d4",
"fcvtzs x4, d0"
]
},
"cvtsd2si rax, xmm0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x2d"
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"mov v4.8b, v16.8b",
"frinti d0, d4",
"fcvtzs x4, d0"
]
},
"cvtsd2si rax, qword [rbx]": {
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x2d"
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d4, [x7]",
"frinti d0, d4",
"fcvtzs x4, d0"
]
},
"sqrtsd xmm0, xmm1": {
"ExpectedInstructionCount": 3,
@@ -116,6 +192,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x51"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fsqrt d4, d4",
"mov v16.d[0], v4.d[0]"
]
},
"addsd xmm0, xmm1": {
@@ -124,6 +205,10 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x58"
],
"ExpectedArm64ASM": [
"fadd d4, d16, d17",
"mov v16.d[0], v4.d[0]"
]
},
"mulsd xmm0, xmm1": {
@@ -132,6 +217,10 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x59"
],
"ExpectedArm64ASM": [
"fmul d4, d16, d17",
"mov v16.d[0], v4.d[0]"
]
},
"cvtsd2ss xmm0, xmm1": {
@@ -140,6 +229,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x5a"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcvt s4, d4",
"mov v16.s[0], v4.s[0]"
]
},
"cvtsd2ss xmm0, [rax]": {
@@ -148,6 +242,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x5a"
],
"ExpectedArm64ASM": [
"ldr d4, [x4]",
"fcvt s4, d4",
"mov v16.s[0], v4.s[0]"
]
},
"subsd xmm0, xmm1": {
@@ -156,6 +255,10 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x5c"
],
"ExpectedArm64ASM": [
"fsub d4, d16, d17",
"mov v16.d[0], v4.d[0]"
]
},
"minsd xmm0, xmm1": {
@@ -164,6 +267,12 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x5d"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmp d16, d4",
"fcsel d4, d16, d4, mi",
"mov v16.d[0], v4.d[0]"
]
},
"divsd xmm0, xmm1": {
@@ -172,6 +281,10 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x5e"
],
"ExpectedArm64ASM": [
"fdiv d4, d16, d17",
"mov v16.d[0], v4.d[0]"
]
},
"maxsd xmm0, xmm1": {
@@ -180,22 +293,58 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0x5f"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmp d16, d4",
"fcsel d4, d4, d16, mi",
"mov v16.d[0], v4.d[0]"
]
},
"pshuflw xmm0, xmm1, 0": {
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x70"
"Comment": "0xf2 0x0f 0x70",
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"mov v0.h[0], v17.h[0]",
"mov v4.16b, v0.16b",
"mov v4.h[1], v17.h[0]",
"mov v4.h[2], v17.h[0]",
"mov v0.16b, v4.16b",
"mov v0.h[3], v17.h[0]",
"mov v16.16b, v0.16b"
]
},
"pshuflw xmm0, xmm1, 1": {
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x70"
"Comment": "0xf2 0x0f 0x70",
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"mov v0.h[0], v17.h[1]",
"mov v4.16b, v0.16b",
"mov v4.h[1], v17.h[0]",
"mov v4.h[2], v17.h[0]",
"mov v0.16b, v4.16b",
"mov v0.h[3], v17.h[0]",
"mov v16.16b, v0.16b"
]
},
"pshuflw xmm0, xmm1, 0xff": {
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x70"
"Comment": "0xf2 0x0f 0x70",
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"mov v0.h[0], v17.h[3]",
"mov v4.16b, v0.16b",
"mov v4.h[1], v17.h[3]",
"mov v4.h[2], v17.h[3]",
"mov v0.16b, v4.16b",
"mov v0.h[3], v17.h[3]",
"mov v16.16b, v0.16b"
]
},
"insertq xmm0, xmm1, 0, 0": {
"ExpectedInstructionCount": 7,
@@ -236,12 +385,32 @@
"haddps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0x7c"
"Comment": "0xf2 0x0f 0x7c",
"ExpectedArm64ASM": [
"faddp v16.4s, v16.4s, v17.4s"
]
},
"hsubps xmm0, xmm1": {
"ExpectedInstructionCount": 15,
"Optimal": "No",
"Comment": "0xf2 0x0f 0x7d"
"Comment": "0xf2 0x0f 0x7d",
"ExpectedArm64ASM": [
"fneg v4.4s, v16.4s",
"fneg v5.4s, v17.4s",
"mov v0.16b, v16.16b",
"mov v0.s[1], v4.s[1]",
"mov v6.16b, v0.16b",
"mov v0.16b, v6.16b",
"mov v0.s[3], v4.s[3]",
"mov v4.16b, v0.16b",
"mov v0.16b, v17.16b",
"mov v0.s[1], v5.s[1]",
"mov v6.16b, v0.16b",
"mov v0.16b, v6.16b",
"mov v0.s[3], v5.s[3]",
"mov v5.16b, v0.16b",
"faddp v16.4s, v4.4s, v5.4s"
]
},
"cmpsd xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
@@ -249,6 +418,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmeq d4, d16, d4",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 1": {
@@ -257,6 +431,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmgt d4, d4, d16",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 2": {
@@ -265,6 +444,11 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmge d4, d4, d16",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 3": {
@@ -273,6 +457,14 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmge d0, d16, d4",
"fcmgt d1, d4, d16",
"orr v4.8b, v0.8b, v1.8b",
"mvn v4.8b, v4.8b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 4": {
@@ -281,6 +473,12 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmeq d4, d16, d4",
"mvn v4.8b, v4.8b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 5": {
@@ -289,6 +487,12 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmgt d4, d4, d16",
"mvn v4.16b, v4.16b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 6": {
@@ -297,6 +501,12 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmge d4, d4, d16",
"mvn v4.16b, v4.16b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 7": {
@@ -305,27 +515,52 @@
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmge d0, d16, d4",
"fcmgt d1, d4, d16",
"orr v4.8b, v0.8b, v1.8b",
"mov v16.d[0], v4.d[0]"
]
},
"addsubps xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0xd0"
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"fadd v4.4s, v16.4s, v17.4s",
"fsub v5.4s, v16.4s, v17.4s",
"uzp1 v5.4s, v5.4s, v5.4s",
"uzp2 v4.4s, v4.4s, v4.4s",
"zip1 v16.4s, v5.4s, v4.4s"
]
},
"movdq2q mm0, xmm0": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0xd6"
"Comment": "0xf2 0x0f 0xd6",
"ExpectedArm64ASM": [
"str d16, [x28, #752]"
]
},
"cvtpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0xe6"
"Comment": "0xf2 0x0f 0xe6",
"ExpectedArm64ASM": [
"fcvtn v4.2s, v17.2d",
"frinti v16.4s, v4.4s",
"fcvtzs v16.4s, v16.4s"
]
},
"lddqu xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0xf2 0x0f 0xf0"
"Comment": "0xf2 0x0f 0xf0",
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
}
}
}
}
unittests/InstructionCountCI/VEX_map1.json
+4711
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File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map2.json
+1951 -3
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map3.json
+4455 -1
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File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map_group.json
+511
View File
@@ -12,6 +12,12 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlw xmm0, xmm1, 15": {
@@ -19,6 +25,13 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"ushr v4.8h, v4.8h, #15",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlw xmm0, xmm1, 16": {
@@ -26,6 +39,13 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlw ymm0, ymm1, 0": {
@@ -33,6 +53,10 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlw ymm0, ymm1, 15": {
@@ -40,6 +64,12 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"lsr z4.h, p7/m, z4.h, #15",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlw ymm0, ymm1, 16": {
@@ -47,6 +77,11 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
]
},
"vpsraw xmm0, xmm1, 0": {
@@ -54,6 +89,12 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsraw xmm0, xmm1, 15": {
@@ -61,6 +102,13 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"sshr v4.8h, v4.8h, #15",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsraw xmm0, xmm1, 16": {
@@ -68,6 +116,13 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"sshr v4.8h, v4.8h, #15",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsraw ymm0, ymm1, 0": {
@@ -75,6 +130,10 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpsraw ymm0, ymm1, 15": {
@@ -82,6 +141,12 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"asr z4.h, p7/m, z4.h, #15",
"mov z16.d, p7/m, z4.d"
]
},
"vpsraw ymm0, ymm1, 16": {
@@ -89,6 +154,12 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"asr z4.h, p7/m, z4.h, #15",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllw xmm0, xmm1, 0": {
@@ -96,6 +167,12 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllw xmm0, xmm1, 15": {
@@ -103,6 +180,13 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"shl v4.8h, v4.8h, #15",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllw xmm0, xmm1, 16": {
@@ -110,6 +194,13 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllw ymm0, ymm1, 0": {
@@ -117,6 +208,10 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllw ymm0, ymm1, 15": {
@@ -124,6 +219,12 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"lsl z4.h, p7/m, z4.h, #15",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllw ymm0, ymm1, 16": {
@@ -131,6 +232,11 @@
"Optimal": "No",
"Comment": [
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrld xmm0, xmm1, 0": {
@@ -138,6 +244,12 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrld xmm0, xmm1, 31": {
@@ -145,6 +257,13 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"ushr v4.4s, v4.4s, #31",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrld xmm0, xmm1, 32": {
@@ -152,6 +271,13 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrld ymm0, ymm1, 0": {
@@ -159,6 +285,10 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrld ymm0, ymm1, 31": {
@@ -166,6 +296,12 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"lsr z4.s, p7/m, z4.s, #31",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrld ymm0, ymm1, 32": {
@@ -173,6 +309,11 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrad xmm0, xmm1, 0": {
@@ -180,6 +321,12 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrad xmm0, xmm1, 31": {
@@ -187,6 +334,13 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"sshr v4.4s, v4.4s, #31",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrad xmm0, xmm1, 32": {
@@ -194,6 +348,13 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"sshr v4.4s, v4.4s, #31",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrad ymm0, ymm1, 0": {
@@ -201,6 +362,10 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrad ymm0, ymm1, 31": {
@@ -208,6 +373,12 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"asr z4.s, p7/m, z4.s, #31",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrad ymm0, ymm1, 32": {
@@ -215,6 +386,12 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"asr z4.s, p7/m, z4.s, #31",
"mov z16.d, p7/m, z4.d"
]
},
"vpslld xmm0, xmm1, 0": {
@@ -222,6 +399,12 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpslld xmm0, xmm1, 31": {
@@ -229,6 +412,13 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"shl v4.4s, v4.4s, #31",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpslld xmm0, xmm1, 32": {
@@ -236,6 +426,13 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpslld ymm0, ymm1, 0": {
@@ -243,6 +440,10 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpslld ymm0, ymm1, 31": {
@@ -250,6 +451,12 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"lsl z4.s, p7/m, z4.s, #31",
"mov z16.d, p7/m, z4.d"
]
},
"vpslld ymm0, ymm1, 32": {
@@ -257,6 +464,11 @@
"Optimal": "No",
"Comment": [
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlq xmm0, xmm1, 0": {
@@ -264,6 +476,12 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlq xmm0, xmm1, 63": {
@@ -271,6 +489,13 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"ushr v4.2d, v4.2d, #63",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlq xmm0, xmm1, 64": {
@@ -278,6 +503,13 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlq ymm0, ymm1, 0": {
@@ -285,6 +517,10 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlq ymm0, ymm1, 63": {
@@ -292,6 +528,12 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"lsr z4.d, p7/m, z4.d, #63",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrlq ymm0, ymm1, 64": {
@@ -299,6 +541,11 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrldq xmm0, xmm1, 0": {
@@ -306,6 +553,13 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v5.2d, #0x0",
"ext v4.16b, v4.16b, v5.16b, #0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrldq xmm0, xmm1, 15": {
@@ -313,6 +567,13 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v5.2d, #0x0",
"ext v4.16b, v4.16b, v5.16b, #15",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrldq xmm0, xmm1, 16": {
@@ -320,6 +581,11 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrldq ymm0, ymm1, 0": {
@@ -327,6 +593,22 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, #0",
"ext v6.16b, v4.16b, v5.16b, #0",
"movprfx z1, z4",
"ext z1.b, z1.b, z5.b, #16",
"mov z4.d, z1.d",
"adr x0, #+0x18",
"ldr p0, [x0]",
"mov z1.q, q4",
"mov z4.d, z6.d",
"mov z4.d, p0/m, z1.d",
"b #+0x8",
"unallocated (Unallocated)",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrldq ymm0, ymm1, 15": {
@@ -334,6 +616,22 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, #0",
"ext v6.16b, v4.16b, v5.16b, #15",
"movprfx z1, z4",
"ext z1.b, z1.b, z5.b, #31",
"mov z4.d, z1.d",
"adr x0, #+0x18",
"ldr p0, [x0]",
"mov z1.q, q4",
"mov z4.d, z6.d",
"mov z4.d, p0/m, z1.d",
"b #+0x8",
"unallocated (Unallocated)",
"mov z16.d, p7/m, z4.d"
]
},
"vpsrldq ymm0, ymm1, 16": {
@@ -341,6 +639,10 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, #0",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllq xmm0, xmm1, 0": {
@@ -348,6 +650,12 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllq xmm0, xmm1, 63": {
@@ -355,6 +663,13 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"shl v4.2d, v4.2d, #63",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllq xmm0, xmm1, 64": {
@@ -362,6 +677,13 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllq ymm0, ymm1, 0": {
@@ -369,6 +691,10 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllq ymm0, ymm1, 63": {
@@ -376,6 +702,12 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movprfx z4, z4",
"lsl z4.d, p7/m, z4.d, #63",
"mov z16.d, p7/m, z4.d"
]
},
"vpsllq ymm0, ymm1, 64": {
@@ -383,6 +715,11 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v4.2d, #0x0",
"mov z16.d, p7/m, z4.d"
]
},
"vpslldq xmm0, xmm1, 0": {
@@ -390,6 +727,11 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpslldq xmm0, xmm1, 15": {
@@ -397,6 +739,13 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"movi v5.2d, #0x0",
"ext v4.16b, v5.16b, v4.16b, #1",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpslldq xmm0, xmm1, 16": {
@@ -404,6 +753,11 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"movi v4.2d, #0x0",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
"vpslldq ymm0, ymm1, 0": {
@@ -411,6 +765,10 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z16.d, p7/m, z4.d"
]
},
"vpslldq ymm0, ymm1, 15": {
@@ -418,6 +776,22 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, #0",
"ext v6.16b, v5.16b, v4.16b, #1",
"movprfx z1, z5",
"ext z1.b, z1.b, z4.b, #17",
"mov z4.d, z1.d",
"adr x0, #+0x18",
"ldr p0, [x0]",
"mov z1.q, q4",
"mov z4.d, z6.d",
"mov z4.d, p0/m, z1.d",
"b #+0x8",
"unallocated (Unallocated)",
"mov z16.d, p7/m, z4.d"
]
},
"vpslldq ymm0, ymm1, 16": {
@@ -425,6 +799,10 @@
"Optimal": "No",
"Comment": [
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"mov z4.d, #0",
"mov z16.d, p7/m, z4.d"
]
},
"vldmxcsr [rax]": {
@@ -432,6 +810,25 @@
"Optimal": "No",
"Comment": [
"Map group 15 0b010"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"ubfx x20, x20, #13, #3",
"and x0, x20, #0x3",
"cmp x0, #0x2 (2)",
"orr w2, wzr, #0x1",
"csel x1, x2, xzr, eq",
"cmp x0, #0x1 (1)",
"orr w2, wzr, #0x2",
"csel x1, x2, x1, eq",
"cmp x0, #0x3 (3)",
"orr w2, wzr, #0x3",
"csel x1, x2, x1, eq",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x20, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
]
},
"vstmxcsr [rax]": {
@@ -439,6 +836,25 @@
"Optimal": "No",
"Comment": [
"Map group 15 0b011"
],
"ExpectedArm64ASM": [
"orr w20, wzr, #0x1f80",
"mrs x21, fpcr",
"lsr x21, x21, #22",
"and x0, x21, #0x3",
"cmp x0, #0x1 (1)",
"orr w2, wzr, #0x2",
"csel x1, x2, xzr, eq",
"cmp x0, #0x2 (2)",
"orr w2, wzr, #0x1",
"csel x1, x2, x1, eq",
"cmp x0, #0x3 (3)",
"orr w2, wzr, #0x3",
"csel x1, x2, x1, eq",
"orr x21, x21, x1",
"bfxil x21, x1, #0, #2",
"bfi w20, w21, #13, #3",
"str w20, [x4]"
]
},
"blsr eax, ebx": {
@@ -446,6 +862,22 @@
"Optimal": "No",
"Comment": [
"Map group 17 0b001 32-bit"
],
"ExpectedArm64ASM": [
"orr w20, wzr, #0x1",
"ubfx x21, x7, #0, #32",
"sub x22, x21, #0x1 (1)",
"and x22, x22, x21",
"ubfx x4, x22, #0, #32",
"mov w23, #0x0",
"tst w22, w22",
"mrs x22, nzcv",
"strb w23, [x28, #708]",
"strb w23, [x28, #706]",
"cmp x21, #0x0 (0)",
"csel x20, x23, x20, eq",
"orr x20, x22, x20, lsl #29",
"str w20, [x28, #728]"
]
},
"blsr rax, rbx": {
@@ -453,6 +885,20 @@
"Optimal": "No",
"Comment": [
"Map group 17 0b001 64-bit"
],
"ExpectedArm64ASM": [
"orr w20, wzr, #0x1",
"sub x21, x7, #0x1 (1)",
"and x4, x21, x7",
"mov w21, #0x0",
"tst x4, x4",
"mrs x22, nzcv",
"strb w21, [x28, #708]",
"strb w21, [x28, #706]",
"cmp x7, #0x0 (0)",
"csel x20, x21, x20, eq",
"orr x20, x22, x20, lsl #29",
"str w20, [x28, #728]"
]
},
"blsmsk eax, ebx": {
@@ -460,6 +906,25 @@
"Optimal": "No",
"Comment": [
"Map group 17 0b010 32-bit"
],
"ExpectedArm64ASM": [
"orr w20, wzr, #0x1",
"ubfx x21, x7, #0, #32",
"sub x22, x21, #0x1 (1)",
"eor x22, x22, x21",
"ubfx x4, x22, #0, #32",
"mov w22, #0x0",
"ldr w23, [x28, #728]",
"bfi w23, w22, #30, #1",
"bfi w23, w22, #28, #1",
"strb w22, [x28, #708]",
"strb w22, [x28, #706]",
"cmp x21, #0x0 (0)",
"csel x20, x22, x20, eq",
"mov w0, w23",
"bfi w0, w20, #29, #1",
"lsr w20, w0, #0",
"str w20, [x28, #728]"
]
},
"blsmsk rax, rbx": {
@@ -467,6 +932,23 @@
"Optimal": "No",
"Comment": [
"Map group 17 0b010 64-bit"
],
"ExpectedArm64ASM": [
"orr w20, wzr, #0x1",
"sub x21, x7, #0x1 (1)",
"eor x4, x21, x7",
"mov w21, #0x0",
"ldr w22, [x28, #728]",
"bfi w22, w21, #30, #1",
"bfi w22, w21, #28, #1",
"strb w21, [x28, #708]",
"strb w21, [x28, #706]",
"cmp x7, #0x0 (0)",
"csel x20, x21, x20, eq",
"mov w0, w22",
"bfi w0, w20, #29, #1",
"lsr w20, w0, #0",
"str w20, [x28, #728]"
]
},
"blsi eax, ebx": {
@@ -474,6 +956,21 @@
"Optimal": "No",
"Comment": [
"Map group 17 0b011 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"neg w21, w20",
"and w4, w20, w21",
"mov w20, #0x0",
"orr w21, wzr, #0x1",
"tst w4, w4",
"mrs x22, nzcv",
"strb w20, [x28, #708]",
"strb w20, [x28, #706]",
"cmp x4, #0x0 (0)",
"csel x20, x20, x21, eq",
"orr x20, x22, x20, lsl #29",
"str w20, [x28, #728]"
]
},
"blsi rax, rbx": {
@@ -481,6 +978,20 @@
"Optimal": "No",
"Comment": [
"Map group 17 0b011 64-bit"
],
"ExpectedArm64ASM": [
"neg x20, x7",
"and x4, x7, x20",
"mov w20, #0x0",
"orr w21, wzr, #0x1",
"tst x4, x4",
"mrs x22, nzcv",
"strb w20, [x28, #708]",
"strb w20, [x28, #706]",
"cmp x4, #0x0 (0)",
"csel x20, x20, x21, eq",
"orr x20, x22, x20, lsl #29",
"str w20, [x28, #728]"
]
}
}
unittests/InstructionCountCI/x87.json
+21064 -2
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