This happened to work with clang-9 but is caught in clang-10 now.
We were constructing an iterator temp then pulling a node through it
past the destruction.
Remove the iterator construction entirely and removes the unused lambda
from the AArch64 JIT that had the same problem.
Turns out my Threadripper stomps these tests so the arbitrary wait time
actually slows down my unit test time.
Don't want to make it shorter since `strace -f` becomes ugly at that
point.
Instead set up a semaphore style waiting structure that waits until
there are no longer any participants in the atomic
There were four independent arrays for each size of the RA.
Missed the 16bit and 8bit registers when removing a register.
This removes the redundant arrays and just uses one and transforms the
register to the right size depending on what the JIT wants
Currently RA is shared between threads(!).
If the RA had been previously allocated then don't allocate it again.
Fixes a race condition when multiple threads are spinning up and one is
compiling code
x86's cvtsi2ss can take a 32bit or 64bit input and convert it to a 32bit
float.
This ensures the register passed in is 32bit so it uses the 32bit
instruction
Fixing some bugs in threading required fixing how the futexes operate.
Instead of the terrible condition variables and atomic values just use
the kernel futex facility directly.
This required fixing some of the threading management since otherwise
there was a issue around the weird mixture of our threads using our
"Futex" class and the kernel expecting real futexes on the values.
Just switch everything over and it ends up being cleaner
Fixes random mutex failures that were happening in various applications
This is pretty easy to implement. Kind of flies in the face of why the
instruction implementation exists (icache and frontend issue overhead
savings) but it is easy to implement.
BMI1 would be straightforward to implement, BMI2 would take a bit more
effort because of the PDEP, PEXT, and BZHI instructions.
Bigger problem is that we don't support VEX three operand decoding in
the frontend at all.
Disable these until then
This is something that TSAN caught was happening.
Grabs the thread creation mutex when checking for idle and extends the
sleep time for WaitForIdle to something that is still below unit test
run time
Sadly this is a fairly substantial change that can't be broken in to
something smaller.
The gist of the problem is that most of the vector ops declared their
own uint8_t RegisterSize and ElementSize variables in their structs.
This was initially done because there were assumptions elsewhere in the
source that sometimes mixed up the IROp member `Size` and `Elements` as
sometimes meaning `Size` elements and `Elements` number of elements.
Other times there was an assumption that `Size` was the full register
size and `Elements` was the number of elements inside that size.
ex: `Size`: 16, `Elements` 8 would sometimes be interpreted as i8v16 OR i128v8
These assumptions are now removed and we also save on average 16bits per
vector operation. This is a necessary evil first step for upcoming IR
considerations.
This should have zero change on runtime behaviour and unit tests confirm
that.
Changes the IR register class definition to exist in the JSON file.
Removes a couple of IR ops that were unused and weren't necessary.
Changes the CPUID IR op to the new paired op which improves perf ever so
slightly.
Changes RA class handling in the RA pass to pull directly from the new
generated helper routine until it hits a complex op
Still need RA constraints to remove extraneous moves that would crop up
Consolidates usage of register class to the one that is defined in the
IR Json file.
Every magic number is replaced with InvalidClass and instead uses the
enums directly
Another bug fix is that the GetHostFlags IR ops was being declared as
using the flags register class, which isn't a real thing yet.
This would most likely have ended up with host flag usage being
scheduled to a GPR that was already scheduled and overwrite it.
Once this IR op ends up in host flags this will be changed as well
Ryan Houdek