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Author SHA1 Message Date
Lioncache b9e4ce4029 ARMEmitter: Handle SVE integer dot product (unpredicated) category 2023-03-29 14:55:06 -04:00
Lioncache 0c048772e0 ARMEmitter: Handle CDOT (vectors) 2023-03-29 14:54:35 -04:00
Ryan Houdek cf66643c60 Merge pull request #2575 from lioncash/store 
OpcodeDispatcher: Handle store variants of VMASKMOVPD/VMASKMOVPS
 2023-03-29 11:26:22 -07:00
Lioncache 830c1884d1 OpcodeDispatcher: Handle store variants of VMASKMOVPD/VMASKMOVPS 
And with that, we support all of the AVX1-only instructions.

The remaining instructions for full AVX1 support is now just the SSE4.2
string instructions.
 2023-03-29 14:03:23 -04:00
Lioncache 5abf9de8a5 IR: Add VStoreVectorMasked IR op 
Will be used to implement the store variants of VPMASKMOV and
VMASKMOVP{D, S}
 2023-03-29 14:03:20 -04:00
Tony Wasserka fa21944428 Thunks/gen: Print stacktrace on crash 
This is useful information e.g. when map lookup from clang::Type pointers
fails during code generation.
 2023-03-29 18:39:50 +02:00
Ryan Houdek 5cdde0bef1 Merge pull request #2572 from lioncash/mask 
OpcodeDispatcher: Handle load variants of VMASKMOVPD/VMASKMOVPS
 2023-03-28 08:01:44 -07:00
Lioncache 25960fe6b1 OpcodeDispatcher: Handle load variants of VMASKMOVP{D, S} 2023-03-28 10:35:23 -04:00
Lioncache eb8626c1f7 IR: Add VLoadVectorMasked IR op 
Will be used to implement the load variants of VMASKMOVP{D, S} and
VPMASKMOV{D, Q}

Particularly useful, since with SVE this behavior can be collapsed into
two instructions (CMPGT followed by the relevant LD1 load instruction)
 2023-03-28 01:57:25 -04:00
Ryan Houdek 100b4d4a5b Merge pull request #2571 from lioncash/asm 
ARMEmitter: Fix treating 32-bit elements as 64-bit with ld1w
 2023-03-27 22:11:13 -07:00
Lioncache ef7853ca4a ARMEmitter: Fix treating 32-bit elements as 64-bit with ld1w 
These conditionals were accidentally inverted and were treating 32-bit
elements as 64-bit ones, when this is unintended.

Also add missing tests to ensure this doesn't slip through in the
future.
 2023-03-28 00:55:04 -04:00
Ryan Houdek 55d65f3aea Merge pull request #2570 from lioncash/mov 
Arm64/VectorOps: Remove a few unnecessary EORs from comparisons in SVE path
 2023-03-27 13:35:48 -07:00
Ryan Houdek 2c2abc550b Merge pull request #2569 from lioncash/psadbw 
OpcodeDispatcher: Handle VMPSADBW
 2023-03-27 13:31:52 -07:00
Lioncache a1dc132f03 Arm64/VectorOps: Eliminate unnecessary EOR and MOV in FP compares 
We can use the zeroing variant of MOVPRFX to perform the same behavior.
 2023-03-27 16:16:28 -04:00
Ryan Houdek 719803bc5a Merge pull request #2568 from lioncash/int 
ARMEmitter: Finish off SVE2 Integer - Predicated group
 2023-03-27 13:01:07 -07:00
Lioncache ef31e0c7c7 OpcodeDispatcher: Handle VMPSADBW 2023-03-27 16:00:24 -04:00
Lioncache eecd016ba8 Arm64/VectorOps: Eliminate unnecessary EOR and MOV in VCMP{EQ,GT} 
We can use the zeroing version of MOVPRFX to perform the same behavior.
 2023-03-27 15:38:03 -04:00
Lioncache b2ec6d5208 OpcodeDispatcher: Move MPSADBW implementation into helper 
This will be used for implementing the AVX variant of this instruction.
 2023-03-27 12:40:28 -04:00
Lioncache 416a7b825d ARMEmitter: Move SVE2IntegerSaturatingAddSub over to using SVE2IntegerPredicated helper 
Deduplicates some code.
 2023-03-27 12:21:42 -04:00
Lioncache c3511ffa48 ARMEmitter: Move SVEIntegerPairwiseArithmetic over to using SVE2IntegerPredicated helper 
Deduplicates some code.
 2023-03-27 12:21:42 -04:00
Lioncache b9c3277b09 ARMEmitter: Move SVE2IntegerHalvingPredicated over to using SVE2IntegerPredicated helper 
Deduplicates some code.
 2023-03-27 12:21:38 -04:00
Lioncache 09f259c458 ARMEmitter: Handle SVE2 saturating/rounding bitwise shift left (predicated) category 2023-03-27 11:58:02 -04:00
Lioncache 7a2d23e189 ARMEmitter: Handle SVE2 integer unary operations (predicated) category 2023-03-27 11:36:06 -04:00
Lioncache 1e10561892 ARMEmitter: Handle SVE2 integer pairwise add accumulate long category 2023-03-27 11:22:39 -04:00
Ryan Houdek dcc8d2a1c7 FEXConfig: Fixes misalignment when advanced option is changed. 
When the textual field is changed, that order changes and there would be
a partial resort where the labels would misalign compared to the text
entries.
Fixes that.
 2023-03-26 03:37:40 -07:00
Ryan Houdek 9183cf144f Merge pull request #2547 from Sonicadvance1/standard_string_theory_versus_fex 
Convert most std::string over to fextl
 2023-03-24 04:37:40 -07:00
Ryan Houdek 043a03547f Resolve review comments 2023-03-24 04:09:03 -07:00
Ryan Houdek 7022b3b825 Review c_str() changes 2023-03-23 12:45:14 -07:00
Ryan Houdek 6016c48f98 SourcecodeResolver: Resolve review 2023-03-23 08:19:12 -07:00
Ryan Houdek 60408241c5 EmulatedFiles: Resolve review 2023-03-23 08:18:56 -07:00
Ryan Houdek bed10000e4 fextl: Add fmt 2023-03-23 08:15:47 -07:00
Ryan Houdek a899444ddd StrConv: Address review comments 2023-03-23 08:11:01 -07:00
Ryan Houdek 72df6a26d5 Merge pull request #2559 from lioncash/shift 
Arm64/VectorOps: Handle 64-bit elements in VSShr
 2023-03-21 19:40:24 -07:00
Lioncache dfeee6a1ed Arm64/VectorOps: Fix comment typo in VUShr 
Meant to write USHL here, rather than SSHL
 2023-03-21 22:25:34 -04:00
Lioncache 91d6dc0528 Arm64/VectorOps: Handle 64-bit elements in VSShr 
Makes it consistent with all of the other variable shift IR ops.

Now this won't explode if we ever implement VPSRAVQ from AVX-512
 2023-03-21 22:23:12 -04:00
Ryan Houdek 54e784742c Merge pull request #2558 from lioncash/shift 
OpcodeDispatcher: Handle VPSLLVD/VPSLLVQ
 2023-03-21 15:15:40 -07:00
Ryan Houdek 22936144ce Merge pull request #2557 from lioncash/pred 
ARMEmitter: Handle SVE Inc/Dec by Predicate Count category
 2023-03-21 15:12:39 -07:00
Lioncache fea0162096 OpcodeDispatcher: Handle VPSLLVD/VPSLLVQ 2023-03-21 17:08:03 -04:00
Lioncache 8287375117 x86_64/VectorOps: Implement VUShl IR op 
This will be used to implement VPSLLVD/VPSLLVQ
 2023-03-21 16:57:48 -04:00
Lioncache 0106f03b44 Arm64/VectorOps: Implement VUShl IR op 
This will be used to implement VPSLLVD/VPSLLVQ
 2023-03-21 16:55:33 -04:00
Lioncache 3e2d1cf8c0 OpcodeDispatcher: Factor out variable shift code into helper 
We can slightly modify the table flags for VPSRAVD in order to
consolidate the variable shift code into one place.

Useful, since we still need to implement VPSLLVD and VPSLLVQ.

Also in the event we start supporting AVX-512, then the code can just be
extended from a single point.
 2023-03-21 16:25:20 -04:00
Lioncache 392438d70a ARMEmitter: Handle SVE inc/dec register by predicate count group 2023-03-21 16:16:13 -04:00
Lioncache 0930a10026 ARMEmitter: Handle SVE inc/dec vector by predicate count group 2023-03-21 16:16:13 -04:00
Lioncache cb8ab3d328 ARMEmitter: Handle SVE saturating inc/dec register by predicate count group 2023-03-21 16:16:13 -04:00
Lioncache a670c1d762 ARMEmitter: Handle SVE saturating inc/dec vector by predicate count group 2023-03-21 16:16:11 -04:00
Ryan Houdek 91f056bd2d Merge pull request #2556 from lioncash/shift 
OpcodeDispatcher: Handle VPSRLVD/VPSRLVQ
 2023-03-21 12:29:19 -07:00
Lioncache efba2aed7d Arm64/VectorOps: Remove unnecessary mov in VSShr 
We can just use the movprfx to move the data to shift into the
destination and then perform the shift directly with Dst as an operand.

This is safe, since no original vectors are used in the ASR operation,
only temporaries are used.

Lets us eliminate a temporary and keep things simpler.
 2023-03-21 15:03:59 -04:00
Lioncache 233aef5289 OpcodeDispatcher: Handle VPSRLVD/VPSRLVQ 2023-03-21 15:03:59 -04:00
Lioncache 9d38bc0c81 x86_64/VectorOps: Implement VUShr IR op 
Will be used for implementing VPSRLV AVX ops
 2023-03-21 15:03:59 -04:00
Lioncache a76967650a Arm64/VectorOps: Implement VUShr IR op 
Will be used for implementing VPSRLV AVX ops
 2023-03-21 15:03:55 -04:00