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Author SHA1 Message Date
Lioncache 8c63afb345 OpcodeDispatcher: Add helper for VTESTP{D,S} 2023-03-08 17:27:38 -05:00
Ryan Houdek c14f4355b7 Merge pull request #2478 from lioncash/maddubsw 
OpcodeDispatcher: Handle VPMADDUBSW
 2023-03-08 13:27:43 -08:00
Ryan Houdek 6645e68c95 Merge pull request #2477 from lioncash/mskb 
OpcodeDispatcher: Handle VPMOVMSKB
 2023-03-08 13:19:22 -08:00
Lioncache ff9de85851 OpcodeDispatcher: Handle VPMADDUBSW 2023-03-08 16:01:34 -05:00
Lioncache 4dca609614 OpcodeDispatcher: Factor out PMADDUBSW implementation into helper 
This will be used to centralize the SSE and AVX implementations.
 2023-03-08 15:40:17 -05:00
Lioncache 4fc365c149 OpcodeDispatcher: Handle VPMOVMSKB 2023-03-08 15:29:58 -05:00
Lioncache 8804e0a62a OpcodeDispatcher: Make MOVMSKOpOne suitable for AVX 
Instead of hardcoding most sizes, derive them off the source register
size.

This will allow us to share the implementation between the SSE and AVX.
 2023-03-08 15:29:55 -05:00
Ryan Houdek 1f512b098e Merge pull request #2476 from lioncash/redundant 
Arm64/VectorOps: Remove unnecessary EOR in VAddP/VFAddP SVE path
 2023-03-08 11:21:49 -08:00
Lioncache a31c3ad87a Arm64/VectorOps: Remove unnecessary EOR in VAddP/VFAddP SVE path 
These aren't necessary for the operations anymore.
 2023-03-08 14:05:52 -05:00
Ryan Houdek e92cfc4d7a Merge pull request #2475 from lioncash/extract 
OpcodeDispatcher: Pass full register size through VExtractToGPR
 2023-03-08 10:56:10 -08:00
Lioncache 820d743321 OpcodeDispatcher: Pass full register size through VExtractToGPR 
While the register size field is currently unused, it's correct to
differentiate between 128-bit and 256-bit registers here.
 2023-03-08 13:29:51 -05:00
Ryan Houdek 3b74e34b47 Merge pull request #2474 from lioncash/ffr 
ARMEmitter: Handle SVE Write FFR group
 2023-03-08 10:04:55 -08:00
Ryan Houdek 054430f004 Merge pull request #2473 from lioncash/vec 
ARMEmitter: Move SVEBitwiseShiftbyVector into private section
 2023-03-08 09:40:31 -08:00
Lioncache aeff4346e8 ARMEmitter: Handle SVE Write FFR group 2023-03-08 12:37:28 -05:00
Lioncache 5b51440c87 ARMEmitter: Put precondition checks inside SVEBitwiseShiftbyVector 
Lets us deduplicate some code.
 2023-03-08 12:16:47 -05:00
Lioncache baace30e30 ARMEmitter: Move SVEBitwiseShiftbyVector into private section 
This is an internal helper, so it shouldn't be exposed.
 2023-03-08 12:08:58 -05:00
Mai 11c6f97643 Merge pull request #2470 from Sonicadvance1/optimize_movs 
OpDispatcher: Implements REP MOVS as Memcpy IR op
 2023-03-07 15:17:12 -05:00
Mai 1f44037d9a Merge pull request #2471 from Sonicadvance1/fix_32bit_clock_nanosleep 
x32: Fixes clock_nanosleep syscall
 2023-03-07 15:15:59 -05:00
Ryan Houdek 3bc484b586 x32: Fixes clock_nanosleep syscall 
Alwa's Awakening had an issue where it was spamming clock_nanosleep and
getting EINVAL, consuming a CPU thread to 100%.

This is due to two things in the previous implementation
1) glibc helper does some data munging and validation of inputs
2) We were updating remain even if TIMER_ABSTIME was used

This only cropped up because this error would only occur when EINTR
occured. Since the game is a mono game, the thread that would be
sleeping would get interrupted and then spin forever with corrupted
data.
 2023-03-07 11:11:40 -08:00
Ryan Houdek 79170a23e5 OpDispatcher: Implements REP MOVS as Memcpy IR op 
Just like the `REP STOS` instruction, this removes a fairly nasty bit of
code generation from our dispatcher. This instruction behaves like a
memcpy/memmove when not dealing with the faulting behaviour around the
instruction.

With a microbench things improves this instruction's throughput by 3.5%
to 25.5% depending on operating size.

There is a TODO for implementing this instruction with ARM's future MOPS
instructions which will accelerate this implementation further.
 2023-03-06 16:39:10 -08:00
Ryan Houdek 81e52ca19f IR: Implements a memcpy operation 
This matches the x86 REP MOVS instruction behaviour.
 2023-03-06 16:38:43 -08:00
Ryan Houdek 5301036968 Int/JIT64: Fixes Memset Prefix 
Accidentally missed appending the prefix to the address in x86 JIT and
interpreter
 2023-03-06 16:37:11 -08:00
Ryan Houdek 2321d2ad97 Merge pull request #2469 from lioncash/change 
ARMEmitter/ASIMDOps: Remove unnecessary template constraints
 2023-03-06 15:54:47 -08:00
Lioncache 9c2d29ee4e ARMEmitter/ASIMDOps: Remove unnecessary template constraints 
Now that our register types are strongly typed and don't implicitly convert
across one another, we can get rid of the templating on some member
functions, turning them into normal member functions.
 2023-03-06 18:37:53 -05:00
Ryan Houdek 4b8ac0f8c6 Merge pull request #2468 from lioncash/asimd 
ARMEmitter/ScalarOps: Move base opcodes into helper functions
 2023-03-06 15:16:29 -08:00
Lioncache 70c93efdfa ScalarOps: Simplify Floating-point data-processing (3 source) category 
We can move the opcode into the helper function
 2023-03-06 17:26:24 -05:00
Lioncache f5e207c28f ScalarOps: Simplify Floating-point data-processing (2 source) 
We can move the base opcode into the helper function
 2023-03-06 17:21:36 -05:00
Lioncache 9c64a22280 ScalarOps: Simplify Floating-point conditional select category 
We can move the base opcode into the helper
 2023-03-06 17:15:47 -05:00
Lioncache 5f57fa4b77 ScalarOps: Simplify Floating-point data-processing (1 source) category 
We can move the opcode into the helper function
 2023-03-06 17:06:58 -05:00
Lioncache fe81523179 ScalarOps: Simplify Advanced SIMD scalar shift by immediate category 
We can move the opcode into the helper
 2023-03-06 16:53:04 -05:00
Lioncache 4be61aaaaf ScalarOps: Simplify Advanced SIMD scalar three same category 
We can move the opcode into the helper
 2023-03-06 16:46:36 -05:00
Lioncache da0681ca81 ScalarOps: Simplify Advanced SIMD scalar three different category 
We can move the opcode into the helper function.
 2023-03-06 16:37:52 -05:00
Lioncache 02258073e3 ScalarOps: Simplify Advanced SIMD scalar two-register miscellaneous category 
We can move the opcode into the helper function.
 2023-03-06 16:34:38 -05:00
Lioncache cde55d44ef ScalarOps: Simplify Advanced SIMD scalar two-register miscellaneous FP16 category 
The opcode can be moved into the helper function, deduplicating it over
several functions
 2023-03-06 16:12:07 -05:00
Lioncache 97c12ef351 ScalarOps: Simplify Advanced SIMD scalar three same FP16 category 
We can move the opcode into the helper itself.
 2023-03-06 16:07:12 -05:00
Ryan Houdek 94e0591601 Merge pull request #2467 from lioncash/unused 
ARMEmitter: Remove unused helper functions
 2023-03-06 12:59:06 -08:00
Lioncache b802f64ffe ScalarOps: Simplify Floating-point compare category 
This category as well can have its opcode moved into the helper function
 2023-03-06 15:58:40 -05:00
Lioncache 0e32d8a8b6 ScalarOps: Simplify Floating-point conditional compare category 
We can move the opcode itself into the helper function, so it can be
deduplicated.
 2023-03-06 15:57:57 -05:00
Lioncache fe8bd17c88 ARMEmitter: Simplify bit size retrieval helpers 
We can collapse the array into a shift, and the others can just use 8 as
the starting value to be shifted instead of multiplying by 8.

Aside from the array change, everything else is likely already constant
folded, but it does make things a little more straightforward
 2023-03-06 15:24:58 -05:00
Lioncache f333068d9a ARMEmitter: Remove unused helper functions 
The templated variants were never used. Also we can just make these
helpers constexpr to begin with.
 2023-03-06 15:21:48 -05:00
Ryan Houdek 3bd4b23af7 Merge pull request #2466 from lioncash/misc 
ARMEmitter: Fully handle SVE Integer Misc - Unpredicated
 2023-03-06 12:19:03 -08:00
Ryan Houdek 060745f98b Merge pull request #2465 from lioncash/constraint 
ARMEmitter: Simplify uses of IsXOrWRegister
 2023-03-06 12:08:26 -08:00
Lioncache 77ae7a8a3f ARMEmitter: Fully handle SVE Integer Misc - Unpredicated 
Finishes off an integer category that, at present, has more floating point
operations in it than anything else.
 2023-03-06 15:05:30 -05:00
Lioncache b989bb9569 ARMEmitter: Simplify uses of IsXOrWRegister 
Turns out these can be nicely simplified to being directly in the
template declaration.

Neat little tip pointed out by @neobrain
 2023-03-06 12:05:46 -05:00
Ryan Houdek 63ce78c41d Docs: Update for release FEX-2303 FEX-2303 2023-03-06 08:50:41 -08:00
Mai fc38df2ff0 Merge pull request #2460 from Sonicadvance1/implement_memset 
OpcodeDispatcher: Optimize REP STOS to MemSet operation
 2023-03-04 11:31:58 -05:00
Mai 2fca207e14 Merge pull request #2462 from Sonicadvance1/fix_proton_2 
FileManagement: Fixes Proton
 2023-03-04 11:29:07 -05:00
Mai 308fa76aa3 Merge pull request #2463 from Sonicadvance1/update_rootfslinks 
FEXRootFSFetcher: Update link to rootfs links file
 2023-03-04 11:27:55 -05:00
Ryan Houdek b6ac26e0e9 FEXRootFSFetcher: Update link to rootfs links file 
Switches to the new CDN which is significantly faster and has other
benefits.

In order to make sure we don't break old clients, switch to the new link
for a few months while leaving the old one operational.

The links file in the old CDN still points to the new rootfs links so
they get the performance improvement on old clients still.
 2023-03-04 01:59:44 -08:00
Ryan Houdek ecd144de6a FileManagement: Fixes Proton 
Need to ensure that dirfd is AT_FDCWD and also need to check flags
correctly.

Flags were incorrectly checking mode for O_WRONLY and also we should
check for O_APPEND. Split it out to a helper function just so it is
easier to see what is going on.

Fixes the issue of proton not finding `/lib64/ld-linux-x86-64.so.2`
 2023-03-03 13:44:17 -08:00