Commit Graph
9533 Commits
Author SHA1 Message Date
Ryan Houdek 7e66508016 OpcodeDispatcher: Optimize REP STOS to MemSet operation
x86's REP STOS instruction is a memset (with element size!) with the
ability to choose a direction of execution.
Additionally it has a feature where if it faults part-way through the
copy, an application can catch the fault and continue afterwards to know
how many bytes got copied.

RCX is the counter which decrements for each element, and RDI is the
memory pointer. On fault these will reflect the last location that was
attempted to be written. FEX doesn't support this behaviour which makes
our lives easier.

Without supporting that feature, this turns in to a directional memset
by element size. Let's remove all the multiple blocks and just emit a
single IR operation to improve performance of the JIT.
Our generated code here was terrible, the IR was terrible, multiblock is
always slow with RA. Just a general overall improvement.

With profiling pressure-vessel this change deletes the hottest block that
appeared in the trace. This instruction is very commonly used for
memsetting a region to zero so it should be quite fast.

We can also optimize REP MOVS in the future with a Memcpy IR operation
in a similar fashion.

Additionally in the future these can be optimized to use ARM's new MOPS
instructions since the most common case is memset by byte. Which is when
we should expose the "Fast REP STOS" CPUID bit. Both setp/setm/sete and
cpyfp/cpyfm/cpyfe match `REP STOS` and `REP MOVS` respectively.
2023-03-03 09:16:28 -08:00
Ryan Houdek d6f50bf7b0 IR: Implement support for MemSet operation
This operation directly matches what the x86 STOS instruction does
without supporting its faulting behaviour.

STOS faulting behaviour is that RCX and RDI get updated to the last word
written. Which is something that FEX hasn't ever supported.
2023-03-03 09:16:28 -08:00
Ryan Houdek e7069f9f95 Merge pull request #2461 from lioncash/pair
ARMEmitter: Tidy up some assertion handling
2023-03-02 08:33:53 -08:00
Lioncache ea96ccb63d ARMEmitter: Add missing SVE floating-point compare vectors instructions
We're missing FACGE/FACGT and the aliases FACLE FACLT
2023-03-02 10:54:54 -05:00
Lioncache 4d4eac0987 ARMEmitter: Simplify SVE floating-point compare vectors
We can move the asserts into the helper function
2023-03-02 10:42:58 -05:00
Lioncache f0ee8a49b2 ARMEmitter: Simplify Emitter: SVE: SVE2 floating-point pairwise operations ops
We can centralize all of the assertion handling in the implementation
function.
2023-03-02 10:35:58 -05:00
Lioncache e0d8fc7c2b ARMEmitter: Simplify SVE2 integer halving add/subtract (predicated) ops
We can centralize all the assertion handling in the implementation
function.
2023-03-02 10:28:07 -05:00
Lioncache adf1de5562 ARMEmitter: Simplify SVE integer pairwise ops
We can centralize everything in the helper function itself, getting rid
of a few duplicated assertions.
2023-03-02 10:17:19 -05:00
Mai e310e29898 Merge pull request #2459 from Sonicadvance1/fix_pressure_vessel
FileManagement: Skip opening emulated writable files
2023-03-02 09:41:39 -05:00
Ryan Houdek 37ec68421c FileManagement: Skip opening emulated writable files
In the case that a file is getting opened to be created or writable then
skip EmuFD and rootfs searching for this file.
This fixes an edge case where if FEX was run with an unpacked rootfs
that was writable then pressure-vessel would break.

Fixes pressure-vessel with unpacked rootfs.
2023-03-02 00:26:34 -08:00
Ryan Houdek 41731e2680 Merge pull request #2458 from lioncash/pred
ARMEmitter: Remove predicate implicit conversion operators
2023-03-01 19:58:13 -08:00
Lioncache 5e6a3c6280 ARMEmitter: Remove predicate implicit conversion operators
Like with the vector registers, we can remove all implicit conversion
operators except the ones that convert down to the base PRegister class.

With this, all of the registers are now adequately constrained, so we
shouldn't have any wonky implicit conversions happening anymore.
2023-03-01 22:44:40 -05:00
Ryan Houdek e71e3ec930 Merge pull request #2457 from lioncash/sxtw
ARMEmitter: Make second sxtw parameter a WRegister
2023-03-01 19:35:31 -08:00
Lioncache 4cac100660 ARMEmitter: Make second sxtw parameter a WRegister
Matches the assembly use of it more closely.
2023-03-01 22:20:42 -05:00
Ryan Houdek 378e0692b9 Merge pull request #2456 from lioncash/reg
ARMEmitter: Remove implicit conversions from Register/XRegister/WRegister
2023-03-01 19:16:26 -08:00
Lioncache 678415c4c9 ARMEmitter: Remove implicit conversions from Register/XRegister/WRegister
Ensures that we're always explicit about the size of a register when
using APIs that enforce it.

The only implicit conversions we keep are conversions that convert down
to Register, but not anything that converts up the hierarchy or across
it.
2023-03-01 21:59:53 -05:00
Ryan Houdek e869b2fe67 Merge pull request #2455 from lioncash/comp
ARMEmitter: Remove predicate uint32_t conversion operators
2023-03-01 18:37:34 -08:00
Lioncache 2194a1027c ARMEmitter: Remove predicate uint32_t conversion operators
Now that we have dedicated comparison operators, we no longer need to
keep these implicit conversion operators around.
2023-03-01 21:16:55 -05:00
Lioncache 52b4378e49 ARMEmitter: Add comparison functions to register types
Gets rid of the need to compare indices directly in order to compare
register equality
2023-03-01 21:15:46 -05:00
Ryan Houdek 0f45318040 Merge pull request #2454 from lioncash/convert
ARMEmitter: Remove most implicit conversion operators for vector register types
2023-03-01 17:57:21 -08:00
Ryan Houdek 21fbcef0bd Merge pull request #2453 from lioncash/explicit
ARMEmitter: Make VRegister constructor explicit
2023-03-01 17:54:49 -08:00
Ryan Houdek ef02083767 Merge pull request #2452 from lioncash/consecutive
ARMEmitter: Handle sequential registers in lists nicer
2023-03-01 17:53:47 -08:00
Ryan Houdek 24904f48c4 Merge pull request #2451 from lioncash/saddl
ARMEmitter: Simplify size handling Advanced SIMD 3 different group
2023-03-01 17:45:42 -08:00
Lioncache 9461ab5094 ARMEmitter: Remove conversion operators for VRegister 2023-03-01 18:40:12 -05:00
Lioncache 66c8b14470 ARMEmitter: Remove conversion operators for QRegister 2023-03-01 18:29:11 -05:00
Lioncache 6ab78ca93b ARMEmitter: Remove conversion operators for DRegister 2023-03-01 18:20:32 -05:00
Lioncache 2fe808f5cd ARMEmitter: Remove conversion operators for SRegister 2023-03-01 18:02:31 -05:00
Lioncache 81a94b9ffe ARMEmitter: Remove conversion operators for BRegister 2023-03-01 18:00:24 -05:00
Lioncache 0d87ed46da ARMEmitter: Remove conversion operators for HRegister 2023-03-01 17:58:06 -05:00
Mai 545a216da6 Merge pull request #2448 from Sonicadvance1/optimize_openat
EmulatedFiles: Optimize openat handler
2023-03-01 17:20:14 -05:00
Lioncache 11f65df554 ARMEmitter: Make VRegister constructor explicit
All other parameter taking constructors for the other register types are
explicit, so this just makes behavior more consistent.
2023-03-01 16:48:10 -05:00
Lioncache 29ff642499 ARMEmitter: Make use of sequential register helper
Fixes assertion behavior on quite a bit of ASIMD load-store operations
as well as a few SVE ops as well
2023-03-01 15:25:46 -05:00
Lioncache d36517a9d3 ARMEmitter: Add helper for determining if vectors are sequential
A few vector instructions that take register lists often require
vector registers within the list to be sequential in the form of an
increasing list modulo the register file size.

For example:

v1,  v2, v3, v4
v31, v0, v1, v2

both fit these requirements.

This will be used to enforce this restriction within the asserts from a
single place.
2023-03-01 15:24:07 -05:00
Lioncache 83419b410d ARMEmitter: Simplify size handling Advanced SIMD 3 different group
A large amount of size handling in this category is just decrementing
the size by 1, so we can tidy up a bunch of conditionals by just doing
that instead.
2023-03-01 11:04:40 -05:00
Mai 77fad28b69 Merge pull request #2447 from Sonicadvance1/add_hypervisorbit_hide_option
CPUID: Adds an config option to hide hypervisor bit
2023-02-28 10:59:21 -05:00
Mai 70aefc9db2 Merge pull request #2450 from Sonicadvance1/fix_fexserver_zombie
FEXServerClient: Fixes instance where FEXServer can create a zombie
2023-02-28 10:58:11 -05:00
Mai d2e0adf540 Merge pull request #2449 from Sonicadvance1/fix_fexserver_daemon_systemd
FEXServer: Change systemd service environment variable key
2023-02-28 10:57:09 -05:00
Ryan Houdek 84060cd947 FEXServerClient: Fixes instance where FEXServer can create a zombie
When FEXServer is daemonizing through an instance of FEXLoader or
FEXInterpreter, it would leave a zombie process which was waiting for us
to read the process status.
Since we don't care about the child status and don't want to get blocked
by waitpid, just ignore the signal.

This tells the kernel that we don't care about the signal and will kill
the zombie process immediately.
Didn't notice this before since FEXServer started failing to daemonize.
2023-02-28 05:09:16 -08:00
Ryan Houdek aaf17b6d41 FEXServer: Change systemd service environment variable key
It looks like `SYSTEMD_EXEC_PID` can leak through to the executable
environment in regular situations. Instead let's key off of
`INVOCATATION_ID` which doesn't leak through.

Fixes an edge case behaviour where FEXServer wouldn't daemonize in some
systemd environments.
2023-02-28 05:07:02 -08:00
Ryan Houdek 8ded25ada7 EmulatedFiles: Optimize openat handler
Fixes #2443
I found out with some profiling that this we were spending a decent
amount of time with the `openat` syscall in heavily utilized situations.
While not super common in active gameplay situations, it matters
significantly in loading screens that this is fairly optimal.

The bulk of the time is spent in the emulated files handler to ensure
that whatever path we are given, we can capture file paths that we need
to emulate. The largest contributor being the std::filesystem::canonical
function call.

A couple of optimizations in place here.
1) Do a quick hashmap check right at the start to see if we exactly fit
2) Change from `std::fs::canonical` to `realpath`
3) Switch `GetEmulatedFDPath` to not use optional so it stops building
   on the stack

I'm still not super happy with the performance of `realpath` and also
not happy that we still need to use `lexically_normal` in one code path.
But short of writing a super hand-optimized `realpath` that fits our
constraints, I don't think we can do better.

Micro benchmark needs to test four different situations due to this
optimization.
1) Non-EmuFD path
2) Non-EmuFD path with dirfs
3) EmuFD path
4) EmuFD path with dirfs

And the performance improvement for each situation respectively
1) 12% performance improvement
  - 213413 openat syscalls/s -> 238999 syscalls/s
2) 17% performance improvement
  - 202085 openat syscalls/s -> 237309 syscalls/s
3) 17% performance improvement (/proc/cpuinfo)
  - 56616 openat syscalls/s -> 66231 syscalls/s
  - Includes overhead of generating temp FD and close syscall
4) 5% performance improvement (/proc/cpuinfo)
  - 51080 openat syscalls/s -> 53956 syscalls/s
  - Includes overhead of generating temp FD and close syscall

And for sake of comparison to the non-emulated system; My test system
can hit around 1-1.1 million openat syscalls per second in the same
microbench.

Nice little performance uplift.
2023-02-28 04:00:28 -08:00
Ryan Houdek 5b9fe8f26b CPUID: Adds an config option to hide hypervisor bit
This is known to cause issues in some cases. We hit the first game that
checks for this bit and early exits if it is found.

Lets the MMORPG Tibia run in non-VM situations.
Looks like they have more checks for VMs other than hypervisor bit, so
running under Parallels still won't work. Running on bare Linux is fine.
2023-02-27 23:11:23 -08:00
Ryan Houdek e65b429c83 Merge pull request #2446 from lioncash/cpy
ARMEmitter: Simplify advanced SIMD copy
2023-02-27 19:52:05 -08:00
Lioncache dd290f129f ARMEmitter: Simplify advanced SIMD copy
Same behavior, but collapses some if statements.
2023-02-27 22:32:39 -05:00
Ryan Houdek 1832cc80d6 Merge pull request #2445 from lioncash/unsigned
ARMEmitter: Centralize handling for unsigned offset load-stores
2023-02-27 18:18:30 -08:00
Ryan Houdek fe1faf9ebe Merge pull request #2444 from lioncash/scalar
ARMEmitter: Handle SVE Integer Compare - Scalars group
2023-02-27 18:16:31 -08:00
Lioncache 12d0a7fa98 ARMEmitter: Use constants for unsigned offset encoding limits
Allows us to give some names to these constants that are used in the
JIT instead of writing them by hand.
2023-02-27 17:44:17 -05:00
Lioncache c1b08079f3 ARMEmitter: Strengthen unsigned immediate load/store helper
Centralizes all the shifting behavior and whatnot into a single
function, making everything much more localized.

Also gets rid of a lot of magic constants related to the encoding limits
of immediates.
2023-02-27 17:44:13 -05:00
Mai d688026fe4 Merge pull request #2442 from Sonicadvance1/fix_misaligned_stack_signals
Dispatcher: Fixes crash with misalign stack returning from signal
2023-02-27 14:48:39 -05:00
Lioncache 1c388b455a ARMEmitter: Move missed SVE public helpers into private section 2023-02-27 14:45:59 -05:00
Lioncache 9426abc98d ARMEmitter: Handle SVE pointer conflict compare group 2023-02-27 14:27:29 -05:00