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Code Issues Packages Projects Releases 67 Wiki Activity
378 Commits 11 Branches 71 Tags
39bac4efea399ce276b767cb867b77879d29cf36
Commit Graph
54 Commits
Author SHA1 Message Date
Ryan Houdek 39bac4efea Fixes 32bit memory load op 
xbyak was silently treating this dword load as a 64bit load because the
destination was a 64bit register
 2020-03-13 17:51:07 -07:00
Ryan Houdek 7fa3a318db Division op fixes 
Some division ops weren't sign extending properly and implements 16bit
ops
 2020-03-13 17:49:38 -07:00
Ryan Houdek 23d516d7f3 Fixes SHL/SHR ops 
Makes sure they are operating at the correct sizes.
Also removes the BMI2 SHRX/SHLX ops
 2020-03-13 17:47:53 -07:00
Ryan Houdek e426a622bb Fixes PRINT op in IR JIT. Needs correct stack alignment 2020-03-13 17:47:25 -07:00
Ryan Houdek cf106289d3 Removes bad vector BFE usage in MOVMSK op 
BFE isn't actually meant to be used on vector ops.
Interpreter got away with it because it doesn't have register classes.
Actually do a correct element extract and sign bit extraction
 2020-03-13 17:45:36 -07:00
Ryan Houdek 4227a0cdc7 Removes old asserts from CMPS instruction 2020-03-13 17:45:14 -07:00
Ryan Houdek 79ffd11c1d Cleans up and renames the CVT ops 
Fixes issue #14.

A lot of these were named in very confusing ways.
Makes them very explicit about what the operation is doing
 2020-03-13 17:42:39 -07:00
Ryan Houdek 121bed017c Merge pull request #24 from Sonicadvance1/fixes_jit_x86 
Various fixes for the x86 JIT
 2020-03-13 15:52:48 -07:00
Ryan Houdek 0e80dc27cc Merge pull request #21 from Sonicadvance1/movshdup 
Implements Movshdup instruction
 2020-03-13 15:52:24 -07:00
Ryan Houdek 30338dd7f4 Merge pull request #20 from Sonicadvance1/pextrw 
Implements PExtrw instruction
 2020-03-13 15:52:09 -07:00
Ryan Houdek 78bcf3960d Merge pull request #19 from Sonicadvance1/psrl_family 
Implements PSRL{W,D,Q} instruction family
 2020-03-13 15:51:58 -07:00
Ryan Houdek 4459a048f7 Merge pull request #18 from Sonicadvance1/Interpreter/vushr 
Removes undefined behaviour in the VUSHR in interpreter
 2020-03-13 13:04:56 -07:00
Ryan Houdek d5481efa6b Fixes AtomicFetch{Add,Sub} for 8bit and 16bit ops in the x86 JIT 2020-03-12 22:13:53 -07:00
Ryan Houdek 600f43779c Fixes and implements a couple vector shift ops in the x86 JIT 2020-03-12 22:13:17 -07:00
Ryan Houdek 12288ab887 Fixes VFCMPLE in x86 JIT 2020-03-12 22:12:34 -07:00
Ryan Houdek 2c44338478 Implements VFCMPNEQ in x86 JIT 2020-03-12 22:11:52 -07:00
Ryan Houdek 2e34f25257 Implements VSQXTUN and VSQXTUN2 in x86 JIT 2020-03-12 22:11:36 -07:00
Ryan Houdek d0a7685bfa Implements VUMULL in x86 JIT 2020-03-12 22:11:18 -07:00
Ryan Houdek 5bb93e5b8e Implements VSQADD and VSQSUB in x86 JIT 2020-03-12 22:09:49 -07:00
Ryan Houdek e3e62f3dd1 Fixes VInsGPR in x86 JIT 2020-03-12 22:09:21 -07:00
Ryan Houdek 6730d5601c Fixes VExtractToGPR on x86 JIT 2020-03-12 22:08:30 -07:00
Ryan Houdek 739b471731 Implements signed/unsigned div/rem on x86 JIT 2020-03-12 22:07:36 -07:00
Ryan Houdek 42830d3e48 Merge pull request #22 from phire/fix_condslt 
Fix Signed LT in x86 jit
 2020-03-12 22:02:12 -07:00
Scott Mansell f2967e8ef9 OP_NEG/OP_NOT: add support for other opsizes. 2020-03-13 17:54:09 +13:00
Scott Mansell 99d1dcad98 Fix Neg IR_OP, Add Not IR_OP 
In some places, Neg meant logical one's complement negation.
In others it meant arithmetic two's complement negation.

As both x87 and aarch64 have neg instructions that do
two's complement negations, we will standardise on that.

Additionally we will add a Not_IR op for one's complement
 2020-03-13 17:53:57 +13:00
Scott Mansell ba4e311dc2 Fix Signed LT in x86 jit 2020-03-13 17:52:49 +13:00
Ryan Houdek 6069fcb9d4 Implements Movshdup instruction 2020-03-12 18:31:33 -07:00
Ryan Houdek 64dd3187d5 Implements PExtrw instruction 2020-03-12 18:28:29 -07:00
Ryan Houdek 612b74d001 Implements PSRL{W,D,Q} 
Saw this family when running mesa softpipe
 2020-03-12 18:23:01 -07:00
Ryan Houdek 5cb9f9e0fa Removes undefined behaviour in the VUSHR in interpreter 2020-03-12 18:20:12 -07:00
Stefanos Kornilios Mitsis Poiitidis 99399ecbac Merge pull request #10 from Sonicadvance1/unittests/cmps 
Adds unit tests for the CMPS instruction family
 2020-03-12 10:57:59 +02:00
Ryan Houdek 1b4ea20b17 Implements REPNE for SCAS 2020-03-10 18:21:16 -07:00
Ryan Houdek a8f4e8a860 Implements CMPS support for REPNE and no prefix 2020-03-10 18:18:06 -07:00
Stefanos Kornilios Mitsis Poiitidis 963de98276 Merge pull request #7 from Sonicadvance1/unittests/primary_1 
Primary table unit tests and a couple fixes
 2020-03-10 15:26:05 +02:00
Stefanos Kornilios Mitsis Poiitidis e2e9e1eb41 Merge pull request #9 from Sonicadvance1/unittests/stos 
Adds unit tests for the STOS instruction family
 2020-03-10 15:25:49 +02:00
Stefanos Kornilios Mitsis Poiitidis dc2ed29e18 Merge pull request #8 from Sonicadvance1/unittests/movs 
Adds unit tests for the MOVS instruction family
 2020-03-10 09:47:29 +02:00
Ryan Houdek 4f0a8187ce Implements support for STOS without REP flag 
It doesn't support REPNE so update that assert as well
 2020-03-09 22:59:07 -07:00
Ryan Houdek edf472a98a Updates assert in the MOVS 
REPNE on MOVS is unsupported, most likely the prefix is ignored but
until a hardware test can confirm update the comment
 2020-03-09 22:31:31 -07:00
Ryan Houdek 7a052000c9 Implements SCAS with no repeat prefix 
This is used in a couple unit tests
 2020-03-09 18:15:05 -07:00
Ryan Houdek 66b08b3bad Fixes MOV to moffset destination 
With how we decode literals the destination actually ends up in Src[1]
 2020-03-09 18:14:20 -07:00
Ryan Houdek 0fc06c7bfa Implements an x86Table flag to partially ignore overlays 
Currently only support partially ignoring for overlay 0x66, this means
we only support no overlay at all and 0x66. Using only two bits of flag
space rather than 3.
If we find an instruction family that supports a different one then we
should break it out to three independent flags. Keeping it two until
then

Unit tests to ensure this keeps working is forthcoming
 2020-03-09 13:06:46 -07:00
Stefanos Kornilios Mitsis Poiitidis 39f639e07a Merge pull request #4 from Sonicadvance1/fix_push_reg 
Fixes PUSH with register encoded in op
 2020-03-09 11:35:20 +02:00
Ryan Houdek e1c7c9c0f3 Fixes BTC, BSF, BSR, and XADD table flags 
They require FLAGS_NO_OVERLAY otherwise the frontend can't find the
instructions.
 2020-03-08 22:07:00 -07:00
Ryan Houdek c11ac417ce Fixes BSR and BSF 32bit op when source is zero 
BSR/BSF needs to not write to destination when source is zero
This ensures it doesn't clear the upper 32bits of the register in this
case.
 2020-03-08 22:05:47 -07:00
Ryan Houdek 30b2f019b4 Implements 16bit SHLD/SHRD 
Unit tests found them missing
 2020-03-08 22:05:08 -07:00
Ryan Houdek 19a6292813 Fixes bug in SHRD 
Need to negate by the size of the op, not just regular negate
instruction
 2020-03-08 22:04:26 -07:00
Ryan Houdek 2726e2512d Fixes PUSH with register encoded in op 
Unittest to ensure this keeps working is forthcoming.
 2020-03-08 16:05:25 -07:00
Ryan Houdek e9092b328b Implements 16bit long div and long remainder in interpreter 
Missed this originally when implementing, unit tests found it missing
 2020-03-07 21:52:40 -08:00
Ryan Houdek 86fb69a5a2 Fixes CVTDQ2PS that unit tests uncovered 
This was actually doing 2xint32 -> 2xdouble translations initially.
Needed to do 4xint32 -> 4xfloat
 2020-03-07 21:51:45 -08:00
Ryan Houdek 2da7e9d29b Minor cleanup in the flag calculation for sub 
No need to make a switch statement to extract the sign bit of the source
 2020-03-07 21:51:04 -08:00