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Code Issues Packages Projects Releases 67 Wiki Activity
6,221 Commits 11 Branches 71 Tags
91d6dc05282a3c1a53e6e0dfd8842be3fc02bfcb
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2494 Commits
Author SHA1 Message Date
Lioncache 91d6dc0528 Arm64/VectorOps: Handle 64-bit elements in VSShr 
Makes it consistent with all of the other variable shift IR ops.

Now this won't explode if we ever implement VPSRAVQ from AVX-512
 2023-03-21 22:23:12 -04:00
Ryan Houdek 54e784742c Merge pull request #2558 from lioncash/shift 
OpcodeDispatcher: Handle VPSLLVD/VPSLLVQ
 2023-03-21 15:15:40 -07:00
Ryan Houdek 22936144ce Merge pull request #2557 from lioncash/pred 
ARMEmitter: Handle SVE Inc/Dec by Predicate Count category
 2023-03-21 15:12:39 -07:00
Lioncache fea0162096 OpcodeDispatcher: Handle VPSLLVD/VPSLLVQ 2023-03-21 17:08:03 -04:00
Lioncache 8287375117 x86_64/VectorOps: Implement VUShl IR op 
This will be used to implement VPSLLVD/VPSLLVQ
 2023-03-21 16:57:48 -04:00
Lioncache 0106f03b44 Arm64/VectorOps: Implement VUShl IR op 
This will be used to implement VPSLLVD/VPSLLVQ
 2023-03-21 16:55:33 -04:00
Lioncache 3e2d1cf8c0 OpcodeDispatcher: Factor out variable shift code into helper 
We can slightly modify the table flags for VPSRAVD in order to
consolidate the variable shift code into one place.

Useful, since we still need to implement VPSLLVD and VPSLLVQ.

Also in the event we start supporting AVX-512, then the code can just be
extended from a single point.
 2023-03-21 16:25:20 -04:00
Lioncache 392438d70a ARMEmitter: Handle SVE inc/dec register by predicate count group 2023-03-21 16:16:13 -04:00
Lioncache 0930a10026 ARMEmitter: Handle SVE inc/dec vector by predicate count group 2023-03-21 16:16:13 -04:00
Lioncache cb8ab3d328 ARMEmitter: Handle SVE saturating inc/dec register by predicate count group 2023-03-21 16:16:13 -04:00
Lioncache a670c1d762 ARMEmitter: Handle SVE saturating inc/dec vector by predicate count group 2023-03-21 16:16:11 -04:00
Ryan Houdek 91f056bd2d Merge pull request #2556 from lioncash/shift 
OpcodeDispatcher: Handle VPSRLVD/VPSRLVQ
 2023-03-21 12:29:19 -07:00
Lioncache efba2aed7d Arm64/VectorOps: Remove unnecessary mov in VSShr 
We can just use the movprfx to move the data to shift into the
destination and then perform the shift directly with Dst as an operand.

This is safe, since no original vectors are used in the ASR operation,
only temporaries are used.

Lets us eliminate a temporary and keep things simpler.
 2023-03-21 15:03:59 -04:00
Lioncache 233aef5289 OpcodeDispatcher: Handle VPSRLVD/VPSRLVQ 2023-03-21 15:03:59 -04:00
Lioncache 9d38bc0c81 x86_64/VectorOps: Implement VUShr IR op 
Will be used for implementing VPSRLV AVX ops
 2023-03-21 15:03:59 -04:00
Lioncache a76967650a Arm64/VectorOps: Implement VUShr IR op 
Will be used for implementing VPSRLV AVX ops
 2023-03-21 15:03:55 -04:00
Ryan Houdek 7f0cccfbe0 Merge pull request #2555 from lioncash/pred 
ARMEmitter: Handle SVE Element Count category
 2023-03-21 10:49:21 -07:00
Lioncache 437ea926b4 ARMEmitter: Handle SVE saturating inc/dec register by element count 2023-03-21 12:55:48 -04:00
Lioncache 4359f7439a ARMEmitter: Handle SVE inc/dec register by element count 2023-03-21 12:32:28 -04:00
Lioncache a1712ab455 ARMEmitter: Handle SVE inc/dec vector by element count group 2023-03-21 12:24:39 -04:00
Lioncache 0553f69eed ARMEmitter: Handle SVE element count category 2023-03-21 12:13:20 -04:00
Lioncache d03dfe2b33 ARMEmitter: Handle SVE saturating inc/dec vector by element count group 2023-03-21 12:06:50 -04:00
Lioncache 97bc3afb84 HostFeatures: Mark DCZID related utilities as [[maybe_unused]] 
When building with the simulator enabled, these aren't used and cause
some unused funtion/variable warnings.

We can silence these with [[maybe_unused]], since these are used in
non-simulator builds.
 2023-03-21 11:26:55 -04:00
Ryan Houdek 606242472a Convert the rest of map to fextl 2023-03-16 03:03:08 -07:00
Ryan Houdek 8941b8a312 Convert the rest of vector to fextl 2023-03-16 03:03:08 -07:00
Ryan Houdek bba8716c7e Merge pull request #2544 from Sonicadvance1/bulk_fextl_discount 
fextl: Bulk merge
 2023-03-16 02:24:34 -07:00
Ryan Houdek aea90287eb Merge pull request #2520 from lioncash/cnt 
ARMEmitter: Handle SVE predicate count group
 2023-03-15 12:23:30 -07:00
Ryan Houdek 95a4994200 Cache: Convert over to fextl 
Requires #2542 merged first. First commit is cherry-picked from that PR.
 2023-03-15 12:22:04 -07:00
Ryan Houdek 7b790903c9 AOT: Convert set to fextl 
This worms its way all the way to the frontend
 2023-03-15 12:16:03 -07:00
Ryan Houdek a9a2c95202 Jit64: Convert unordered_map to fextl 
Interpreter just remove the destination as a map. This isn't useful
anymore.
 2023-03-15 12:14:59 -07:00
Ryan Houdek 6b053d298e VDSOEmulation: Convert vector to fextl 
Pipes back to thunk definitions in FEXCore as well.
 2023-03-15 12:08:58 -07:00
Ryan Houdek e8132b82d0 LookupCache: Convert vector to fextl 2023-03-15 12:05:42 -07:00
Ryan Houdek cdac296ce3 GDBServer: Convert vector to fextl 2023-03-15 12:05:37 -07:00
Ryan Houdek ffbcc52af6 Frontend/OpDispatcher: Convert vector to fextl 
These two are intrinsicly linked. Need to cover both at the same time.
 2023-03-15 12:05:30 -07:00
Ryan Houdek ddafc172fc CPUID: Convert vector to fextl 2023-03-15 12:05:26 -07:00
Ryan Houdek df17f7adbb JITs: Convert relocations vector to fextl 
Kind of goes places.
 2023-03-15 12:05:12 -07:00
Ryan Houdek 9ffbffe463 Interpreter: Convert vector to fextl 2023-03-15 12:05:07 -07:00
Ryan Houdek 1aaa03a10d Dispatcher: Removes signal frame stack 
This wasn't used anymore. Removed.
 2023-03-15 12:05:02 -07:00
Ryan Houdek e4b2ed72a8 CodeEmitter: Convert vector to fextl 
Needs #2506 merged first. First commit is cherry-picked from it.
 2023-03-15 12:04:57 -07:00
Lioncache 02e245d61f OpcodeDispatcher: Handle VCVTSI2SD 2023-03-14 15:36:54 -04:00
Lioncache 03724c8486 OpcodeDispatcher: Handle VCVTSI2SS 2023-03-14 15:28:55 -04:00
Lioncache f8a575a982 OpcodeDispatcher: Factor out CVTGPR_To_FPR impl to helper 
This can be used for the AVX implementations as well.
 2023-03-14 15:12:21 -04:00
Lioncache 8b20921341 ARMEmitter: Handle SVE predicate count group 2023-03-14 14:49:38 -04:00
Ryan Houdek 8633528cee Merge pull request #2502 from lioncash/flag 
OpcodeDispatcher: Handle VPINSRB/VPINSRD/VPINSRQ/VPINSRW
 2023-03-14 11:44:06 -07:00
Lioncache ce961a3ef4 OpcodeDispatcher: Handle VPINSRD/VPINSRQ 
These are handled from the same encoding via the VEX.W bit.
 2023-03-14 14:17:59 -04:00
Lioncache 8ce87d3b27 OpcodeDispatcher: Handle VPINSRW 2023-03-14 14:17:55 -04:00
Lioncache 24f03dd740 OpcodeDispatcher: Handle VPINSRB 2023-03-14 14:16:44 -04:00
Lioncache a1b0d1853b OpcodeDispatcher: Move PINSROp implementation to helper 2023-03-14 14:16:44 -04:00
Lioncache 6531d369cd Frontend: Handle 'op DST_XMM, SRC_XMM, GPR' AVX patterns 
Things like VPINSRB and co. use this pattern, as well as VCVTSI2S{D,S}.

No other VEX-encoded instructions expect the first source to be a GPR
aside from some of the BMI1/BMI2 instructions, so we'll need to check
for this case.
 2023-03-14 14:16:41 -04:00
Ryan Houdek 7344680672 Merge pull request #2501 from lioncash/ind 
ARMEmitter: Handle floating-point multiply add (indexed) groups
 2023-03-14 08:58:35 -07:00