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Author SHA1 Message Date
Ryan Houdek 2c64523317 InstCountCI: Fix some mislabeled instructions 
These were all optimal. Fixed now.
 2023-08-22 18:47:17 -07:00
Lioncache 2b071e282e OpcodeDispatcher: Remove unnecessary moves from AVXVariableShiftImpl 
We already zero-extend on a store if necessary.
 2023-08-22 21:20:34 -04:00
Ryan Houdek 14144523f7 Merge pull request #2961 from lioncash/minpos 
OpcodeDispatcher: Remove unnecessary move from VPHMINPOSUW
 2023-08-22 18:19:46 -07:00
Ryan Houdek 1f2c5fc6c6 Merge pull request #2960 from lioncash/index 
Arm64: Optimize SVE VInsElement
 2023-08-22 18:19:13 -07:00
Mai 42200bf7b6 Merge pull request #2959 from Sonicadvance1/movlpd_store 
X86Tables: Optimize MOVLPD stores
 2023-08-22 21:02:23 -04:00
Lioncache fa17d9fae9 OpcodeDispatcher: Remove unnecessary move from VPHMINPOSUW 
We already do a zero-extend if necessary in StoreResult.

This also lets us unify both the SSE and AVX handling code.
 2023-08-22 20:59:56 -04:00
Lioncache 398a70312e Arm64: Optimize SVE VInsElement 
This can be done without storing any data to memory and also
compressing the amount of instructions being used.

Thanks to @dougallj for the optimization suggestions.
 2023-08-22 20:36:29 -04:00
Ryan Houdek 76afc653e8 InstCountCI: Update for movlpd store optimization 2023-08-22 17:34:15 -07:00
Ryan Houdek d3ed9766e8 X86Tables: Optimize MOVLPD stores 
Just use the full register size and store the lower bits.
 2023-08-22 17:33:34 -07:00
Ryan Houdek ed7f1b017d Merge pull request #2958 from Sonicadvance1/optimize_phminpos 
OpcodeDispatcher: Optimize phminposuw
 2023-08-22 16:58:27 -07:00
Ryan Houdek fb60f9e406 InstCountCI: Update for phminposuw optimization 2023-08-22 16:29:06 -07:00
Ryan Houdek c795d42d21 OpcodeDispatcher: Optimize phminposuw 
I would now consider the XMM version of this to be optimal.

Thanks to @rygorous for giving the idea for how to optimize this!
 2023-08-22 16:29:06 -07:00
Ryan Houdek bbf9cb9d52 IR: Implements new VRev32 and LoadNamedVectorConstant ops 
VRev32 matches Arm64 semantics directly.
LoadNamedVectorConstant allows FEX to quickly load "named constants".
This will allow us to have specific hardcoded vector constant values
that we can load with a ldr(State)+ldr(Value) and will be more abused in
the future.
This also allows us to do a very simple optimization in the future where
we can optimize away redundant loads of these loads if they are used
multiple times in the same block. (Not implemented here).
 2023-08-22 16:29:06 -07:00
Mai 6c7933e7b1 Merge pull request #2957 from Sonicadvance1/optimize_pfnacc 
OpcodeDispatcher: Optimize PFNACC
 2023-08-22 10:10:11 -04:00
Ryan Houdek 364f084604 Merge pull request #2956 from Sonicadvance1/optimize_hsubp 
OpcodeDispatcher: Optimize hsubp
 2023-08-21 20:47:50 -07:00
Ryan Houdek ffa8f1e3dc Merge pull request #2955 from lioncash/sign 
OpcodeDispatcher: Remove redundant move from VPSIGN
 2023-08-21 20:47:41 -07:00
Ryan Houdek be5d5b06f8 InstCountCI: Update for pfnacc 2023-08-21 20:38:25 -07:00
Ryan Houdek ad6738939b OpcodeDispatcher: Optimize PFNACC 
Turns out this can be even more optimal.
 2023-08-21 20:38:18 -07:00
Mai 9df94d8a93 Merge pull request #2954 from Sonicadvance1/optimize_pmuludq 
OpcodeDispatcher: Optimize pmuludq
 2023-08-21 23:33:45 -04:00
Ryan Houdek 9ae85b2251 InstCountCI: Update for hsubp 2023-08-21 20:24:37 -07:00
Ryan Houdek dcb3e4ee86 OpcodeDispatcher: Optimize hsubp 
This makes the SSE version optimal.
This dramatically improves the AVX version as well.
 2023-08-21 20:22:14 -07:00
Lioncache dbbe6288de OpcodeDispatcher: Remove redundant move from VPSIGN 
StoreResult will already zero-extend if the vector is 128-bit.
 2023-08-21 23:11:07 -04:00
Ryan Houdek de1f75f7a5 InstCountCI: Update for pmuludq 2023-08-21 20:08:19 -07:00
Ryan Houdek 1563398d2c OpcodeDispatcher: Optimize pmuludq 
MMX version was already optimal, SSE version is now also.
AVX version is significantly improved.
 2023-08-21 20:07:35 -07:00
Ryan Houdek 71984fc0ea Merge pull request #2953 from lioncash/scalar 
OpcodeDispatcher: Remove redundant move in AVXVectorScalarALUOpImpl
 2023-08-21 19:51:23 -07:00
Lioncache 920a0fb132 OpcodeDispatcher: Remove redundant move in AVXVectorScalarALUOpImpl 
Our store will already zero-extend if the vector is 128-bit.
 2023-08-21 22:39:07 -04:00
Ryan Houdek 3c88671cca Merge pull request #2952 from lioncash/alu 
OpcodeDispatcher: Remove redundant moves in AVXVectorALUOp
 2023-08-21 19:26:22 -07:00
Lioncache ce8169794f OpcodeDispatcher: Remove redundant moves in AVXVectorALUOp 
We already zero-extend on a store if we have 256-bit vectors and the stored
vector is 128-bit.
 2023-08-21 22:13:29 -04:00
Mai 185e3bfcb6 Merge pull request #2950 from Sonicadvance1/optimize_pmaddwd 
OpcodeDispatcher: Optimize pmaddwd
 2023-08-21 21:39:30 -04:00
Mai 3c49b3238a Merge pull request #2949 from Sonicadvance1/optimize_phsub 
OpcodeDispatcher: Optimize phsub
 2023-08-21 21:39:02 -04:00
Ryan Houdek 2d7a3a578e Merge pull request #2931 from Sonicadvance1/optimize_psign 
Optimize PSIGN and VBSL
 2023-08-21 18:30:55 -07:00
Ryan Houdek 3a2a576c35 Merge pull request #2951 from lioncash/shift 
OpcodeDispatcher: Handle zero immediate shifts better
 2023-08-21 18:20:18 -07:00
Ryan Houdek fe4de26250 InstCountCI: Updates tests for pmaddwd optimization 
MMX and SSE implementations are now optimal.
 2023-08-21 17:55:20 -07:00
Ryan Houdek 869136b907 OpcodeDispatcher: Optimize pmaddwd 
This is actually fairly trivial looking at it.
 2023-08-21 17:53:32 -07:00
Lioncache af8b6766d8 OpcodeDispatcher: Handle zero immediate shifts better 
In the SSE and lower cases, we don't need to do anything,
since the value is already in the destination.
 2023-08-21 20:46:41 -04:00
Ryan Houdek d283d1ba11 InstCountCI: Update for phsub optimization 
MMX and SSE now optimal
 2023-08-21 17:38:24 -07:00
Ryan Houdek 30e9beba51 JIT64: Fixes i32v2 unzips 
This has just been broken since it was implemented. Turns out we had
never used these with XMM operations before today.
 2023-08-21 17:38:24 -07:00
Ryan Houdek 8ee6262e5e Merge pull request #2946 from Sonicadvance1/optimize_mpsad 
OpcodeDispatcher: Optimizes mpsadbw
 2023-08-21 17:33:03 -07:00
Ryan Houdek 637a5d3b18 InstCountCI: Updates results from mpsadbw optimization 
Pretty sure the SSE versions are optimal implementations.
The AVX versions still have spurious moves that can probably get
removed.
 2023-08-21 16:57:13 -07:00
Ryan Houdek a29076244f OpcodeDispatcher: Optimizes mpsadbw 
Two optimizations here:
1) The final VInsElement was generating three instructions
   - This itself could have been change to vzip, which would have
     removed two instructions.
2) Optimize how the pairwise elements are calculated to shave one
   instruction off the calculation.
   - addp odd elements and even elemnts first
   - Then transpose those elements
   - Then use one final addp to generate the result in the correct
     order.

The ext+uabdl+addp pairs of operations could be reordered to shave off
one temporary register usage if we really care later.
 2023-08-21 16:56:41 -07:00
Ryan Houdek 445c43792b OpcodeDispatcher: Optimize phsub 
This was...surprisingly bad. I blame myself entirely.
 2023-08-21 16:54:35 -07:00
Mai f4f9b20f32 Merge pull request #2948 from Sonicadvance1/fix_newline 
InstCountCI: Add newline to end of file
 2023-08-21 19:50:53 -04:00
Mai 34a7feffe8 Merge pull request #2947 from Sonicadvance1/optimize_pmaddubsw 
OpcodeDispatcher: Optimize SSE/AVX pmaddubsw
 2023-08-21 19:50:10 -04:00
Ryan Houdek b559982515 InstCountCI: Update for newlines 2023-08-21 16:26:46 -07:00
Ryan Houdek ca96a25a7a InstCountCI: Add newline to end of file 
This way these endlines don't constantly keep getting toggled.
 2023-08-21 16:26:20 -07:00
Ryan Houdek 3f82c8cfe5 InstCountCI: Update for pmaddubsw 
Not quite optimal but a heck of a lot better.
 2023-08-21 16:22:00 -07:00
Ryan Houdek b35f4df798 OpcodeDispatcher: Optimize SSE pmaddubsw 
Can be slightly more optimal with a slightly change algorithm but will
require implementing some IR ops which can be put off. It's only about
an instruction savings.
 2023-08-21 16:21:01 -07:00
Ryan Houdek e765bd8986 Merge pull request #2945 from lioncash/interpdata 
Interpreter: Tie SSA data elements to supported vector width
 2023-08-21 11:52:01 -07:00
Lioncache f1d020ce95 Interpreter: Tie SSA data elements to supported vector width 
Now, if we ever increase our vector sizes, the allocated data elements
will follow suit without needing to remember to handle this as well.
 2023-08-21 14:41:00 -04:00
Ryan Houdek 8b9ee997b2 Merge pull request #2944 from lioncash/interparray 
Interpreter: Use alias for temporary vector data
 2023-08-21 11:28:24 -07:00