steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-27 17:00:33 +01:00
Code Issues Packages Projects Releases 67 Wiki Activity
9,533 Commits 11 Branches 71 Tags
c28824f94de6cb3e83becbbcd9473cfc9d2bfd22
Commit Graph
9533 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Ryan Houdek df99b7b9b6 Merge pull request #2994 from Sonicadvance1/cache_namedvectorconstants 
OpcodeDispatcher: Cache named vector constants in the block
 2023-08-24 15:00:05 -07:00
Ryan Houdek 565b30e15e OpcodeDispatcher: Cache named vector constants in the block 
If the named constant of that size gets used multiple times then just
use the previous value if it was in scope.

Makes addsubp{s,d} and phminposuw more optimal for each that are in a
block.

Needs #2993 merged first.
 2023-08-24 14:46:37 -07:00
Mai ab83ab42dd Merge pull request #2993 from Sonicadvance1/addsub_opt 
OpcodeDispatcher: Optimize AddSubP{S,D}
 2023-08-24 17:44:41 -04:00
Ryan Houdek b0ec4197ba Merge pull request #2997 from lioncash/fmt 
Externals: Update fmt to 10.1.0
 2023-08-24 14:19:18 -07:00
Lioncache 9035a29906 Externals: Update fmt to 10.1.0 
Updates fmt to the latest version.
 2023-08-24 17:01:40 -04:00
Ryan Houdek b547550442 InstCountCI: Update for addsubp 2023-08-23 20:33:55 -07:00
Ryan Houdek f300196d90 OpcodeDispatcher: Optimize AddSubP{S,D} 
Use a named constant for loading the sign inversion, then EOR the second
source and just FAdd it all.
In a vacuum it isn't a significant improvement, but as soon as more than
one instruction is in a block it will eventually get optimized with
named constant caching and be a significant win.

Thanks to @rygorous for the idea!
 2023-08-23 20:32:51 -07:00
Ryan Houdek c5f358b47a Merge pull request #2992 from lioncash/doc 
x86_64/MemoryOps: Fix mislabeled IR op messages
 2023-08-23 20:05:39 -07:00
Lioncache 42ccc18606 x86_64/MemoryOps: Fix mislabeled IR op messages 2023-08-23 22:54:36 -04:00
Mai 66c6f96120 Merge pull request #2990 from Sonicadvance1/optimize_pmulh 
OpcodeDispatcher: Optimize PMULH{U,}W using new IR operations
 2023-08-23 22:06:14 -04:00
Ryan Houdek 1aa2c534f7 Merge pull request #2991 from lioncash/pcl 
OpcodeDispatcher: Remove redundant moves from PCLMULQDQ and AES operations
 2023-08-23 18:47:52 -07:00
Ryan Houdek e9f292462a InstCountCI: Update for pmulh{u,}w optimization 2023-08-23 18:38:05 -07:00
Ryan Houdek 77b6d854b9 OpcodeDispatcher: Optimize PMULH{U,}W using new IR operations 
SSE implementations are now optimal.
SVE-128bit operation makes it more optimal.
 2023-08-23 18:38:05 -07:00
Ryan Houdek 05b9651279 IR: Implements new vector multiply returning high bits 
SVE implemented a new instruction that does this explicitly, so we
should support it directly.
 2023-08-23 18:38:05 -07:00
Lioncache 26c81224ac OpcodeDispatcher: Remove redundant moves from AESIMC 
Zero-extension will occur automatically upon storing if necessary.

We can also join the SSE and AVX implementations together.
 2023-08-23 21:34:37 -04:00
Lioncache 8a622a3c1a OpcodeDispatcher: Remove redundant moves from VAESEnc 
Zero-extension will occur automatically upon storing if necessary.
 2023-08-23 21:30:06 -04:00
Lioncache f4848fd1a7 OpcodeDispatcher: Remove redundant moves from VAESEncLast 
Zero-extension will occur automatically upon storing if necessary.
 2023-08-23 21:28:14 -04:00
Lioncache d37ce08ae9 OpcodeDispatcher: Remove redundant move from VAESDec 
Zero-extension will occur automatically upon storing if necessary.
 2023-08-23 21:26:49 -04:00
Lioncache a6f1a9f8e8 OpcodeDispatcher: Remove redundant moves from VAESDecLast 
Zero-extension will occur upon storing if necessary.
 2023-08-23 21:25:15 -04:00
Lioncache 52ab3f6a1e OpcodeDispatcher: Remove redundant moves from VAESKeyGenAssist 
Zero-extension will occur upon storing if necessary.

We can also join the AVX implementation with the SSE one.
 2023-08-23 21:22:00 -04:00
Lioncache 410e99ba09 OpcodeDispatcher: Remove redundant moves from VPCLMULQDQOp 
Zero-extension will occur if necessary upon storing.
 2023-08-23 21:18:39 -04:00
Ryan Houdek 6e4765d48b Merge pull request #2989 from lioncash/ins 
Arm64/ConversionOps: Remove redundant moves in AdvSIMD VInsGPR
 2023-08-23 18:09:15 -07:00
Ryan Houdek 172c8f3ba6 Merge pull request #2988 from lioncash/half 
Arm64/ConversionOps: Add missing half-precision conversions to scalar functions
 2023-08-23 17:56:23 -07:00
Lioncache 203a2b1105 Arm64/ConversionOps: Remove redundant moves in AdvSIMD VInsGPR 
If Dst and DestVector alias one another, then we don't need to
move the vector unnecessarily.
 2023-08-23 20:50:21 -04:00
Ryan Houdek 4297e13fcf Merge pull request #2986 from lioncash/ext 
Arm64/VectorOps: Remove redundant moves in SVE VExtr when possible
 2023-08-23 17:40:50 -07:00
Ryan Houdek 5b8a0f1e0d Merge pull request #2987 from lioncash/shift 
Arm64/VectorOps: Remove redundant moves from VSQXTN2/VSQXTUN2/VSQSHL/VSRSHR
 2023-08-23 17:40:39 -07:00
Lioncache 5ad56ad52e Arm64/ConversionOps: Add missing half-precision operations to Float_FromGPR_S 
Provides parity with vector operations.
 2023-08-23 20:36:34 -04:00
Lioncache 24e7baf28f Arm64/ConversionOps: Add missing half-precision conversions to Float_FToF 
Provides parity with the vector conversion operations.
 2023-08-23 20:31:49 -04:00
Lioncache b248ae4c04 Arm64/VectorOps: Remove redundant moves from SVE SQSHL 
We don't need to emit a move if the destination and source alias.
 2023-08-23 20:12:09 -04:00
Lioncache 95bea864cf Arm64/VectorOps: Remove redundant moves from SVE SRSHR 
We don't need to perform a move is the destination aliases
the source vector to be shifted.
 2023-08-23 20:10:51 -04:00
Lioncache 47c4507bb6 Arm64/VectorOps: Remove redundant moves from SVE VSQXTUN2 
We don't need to perform a move if the destination aliases the lower vector.
 2023-08-23 20:10:29 -04:00
Lioncache 5ea0b6db28 Arm64/VectorOps: Remove redundant moves from SVE VSQXTN2 
We don't need to perform a move if the destination aliases the
lower vector.
 2023-08-23 20:02:28 -04:00
Mai ee10153d14 Merge pull request #2984 from Sonicadvance1/optimize_pack 
OpcodeDispatcher: Use new IR ops for pack instructions
 2023-08-23 20:02:16 -04:00
Lioncache d0d94adabe Arm64/VectorOps: Remove redundant moves in SVE VExtr when possible 
We don't need to do any moves here is the destination aliases the
lower bits.
 2023-08-23 19:56:10 -04:00
Ryan Houdek 926b8c2c97 Merge pull request #2985 from lioncash/shift 
Arm64/VectorOps: Remove redundant moves from SVE variable/immediate/vector shifts when possible
 2023-08-23 16:41:39 -07:00
Lioncache 18ebcdc9de Arm64/VectorOps: Remove redundant moves in VUshrNI2 
If the destination and VectorLower alias, then we don't need
to emit a movprfx.
 2023-08-23 18:52:32 -04:00
Lioncache f31a9a52e6 Arm64/VectorOps: Remove redundant moves from SVE immediate vector shifts when possible 
If the destination and source vector alias one another, then the
operation can largely be done in place.
 2023-08-23 18:36:21 -04:00
Lioncache 03504a5f8c Arm64/VectorOps: Remove redundant moves from SVE vector shifts when possible 
If the destination and the vector to be shifted alias, then we can
avoid needing to move some data around.
 2023-08-23 18:24:58 -04:00
Lioncache d29b4de1ee Arm64/VectorOps: Remove redundant moves from SVE variable vector register shifts when possible 
In the event that the destination and the vector to be shifted
alias one another, then we can skip the movprfx, since it's not
necessary.
 2023-08-23 18:24:53 -04:00
Ryan Houdek 5e20be756e InstCountCI: Update for pack instruction optimization 2023-08-23 15:16:54 -07:00
Ryan Houdek fc4559d3c4 OpcodeDispatcher: Use new IR ops for pack instructions 
The MMX and SSE versions of these instructions are now optimal.
 2023-08-23 15:14:38 -07:00
Ryan Houdek c508570da0 IR: Implements VSQXT{U,}NPair operations 
This takes the two independent VSXT{U}N{2,} operations and merges them
in to a single IR operations.
In some cases this can result in a more optimal implementation since
there is no need for moves inbetween.
 2023-08-23 15:13:07 -07:00
Ryan Houdek ec6548e302 Merge pull request #2983 from lioncash/bsl 
Arm64/VectorOps: Remove redundant moves from SVE BSL when possible
 2023-08-23 15:11:34 -07:00
Lioncache d5e145c4b0 Arm64/VectorOps: Remove redundant moves from SVE BSL when possible 
If the destination and true vector alias one another, then we can
perform the operation in place instead of moving data around.
 2023-08-23 17:54:10 -04:00
Ryan Houdek 350bca97c6 Merge pull request #2982 from lioncash/imin 
Arm64/VectorOps: Remove redundant moves from SVE V{S,U}Min/V{S,U}Max when possible
 2023-08-23 14:53:15 -07:00
Ryan Houdek 226405880f Merge pull request #2981 from lioncash/fmin 
Arm64/VectorOps: Remove redundant moves from SVE VFMin/VFMax when possible
 2023-08-23 14:46:03 -07:00
Lioncache 37a8cb6821 Arm64/VectorOps: Remove redundant moves from SVE VSMax when possible 
When the destination and first source alias one another, then we
can perform the operation in place instead of moving data around.
 2023-08-23 17:34:52 -04:00
Lioncache fe2c7dbf97 Arm64/VectorOps: Remove redundant moves from SVE VUMax when possible 
When the destination and source alias one another, then we
can perform the operation in place without needing to move
data around.
 2023-08-23 17:32:17 -04:00
Lioncache 787b4f37fb Arm64/VectorOps: Remove redundant moves from SVE VSMin when possible 
When the destination and first source alias one another, then we can
perform the operation in place without moving any data.
 2023-08-23 17:30:08 -04:00
Lioncache c3faa019f5 Arm64/VectorOps: Remove redundant moves from SVE VUMin when possible 
If the destination and first source alias, then we can perfom the operation
in place.
 2023-08-23 17:27:52 -04:00