Docs: Update for release FEX-2408

Merge pull request #3945 from Sonicadvance1/config_nonnullable
Config: Little assume non-null check
2026-10-17 23:00:36 +02:00 · 2024-08-12 15:05:37 -07:00 · 2024-08-11 15:23:37 -04:00 · 2024-08-11 10:25:53 -07:00 · 2024-08-10 20:07:43 -04:00 · 2024-08-10 09:07:58 -07:00
909 changed files with 333819 additions and 123546 deletions
@@ -0,0 +1,109 @@
+Language: Cpp
+BasedOnStyle: WebKit
+AccessModifierOffset: -2
+AlignAfterOpenBracket: Align
+AlignArrayOfStructures: None
+AlignConsecutiveAssignments: None
+AlignConsecutiveBitFields: Consecutive
+AlignConsecutiveDeclarations: None
+AlignConsecutiveMacros: None
+AlignEscapedNewlines: Left
+AlignOperands: Align
+AlignTrailingComments: true
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortCaseLabelsOnASingleLine: true
+AllowShortEnumsOnASingleLine: true
+AllowShortFunctionsOnASingleLine: Empty
+AllowShortIfStatementsOnASingleLine: WithoutElse
+AllowShortLambdasOnASingleLine: Inline
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: true
+AttributeMacros:
+  - JEMALLOC_NOTHROW
+  - FEX_ALIGNED
+  - FEX_ANNOTATE
+  - FEX_DEFAULT_VISIBILITY
+  - FEX_NAKED
+  - FEX_PACKED
+  - FEXCORE_PRESERVE_ALL_ATTR
+  - GLIBC_ALIAS_FUNCTION
+BinPackArguments: true
+BinPackParameters: true
+BitFieldColonSpacing: Both
+BreakAfterAttributes: Always # clang 16 required
+BreakBeforeBraces: Attach
+BreakBeforeBinaryOperators: None
+BreakBeforeInlineASMColon: OnlyMultiline # clang 16 required
+BreakBeforeTernaryOperators: false
+BreakConstructorInitializers: BeforeComma
+BreakInheritanceList: BeforeColon
+ColumnLimit: 140
+CompactNamespaces: false
+ConstructorInitializerIndentWidth: 2
+ContinuationIndentWidth: 2
+Cpp11BracedListStyle: true
+DerivePointerAlignment: false
+EmptyLineAfterAccessModifier: Leave
+EmptyLineBeforeAccessModifier: Leave
+ExperimentalAutoDetectBinPacking: false
+FixNamespaceComments: true
+IncludeBlocks: Preserve
+IndentAccessModifiers: false
+IndentCaseBlocks: false
+IndentCaseLabels: false
+IndentExternBlock: AfterExternBlock
+IndentGotoLabels: false
+IndentPPDirectives: None
+IndentRequires: false
+IndentWidth: 2
+InsertBraces: true
+KeepEmptyLinesAtTheStartOfBlocks: true
+LambdaBodyIndentation: OuterScope
+LineEnding: LF # clang 16 required
+MaxEmptyLinesToKeep: 2
+NamespaceIndentation: Inner
+QualifierAlignment: Left
+PackConstructorInitializers: Never
+PenaltyBreakAssignment: 2
+PenaltyBreakBeforeFirstCallParameter: 2
+PenaltyBreakOpenParenthesis: 2
+PenaltyBreakString: 10
+PenaltyBreakTemplateDeclaration: 8
+PenaltyExcessCharacter: 2
+PenaltyReturnTypeOnItsOwnLine: 16
+PointerAlignment: Left
+RemoveBracesLLVM: false
+ReferenceAlignment: Left
+ReflowComments: true
+RequiresClausePosition: WithPreceding
+SeparateDefinitionBlocks: Leave
+SortIncludes: Never
+SpaceAfterCStyleCast: false
+SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: false
+SpaceAroundPointerQualifiers: Default
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCaseColon: false
+SpaceBeforeCpp11BracedList: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeParens: Custom
+SpaceBeforeParensOptions:
+  AfterControlStatements: true
+  AfterFunctionDeclarationName: false
+  AfterFunctionDefinitionName: false
+  AfterOverloadedOperator: false
+  AfterRequiresInClause: true
+  BeforeNonEmptyParentheses: false
+SpaceBeforeRangeBasedForLoopColon: true
+SpaceBeforeSquareBrackets: false
+SpaceInEmptyBlock: false
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 1
+SpacesInAngles: Leave
+SpacesInCStyleCastParentheses: false
+SpacesInConditionalStatement: false
+SpacesInParentheses: false
+Standard: c++20
+UseTab: Never
@@ -0,0 +1,12 @@
+# This file is used to ignore files and directories from clang-format
+
+# Ignore all files in the External directory
+External/*
+
+# SoftFloat-3e code doesn't belong to us 
+FEXCore/Source/Common/SoftFloat-3e/*
+Source/Common/cpp-optparse/*
+
+# Files with human-indented tables for readability - don't mess with these
+FEXCore/Source/Interface/Core/X86Tables/*
+
@@ -0,0 +1,15 @@
+# Since version 2.23 (released in August 2019), git-blame has a feature
+# to ignore or bypass certain commits.
+#
+# This file contains a list of commits that are not likely what you
+# are looking for in a blame, such as mass reformatting or renaming.
+# You can set this file as a default ignore file for blame by running
+# the following command.
+#
+# $ git config blame.ignoreRevsFile .git-blame-ignore-revs
+
+# Whole tree reformat PR#3571
+2b4ec88daebd35fefb5bf5c73d7fc2b4155771ed
+
+# Second reformat to find fixed point PR#3577
+905aa935f5ce344a48ef4d5edab3c31efa8d793e
@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  build_plus_test:
@@ -20,7 +20,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  glibc_fault_test:
@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  hostrunner_tests:
@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  instcountci_tests:
@@ -10,14 +10,13 @@ on:

 env:
  BUILD_TYPE: Debug
-  FEX_ENABLEAVX: 1

 jobs:
  mingw_build:
    runs-on: ${{ matrix.arch }}
    strategy:
      matrix:
-        arch: [[self-hosted, ARM64, mingw]]
+        arch: [[self-hosted, ARM64, mingw], [self-hosted, ARM64EC, mingw, ARM64]]
      fail-fast: false

    steps:
@@ -39,6 +38,11 @@ jobs:
      run: |
        echo "MINGW_TRIPLE=aarch64-w64-mingw32" >> $GITHUB_ENV

+    - name: Set CC Arm64EC
+      if: matrix.arch[1] == 'ARM64EC'
+      run: |
+        echo "MINGW_TRIPLE=arm64ec-w64-mingw32" >> $GITHUB_ENV
+
    - name: Set rootfs paths
      run: |
        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
@@ -74,7 +78,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/toolchain_mingw.cmake -DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_TESTS=False -DENABLE_JEMALLOC=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/toolchain_mingw.cmake -DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_TESTS=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -0,0 +1,76 @@
+# Inspired by LLVM's pr-code-format.yml at 
+# https://github.com/llvm/llvm-project/blob/main/.github/workflows/pr-code-format.yml
+
+name: "Check code formatting"
+on:
+  pull_request:
+    branches:
+      - main
+
+jobs:
+  code_formatter:
+    runs-on: [self-hosted, X64]
+    if: github.repository == 'FEX-Emu/FEX'
+
+    steps:
+      - name: Fetch FEX sources
+        uses: actions/checkout@v4
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+
+      - name: Checkout through merge base
+        uses: rmacklin/fetch-through-merge-base@v0
+        timeout-minutes: 3
+        with:
+          base_ref: ${{ github.event.pull_request.base.ref }}
+          head_ref: ${{ github.event.pull_request.head.sha }}
+          deepen_length: 500
+
+      - name: Get changed files
+        id: changed-files
+        uses: tj-actions/changed-files@v39
+        with:
+          separator: ","
+          skip_initial_fetch: true
+
+      - name: "Listed files"
+        env:
+          CHANGED_FILES: ${{ steps.changed-files.outputs.all_changed_files }}
+        run: |
+          echo "Formatting files:"
+          echo "$CHANGED_FILES"
+
+      - name: Check for correct clang-format version
+        run: clang-format --version | grep -qF '16.0.6'
+
+      - name: Check git-clang-format-16 exists
+        run: which git-clang-format-16
+
+      - name: Setup Python env
+        uses: actions/setup-python@v4
+        with:
+          python-version: '3.11'
+          cache: 'pip'
+          cache-dependency-path: './External/code-format-helper/requirements_formatting.txt'
+
+      - name: Install python dependencies
+        run: pip install -r ./External/code-format-helper/requirements_formatting.txt
+
+      - name: Run code formatter
+        env:
+          CLANG_FORMAT_PATH: 'git-clang-format-16'
+          GITHUB_PR_NUMBER: ${{ github.event.pull_request.number }}
+          START_REV: ${{ github.event.pull_request.base.sha }}
+          END_REV: ${{ github.event.pull_request.head.sha }}
+          CHANGED_FILES: ${{ steps.changed-files.outputs.all_changed_files }}
+        # TODO(pmatos): Once we adopt v18, we should be able
+        # to take advantage of the new --diff_from_common_commit option
+        # explicitly in code-format-helper.py and not have to diff starting at
+        # the merge base.
+        run: |
+          python ./External/code-format-helper/code-format-helper.py \
+            --repo "FEX-emu/FEX" \
+            --issue-number $GITHUB_PR_NUMBER \
+            --start-rev $(git merge-base $START_REV $END_REV) \
+            --end-rev $END_REV \
+            --changed-files "$CHANGED_FILES"
@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  vixl_simulator:
@@ -73,23 +72,22 @@ jobs:
      # Execute the build.  You can specify a specific target with "--target <NAME>"
      run: cmake --build . --config $BUILD_TYPE

-    - name: ASM Tests
+    - name: ASM Tests - SVE256
      working-directory: ${{runner.workspace}}/build
      shell: bash
      # Execute the unit tests
      run: cmake --build . --config $BUILD_TYPE --target asm_tests

-    - name: ASM Test Results move
+    - name: ASM Test SVE256 Results move
      if: ${{ always() }}
      shell: bash
      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM_SVE256Bit.log || true

-    - name: ASM Tests 128-bit
+    - name: ASM Tests - SVE128
      working-directory: ${{runner.workspace}}/build
      shell: bash
      env:
-        FEX_HOSTFEATURES: "disableavx"
        FEX_FORCESVEWIDTH: "128"
      # Execute the unit tests
      run: cmake --build . --config $BUILD_TYPE --target asm_tests
@@ -98,7 +96,21 @@ jobs:
      if: ${{ always() }}
      shell: bash
      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM128bit.log || true
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM_SVE128Bit.log || true
+
+    - name: ASM Tests - ASIMD
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      env:
+        FEX_HOSTFEATURES: "disablesve"
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test ASIMD Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM_ASIMD.log || true

    - name: Truncate test results
      if: ${{ always() }}
@@ -1,5 +1,5 @@
 cmake_minimum_required(VERSION 3.14)
-project(FEX)
+project(FEX C CXX ASM)

 INCLUDE (CheckIncludeFiles)
 CHECK_INCLUDE_FILES ("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
@@ -9,13 +9,13 @@ option(BUILD_FEX_LINUX_TESTS "Build FEXLinuxTests, requires x86 compiler" FALSE)
 option(BUILD_THUNKS "Build thunks" FALSE)
 option(BUILD_FEXCONFIG "Build FEXConfig, requires SDL2 and X11" TRUE)
 option(ENABLE_CLANG_THUNKS "Build thunks with clang" FALSE)
-option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
 option(ENABLE_IWYU "Enables include what you use program" FALSE)
 option(ENABLE_LTO "Enable LTO with compilation" TRUE)
 option(ENABLE_XRAY "Enable building with LLVM X-Ray" FALSE)
 set(USE_LINKER "" CACHE STRING "Allow overriding the linker path directly")
 option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
 option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
+option(ENABLE_COVERAGE "Enables Coverage" FALSE)
 option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_GDB_SYMBOLS "Enables GDBSymbols integration support" ${HAVE_GDB_JIT_READER_H})
 option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
@@ -32,6 +32,7 @@ option(COMPILE_VIXL_DISASSEMBLER "Compiles the vixl disassembler in to vixl" FAL
 option(ENABLE_FEXCORE_PROFILER "Enables use of the FEXCore timeline profiling capabilities" FALSE)
 set (FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend you want to use for the FEXCore profiler")
 option(ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT "Enables glibc memory allocation hooking with fault for CI testing")
+option(USE_PDB_DEBUGINFO "Builds debug info in PDB format" FALSE)

 set (X86_32_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_32.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting i686")
 set (X86_64_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_64.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting x86_64")
@@ -41,7 +42,16 @@ string(FIND ${CMAKE_BASE_NAME} mingw CONTAINS_MINGW)
 if (NOT CONTAINS_MINGW EQUAL -1)
  message (STATUS "Mingw build")
  set (MINGW_BUILD TRUE)
-  set (ENABLE_JEMALLOC FALSE)
+  set (ENABLE_JEMALLOC TRUE)
+  set (ENABLE_JEMALLOC_GLIBC_ALLOC FALSE)
+endif()
+
+if (NOT MINGW_BUILD)
+  message (STATUS "Clang version ${CMAKE_CXX_COMPILER_VERSION}")
+  set (CLANG_MINIMUM_VERSION 12.0)
+  if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS ${CLANG_MINIMUM_VERSION})
+    message (FATAL_ERROR "Clang version too old for FEX. Need at least ${CLANG_MINIMUM_VERSION} but has ${CMAKE_CXX_COMPILER_VERSION}")
+  endif()
 endif()

 if (ENABLE_FEXCORE_PROFILER)
@@ -111,6 +121,12 @@ else()
 endif()

 if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+  option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
+  if (NOT ENABLE_X86_HOST_DEBUG)
+    message(FATAL_ERROR
+    " FEX-Emu doesn't support compiling for x86-64 hosts!"
+    " This is /only/ a supported configuration for FEX CI and nothing else!")
+  endif()
  set(_M_X86_64 1)
  add_definitions(-D_M_X86_64=1)
  set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
@@ -126,6 +142,39 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "^arm64ec")
  add_definitions(-D_M_ARM_64EC=1)
 endif()

+include(CheckCXXSourceCompiles)
+set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
+check_cxx_source_compiles(
+  "
+  __attribute__((preserve_all))
+  int Testy(int a, int b, int c, int d, int e, int f) {
+  return a + b + c + d + e + f;
+  }
+  int main() {
+  return Testy(0, 1, 2, 3, 4, 5);
+  }"
+  HAS_CLANG_PRESERVE_ALL)
+unset(CMAKE_REQUIRED_FLAGS)
+if (HAS_CLANG_PRESERVE_ALL)
+  if (MINGW_BUILD)
+    message(STATUS "Ignoring broken clang::preserve_all support")
+    set(HAS_CLANG_PRESERVE_ALL FALSE)
+  else()
+    message(STATUS "Has clang::preserve_all")
+  endif()
+endif ()
+
+if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL)
+  add_definitions("-DFEX_PRESERVE_ALL_ATTR=__attribute__((preserve_all))" "-DFEX_HAS_PRESERVE_ALL_ATTR=1")
+else()
+  add_definitions("-DFEX_PRESERVE_ALL_ATTR=" "-DFEX_HAS_PRESERVE_ALL_ATTR=0")
+endif()
+
+if (ENABLE_VIXL_SIMULATOR)
+  # We can run the simulator on both x86-64 or AArch64 hosts
+  add_definitions(-DVIXL_SIMULATOR=1 -DVIXL_INCLUDE_SIMULATOR_AARCH64=1)
+endif()
+
 if (ENABLE_CCACHE)
  find_program(CCACHE_PROGRAM ccache)
  if(CCACHE_PROGRAM)
@@ -173,13 +222,18 @@ if (ENABLE_TSAN)
  link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
 endif()

+if (ENABLE_COVERAGE)
+  add_compile_options(-fprofile-instr-generate -fcoverage-mapping)
+  link_libraries(-fprofile-instr-generate -fcoverage-mapping)
+endif()
+
 if (ENABLE_JEMALLOC_GLIBC_ALLOC)
  # The glibc jemalloc subproject which hooks the glibc allocator.
  # Required for thunks to work.
  # All host native libraries will use this allocator, while *most* other FEX internal allocations will use the other jemalloc allocator.
  add_definitions(-DENABLE_JEMALLOC_GLIBC=1)
  add_subdirectory(External/jemalloc_glibc/)
-else()
+elseif (NOT MINGW_BUILD)
  message (STATUS
    " jemalloc glibc allocator disabled!\n"
    " This is not a recommended configuration!\n"
@@ -192,7 +246,7 @@ if (ENABLE_JEMALLOC)
  add_definitions(-DENABLE_JEMALLOC=1)
  add_subdirectory(External/jemalloc/)
  include_directories(External/jemalloc/pregen/include/)
-else()
+elseif (NOT MINGW_BUILD)
  message (STATUS
    " jemalloc disabled!\n"
    " This is not a recommended configuration!\n"
@@ -200,6 +254,11 @@ else()
    " Use at your own risk!")
 endif()

+if (USE_PDB_DEBUGINFO)
+  add_compile_options(-g -gcodeview)
+  add_link_options(-g -Wl,--pdb=)
+endif()
+
 set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
 set (CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")

@@ -233,8 +292,6 @@ add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")

 if (BUILD_TESTS)
-  option(CATCH_BUILD_STATIC_LIBRARY "" ON)
-  set(CATCH_BUILD_STATIC_LIBRARY ON)
  add_subdirectory(External/Catch2/)

  # Pull in catch_discover_tests definition
@@ -255,8 +312,6 @@ include_directories(External/json-maker/)
 add_subdirectory(External/tiny-json/)
 include_directories(External/tiny-json/)

-include_directories(External/xbyak/)
-
 include_directories(Source/)
 include_directories("${CMAKE_BINARY_DIR}/Source/")

@@ -344,57 +399,6 @@ if (ENABLE_IWYU)
  endif()
 endif()

-if (ENABLE_CLANG_FORMAT)
-  find_program(CLANG_TIDY_EXE "clang-tidy")
-  if (NOT CLANG_TIDY_EXE)
-    message(FATAL_ERROR "Couldn't find clang-tidy")
-  endif()
-
-  set(CLANG_TIDY_FLAGS
-    "-checks=*"
-    "-fuchsia*"
-    "-bugprone-macro-parentheses"
-    "-clang-analyzer-core.*"
-    "-cppcoreguidelines-pro-type-*"
-    "-cppcoreguidelines-pro-bounds-array-to-pointer-decay"
-    "-cppcoreguidelines-pro-bounds-pointer-arithmetic"
-    "-cppcoreguidelines-avoid-c-arrays"
-    "-cppcoreguidelines-avoid-magic-numbers"
-    "-cppcoreguidelines-pro-bounds-constant-array-index"
-    "-cppcoreguidelines-no-malloc"
-    "-cppcoreguidelines-special-member-functions"
-    "-cppcoreguidelines-owning-memory"
-    "-cppcoreguidelines-macro-usage"
-    "-cppcoreguidelines-avoid-goto"
-    "-google-readability-function-size"
-    "-google-readability-namespace-comments"
-    "-google-readability-braces-around-statements"
-    "-google-build-using-namespace"
-    "-hicpp-*"
-    "-llvm-namespace-comment"
-    "-llvm-include-order" # Messes up with case sensitivity
-    "-llvmlibc-*"
-    "-misc-unused-parameters"
-    "-modernize-loop-convert"
-    "-modernize-use-auto"
-    "-modernize-avoid-c-arrays"
-    "-modernize-use-nodiscard"
-    "readability-*"
-    "-readability-function-size"
-    "-readability-implicit-bool-conversion"
-    "-readability-braces-around-statements"
-    "-readability-else-after-return"
-    "-readability-magic-numbers"
-    "-readability-named-parameter"
-    "-readability-uppercase-literal-suffix"
-    "-cert-err34-c"
-    "-cert-err58-cpp"
-    "-bugprone-exception-escape"
-    )
-  string(REPLACE ";" "," CLANG_TIDY_FLAGS "${CLANG_TIDY_FLAGS}")
-  set(CMAKE_CXX_CLANG_TIDY ${CLANG_TIDY_EXE} "${CLANG_TIDY_FLAGS}")
-endif()
-
 add_compile_options(-Wall)

 configure_file(
@@ -405,9 +409,18 @@ if (BUILD_TESTS)
  include(CTest)
  enable_testing()
  message(STATUS "Unit tests are enabled")
+
+  set (TEST_JOB_COUNT "" CACHE STRING "Override number of parallel jobs to use while running tests")
+  if (TEST_JOB_COUNT)
+    message(STATUS "Running tests with ${TEST_JOB_COUNT} jobs")
+  elseif(CMAKE_VERSION VERSION_LESS "3.29")
+    execute_process(COMMAND "nproc" OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE TEST_JOB_COUNT)
+  endif()
+  set(TEST_JOB_FLAG "-j${TEST_JOB_COUNT}")
 endif()

 add_subdirectory(FEXHeaderUtils/)
+add_subdirectory(CodeEmitter/)
 add_subdirectory(FEXCore/)

 # Binfmt_misc files must be installed prior to Source/ installs
@@ -0,0 +1,2 @@
+add_library(CodeEmitter INTERFACE)
+target_include_directories(CodeEmitter INTERFACE .)
@@ -8,11 +8,11 @@ public:
  public:
    // Conditional branch immediate
    ///< Branch conditional
-    void b(FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+    void b(ARMEmitter::Condition Cond, uint32_t Imm) {
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 0, Cond, Imm);
    }
-    void b(FEXCore::ARMEmitter::Condition Cond, BackwardLabel const* Label) {
+    void b(ARMEmitter::Condition Cond, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
      constexpr uint32_t Op = 0b0101'010 << 25;
@@ -20,13 +20,13 @@ public:
    }
    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void b(FEXCore::ARMEmitter::Condition Cond, LabelType *Label) {
+    void b(ARMEmitter::Condition Cond, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 0, Cond, 0);
    }

-    void b(FEXCore::ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
+    void b(ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        b(Cond, &Label->Backward);
      }
@@ -36,11 +36,11 @@ public:
    }

    ///< Branch consistent conditional
-    void bc(FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+    void bc(ARMEmitter::Condition Cond, uint32_t Imm) {
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 1, Cond, Imm);
    }
-    void bc(FEXCore::ARMEmitter::Condition Cond, BackwardLabel const* Label) {
+    void bc(ARMEmitter::Condition Cond, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
      constexpr uint32_t Op = 0b0101'010 << 25;
@@ -49,13 +49,13 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void bc(FEXCore::ARMEmitter::Condition Cond, LabelType *Label) {
+    void bc(ARMEmitter::Condition Cond, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 1, Cond, 0);
    }

-    void bc(FEXCore::ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
+    void bc(ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        bc(Cond, &Label->Backward);
      }
@@ -65,7 +65,7 @@ public:
    }

    // Unconditional branch register
-    void br(FEXCore::ARMEmitter::Register rn) {
+    void br(ARMEmitter::Register rn) {
      constexpr uint32_t Op = 0b1101011 << 25 |
                              0b0'000 << 21 |   // opc
                              0b1'1111 << 16 |  // op2
@@ -74,7 +74,7 @@ public:

      UnconditionalBranch(Op, rn);
    }
-    void blr(FEXCore::ARMEmitter::Register rn) {
+    void blr(ARMEmitter::Register rn) {
      constexpr uint32_t Op = 0b1101011 << 25 |
                              0b0'001 << 21 |   // opc
                              0b1'1111 << 16 |  // op2
@@ -83,7 +83,7 @@ public:

      UnconditionalBranch(Op, rn);
    }
-    void ret(FEXCore::ARMEmitter::Register rn = FEXCore::ARMEmitter::Reg::r30) {
+    void ret(ARMEmitter::Register rn = ARMEmitter::Reg::r30) {
      constexpr uint32_t Op = 0b1101011 << 25 |
                              0b0'010 << 21 |   // opc
                              0b1'1111 << 16 |  // op2
@@ -156,13 +156,13 @@ public:
    }

    // Compare and branch
-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
+    void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) {
      constexpr uint32_t Op = 0b0011'0100 << 24;

      CompareAndBranch(Op, s, rt, Imm);
    }

-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BackwardLabel const* Label) {
+    void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");

@@ -173,7 +173,7 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, LabelType *Label) {
+    void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });

      constexpr uint32_t Op = 0b0011'0100 << 24;
@@ -181,7 +181,7 @@ public:
      CompareAndBranch(Op, s, rt, 0);
    }

-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BiDirectionalLabel *Label) {
+    void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        cbz(s, rt, &Label->Backward);
      }
@@ -190,13 +190,13 @@ public:
      }
    }

-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
+    void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) {
      constexpr uint32_t Op = 0b0011'0101 << 24;

      CompareAndBranch(Op, s, rt, Imm);
    }

-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BackwardLabel const* Label) {
+    void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");

@@ -207,7 +207,7 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, LabelType *Label) {
+    void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });

      constexpr uint32_t Op = 0b0011'0101 << 24;
@@ -215,7 +215,7 @@ public:
      CompareAndBranch(Op, s, rt, 0);
    }

-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BiDirectionalLabel *Label) {
+    void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        cbnz(s, rt, &Label->Backward);
      }
@@ -225,12 +225,12 @@ public:
    }

    // Test and branch immediate
-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+    void tbz(ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
      constexpr uint32_t Op = 0b0011'0110 << 24;

      TestAndBranch(Op, rt, Bit, Imm);
    }
-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
+    void tbz(ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");

@@ -241,7 +241,7 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
+    void tbz(ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::TEST_BRANCH });

      constexpr uint32_t Op = 0b0011'0110 << 24;
@@ -249,7 +249,7 @@ public:
      TestAndBranch(Op, rt, Bit, 0);
    }

-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
+    void tbz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        tbz(rt, Bit, &Label->Backward);
      }
@@ -258,12 +258,12 @@ public:
      }
    }

-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+    void tbnz(ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
      constexpr uint32_t Op = 0b0011'0111 << 24;

      TestAndBranch(Op, rt, Bit, Imm);
    }
-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
+    void tbnz(ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");

@@ -274,14 +274,14 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
+    void tbnz(ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::TEST_BRANCH });
      constexpr uint32_t Op = 0b0011'0111 << 24;

      TestAndBranch(Op, rt, Bit, 0);
    }

-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
+    void tbnz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        tbnz(rt, Bit, &Label->Backward);
      }
@@ -292,7 +292,7 @@ public:

 private:
    // Conditional branch immediate
-    void Branch_Conditional(uint32_t Op, uint32_t Op1, uint32_t Op0, FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+    void Branch_Conditional(uint32_t Op, uint32_t Op1, uint32_t Op0, ARMEmitter::Condition Cond, uint32_t Imm) {
      uint32_t Instr = Op;

      Instr |= Op1 << 24;
@@ -304,7 +304,7 @@ private:
    }

    // Unconditional branch register
-    void UnconditionalBranch(uint32_t Op, FEXCore::ARMEmitter::Register rn) {
+    void UnconditionalBranch(uint32_t Op, ARMEmitter::Register rn) {
      uint32_t Instr = Op;
      Instr |= Encode_rn(rn);
      dc32(Instr);
@@ -318,8 +318,8 @@ private:
    }

    // Compare and branch
-    void CompareAndBranch(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
-      const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+    void CompareAndBranch(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) {
+      const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;

      uint32_t Instr = Op;

@@ -330,7 +330,7 @@ private:
    }

    // Test and branch - immediate
-    void TestAndBranch(uint32_t Op, FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+    void TestAndBranch(uint32_t Op, ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
      uint32_t Instr = Op;

      Instr |= (Bit >> 5) << 31;
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: MIT
+#pragma once
+#include <cstddef>
+#include <cstdint>
+#include <cstring>
+
+namespace ARMEmitter {
+class Buffer {
+public:
+  Buffer() {
+    SetBuffer(nullptr, 0);
+  }
+
+  Buffer(uint8_t* Base, uint64_t BaseSize) {
+    SetBuffer(Base, BaseSize);
+  }
+
+  void SetBuffer(uint8_t* Base, uint64_t BaseSize) {
+    BufferBase = Base;
+    CurrentOffset = BufferBase;
+    Size = BaseSize;
+  }
+
+  void dc8(uint8_t Data) {
+    decltype(Data)* Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
+    *Memory = Data;
+    CurrentOffset += sizeof(Data);
+  }
+
+  void dc16(uint16_t Data) {
+    decltype(Data)* Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
+    *Memory = Data;
+    CurrentOffset += sizeof(Data);
+  }
+
+  void dc32(uint32_t Data) {
+    decltype(Data)* Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
+    *Memory = Data;
+    CurrentOffset += sizeof(Data);
+  }
+
+  void dc64(uint64_t Data) {
+    decltype(Data)* Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
+    *Memory = Data;
+    CurrentOffset += sizeof(Data);
+  }
+  void EmitString(const char* String) {
+    const auto StringLength = strlen(String);
+    memcpy(CurrentOffset, String, StringLength);
+    CurrentOffset += StringLength;
+  }
+
+  void Align() {
+    // Align the buffer to instruction size
+    auto CurrentAlignment = reinterpret_cast<uint64_t>(CurrentOffset) & 0b11;
+    if (!CurrentAlignment) {
+      return;
+    }
+    CurrentOffset += 4 - CurrentAlignment;
+  }
+
+  template<typename T>
+  T GetCursorAddress() const {
+    return reinterpret_cast<T>(CurrentOffset);
+  }
+
+  static void ClearICache(void* Begin, std::size_t Length) {
+    __builtin___clear_cache(static_cast<char*>(Begin), static_cast<char*>(Begin) + Length);
+  }
+
+  size_t GetCursorOffset() const {
+    return static_cast<size_t>(CurrentOffset - BufferBase);
+  }
+
+  uint8_t* GetBufferBase() const {
+    return BufferBase;
+  }
+
+  void CursorIncrement(size_t Size) {
+    CurrentOffset += Size;
+  }
+
+  void SetCursorOffset(size_t Offset) {
+    CurrentOffset = BufferBase + Offset;
+  }
+
+  uint64_t GetBufferSize() const {
+    return Size;
+  }
+
+  template<typename T>
+  size_t GetCursorOffsetFromAddress(const T* Address) const {
+    return static_cast<size_t>(reinterpret_cast<const uint8_t*>(Address) - BufferBase);
+  }
+
+protected:
+
+  void ResetBuffer() {
+    CurrentOffset = BufferBase;
+  }
+
+  uint8_t* BufferBase;
+  uint8_t* CurrentOffset;
+  uint64_t Size;
+};
+} // namespace ARMEmitter
@@ -0,0 +1,843 @@
+// SPDX-License-Identifier: MIT
+#pragma once
+
+#include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/EnumUtils.h>
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/MathUtils.h>
+#include <FEXCore/fextl/vector.h>
+
+#include <FEXHeaderUtils/BitUtils.h>
+#include <CodeEmitter/Buffer.h>
+#include <CodeEmitter/Registers.h>
+
+#include <array>
+#include <cstdint>
+#include <utility>
+#include <type_traits>
+
+/*
+ * Welcome to FEX-Emu's custom AArch64 emitter.
+ * This was written specifically to avoid the performance cost of the vixl emitter.
+ *
+ * There are some specific design constraints in this design to target a couple features:
+ *   - High performance
+ *   - Low CPU cache performance hit
+ *   - Significantly reduced code footprint
+ *   - Low number of branches
+ *
+ * These requirements are mostly achieved by removing a bunch of developer conveniences
+ * that vixl provides. The developer needs to take a lot of care to not shoot themselves in the foot.
+ *
+ * Misc design decisions:
+ * - Registers are encoded as basic uint32_t enums.
+ *   - Converting between different registers is zero-cost.
+ *   - Passing around as arguments are as cheap as registers
+ *     - Contrast to vixl where every register requires living on the stack.
+ *   - Registers can get encoded in to instructions with a simple `BFM` instruction.
+ *
+ * - Instructions are very simply emitted, allowing direct inlining most of the time.
+ *   - These are simple enough that multiple back-to-back instructions get optimized to 128-bit load-store operations.
+ *     - Contrast to vixl where pretty much no instruction emitter gets inlined.
+ *
+ * - Instruction emitters are /mostly/ unsized. Most instructions take a size argument first, which gets encoded
+ *   directly in to the instruction.
+ *   - Contrast to vixl where the register arguments are how the instructions determine operating size.
+ *   - Size argument allows FEX to use `CSEL` to select a size at runtime, instead of branching.
+ *   - Some instructions are explicitly sized based on register type. Read comments in the respective `inl` files to
+ *     see why.
+ *     Some scalar/vector operations are an example of this.
+ *
+ * - Almost zero helper functions.
+ *   - Primary exception to this rule is load-store operations. These will use a helper to make
+ *     it easier to select the correct load-store instruction. Mostly because these are a nightmare selecting
+ *     the right instruction.
+ */
+namespace ARMEmitter {
+/*
+ * This `Size` enum is used for most ALU operations.
+ * These follow the AArch64 encoding style in most cases.
+ */
+enum class Size : uint32_t {
+  i32Bit = 0,
+  i64Bit,
+};
+
+// This allows us to get the `Size` enum in bits.
+[[nodiscard]]
+constexpr size_t RegSizeInBits(Size size) {
+  return size_t {32} << FEXCore::ToUnderlying(size);
+}
+
+/* This `SubRegSize` enum is used for most ASIMD operations.
+ * These follow the AArch64 encoding style in most cases.
+ */
+enum class SubRegSize : uint32_t {
+  i8Bit = 0b00,
+  i16Bit = 0b01,
+  i32Bit = 0b10,
+  i64Bit = 0b11,
+  i128Bit = 0b100,
+};
+
+// This allows us to get the `SubRegSize` in bits.
+[[nodiscard]]
+constexpr size_t SubRegSizeInBits(SubRegSize size) {
+  return size_t {8} << FEXCore::ToUnderlying(size);
+}
+
+/* This `ScalarRegSize` enum is used for most scalar float
+ * operations.
+ *
+ * This is specifically duplicated from `SubRegSize` to have strongly
+ * typed functions.
+ *
+ * `ScalarRegSize` specifically doesn't have `i128Bit` because scalar operations
+ * can't operate at 128-bit.
+ */
+enum class ScalarRegSize : uint32_t {
+  i8Bit = 0b00,
+  i16Bit = 0b01,
+  i32Bit = 0b10,
+  i64Bit = 0b11,
+};
+
+// This allows us to get the `ScalarRegSize` in bits.
+[[nodiscard]]
+constexpr size_t ScalarRegSizeInBits(ScalarRegSize size) {
+  return size_t {8} << FEXCore::ToUnderlying(size);
+}
+
+/* This `VectorRegSizePair` union allows us to have an overlapping type
+ * to select a scalar operation or a vector depending on which operation
+ * we pass in.
+ * Useful in FEX's vector operations that behave as scalar or vector
+ * depending on various factors. But since the operation will have the sa,e
+ * element size, we want to choose the operation more easily
+ */
+union VectorRegSizePair {
+  ScalarRegSize Scalar;
+  SubRegSize Vector;
+};
+
+// This allows us to create a `VectorRegSizePair` union.
+[[nodiscard]]
+constexpr VectorRegSizePair ToVectorSizePair(SubRegSize size) {
+  return VectorRegSizePair {.Vector = size};
+}
+[[nodiscard]]
+constexpr VectorRegSizePair ToVectorSizePair(ScalarRegSize size) {
+  return VectorRegSizePair {.Scalar = size};
+}
+
+// This `ShiftType` enum is used for ALU shift-register encoded instructions.
+enum class ShiftType : uint32_t {
+  LSL = 0,
+  LSR,
+  ASR,
+  ROR,
+};
+
+// This `ExtendedType` enum is used for ALU extended-register encoded instructions.
+enum class ExtendedType : uint32_t {
+  UXTB = 0b000,
+  UXTH = 0b001,
+  UXTW = 0b010,
+  UXTX = 0b011,
+  SXTB = 0b100,
+  SXTH = 0b101,
+  SXTW = 0b110,
+  SXTX = 0b111,
+  LSL_32 = UXTW,
+  LSL_64 = UXTX,
+};
+
+// This `Condition` enum is used for various conditional instructions.
+enum class Condition : uint32_t {
+  // Meaning:   Int                    - Float
+  CC_EQ = 0, // Equal                  - Equal
+  CC_NE,     // Not Eq                 - Not Eq or unordered
+  CC_CS,     // Carry set              - Greater than, equal, or unordered
+  CC_CC,     // Carry clear            - Less than
+  CC_MI,     // Minus/Negative         - Less than
+  CC_PL,     // Plus, positive or zero - GT, equal, or unordered
+  CC_VS,     // Overflow               - Unordered
+  CC_VC,     // No Overflow            - Ordered
+  CC_HI,     // Unsigned higher        - GT, or unordered
+  CC_LS,     // Unsigned lower or same - LT or EQ
+  CC_GE,     // Signed GT or EQ        - GT or EQ
+  CC_LT,     // Signed LT              - LT or Unordered
+  CC_GT,     // Signed GT              - GT
+  CC_LE,     // Signed LT or EQ        - LT, EQ, or Unordered
+  CC_AL,     // Always                 - Always
+  CC_NV,     // Always                 - Always
+
+  // Aliases
+  CC_HS = CC_CS,
+  CC_LO = CC_CC,
+};
+
+/*
+ * This `StatusFlags` enum is used for conditional compare encoded instructions.
+ * These directly encode to the `nzcv` flags.
+ */
+enum class StatusFlags : uint32_t {
+  None = 0,
+  Flag_V = 0b0001,
+  Flag_C = 0b0010,
+  Flag_Z = 0b0100,
+  Flag_N = 0b1000,
+
+  Flag_NZCV = Flag_N | Flag_Z | Flag_C | Flag_V,
+};
+
+
+/*
+ * This `IndexType` enum is used for load-store instructions.
+ * Not all load-store instructions use this, so the user needs to be careful.
+ */
+enum class IndexType {
+  POST,
+  OFFSET,
+  PRE,
+
+  UNPRIVILEGED,
+};
+
+// Used with adr and scalar + vector load/store variants to denote
+// a modifier operation.
+enum class SVEModType : uint8_t {
+  MOD_UXTW,
+  MOD_SXTW,
+  MOD_LSL,
+  MOD_NONE,
+};
+
+/* This `SVEMemOperand` class is used for the helper SVE load-store instructions.
+ * Load-store instructions are quite expressive, so having a helper that handles these differences is worth it.
+ */
+class SVEMemOperand final {
+public:
+  enum class Type {
+    ScalarPlusScalar,
+    ScalarPlusImm,
+    ScalarPlusVector,
+    VectorPlusImm,
+  };
+
+  SVEMemOperand(XRegister rn, XRegister rm = XReg::zr)
+    : rn {rn}
+    , MemType {Type::ScalarPlusScalar}
+    , MetaType {.ScalarScalarType {
+        .rm = rm,
+      }} {}
+  SVEMemOperand(XRegister rn, int32_t imm = 0)
+    : rn {rn}
+    , MemType {Type::ScalarPlusImm}
+    , MetaType {.ScalarImmType {
+        .Imm = imm,
+      }} {}
+  SVEMemOperand(XRegister rn, ZRegister zm, SVEModType mod = SVEModType::MOD_NONE, uint8_t scale = 0)
+    : rn {rn}
+    , MemType {Type::ScalarPlusVector}
+    , MetaType {.ScalarVectorType {
+        .zm = zm,
+        .mod = mod,
+        .scale = scale,
+      }} {}
+  SVEMemOperand(ZRegister zn, uint32_t imm)
+    : rn {Register {zn.Idx()}}
+    , MemType {Type::VectorPlusImm}
+    , MetaType {.VectorImmType {
+        .Imm = imm,
+      }} {}
+
+  [[nodiscard]]
+  bool IsScalarPlusScalar() const {
+    return MemType == Type::ScalarPlusScalar;
+  }
+  [[nodiscard]]
+  bool IsScalarPlusImm() const {
+    return MemType == Type::ScalarPlusImm;
+  }
+  [[nodiscard]]
+  bool IsScalarPlusVector() const {
+    return MemType == Type::ScalarPlusVector;
+  }
+  [[nodiscard]]
+  bool IsVectorPlusImm() const {
+    return MemType == Type::VectorPlusImm;
+  }
+
+  union Data {
+    struct {
+      Register rm;
+    } ScalarScalarType;
+
+    struct {
+      int32_t Imm;
+    } ScalarImmType;
+
+    struct {
+      ZRegister zm;
+      SVEModType mod;
+      uint8_t scale;
+    } ScalarVectorType;
+
+    struct {
+      // rn will be a ZRegister
+      uint32_t Imm;
+    } VectorImmType;
+  };
+
+  Register rn;
+  Type MemType;
+  Data MetaType;
+};
+
+/* This `ExtendedMemOperand` class is used for the helper load-store instructions.
+ * Load-store instructions are quite expressive, so having a helper that handles these differences is worth it.
+ */
+class ExtendedMemOperand final {
+public:
+  ExtendedMemOperand(XRegister rn, XRegister rm = XReg::zr, ExtendedType Option = ExtendedType::LSL_64, uint32_t Shift = 0)
+    : rn {rn}
+    , MetaType {.ExtendedType {
+        .Header = {.MemType = TYPE_EXTENDED},
+        .rm = rm,
+        .Option = Option,
+        .Shift = Shift,
+      }} {}
+  ExtendedMemOperand(XRegister rn, IndexType Index = IndexType::OFFSET, int32_t Imm = 0)
+    : rn {rn}
+    , MetaType {.ImmType {
+        .Header = {.MemType = TYPE_IMM},
+        .Index = Index,
+        .Imm = Imm,
+      }} {}
+
+  Register rn;
+  enum Type {
+    TYPE_EXTENDED,
+    TYPE_IMM,
+  };
+  struct HeaderStruct {
+    Type MemType;
+  };
+  union {
+    HeaderStruct Header;
+    struct {
+      HeaderStruct Header;
+      Register rm;
+      ExtendedType Option;
+      uint32_t Shift;
+    } ExtendedType;
+    struct {
+      HeaderStruct Header;
+      IndexType Index;
+      int32_t Imm;
+    } ImmType;
+  } MetaType;
+};
+
+template<uint32_t op0, uint32_t op1, uint32_t CRn, uint32_t CRm, uint32_t op2>
+constexpr uint32_t GenSystemReg() {
+  return op0 << 19 | op1 << 16 | CRn << 12 | CRm << 8 | op2 << 5;
+};
+
+// This `SystemRegister` enum is used for the mrs/msr instructions.
+enum class SystemRegister : uint32_t {
+  CTR_EL0 = GenSystemReg<0b11, 0b011, 0b0000, 0b0000, 0b001>(),
+  DCZID_EL0 = GenSystemReg<0b11, 0b011, 0b0000, 0b0000, 0b111>(),
+  TPIDR_EL0 = GenSystemReg<0b11, 0b011, 0b1101, 0b0000, 0b010>(),
+  RNDR = GenSystemReg<0b11, 0b011, 0b0010, 0b0100, 0b000>(),
+  RNDRRS = GenSystemReg<0b11, 0b011, 0b0010, 0b0100, 0b001>(),
+  NZCV = GenSystemReg<0b11, 0b011, 0b0100, 0b0010, 0b000>(),
+  FPCR = GenSystemReg<0b11, 0b011, 0b0100, 0b0100, 0b000>(),
+  CNTFRQ_EL0 = GenSystemReg<0b11, 0b011, 0b1110, 0b0000, 0b000>(),
+  CNTVCT_EL0 = GenSystemReg<0b11, 0b011, 0b1110, 0b0000, 0b010>(),
+};
+
+template<uint32_t op1, uint32_t CRm, uint32_t op2>
+constexpr uint32_t GenDCReg() {
+  return op1 << 16 | CRm << 8 | op2 << 5;
+};
+
+// This `DataCacheOperation` enum is used for the dc instruction.
+enum class DataCacheOperation : uint32_t {
+  IVAC = GenDCReg<0b000, 0b0110, 0b001>(),
+  ISW = GenDCReg<0b000, 0b0110, 0b010>(),
+  CSW = GenDCReg<0b000, 0b1010, 0b010>(),
+  CISW = GenDCReg<0b000, 0b1110, 0b010>(),
+  ZVA = GenDCReg<0b011, 0b0100, 0b001>(),
+  CVAC = GenDCReg<0b011, 0b1010, 0b001>(),
+  CVAU = GenDCReg<0b011, 0b1011, 0b001>(),
+  CIVAC = GenDCReg<0b011, 0b1110, 0b001>(),
+
+  // MTE2
+  IGVAC = GenDCReg<0b000, 0b0110, 0b011>(),
+  IGSW = GenDCReg<0b000, 0b0110, 0b100>(),
+  IGDVAC = GenDCReg<0b000, 0b0110, 0b101>(),
+  IGDSW = GenDCReg<0b000, 0b0110, 0b110>(),
+  CGSW = GenDCReg<0b000, 0b1010, 0b100>(),
+  CGDSW = GenDCReg<0b000, 0b1010, 0b110>(),
+  CIGSW = GenDCReg<0b000, 0b1110, 0b100>(),
+  CIGDSW = GenDCReg<0b000, 0b1110, 0b110>(),
+
+  // MTE
+  GVA = GenDCReg<0b011, 0b0100, 0b011>(),
+  GZVA = GenDCReg<0b011, 0b0100, 0b100>(),
+  CGVAC = GenDCReg<0b011, 0b1010, 0b011>(),
+  CGDVAC = GenDCReg<0b011, 0b1010, 0b101>(),
+  CGVAP = GenDCReg<0b011, 0b1100, 0b011>(),
+  CGDVAP = GenDCReg<0b011, 0b1100, 0b101>(),
+  CGVADP = GenDCReg<0b011, 0b1101, 0b011>(),
+  CGDVADP = GenDCReg<0b011, 0b1101, 0b101>(),
+  CIGVAC = GenDCReg<0b011, 0b1110, 0b011>(),
+  CIGDVAC = GenDCReg<0b011, 0b1110, 0b101>(),
+
+  // DPB
+  CVAP = GenDCReg<0b011, 0b1100, 0b001>(),
+
+  // DPB2
+  CVADP = GenDCReg<0b011, 0b1101, 0b001>(),
+};
+
+template<uint32_t CRm, uint32_t op2>
+constexpr uint32_t GenHintBarrierReg() {
+  return CRm << 8 | op2 << 5;
+}
+
+// This `HintRegister` enum is used for the hint instruction.
+enum class HintRegister : uint32_t {
+  NOP = GenHintBarrierReg<0b0000, 0b000>(),
+  YIELD = GenHintBarrierReg<0b0000, 0b001>(),
+  WFE = GenHintBarrierReg<0b0000, 0b010>(),
+  WFI = GenHintBarrierReg<0b0000, 0b011>(),
+  SEV = GenHintBarrierReg<0b0000, 0b100>(),
+  SEVL = GenHintBarrierReg<0b0000, 0b101>(),
+  DGH = GenHintBarrierReg<0b0000, 0b110>(),
+  CSDB = GenHintBarrierReg<0b0010, 0b100>(),
+};
+
+// This `BarrierRegister` enum is used for the various barrier instructions.
+enum class BarrierRegister : uint32_t {
+  CLREX = GenHintBarrierReg<0b0000, 0b010>(),
+  TCOMMIT = GenHintBarrierReg<0b0000, 0b011>(),
+  DSB = GenHintBarrierReg<0b0000, 0b100>(),
+  DMB = GenHintBarrierReg<0b0000, 0b101>(),
+  ISB = GenHintBarrierReg<0b0000, 0b110>(),
+  SB = GenHintBarrierReg<0b0000, 0b111>(),
+};
+
+// This `BarrierScope` enum is used for the dsb/dmb instructions.
+enum class BarrierScope : uint32_t {
+  // Outer shareable
+  OSHLD = 0b0001,
+  OSHST = 0b0010,
+  OSH = 0b0011,
+  // Non shareable
+  NSHLD = 0b0101,
+  NSHST = 0b0110,
+  NSH = 0b0111,
+  // Inner shareable
+  ISHLD = 0b1001,
+  ISHST = 0b1010,
+  ISH = 0b1011,
+  // Full System visibility
+  LD = 0b1101,
+  ST = 0b1110,
+  SY = 0b1111,
+};
+
+// This `Prefetch` enum is used for prefetch instructions.
+enum class Prefetch : uint32_t {
+  // Prefetch for load
+  PLDL1KEEP = 0b00000,
+  PLDL1STRM = 0b00001,
+  PLDL2KEEP = 0b00010,
+  PLDL2STRM = 0b00011,
+  PLDL3KEEP = 0b00100,
+  PLDL3STRM = 0b00101,
+
+  // Preload instructions
+  PLIL1KEEP = 0b01000,
+  PLIL1STRM = 0b01001,
+  PLIL2KEEP = 0b01010,
+  PLIL2STRM = 0b01011,
+  PLIL3KEEP = 0b01100,
+  PLIL3STRM = 0b01101,
+
+  // Preload for store
+  PSTL1KEEP = 0b10000,
+  PSTL1STRM = 0b10001,
+  PSTL2KEEP = 0b10010,
+  PSTL2STRM = 0b10011,
+  PSTL3KEEP = 0b10100,
+  PSTL3STRM = 0b10101,
+};
+
+// This `PredicatePattern` enun is used for some SVE instructions.
+enum class PredicatePattern : uint32_t {
+  SVE_POW2 = 0b00000,
+  SVE_VL1 = 0b00001,
+  SVE_VL2 = 0b00010,
+  SVE_VL3 = 0b00011,
+  SVE_VL4 = 0b00100,
+  SVE_VL5 = 0b00101,
+  SVE_VL6 = 0b00110,
+  SVE_VL7 = 0b00111,
+  SVE_VL8 = 0b01000,
+  SVE_VL16 = 0b01001,
+  SVE_VL32 = 0b01010,
+  SVE_VL64 = 0b01011,
+  SVE_VL128 = 0b01100,
+  SVE_VL256 = 0b01101,
+  SVE_MUL4 = 0b11101,
+  SVE_MUL3 = 0b11110,
+  SVE_ALL = 0b11111,
+};
+
+// Used with SVE FP immediate arithmetic instructions
+enum class SVEFAddSubImm : uint32_t {
+  _0_5,
+  _1_0,
+};
+enum class SVEFMulImm : uint32_t {
+  _0_5,
+  _2_0,
+};
+enum class SVEFMaxMinImm : uint32_t {
+  _0_0,
+  _1_0,
+};
+
+/* This `BackwardLabel` struct used for retaining a location for PC-Relative instructions.
+ * This is specifically a label for a target that is logically `below` an instruction that uses it.
+ * Which means that a branch would jump backwards.
+ */
+struct BackwardLabel {
+  uint8_t* Location {};
+};
+
+/* This `SingleUseForwardLabel` struct used for retaining a location for PC-Relative instructions.
+ * This is specifically a label for a target that is logically `above` an instruction that uses it.
+ * Which means that a branch would jump forwards.
+ *
+ * The `ForwardLabel` struct can be bound to multiple instructions, so it needs a vector for each bind instruction type.
+ */
+struct SingleUseForwardLabel {
+  enum class InstType {
+    UNKNOWN,
+    ADR,
+    ADRP,
+    B,
+    BC,
+    TEST_BRANCH,
+    RELATIVE_LOAD,
+    LONG_ADDRESS_GEN,
+  };
+  uint8_t* Location {};
+  InstType Type = InstType::UNKNOWN;
+};
+
+struct ForwardLabel {
+  fextl::vector<SingleUseForwardLabel> Insts {};
+};
+
+/* This `BiDirectionalLabel` struct used for retaining a location for PC-Relative instructions.
+ * This is specifically a label for a target that is in either direction of an instruction that uses it.
+ * Which means a branch could jump backwards or forwards depending on situation.
+ */
+struct BiDirectionalLabel {
+  BackwardLabel Backward;
+  ForwardLabel Forward;
+};
+
+static inline void AddLocationToLabel(SingleUseForwardLabel* Label, SingleUseForwardLabel&& Location) {
+  LOGMAN_THROW_A_FMT(Label->Type == SingleUseForwardLabel::InstType::UNKNOWN, "Trying to bind a SingleUseForwardLabel to multiple "
+                                                                              "locations. Use ForwardLabel instead.");
+  *Label = std::move(Location);
+}
+
+static inline void AddLocationToLabel(ForwardLabel* Label, SingleUseForwardLabel&& Location) {
+  Label->Insts.emplace_back(std::move(Location));
+}
+
+// Some FCMA ASIMD instructions support a rotation argument.
+enum class Rotation : uint32_t {
+  ROTATE_0 = 0b00,
+  ROTATE_90 = 0b01,
+  ROTATE_180 = 0b10,
+  ROTATE_270 = 0b11,
+};
+
+// Concept for contraining some instructions to accept only an XRegister or WRegister.
+// Particularly for operations that differ encodings depending on which one is used.
+template<typename T>
+concept IsXOrWRegister = std::is_same_v<T, XRegister> || std::is_same_v<T, WRegister>;
+
+// Whether or not a given set of vector registers are sequential
+// in increasing order as far as the register file is concerned (modulo its size)
+//
+// For example, a set of registers like:
+//
+// v1,  v2, v3 and
+// v31, v0, v1
+//
+// would both be considered sequential sequences, and some instructions in particular
+// limit register lists to these kind of sequences.
+//
+template<typename T, typename... Args>
+constexpr bool AreVectorsSequential(T first, const Args&... args) {
+  // Ensure we always have a pair of registers to compare against.
+  static_assert(sizeof...(args) >= 1, "Number of arguments must be greater than 1");
+
+  const auto fn = [](auto& lhs, const auto& rhs) {
+    const auto result = ((lhs.Idx() + 1) % 32) == rhs.Idx();
+    lhs = rhs;
+    return result;
+  };
+
+  return (fn(first, args) && ...);
+}
+
+// Returns if the immediate can fit in to add/sub immediate instruction encodings.
+constexpr bool IsImmAddSub(uint64_t imm) {
+  constexpr uint64_t U12Mask = 0xFFF;
+  auto FitsWithin12Bits = [](uint64_t imm) {
+    return (imm & ~U12Mask) == 0;
+  };
+  // Can fit in to the instruction encoding:
+  // - if only bits [11:0] are set.
+  // - if only bits [23:12] are set.
+  return FitsWithin12Bits(imm) || (FitsWithin12Bits(imm >> 12) && (imm & U12Mask) == 0);
+}
+
+// This is an emitter that is designed around the smallest code bloat as possible.
+// Eschewing most developer convenience in order to keep code as small as possible.
+
+// Choices:
+// - Size of ops passed as an argument rather than template to let the compiler use csel instead of branching.
+// - Registers are unsized so they can be passed in a GPR and not need conversion operations
+class Emitter : public ARMEmitter::Buffer {
+public:
+  Emitter() = default;
+
+  Emitter(uint8_t* Base, uint64_t BaseSize)
+    : Buffer(Base, BaseSize) {}
+
+  // Bind a backward label to an address.
+  // Address that is bound is the current emitter location.
+  void Bind(BackwardLabel* Label) {
+    LOGMAN_THROW_AA_FMT(Label->Location == nullptr, "Trying to bind a label twice");
+    Label->Location = GetCursorAddress<uint8_t*>();
+  }
+
+  void Bind(const SingleUseForwardLabel* Label) {
+    uint8_t* CurrentAddress = GetCursorAddress<uint8_t*>();
+    // Patch up the instructions
+    switch (Label->Type) {
+    case SingleUseForwardLabel::InstType::ADR: {
+      uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+      int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+      LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large");
+      uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
+      uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
+      uint32_t Inst = *Instruction & ~InstMask;
+      Inst |= (Offset & 0b11) << 29;
+      Inst |= (Offset >> 2) << 5;
+      *Instruction = Inst;
+      break;
+    }
+    case SingleUseForwardLabel::InstType::ADRP: {
+      uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+      int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+      LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large");
+      Imm >>= 12;
+      uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
+      uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
+      uint32_t Inst = *Instruction & ~InstMask;
+      Inst |= (Offset & 0b11) << 29;
+      Inst |= (Offset >> 2) << 5;
+      *Instruction = Inst;
+      break;
+    }
+
+    case SingleUseForwardLabel::InstType::B: {
+      uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+      int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+      LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+      Imm >>= 2;
+      uint32_t InstMask = 0x3FF'FFFF;
+      uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+      uint32_t Inst = *Instruction & ~InstMask;
+      Inst |= Offset;
+      *Instruction = Inst;
+
+      break;
+    }
+
+    case SingleUseForwardLabel::InstType::TEST_BRANCH: {
+      uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+      int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+      LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+      Imm >>= 2;
+      uint32_t InstMask = 0x3FFF;
+      uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+      uint32_t Inst = *Instruction & ~(InstMask << 5);
+      Inst |= Offset << 5;
+      *Instruction = Inst;
+
+      break;
+    }
+    case SingleUseForwardLabel::InstType::BC:
+    case SingleUseForwardLabel::InstType::RELATIVE_LOAD: {
+      uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+      int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+      Imm >>= 2;
+      uint32_t InstMask = 0x7'FFFF;
+      uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+      uint32_t Inst = *Instruction & ~(InstMask << 5);
+      Inst |= Offset << 5;
+      *Instruction = Inst;
+      break;
+    }
+    case SingleUseForwardLabel::InstType::LONG_ADDRESS_GEN: {
+      uint32_t* Instructions = reinterpret_cast<uint32_t*>(Label->Location);
+      int64_t ImmInstOne = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[0]);
+      int64_t ImmInstTwo = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[1]);
+      auto OriginalOffset = GetCursorOffset();
+
+      auto InstOffset = GetCursorOffsetFromAddress(Instructions);
+      SetCursorOffset(InstOffset);
+
+      // We encoded the destination register in to the first instruction space.
+      // Read it back.
+      ARMEmitter::Register DestReg(Instructions[0]);
+
+      if (IsADRRange(ImmInstTwo)) {
+        // If within ADR range from the second instruction, then we can emit NOP+ADR
+        nop();
+        adr(DestReg, static_cast<uint32_t>(ImmInstTwo) & 0x7FFF);
+      } else if (IsADRPRange(ImmInstOne)) {
+
+        // If within ADRP range from the first instruction, then we are /definitely/ in range for the second instruction.
+        // First check if we are in non-offset range for second instruction.
+        if (IsADRPAligned(reinterpret_cast<uint64_t>(CurrentAddress))) {
+          // We can emit nop + adrp
+          nop();
+          adrp(DestReg, static_cast<uint32_t>(ImmInstTwo >> 12) & 0x7FFF);
+        } else {
+          // Not aligned, need adrp + add
+          adrp(DestReg, static_cast<uint32_t>(ImmInstOne >> 12) & 0x7FFF);
+          add(ARMEmitter::Size::i64Bit, DestReg, DestReg, ImmInstOne & 0xFFF);
+        }
+      } else {
+        LOGMAN_MSG_A_FMT("Unscaled offset is too large");
+        FEX_UNREACHABLE;
+      }
+
+      SetCursorOffset(OriginalOffset);
+      break;
+    }
+    default: LOGMAN_MSG_A_FMT("Unexpected inst type in label fixup");
+    }
+  }
+
+  // Bind a forward label to a location.
+  // This walks all the instructions in the label's vector.
+  // Then backpatching all instructions that have used the label.
+  template<bool WarnAboutEmpty = false>
+  void Bind(ForwardLabel* Label) {
+    if constexpr (WarnAboutEmpty) {
+      LOGMAN_THROW_A_FMT(Label->Insts.empty() == false, "Binding forward label that didn't have any instructions using it");
+    }
+    for (auto& Inst : Label->Insts) {
+      Bind(&Inst);
+    }
+  }
+
+  // Bind a bidirectional location to a location.
+  // Binds both forwards and backwards depending on how the label was used.
+  void Bind(BiDirectionalLabel* Label) {
+    if (!Label->Backward.Location) {
+      Bind(&Label->Backward);
+    }
+    Bind<false>(&Label->Forward);
+  }
+
+#include <CodeEmitter/VixlUtils.inl>
+
+public:
+  // TODO: Implement SME when it matters.
+#include <CodeEmitter/ALUOps.inl>
+#include <CodeEmitter/BranchOps.inl>
+#include <CodeEmitter/LoadstoreOps.inl>
+#include <CodeEmitter/SystemOps.inl>
+#include <CodeEmitter/ScalarOps.inl>
+#include <CodeEmitter/ASIMDOps.inl>
+#include <CodeEmitter/SVEOps.inl>
+
+private:
+  template<typename T>
+  uint32_t Encode_ra(T Reg) const {
+    return Reg.Idx() << 10;
+  }
+  uint32_t Encode_ra(uint32_t Reg) const {
+    return Reg << 10;
+  }
+  template<typename T>
+  uint32_t Encode_rt2(T Reg) const {
+    return Reg.Idx() << 10;
+  }
+  template<>
+  uint32_t Encode_rt2(uint32_t Reg) const {
+    return Reg << 10;
+  }
+  template<typename T>
+  uint32_t Encode_rm(T Reg) const {
+    return Reg.Idx() << 16;
+  }
+  uint32_t Encode_rm(uint32_t Reg) const {
+    return Reg << 16;
+  }
+  template<typename T>
+  uint32_t Encode_rs(T Reg) const {
+    return Reg.Idx() << 16;
+  }
+  uint32_t Encode_rs(uint32_t Reg) const {
+    return Reg << 16;
+  }
+  template<typename T>
+  uint32_t Encode_rn(T Reg) const {
+    return Reg.Idx() << 5;
+  }
+  uint32_t Encode_rn(uint32_t Reg) const {
+    return Reg << 5;
+  }
+  template<typename T>
+  uint32_t Encode_rd(T Reg) const {
+    return Reg.Idx();
+  }
+  uint32_t Encode_rd(uint32_t Reg) const {
+    return Reg;
+  }
+  template<typename T>
+  uint32_t Encode_rt(T Reg) const {
+    return Reg.Idx();
+  }
+  template<>
+  uint32_t Encode_rt(Prefetch Reg) const {
+    return FEXCore::ToUnderlying(Reg);
+  }
+  uint32_t Encode_rt(uint32_t Reg) const {
+    return Reg;
+  }
+  template<typename T>
+  uint32_t Encode_pd(T Reg) const {
+    return FEXCore::ToUnderlying(Reg);
+  }
+};
+} // namespace ARMEmitter
@@ -1506,13 +1506,14 @@ public:
  }

  // SVE broadcast floating-point immediate (unpredicated)
-  void fdup(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, float Value) {
-    LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit ||
-                        size == FEXCore::ARMEmitter::SubRegSize::i32Bit ||
-                        size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size");
+  void fdup(ARMEmitter::SubRegSize size, ARMEmitter::ZRegister zd, float Value) {
+    LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit ||
+                        size == ARMEmitter::SubRegSize::i32Bit ||
+                        size == ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size");
    uint32_t Imm{};
    if (size == SubRegSize::i16Bit) {
-      Imm = FP16ToImm8(vixl::Float16(Value));
+      LOGMAN_MSG_A_FMT("Unsupported");
+      FEX_UNREACHABLE;
    } else if (size == SubRegSize::i32Bit) {
      Imm = FP32ToImm8(Value);
    } else if (size == SubRegSize::i64Bit) {
@@ -1521,7 +1522,7 @@ public:

    SVEBroadcastFloatImmUnpredicated(0b00, 0, Imm, size, zd);
  }
-  void fmov(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, float Value) {
+  void fmov(ARMEmitter::SubRegSize size, ARMEmitter::ZRegister zd, float Value) {
    fdup(size, zd, Value);
  }

@@ -2568,7 +2569,19 @@ public:
  }

  // SVE contiguous non-temporal load (scalar plus immediate)
-  // XXX:
+  void ldnt1b(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalLoad(0b00, zt, pg, rn, Imm);
+  }
+  void ldnt1h(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalLoad(0b01, zt, pg, rn, Imm);
+  }
+  void ldnt1w(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalLoad(0b10, zt, pg, rn, Imm);
+  }
+  void ldnt1d(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalLoad(0b11, zt, pg, rn, Imm);
+  }
+
  // SVE contiguous non-temporal load (scalar plus scalar)
  // XXX:
  // SVE load multiple structures (scalar plus immediate)
@@ -3320,7 +3333,18 @@ public:

  // SVE Memory - Contiguous Store with Immediate Offset
  // SVE contiguous non-temporal store (scalar plus immediate)
-  // XXX:
+  void stnt1b(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalStore(0b00, zt, pg, rn, Imm);
+  }
+  void stnt1h(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalStore(0b01, zt, pg, rn, Imm);
+  }
+  void stnt1w(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalStore(0b10, zt, pg, rn, Imm);
+  }
+  void stnt1d(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalStore(0b11, zt, pg, rn, Imm);
+  }

  // SVE store multiple structures (scalar plus immediate)
  void st2b(ZRegister zt1, ZRegister zt2, PRegister pg, Register rn, int32_t Imm = 0) {
@@ -3513,7 +3537,8 @@ private:
                        size == SubRegSize::i64Bit, "Unsupported fcpy/fmov size");
    uint32_t imm{};
    if (size == SubRegSize::i16Bit) {
-      imm = FP16ToImm8(vixl::Float16(value));
+      LOGMAN_MSG_A_FMT("Unsupported");
+      FEX_UNREACHABLE;
    } else if (size == SubRegSize::i32Bit) {
      imm = FP32ToImm8(value);
    } else if (size == SubRegSize::i64Bit) {
@@ -3717,7 +3742,7 @@ private:

  // SVE bitwise logical operations (predicated)
  void SVEBitwiseLogicalPredicated(uint32_t opc, SubRegSize size, PRegister pg, ZRegister zdn, ZRegister zm, ZRegister zd) {
-    LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i128Bit, "Can't use 128-bit size");
+    LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i128Bit, "Can't use 128-bit size");
    LOGMAN_THROW_A_FMT(zd == zdn, "zd needs to equal zdn");
    LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");

@@ -4479,6 +4504,38 @@ private:
    dc32(Instr);
  }

+  // SVE contiguous non-temporal load (scalar plus immediate)
+  void SVEContiguousNontemporalLoad(uint32_t msz, ZRegister zt, PRegister pg, Register rn, int32_t imm) {
+    LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");
+    LOGMAN_THROW_AA_FMT(imm >= -8 && imm <= 7,
+                        "Invalid loadstore offset ({}). Must be between [-8, 7]", imm);
+
+    const auto imm4 = static_cast<uint32_t>(imm) & 0xF;
+    uint32_t Instr = 0b1010'0100'0000'0000'1110'0000'0000'0000;
+    Instr |= msz << 23;
+    Instr |= imm4 << 16;
+    Instr |= pg.Idx() << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= zt.Idx();
+    dc32(Instr);
+  }
+
+  // SVE contiguous non-temporal store (scalar plus immediate)
+  void SVEContiguousNontemporalStore(uint32_t msz, ZRegister zt, PRegister pg, Register rn, int32_t imm) {
+    LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");
+    LOGMAN_THROW_AA_FMT(imm >= -8 && imm <= 7,
+                        "Invalid loadstore offset ({}). Must be between [-8, 7]", imm);
+
+    const auto imm4 = static_cast<uint32_t>(imm) & 0xF;
+    uint32_t Instr = 0b1110'0100'0001'0000'1110'0000'0000'0000;
+    Instr |= msz << 23;
+    Instr |= imm4 << 16;
+    Instr |= pg.Idx() << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= zt.Idx();
+    dc32(Instr);
+  }
+
  void SVEContiguousLoadImm(bool is_store, uint32_t dtype, int32_t imm, PRegister pg, Register rn, ZRegister zt) {
    LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");
    LOGMAN_THROW_AA_FMT(imm >= -8 && imm <= 7,
@@ -4743,7 +4800,7 @@ private:
    dc32(Instr);
  }

-  void SVEPermuteVector(uint32_t op0, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::ZRegister zm, uint32_t Imm) {
+  void SVEPermuteVector(uint32_t op0, ARMEmitter::ZRegister zd, ARMEmitter::ZRegister zm, uint32_t Imm) {
    constexpr uint32_t Op = 0b0000'0101'0010'0000'000 << 13;
    uint32_t Instr = Op;

@@ -5228,15 +5285,14 @@ private:

  // Alias that returns the equivalently sized unsigned type for a floating-point type T.
  template <typename T>
-  requires(std::is_same_v<T, float> || std::is_same_v<T, double> || std::is_same_v<T, vixl::Float16>)
-  using FloatToEquivalentUInt = std::conditional_t<std::is_same_v<T, vixl::Float16>, uint16_t,
-                                                   std::conditional_t<std::is_same_v<T, float>, uint32_t, uint64_t>>;
+  requires(std::is_same_v<T, float> || std::is_same_v<T, double>)
+  using FloatToEquivalentUInt = std::conditional_t<std::is_same_v<T, float>, uint32_t, uint64_t>;

  // Determines if a floating-point value is capable of being converted
  // into an 8-bit immediate. See pseudocode definition of VFPExpandImm
  // in ARM A-profile reference manual for a general overview of how this was derived.
  template <typename T>
-  requires(std::is_same_v<T, float> || std::is_same_v<T, double> || std::is_same_v<T, vixl::Float16>)
+  requires(std::is_same_v<T, float> || std::is_same_v<T, double>)
  [[nodiscard, maybe_unused]] static bool IsValidFPValueForImm8(T value) {
    const uint64_t bits = FEXCore::BitCast<FloatToEquivalentUInt<T>>(value);
    const uint64_t datasize_idx = FEXCore::ilog2(sizeof(T)) - 1;
@@ -5277,18 +5333,6 @@ private:
    return true;
  }

-  static uint32_t FP16ToImm8(vixl::Float16 value) {
-    LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value),
-                       "Value cannot be encoded into an 8-bit immediate");
-
-    const uint32_t bits = vixl::Float16ToRawbits(value);
-    const uint32_t sign = (bits & 0x8000) >> 8;
-    const uint32_t expb2 = (bits & 0x2000) >> 7;
-    const uint32_t b5_to_0 = (bits >> 6) & 0x3F;
-
-    return sign | expb2 | b5_to_0;
-  }
-
  static uint32_t FP32ToImm8(float value) {
    LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value),
                       "Value ({}) cannot be encoded into an 8-bit immediate", value);
@@ -33,7 +33,7 @@ public:
    ASIMDScalarCopy(Op, 1, imm5, 0b0000, rd, rn);
  }

-  void mov(FEXCore::ARMEmitter::ScalarRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, uint32_t Index) {
+  void mov(ARMEmitter::ScalarRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, uint32_t Index) {
    dup(size, rd, rn, Index);
  }

@@ -1052,21 +1052,21 @@ public:
  }

 // Floating-point immediate
-  void fmov(FEXCore::ARMEmitter::ScalarRegSize size, FEXCore::ARMEmitter::VRegister rd, float Value) {
+  void fmov(ARMEmitter::ScalarRegSize size, ARMEmitter::VRegister rd, float Value) {
    uint32_t M = 0;
    uint32_t S = 0;
    uint32_t ptype;
    uint32_t imm8;
    uint32_t imm5 = 0b0'0000;
-    if (size == FEXCore::ARMEmitter::ScalarRegSize::i16Bit) {
-      ptype = 0b11;
-      imm8 = FP16ToImm8(vixl::Float16(Value));
+    if (size == ARMEmitter::ScalarRegSize::i16Bit) {
+      LOGMAN_MSG_A_FMT("Unsupported");
+      FEX_UNREACHABLE;
    }
-    else if (size == FEXCore::ARMEmitter::ScalarRegSize::i32Bit) {
+    else if (size == ARMEmitter::ScalarRegSize::i32Bit) {
      ptype = 0b00;
      imm8 = FP32ToImm8(Value);
    }
-    else if (size == FEXCore::ARMEmitter::ScalarRegSize::i64Bit) {
+    else if (size == ARMEmitter::ScalarRegSize::i64Bit) {
      ptype = 0b01;
      imm8 = FP64ToImm8(Value);
    }
@@ -1077,7 +1077,7 @@ public:
    FloatScalarImmediate(M, S, ptype, imm8, imm5, rd);
  }

-  void FloatScalarImmediate(uint32_t M, uint32_t S, uint32_t ptype, uint32_t imm8, uint32_t imm5, FEXCore::ARMEmitter::VRegister rd) {
+  void FloatScalarImmediate(uint32_t M, uint32_t S, uint32_t ptype, uint32_t imm8, uint32_t imm5, ARMEmitter::VRegister rd) {
    constexpr uint32_t Op = 0b0001'1110'0010'0000'0001'00 << 10;
    uint32_t Instr = Op;

@@ -1286,7 +1286,7 @@ public:

 private:
 // Advanced SIMD scalar copy
-  void ASIMDScalarCopy(uint32_t Op, uint32_t Q, uint32_t imm5, uint32_t imm4, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) {
+  void ASIMDScalarCopy(uint32_t Op, uint32_t Q, uint32_t imm5, uint32_t imm4, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) {
    uint32_t Instr = Op;

    Instr |= Q << 30;
@@ -11,7 +11,7 @@ public:
    // TODO: AT
    // TODO: CFP
    // TODO: CPP
-    void dc(FEXCore::ARMEmitter::DataCacheOperation DCOp, FEXCore::ARMEmitter::Register rt) {
+    void dc(ARMEmitter::DataCacheOperation DCOp, ARMEmitter::Register rt) {
      constexpr uint32_t Op = 0b1101'0101'0000'1000'0111 << 12;
      SystemInstruction(Op, 0, FEXCore::ToUnderlying(DCOp), rt);
    }
@@ -48,67 +48,67 @@ public:
      ExceptionGeneration(0b101, 0b000, 0b11, Imm);
    }
    // System instructions with register argument
-    void wfet(FEXCore::ARMEmitter::Register rt) {
+    void wfet(ARMEmitter::Register rt) {
      SystemInstructionWithReg(0b0000, 0b000, rt);
    }
-    void wfit(FEXCore::ARMEmitter::Register rt) {
+    void wfit(ARMEmitter::Register rt) {
      SystemInstructionWithReg(0b0000, 0b001, rt);
    }

    // Hints
    void nop() {
-      Hint(FEXCore::ARMEmitter::HintRegister::NOP);
+      Hint(ARMEmitter::HintRegister::NOP);
    }
    void yield() {
-      Hint(FEXCore::ARMEmitter::HintRegister::YIELD);
+      Hint(ARMEmitter::HintRegister::YIELD);
    }
    void wfe() {
-      Hint(FEXCore::ARMEmitter::HintRegister::WFE);
+      Hint(ARMEmitter::HintRegister::WFE);
    }
    void wfi() {
-      Hint(FEXCore::ARMEmitter::HintRegister::WFI);
+      Hint(ARMEmitter::HintRegister::WFI);
    }
    void sev() {
-      Hint(FEXCore::ARMEmitter::HintRegister::SEV);
+      Hint(ARMEmitter::HintRegister::SEV);
    }
    void sevl() {
-      Hint(FEXCore::ARMEmitter::HintRegister::SEVL);
+      Hint(ARMEmitter::HintRegister::SEVL);
    }
    void dgh() {
-      Hint(FEXCore::ARMEmitter::HintRegister::DGH);
+      Hint(ARMEmitter::HintRegister::DGH);
    }
    void csdb() {
-      Hint(FEXCore::ARMEmitter::HintRegister::CSDB);
+      Hint(ARMEmitter::HintRegister::CSDB);
    }

    // Barriers
    void clrex(uint32_t imm = 15) {
      LOGMAN_THROW_AA_FMT(imm < 16, "Immediate out of range");
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::CLREX, imm);
+      Barrier(ARMEmitter::BarrierRegister::CLREX, imm);
    }
-    void dsb(FEXCore::ARMEmitter::BarrierScope Scope) {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::DSB, FEXCore::ToUnderlying(Scope));
+    void dsb(ARMEmitter::BarrierScope Scope) {
+      Barrier(ARMEmitter::BarrierRegister::DSB, FEXCore::ToUnderlying(Scope));
    }
-    void dmb(FEXCore::ARMEmitter::BarrierScope Scope) {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::DMB, FEXCore::ToUnderlying(Scope));
+    void dmb(ARMEmitter::BarrierScope Scope) {
+      Barrier(ARMEmitter::BarrierRegister::DMB, FEXCore::ToUnderlying(Scope));
    }
    void isb() {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::ISB, FEXCore::ToUnderlying(FEXCore::ARMEmitter::BarrierScope::SY));
+      Barrier(ARMEmitter::BarrierRegister::ISB, FEXCore::ToUnderlying(ARMEmitter::BarrierScope::SY));
    }
    void sb() {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::SB, 0);
+      Barrier(ARMEmitter::BarrierRegister::SB, 0);
    }
    void tcommit() {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::TCOMMIT, 0);
+      Barrier(ARMEmitter::BarrierRegister::TCOMMIT, 0);
    }

    // System register move
-    void msr(FEXCore::ARMEmitter::SystemRegister reg, FEXCore::ARMEmitter::Register rt) {
+    void msr(ARMEmitter::SystemRegister reg, ARMEmitter::Register rt) {
      constexpr uint32_t Op = 0b1101'0101'0001 << 20;
      SystemRegisterMove(Op, rt, reg);
    }

-    void mrs(FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SystemRegister reg) {
+    void mrs(ARMEmitter::Register rd, ARMEmitter::SystemRegister reg) {
      constexpr uint32_t Op = 0b1101'0101'0011 << 20;
      SystemRegisterMove(Op, rd, reg);
    }
@@ -130,7 +130,7 @@ private:
    }

    // System instructions with register argument
-    void SystemInstructionWithReg(uint32_t CRm, uint32_t op2, FEXCore::ARMEmitter::Register rt) {
+    void SystemInstructionWithReg(uint32_t CRm, uint32_t op2, ARMEmitter::Register rt) {
      uint32_t Instr = 0b1101'0101'0000'0011'0001 << 12;

      Instr |= CRm << 8;
@@ -140,13 +140,13 @@ private:
    }

    // Hints
-    void Hint(FEXCore::ARMEmitter::HintRegister Reg) {
+    void Hint(ARMEmitter::HintRegister Reg) {
      uint32_t Instr = 0b1101'0101'0000'0011'0010'0000'0001'1111U;
      Instr |= FEXCore::ToUnderlying(Reg);
      dc32(Instr);
    }
    // Barriers
-    void Barrier(FEXCore::ARMEmitter::BarrierRegister Reg, uint32_t CRm) {
+    void Barrier(ARMEmitter::BarrierRegister Reg, uint32_t CRm) {
      uint32_t Instr = 0b1101'0101'0000'0011'0011'0000'0001'1111U;
      Instr |= CRm << 8;
      Instr |= FEXCore::ToUnderlying(Reg);
@@ -154,7 +154,7 @@ private:
    }

    // System Instruction
-    void SystemInstruction(uint32_t Op, uint32_t L, uint32_t SubOp, FEXCore::ARMEmitter::Register rt) {
+    void SystemInstruction(uint32_t Op, uint32_t L, uint32_t SubOp, ARMEmitter::Register rt) {
      uint32_t Instr = Op;

      Instr |= L << 21;
@@ -165,7 +165,7 @@ private:
    }

    // System register move
-    void SystemRegisterMove(uint32_t Op, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::SystemRegister reg) {
+    void SystemRegisterMove(uint32_t Op, ARMEmitter::Register rt, ARMEmitter::SystemRegister reg) {
      uint32_t Instr = Op;

      Instr |= FEXCore::ToUnderlying(reg);
@@ -0,0 +1,351 @@
+// Collection of utilities from vixl.
+// Following is the vixl license.
+// Copyright 2015, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+// Test if a given value can be encoded in the immediate field of a logical
+// instruction.
+// If it can be encoded, the function returns true, and values pointed to by n,
+// imm_s and imm_r are updated with immediates encoded in the format required
+// by the corresponding fields in the logical instruction.
+// If it can not be encoded, the function returns false, and the values pointed
+// to by n, imm_s and imm_r are undefined.
+static bool IsImmLogical(uint64_t value,
+                             unsigned width,
+                             unsigned* n = nullptr,
+                             unsigned* imm_s = nullptr,
+                             unsigned* imm_r = nullptr) {
+  [[maybe_unused]] constexpr auto kBRegSize = 8;
+  [[maybe_unused]] constexpr auto kHRegSize = 16;
+  [[maybe_unused]] constexpr auto kSRegSize = 32;
+  [[maybe_unused]] constexpr auto kDRegSize = 64;
+
+  constexpr auto kWRegSize = 32;
+  constexpr auto kXRegSize = 64;
+
+  LOGMAN_THROW_A_FMT((width == kBRegSize) || (width == kHRegSize) ||
+              (width == kSRegSize) || (width == kDRegSize), "Unexpected imm size");
+
+  bool negate = false;
+
+  // Logical immediates are encoded using parameters n, imm_s and imm_r using
+  // the following table:
+  //
+  //    N   imms    immr    size        S             R
+  //    1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
+  //    0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
+  //    0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
+  //    0  110sss  xxxrrr     8    UInt(sss)     UInt(rrr)
+  //    0  1110ss  xxxxrr     4    UInt(ss)      UInt(rr)
+  //    0  11110s  xxxxxr     2    UInt(s)       UInt(r)
+  // (s bits must not be all set)
+  //
+  // A pattern is constructed of size bits, where the least significant S+1 bits
+  // are set. The pattern is rotated right by R, and repeated across a 32 or
+  // 64-bit value, depending on destination register width.
+  //
+  // Put another way: the basic format of a logical immediate is a single
+  // contiguous stretch of 1 bits, repeated across the whole word at intervals
+  // given by a power of 2. To identify them quickly, we first locate the
+  // lowest stretch of 1 bits, then the next 1 bit above that; that combination
+  // is different for every logical immediate, so it gives us all the
+  // information we need to identify the only logical immediate that our input
+  // could be, and then we simply check if that's the value we actually have.
+  //
+  // (The rotation parameter does give the possibility of the stretch of 1 bits
+  // going 'round the end' of the word. To deal with that, we observe that in
+  // any situation where that happens the bitwise NOT of the value is also a
+  // valid logical immediate. So we simply invert the input whenever its low bit
+  // is set, and then we know that the rotated case can't arise.)
+
+  if (value & 1) {
+    // If the low bit is 1, negate the value, and set a flag to remember that we
+    // did (so that we can adjust the return values appropriately).
+    negate = true;
+    value = ~value;
+  }
+
+  if (width <= kWRegSize) {
+    // To handle 8/16/32-bit logical immediates, the very easiest thing is to repeat
+    // the input value to fill a 64-bit word. The correct encoding of that as a
+    // logical immediate will also be the correct encoding of the value.
+
+    // Avoid making the assumption that the most-significant 56/48/32 bits are zero by
+    // shifting the value left and duplicating it.
+    for (unsigned bits = width; bits <= kWRegSize; bits *= 2) {
+      value <<= bits;
+      uint64_t mask = (UINT64_C(1) << bits) - 1;
+      value |= ((value >> bits) & mask);
+    }
+  }
+
+  // The basic analysis idea: imagine our input word looks like this.
+  //
+  //    0011111000111110001111100011111000111110001111100011111000111110
+  //                                                          c  b    a
+  //                                                          |<--d-->|
+  //
+  // We find the lowest set bit (as an actual power-of-2 value, not its index)
+  // and call it a. Then we add a to our original number, which wipes out the
+  // bottommost stretch of set bits and replaces it with a 1 carried into the
+  // next zero bit. Then we look for the new lowest set bit, which is in
+  // position b, and subtract it, so now our number is just like the original
+  // but with the lowest stretch of set bits completely gone. Now we find the
+  // lowest set bit again, which is position c in the diagram above. Then we'll
+  // measure the distance d between bit positions a and c (using CLZ), and that
+  // tells us that the only valid logical immediate that could possibly be equal
+  // to this number is the one in which a stretch of bits running from a to just
+  // below b is replicated every d bits.
+  uint64_t a = LowestSetBit(value);
+  uint64_t value_plus_a = value + a;
+  uint64_t b = LowestSetBit(value_plus_a);
+  uint64_t value_plus_a_minus_b = value_plus_a - b;
+  uint64_t c = LowestSetBit(value_plus_a_minus_b);
+
+  int d, clz_a, out_n;
+  uint64_t mask;
+
+  if (c != 0) {
+    // The general case, in which there is more than one stretch of set bits.
+    // Compute the repeat distance d, and set up a bitmask covering the basic
+    // unit of repetition (i.e. a word with the bottom d bits set). Also, in all
+    // of these cases the N bit of the output will be zero.
+    clz_a = CountLeadingZeros(a, kXRegSize);
+    int clz_c = CountLeadingZeros(c, kXRegSize);
+    d = clz_a - clz_c;
+    mask = ((UINT64_C(1) << d) - 1);
+    out_n = 0;
+  } else {
+    // Handle degenerate cases.
+    //
+    // If any of those 'find lowest set bit' operations didn't find a set bit at
+    // all, then the word will have been zero thereafter, so in particular the
+    // last lowest_set_bit operation will have returned zero. So we can test for
+    // all the special case conditions in one go by seeing if c is zero.
+    if (a == 0) {
+      // The input was zero (or all 1 bits, which will come to here too after we
+      // inverted it at the start of the function), for which we just return
+      // false.
+      return false;
+    } else {
+      // Otherwise, if c was zero but a was not, then there's just one stretch
+      // of set bits in our word, meaning that we have the trivial case of
+      // d == 64 and only one 'repetition'. Set up all the same variables as in
+      // the general case above, and set the N bit in the output.
+      clz_a = CountLeadingZeros(a, kXRegSize);
+      d = 64;
+      mask = ~UINT64_C(0);
+      out_n = 1;
+    }
+  }
+
+  // If the repeat period d is not a power of two, it can't be encoded.
+  if (!IsPowerOf2(d)) {
+    return false;
+  }
+
+  if (((b - a) & ~mask) != 0) {
+    // If the bit stretch (b - a) does not fit within the mask derived from the
+    // repeat period, then fail.
+    return false;
+  }
+
+  // The only possible option is b - a repeated every d bits. Now we're going to
+  // actually construct the valid logical immediate derived from that
+  // specification, and see if it equals our original input.
+  //
+  // To repeat a value every d bits, we multiply it by a number of the form
+  // (1 + 2^d + 2^(2d) + ...), i.e. 0x0001000100010001 or similar. These can
+  // be derived using a table lookup on CLZ(d).
+  static const uint64_t multipliers[] = {
+      0x0000000000000001UL,
+      0x0000000100000001UL,
+      0x0001000100010001UL,
+      0x0101010101010101UL,
+      0x1111111111111111UL,
+      0x5555555555555555UL,
+  };
+  uint64_t multiplier = multipliers[CountLeadingZeros(d, kXRegSize) - 57];
+  uint64_t candidate = (b - a) * multiplier;
+
+  if (value != candidate) {
+    // The candidate pattern doesn't match our input value, so fail.
+    return false;
+  }
+
+  // We have a match! This is a valid logical immediate, so now we have to
+  // construct the bits and pieces of the instruction encoding that generates
+  // it.
+
+  // Count the set bits in our basic stretch. The special case of clz(0) == -1
+  // makes the answer come out right for stretches that reach the very top of
+  // the word (e.g. numbers like 0xffffc00000000000).
+  int clz_b = (b == 0) ? -1 : CountLeadingZeros(b, kXRegSize);
+  int s = clz_a - clz_b;
+
+  // Decide how many bits to rotate right by, to put the low bit of that basic
+  // stretch in position a.
+  int r;
+  if (negate) {
+    // If we inverted the input right at the start of this function, here's
+    // where we compensate: the number of set bits becomes the number of clear
+    // bits, and the rotation count is based on position b rather than position
+    // a (since b is the location of the 'lowest' 1 bit after inversion).
+    s = d - s;
+    r = (clz_b + 1) & (d - 1);
+  } else {
+    r = (clz_a + 1) & (d - 1);
+  }
+
+  // Now we're done, except for having to encode the S output in such a way that
+  // it gives both the number of set bits and the length of the repeated
+  // segment. The s field is encoded like this:
+  //
+  //     imms    size        S
+  //    ssssss    64    UInt(ssssss)
+  //    0sssss    32    UInt(sssss)
+  //    10ssss    16    UInt(ssss)
+  //    110sss     8    UInt(sss)
+  //    1110ss     4    UInt(ss)
+  //    11110s     2    UInt(s)
+  //
+  // So we 'or' (2 * -d) with our computed s to form imms.
+  if ((n != NULL) || (imm_s != NULL) || (imm_r != NULL)) {
+    *n = out_n;
+    *imm_s = ((2 * -d) | (s - 1)) & 0x3f;
+    *imm_r = r;
+  }
+
+  return true;
+}
+
+static inline bool IsIntN(unsigned n, int64_t x) {
+  if (n == 64) return true;
+  int64_t limit = INT64_C(1) << (n - 1);
+  return (-limit <= x) && (x < limit);
+}
+
+static inline bool IsUintN(unsigned n, int64_t x) {
+  // Convert to an unsigned integer to avoid implementation-defined behavior.
+  return !(static_cast<uint64_t>(x) >> n);
+}
+
+// clang-format off
+#define INT_1_TO_32_LIST(V)                                                    \
+V(1)  V(2)  V(3)  V(4)  V(5)  V(6)  V(7)  V(8)                                 \
+V(9)  V(10) V(11) V(12) V(13) V(14) V(15) V(16)                                \
+V(17) V(18) V(19) V(20) V(21) V(22) V(23) V(24)                                \
+V(25) V(26) V(27) V(28) V(29) V(30) V(31) V(32)
+
+#define INT_33_TO_63_LIST(V)                                                   \
+V(33) V(34) V(35) V(36) V(37) V(38) V(39) V(40)                                \
+V(41) V(42) V(43) V(44) V(45) V(46) V(47) V(48)                                \
+V(49) V(50) V(51) V(52) V(53) V(54) V(55) V(56)                                \
+V(57) V(58) V(59) V(60) V(61) V(62) V(63)
+
+#define INT_1_TO_63_LIST(V) INT_1_TO_32_LIST(V) INT_33_TO_63_LIST(V)
+
+// clang-format on
+
+#define DECLARE_IS_INT_N(N)                                       \
+  static inline bool IsInt##N(int64_t x) { return IsIntN(N, x); }
+
+#define DECLARE_IS_UINT_N(N)                                        \
+  static inline bool IsUint##N(int64_t x) { return IsUintN(N, x); }
+
+INT_1_TO_63_LIST(DECLARE_IS_INT_N)
+INT_1_TO_63_LIST(DECLARE_IS_UINT_N)
+
+#undef DECLARE_IS_INT_N
+#undef DECLARE_IS_UINT_N
+
+private:
+
+template <typename V>
+static inline bool IsPowerOf2(V value) {
+  return (value != 0) && ((value & (value - 1)) == 0);
+}
+
+// Some compilers dislike negating unsigned integers,
+// so we provide an equivalent.
+template <typename T>
+static inline T UnsignedNegate(T value) {
+  static_assert(std::is_unsigned<T>::value);
+  return ~value + 1;
+}
+
+static inline uint64_t LowestSetBit(uint64_t value) {
+  return value & UnsignedNegate(value);
+}
+
+template <typename V>
+static inline int CountLeadingZeros(V value, int width = (sizeof(V) * 8)) {
+#if COMPILER_HAS_BUILTIN_CLZ
+  if (width == 32) {
+    return (value == 0) ? 32 : __builtin_clz(static_cast<unsigned>(value));
+  } else if (width == 64) {
+    return (value == 0) ? 64 : __builtin_clzll(value);
+  }
+#endif
+  return CountLeadingZerosFallBack(value, width);
+}
+
+static inline int CountLeadingZerosFallBack(uint64_t value, int width) {
+  LOGMAN_THROW_A_FMT(IsPowerOf2(width) && (width <= 64), "Invalid width");
+  if (value == 0) {
+    return width;
+  }
+  int count = 0;
+  value = value << (64 - width);
+  if ((value & UINT64_C(0xffffffff00000000)) == 0) {
+    count += 32;
+    value = value << 32;
+  }
+  if ((value & UINT64_C(0xffff000000000000)) == 0) {
+    count += 16;
+    value = value << 16;
+  }
+  if ((value & UINT64_C(0xff00000000000000)) == 0) {
+    count += 8;
+    value = value << 8;
+  }
+  if ((value & UINT64_C(0xf000000000000000)) == 0) {
+    count += 4;
+    value = value << 4;
+  }
+  if ((value & UINT64_C(0xc000000000000000)) == 0) {
+    count += 2;
+    value = value << 2;
+  }
+  if ((value & UINT64_C(0x8000000000000000)) == 0) {
+    count += 1;
+  }
+  count += (value == 0);
+  return count;
+}
+
+public:
@@ -0,0 +1,6 @@
+{
+  "Comment": "Bypasses libGL's glX and instead sends GLX requests directly via xcb",
+  "ThunksDB": {
+    "GL": 0
+  }
+}
@@ -2,9 +2,6 @@
  "DB": {
    "GL": {
      "Library" : "libGL-guest.so",
-      "Depends": [
-        "X11"
-      ],
      "Overlay": [
        "@PREFIX_LIB@/libGL.so",
        "@PREFIX_LIB@/libGL.so.1",
@@ -33,16 +30,10 @@
    },
    "Vulkan": {
      "Library": "libvulkan-guest.so",
-      "Depends": [
-        "xcb"
-      ],
      "Overlay": [
        "@PREFIX_LIB@/libvulkan.so",
        "@PREFIX_LIB@/libvulkan.so.1",
        "@HOME@/.local/share/Steam/ubuntu12_32/steam-runtime/pinned_libs_64/libvulkan.so.1"
-      ],
-      "Comment": [
-        "Vulkan library relies on xcb, otherwise it crashes with jemalloc"
      ]
    },
    "xcb": {
@@ -0,0 +1,336 @@
+#!/usr/bin/env python3
+#
+# ====- code-format-helper, runs code formatters from the ci or in a hook --*- python -*--==#
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# ==--------------------------------------------------------------------------------------==#
+
+import argparse
+import os
+import subprocess
+import sys
+from typing import List, Optional
+
+"""
+This script is run by GitHub actions to ensure that the code in PR's conform to
+the coding style of LLVM. It can also be installed as a pre-commit git hook to
+check the coding style before submitting it. The canonical source of this script
+is in the LLVM source tree under llvm/utils/git.
+
+For C/C++ code it uses clang-format.
+
+You can learn more about the LLVM coding style on llvm.org:
+https://llvm.org/docs/CodingStandards.html
+
+You can install this script as a git hook by symlinking it to the .git/hooks
+directory:
+
+ln -s $(pwd)/llvm/utils/git/code-format-helper.py .git/hooks/pre-commit
+
+You can control the exact path to clang-format with the following
+environment variable: $CLANG_FORMAT_PATH.
+"""
+
+
+class FormatArgs:
+    start_rev: str = None
+    end_rev: str = None
+    repo: str = None
+    changed_files: List[str] = []
+    token: str = None
+    verbose: bool = True
+    issue_number: int = 0
+    write_comment_to_file: str = None
+
+    def __init__(self, args: argparse.Namespace = None) -> None:
+        if not args is None:
+            self.start_rev = args.start_rev
+            self.end_rev = args.end_rev
+            self.repo = args.repo
+            self.token = args.token
+            self.changed_files = args.changed_files
+            self.issue_number = args.issue_number
+            self.write_comment_to_file = args.write_comment_to_file
+
+
+class FormatHelper:
+    COMMENT_TAG = "<!--CODE FORMAT COMMENT: {fmt}-->"
+    name: str
+    friendly_name: str
+    comment: dict = None
+
+    @property
+    def comment_tag(self) -> str:
+        return self.COMMENT_TAG.replace("fmt", self.name)
+
+    @property
+    def instructions(self) -> str:
+        raise NotImplementedError()
+
+    def has_tool(self) -> bool:
+        raise NotImplementedError()
+
+    def format_run(self, changed_files: List[str], args: FormatArgs) -> Optional[str]:
+        raise NotImplementedError()
+
+    def pr_comment_text_for_diff(self, diff: str) -> str:
+        return f"""
+:warning: {self.friendly_name}, {self.name} found issues in your code. :warning:
+
+<details>
+<summary>
+You can test this locally with the following command:
+</summary>
+
+``````````bash
+{self.instructions}
+``````````
+
+</details>
+
+<details>
+<summary>
+View the diff from {self.name} here.
+</summary>
+
+``````````diff
+{diff}
+``````````
+
+</details>
+"""
+
+    # TODO: any type should be replaced with the correct github type, but it requires refactoring to
+    # not require the github module to be installed everywhere.
+    def find_comment(self, pr: any) -> any:
+        for comment in pr.as_issue().get_comments():
+            if self.comment_tag in comment.body:
+                return comment
+        return None
+
+    def update_pr(self, comment_text: str, args: FormatArgs, create_new: bool) -> None:
+        import github
+        from github import IssueComment, PullRequest
+
+        repo = github.Github(args.token).get_repo(args.repo)
+        pr = repo.get_issue(args.issue_number).as_pull_request()
+
+        comment_text = self.comment_tag + "\n\n" + comment_text
+
+        existing_comment = self.find_comment(pr)
+
+        if args.write_comment_to_file:
+            if create_new or existing_comment:
+                self.comment = {"body": comment_text}
+            if existing_comment:
+                self.comment["id"] = existing_comment.id
+            return
+
+        if existing_comment:
+            existing_comment.edit(comment_text)
+        elif create_new:
+            pr.as_issue().create_comment(comment_text)
+
+    def run(self, changed_files: List[str], args: FormatArgs) -> bool:
+        changed_files = [arg for arg in changed_files if "third-party" not in arg]
+        diff = self.format_run(changed_files, args)
+        should_update_gh = args.token is not None and args.repo is not None
+
+        if diff is None:
+            if should_update_gh:
+                comment_text = (
+                    ":white_check_mark: With the latest revision "
+                    f"this PR passed the {self.friendly_name}."
+                )
+                self.update_pr(comment_text, args, create_new=False)
+            return True
+        elif len(diff) > 0:
+            if should_update_gh:
+                comment_text = self.pr_comment_text_for_diff(diff)
+                self.update_pr(comment_text, args, create_new=True)
+            else:
+                print(
+                    f"Warning: {self.friendly_name}, {self.name} detected "
+                    "some issues with your code formatting..."
+                )
+            return False
+        else:
+            # The formatter failed but didn't output a diff (e.g. some sort of
+            # infrastructure failure).
+            comment_text = (
+                f":warning: The {self.friendly_name} failed without printing "
+                "a diff. Check the logs for stderr output. :warning:"
+            )
+            self.update_pr(comment_text, args, create_new=False)
+            return False
+
+
+class ClangFormatHelper(FormatHelper):
+    name = "clang-format"
+    friendly_name = "C/C++ code formatter"
+
+    @property
+    def cformat_wrapper_path(self) -> str:
+        relpath = "../../Scripts/clang-format.py"
+        curpath = os.path.dirname(os.path.abspath(__file__))
+        return os.path.abspath(os.path.normpath(os.path.join(curpath, relpath)))
+
+    @property
+    def instructions(self) -> str:
+        return " ".join(self.cf_cmd)
+
+    def should_include_extensionless_file(self, path: str) -> bool:
+        return path.startswith("libcxx/include")
+
+    def filter_changed_files(self, changed_files: List[str]) -> List[str]:
+        filtered_files = []
+        for path in changed_files:
+            _, ext = os.path.splitext(path)
+            if ext in (".cpp", ".c", ".h", ".hpp", ".hxx", ".cxx", ".inc", ".cppm"):
+                filtered_files.append(path)
+            elif ext == "" and self.should_include_extensionless_file(path):
+                filtered_files.append(path)
+        return filtered_files
+
+    @property
+    def clang_fmt_path(self) -> str:
+        if "CLANG_FORMAT_PATH" in os.environ:
+            return os.environ["CLANG_FORMAT_PATH"]
+        return "git-clang-format"
+
+    def has_tool(self) -> bool:
+        cmd = [self.clang_fmt_path, "-h"]
+        proc = None
+        try:
+            proc = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+        except:
+            return False
+        return proc.returncode == 0
+
+    def format_run(self, changed_files: List[str], args: FormatArgs) -> Optional[str]:
+        cpp_files = self.filter_changed_files(changed_files)
+        if not cpp_files:
+            return None
+
+        cf_cmd = [
+            self.clang_fmt_path,
+            f"--binary={self.cformat_wrapper_path}",
+            "--diff",
+        ]
+
+        if args.start_rev and args.end_rev:
+            cf_cmd.append(args.start_rev)
+            cf_cmd.append(args.end_rev)
+
+        cf_cmd.append("--")
+        cf_cmd += cpp_files
+
+        if args.verbose:
+            print(f"Running: {' '.join(cf_cmd)}")
+        self.cf_cmd = cf_cmd
+        proc = subprocess.run(cf_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+        sys.stdout.write(proc.stderr.decode("utf-8"))
+
+        if proc.returncode != 0:
+            # formatting needed, or the command otherwise failed
+            if args.verbose:
+                print(f"error: {self.name} exited with code {proc.returncode}")
+                # Print the diff in the log so that it is viewable there
+                print(proc.stdout.decode("utf-8"))
+            return proc.stdout.decode("utf-8")
+        else:
+            return None
+
+ALL_FORMATTERS = [ClangFormatHelper()]
+
+def hook_main():
+    # fill out args
+    args = FormatArgs()
+    args.verbose = False
+
+    # find the changed files
+    cmd = ["git", "diff", "--cached", "--name-only", "--diff-filter=d"]
+    proc = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+    output = proc.stdout.decode("utf-8")
+    for line in output.splitlines():
+        args.changed_files.append(line)
+
+    failed_fmts = []
+    for fmt in ALL_FORMATTERS:
+        if fmt.has_tool():
+            if not fmt.run(args.changed_files, args):
+                failed_fmts.append(fmt.name)
+            if fmt.comment:
+                comments.append(fmt.comment)
+        else:
+            print(f"Couldn't find {fmt.name}, can't check " + fmt.friendly_name.lower())
+
+    if len(failed_fmts) > 0:
+        sys.exit(1)
+
+    sys.exit(0)
+
+
+if __name__ == "__main__":
+    script_path = os.path.abspath(__file__)
+    if ".git/hooks" in script_path:
+        hook_main()
+        sys.exit(0)
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "--token", type=str, required=False, help="GitHub authentication token"
+    )
+    parser.add_argument(
+        "--repo",
+        type=str,
+        default=os.getenv("GITHUB_REPOSITORY", "llvm/llvm-project"),
+        help="The GitHub repository that we are working with in the form of <owner>/<repo> (e.g. llvm/llvm-project)",
+    )
+    parser.add_argument("--issue-number", type=int, required=True)
+    parser.add_argument(
+        "--start-rev",
+        type=str,
+        required=True,
+        help="Compute changes from this revision.",
+    )
+    parser.add_argument(
+        "--end-rev", type=str, required=True, help="Compute changes to this revision"
+    )
+    parser.add_argument(
+        "--changed-files",
+        type=str,
+        help="Comma separated list of files that has been changed",
+    )
+    parser.add_argument(
+        "--write-comment-to-file",
+        type=str,
+        help="Don't post comments on the PR, instead write the comments and metadata a file",
+    )
+
+    args = FormatArgs(parser.parse_args())
+
+    changed_files = []
+    if args.changed_files:
+        changed_files = args.changed_files.split(",")
+
+    failed_formatters = []
+    comments = []
+    for fmt in ALL_FORMATTERS:
+        if not fmt.run(changed_files, args):
+            failed_formatters.append(fmt.name)
+        if fmt.comment:
+            comments.append(fmt.comment)
+
+    if len(comments):
+        with open(args.write_comment_to_file, "w") as f:
+            import json
+
+            json.dump(comments, f)
+
+    if len(failed_formatters) > 0:
+        print(f"error: some formatters failed: {' '.join(failed_formatters)}")
+        sys.exit(1)
@@ -0,0 +1,52 @@
+#
+# This file is autogenerated by pip-compile with Python 3.11
+# by the following command:
+#
+#    pip-compile --output-file=llvm/utils/git/requirements_formatting.txt llvm/utils/git/requirements_formatting.txt.in
+#
+black==23.9.1
+    # via
+    #   -r llvm/utils/git/requirements_formatting.txt.in
+    #   darker
+certifi==2023.7.22
+    # via requests
+cffi==1.15.1
+    # via
+    #   cryptography
+    #   pynacl
+charset-normalizer==3.2.0
+    # via requests
+click==8.1.7
+    # via black
+cryptography==41.0.3
+    # via pyjwt
+darker==1.7.2
+    # via -r llvm/utils/git/requirements_formatting.txt.in
+deprecated==1.2.14
+    # via pygithub
+idna==3.4
+    # via requests
+mypy-extensions==1.0.0
+    # via black
+packaging==23.1
+    # via black
+pathspec==0.11.2
+    # via black
+platformdirs==3.10.0
+    # via black
+pycparser==2.21
+    # via cffi
+pygithub==1.59.1
+    # via -r llvm/utils/git/requirements_formatting.txt.in
+pyjwt[crypto]==2.8.0
+    # via pygithub
+pynacl==1.5.0
+    # via pygithub
+requests==2.31.0
+    # via pygithub
+toml==0.10.2
+    # via darker
+urllib3==2.0.4
+    # via requests
+wrapt==1.15.0
+    # via deprecated
@@ -13,8 +13,6 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "^aarch64|^arm64|^armv8\.*")
  set(_M_ARM_64 1)
 endif()

-option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
-
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
 cmake_policy(SET CMP0083 NEW) # Follow new PIE policy
 include(CheckPIESupported)
@@ -26,27 +24,6 @@ include(CheckCXXCompilerFlag)
 include(CheckIncludeFileCXX)
 include(CheckCXXSourceCompiles)

-set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
-check_cxx_source_compiles(
-  "
-  __attribute__((preserve_all))
-  int Testy(int a, int b, int c, int d, int e, int f) {
-  return a + b + c + d + e + f;
-  }
-  int main() {
-  return Testy(0, 1, 2, 3, 4, 5);
-  }"
-  HAS_CLANG_PRESERVE_ALL)
-unset(CMAKE_REQUIRED_FLAGS)
-if (HAS_CLANG_PRESERVE_ALL)
-  if (MINGW_BUILD)
-    message(STATUS "Ignoring broken clang::preserve_all support")
-    set(HAS_CLANG_PRESERVE_ALL FALSE)
-  else()
-    message(STATUS "Has clang::preserve_all")
-  endif()
-endif ()
-
 if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
    # Useful to have for freestanding libFEXCore
    add_subdirectory(External/vixl/)
@@ -148,9 +148,8 @@ def print_man_options(options):
            if (value_type == "strenum"):
                Enums = op_vals["Enums"]
                output_man.write("\\fBAvailable Options:\\fR\n")
-                for enum_op_key, enum_op_vals in Enums.items():
-                    output_man.write("{}, ".format(enum_op_vals))
-                output_man.write("\n")
+                output_man.write(", ".join(f"{enum_op_val}" for [_, enum_op_val] in Enums.items()))
+                output_man.write("\n.sp\n")

    output_man.write(".El\n")

@@ -179,9 +178,8 @@ def print_man_environment(options):
            if (value_type == "strenum"):
                Enums = op_vals["Enums"]
                output_man.write("\\fBAvailable Options:\\fR\n")
-                for enum_op_key, enum_op_vals in Enums.items():
-                    output_man.write("{}, ".format(enum_op_vals))
-                output_man.write("\n")
+                output_man.write(", ".join(f"{enum_op_val}" for [_, enum_op_val] in Enums.items()))
+                output_man.write("\n.sp\n")

    print_man_environment_tail()
    output_man.write(".El\n")
@@ -2,6 +2,7 @@
 import json
 import sys
 from dataclasses import dataclass, field
+import textwrap

 def ExitError(msg):
    print(msg)
@@ -53,8 +54,10 @@ class OpDefinition:
    SSAArgNum: int
    NonSSAArgNum: int
    DynamicDispatch: bool
+    LoweredX87: bool
    JITDispatch: bool
    JITDispatchOverride: str
+    TiedSource: int
    Arguments: list
    EmitValidation: list
    Desc: list
@@ -75,8 +78,10 @@ class OpDefinition:
        self.SSAArgNum = 0
        self.NonSSAArgNum = 0
        self.DynamicDispatch = False
+        self.LoweredX87 = False
        self.JITDispatch = True
        self.JITDispatchOverride = None
+        self.TiedSource = -1
        self.Arguments = []
        self.EmitValidation = []
        self.Desc = []
@@ -202,7 +207,7 @@ def parse_ops(ops):
                        (OpArg.Type == "GPR" or
                        OpArg.Type == "GPRPair" or
                        OpArg.Type == "FPR")):
-                        OpDef.EmitValidation.append("GetOpRegClass({}) == InvalidClass || WalkFindRegClass({}) == {}Class".format(NameWithPrefix, NameWithPrefix, OpArg.Type))
+                        OpDef.EmitValidation.append(f"GetOpRegClass({ArgName}) == InvalidClass || WalkFindRegClass({ArgName}) == {OpArg.Type}Class")

                    OpArg.Name = ArgName
                    OpArg.NameWithPrefix = NameWithPrefix
@@ -248,17 +253,23 @@ def parse_ops(ops):
            if "JITDispatchOverride" in op_val:
                OpDef.JITDispatchOverride = op_val["JITDispatchOverride"]

+            if "X87" in op_val:
+                OpDef.LoweredX87 = op_val["X87"]
+
+                # X87 implies !JITDispatch
+                assert("JITDispatch" not in op_val)
+                OpDef.JITDispatch = False
+
+            if "TiedSource" in op_val:
+                OpDef.TiedSource = op_val["TiedSource"]
+
            # Do some fixups of the data here
            if len(OpDef.EmitValidation) != 0:
                for i in range(len(OpDef.EmitValidation)):
                    # Patch up all the argument names
                    for Arg in OpDef.Arguments:
-                        if Arg.Temporary:
-                            # Temporary ops just replace all instances no prefix variant
-                            OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, Arg.Name)
-                        else:
-                            # All other ops replace $ with _ variant for argument passed in
-                            OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, "_{}".format(Arg.Name))
+                        # Temporary ops just replace all instances no prefix variant
+                        OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, Arg.Name)

            #OpDef.print()

@@ -363,25 +374,28 @@ def print_ir_sizes():
        if op.Name == "Last":
            output_file.write("\t-1ULL,\n")
        else:
-            output_file.write("\tsizeof(IROp_{}),\n".format(op.Name))
+            output_file.write(f"\tsizeof(IROp_{op.Name}),\n")

-    output_file.write("};\n\n")
+    output_file.write(textwrap.dedent("""
+    };

-    output_file.write("// Make sure our array maps directly to the IROps enum\n")
-    output_file.write("static_assert(IRSizes[IROps::OP_LAST] == -1ULL);\n\n")
+    // Make sure our array maps directly to the IROps enum
+    static_assert(IRSizes[IROps::OP_LAST] == -1ULL);

-    output_file.write("[[maybe_unused, nodiscard]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }\n\n")
+    [[maybe_unused, nodiscard]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }
+    [[nodiscard, gnu::const, gnu::visibility("default")]] std::string_view const& GetName(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetArgs(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetRAArgs(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool HasSideEffects(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool ImplicitFlagClobber(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool GetHasDest(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool LoweredX87(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] int8_t TiedSource(IROps Op);

-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] std::string_view const& GetName(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetArgs(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetRAArgs(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool HasSideEffects(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool ImplicitFlagClobber(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool GetHasDest(IROps Op);\n")
-
-    output_file.write("#undef IROP_SIZES\n")
-    output_file.write("#endif\n\n")
+    #undef IROP_SIZES
+    #endif
+    """))

 def print_ir_reg_classes():
    output_file.write("#ifdef IROP_REG_CLASSES_IMPL\n")
@@ -471,16 +485,27 @@ def print_ir_getraargs():
 def print_ir_hassideeffects():
    output_file.write("#ifdef IROP_HASSIDEEFFECTS_IMPL\n")

-    for array, prop in [("SideEffects", "HasSideEffects"),
-                        ("ImplicitFlagClobbers", "ImplicitFlagClobber")]:
-        output_file.write(f"constexpr std::array<uint8_t, OP_LAST + 1> {array} = {{\n")
+    for prop, T in [
+        ("HasSideEffects", "bool"),
+        ("ImplicitFlagClobber", "bool"),
+        ("LoweredX87", "bool"),
+        ("TiedSource", "int8_t"),
+    ]:
+        output_file.write(
+            f"constexpr std::array<{'uint8_t' if T == 'bool' else T}, OP_LAST + 1> {prop}_ = {{\n"
+        )
        for op in IROps:
-            output_file.write("\t{},\n".format(("true" if getattr(op, prop) else "false")))
+            if T == "bool":
+                output_file.write(
+                    "\t{},\n".format(("true" if getattr(op, prop) else "false"))
+                )
+            else:
+                output_file.write(f"\t{getattr(op, prop)},\n")

        output_file.write("};\n\n")

-        output_file.write(f"bool {prop}(IROps Op) {{\n")
-        output_file.write(f"  return {array}[Op];\n")
+        output_file.write(f"{T} {prop}(IROps Op) {{\n")
+        output_file.write(f"  return {prop}_[Op];\n")
        output_file.write("}\n")

    output_file.write("#undef IROP_HASSIDEEFFECTS_IMPL\n")
@@ -520,14 +545,20 @@ def print_ir_arg_printer():
            output_file.write("\t*out << \" \";\n")

            SSAArgNum = 0
+            FirstArg = True
            for i in range(0, len(op.Arguments)):
                arg = op.Arguments[i]
-                LastArg = len(op.Arguments) - i - 1 == 0

+                # No point printing temporaries that we can't recover
                if arg.Temporary:
-                    # Temporary that we can't recover
-                    output_file.write("\t*out << \"{}:Tmp:{}\";\n".format(arg.Type, arg.Name))
-                elif arg.IsSSA:
+                    continue
+
+                if FirstArg:
+                    FirstArg = False
+                else:
+                    output_file.write('\t*out << ", ";\n')
+
+                if arg.IsSSA:
                    # SSA value
                    output_file.write("\tPrintArg(out, IR, Op->Header.Args[{}], RAData);\n".format(SSAArgNum))
                    SSAArgNum = SSAArgNum + 1
@@ -535,9 +566,6 @@ def print_ir_arg_printer():
                    # User defined op that is stored
                    output_file.write("\tPrintArg(out, IR, Op->{});\n".format(arg.Name))

-                if not LastArg:
-                    output_file.write("\t*out << \", \";\n")
-
        output_file.write("break;\n")
        output_file.write("}\n")

@@ -636,11 +664,11 @@ def print_ir_allocator_helpers():
                    output_file.write("{} {}".format(CType, arg.Name));
                elif arg.IsSSA:
                    # SSA value
-                    output_file.write("OrderedNode *_{}".format(arg.Name))
+                    output_file.write("OrderedNode *{}".format(arg.Name))
                else:
                    # User defined op that is stored
                    CType = IRTypesToCXX[arg.Type].CXXName
-                    output_file.write("{} _{}".format(CType, arg.Name));
+                    output_file.write("{} {}".format(CType, arg.Name));

                if arg.DefaultInitializer != None:
                    output_file.write(" = {}".format(arg.DefaultInitializer))
@@ -654,23 +682,28 @@ def print_ir_allocator_helpers():
            if op.ImplicitFlagClobber:
                output_file.write("\t\tSaveNZCV(IROps::OP_{});".format(op.Name.upper()))

-            output_file.write("\t\tauto Op = AllocateOp<IROp_{}, IROps::OP_{}>();\n".format(op.Name, op.Name.upper()))
+            # We gather the "has x87?" flag as we go. This saves the user from
+            # having to keep track of whether they emitted any x87.
+            if op.LoweredX87:
+                output_file.write("\t\tRecordX87Use();\n")
+
+            output_file.write("\t\tauto _Op = AllocateOp<IROp_{}, IROps::OP_{}>();\n".format(op.Name, op.Name.upper()))

            if op.SSAArgNum != 0:
                output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n")
                for arg in op.Arguments:
                    if arg.IsSSA:
-                        output_file.write("\t\tOp.first->{} = _{}->Wrapped(ListDataBegin);\n".format(arg.Name, arg.Name))
+                        output_file.write("\t\t_Op.first->{} = {}->Wrapped(ListDataBegin);\n".format(arg.Name, arg.Name))

            if op.SSAArgNum != 0:
                for arg in op.Arguments:
                    if arg.IsSSA:
-                        output_file.write("\t\t_{}->AddUse();\n".format(arg.Name))
+                        output_file.write("\t\t{}->AddUse();\n".format(arg.Name))

            if len(op.Arguments) != 0:
                for arg in op.Arguments:
                    if not arg.Temporary and not arg.IsSSA:
-                        output_file.write("\t\tOp.first->{} = _{};\n".format(arg.Name, arg.Name))
+                        output_file.write("\t\t_Op.first->{} = {};\n".format(arg.Name, arg.Name))

            if (op.HasDest):
                # We can only infer a size if we have arguments
@@ -680,22 +713,22 @@ def print_ir_allocator_helpers():
                    if len(op.Arguments) != 0:
                        for arg in op.Arguments:
                            if arg.IsSSA:
-                                output_file.write("\t\tuint8_t Size{} = GetOpSize(_{});\n".format(arg.Name, arg.Name))
+                                output_file.write("\t\tuint8_t Size{} = GetOpSize({});\n".format(arg.Name, arg.Name))
                        for arg in op.Arguments:
                            if arg.IsSSA:
                                output_file.write("\t\tInferSize = std::max(InferSize, Size{});\n".format(arg.Name))

-                    output_file.write("\t\tOp.first->Header.Size = InferSize;\n")
+                    output_file.write("\t\t_Op.first->Header.Size = InferSize;\n")

            # Some ops without a destination still need an operating size
            # Effectively reusing the destination size value for operation size
            if op.DestSize != None:
-                output_file.write("\t\tOp.first->Header.Size = {};\n".format(op.DestSize))
+                output_file.write("\t\t_Op.first->Header.Size = {};\n".format(op.DestSize))

            if op.NumElements == None:
-                output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / ({});\n".format(1))
+                output_file.write("\t\t_Op.first->Header.ElementSize = _Op.first->Header.Size / ({});\n".format(1))
            else:
-                output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / ({});\n".format(op.NumElements))
+                output_file.write("\t\t_Op.first->Header.ElementSize = _Op.first->Header.Size / ({});\n".format(op.NumElements))

            # Insert validation here
            if op.EmitValidation != None:
@@ -706,58 +739,12 @@ def print_ir_allocator_helpers():
                    output_file.write("\tLOGMAN_THROW_A_FMT({}, \"{}\");\n".format(Validation, Sanitized))
                output_file.write("\t\t#endif\n")

-            output_file.write("\t\treturn Op;\n")
+            output_file.write("\t\treturn _Op;\n")
            output_file.write("\t}\n\n")

    output_file.write("#undef IROP_ALLOCATE_HELPERS\n")
    output_file.write("#endif\n")

-def print_ir_parser_switch_helper():
-    output_file.write("#ifdef IROP_PARSER_SWITCH_HELPERS\n")
-    for op in IROps:
-        if op.Name != "Last" and op.SwitchGen:
-            output_file.write("\tcase FEXCore::IR::IROps::OP_%s: {\n" % (op.Name.upper()))
-
-            for i in range(0, len(op.Arguments)):
-                arg = op.Arguments[i]
-                LastArg = len(op.Arguments) - i - 1 == 0
-
-                if arg.Temporary:
-                    CType = IRTypesToCXX[arg.Type].CXXName
-                    output_file.write("\t\tauto arg{} = DecodeValue<{}>(Def.Args[{}]);\n".format(i, CType, i))
-                    output_file.write("\t\tif (!CheckPrintErrorArg(Def, arg{}.first, {})) return false;\n".format(i, i))
-                elif arg.IsSSA:
-                    # SSA value
-                    output_file.write("\t\tauto arg{} = DecodeValue<OrderedNode*>(Def.Args[{}]);\n".format(i, i))
-                    output_file.write("\t\tif (!CheckPrintErrorArg(Def, arg{}.first, {})) return false;\n".format(i, i))
-                else:
-                    # User defined op that is stored
-                    CType = IRTypesToCXX[arg.Type].CXXName
-                    output_file.write("\t\tauto arg{} = DecodeValue<{}>(Def.Args[{}]);\n".format(i, CType, i))
-                    output_file.write("\t\tif (!CheckPrintErrorArg(Def, arg{}.first, {})) return false;\n".format(i, i))
-
-            output_file.write("\t\tDef.Node = _{}(\n".format(op.Name))
-
-            for i in range(0, len(op.Arguments)):
-                arg = op.Arguments[i]
-                LastArg = len(op.Arguments) - i - 1 == 0
-                output_file.write("\t\t\targ{}.second".format(i))
-                if not LastArg:
-                    output_file.write(",\n")
-                else:
-                    output_file.write("\n")
-
-            output_file.write("\t\t);\n")
-
-            output_file.write("\t\tSSANameMapper[Def.Definition] = Def.Node;\n")
-
-            output_file.write("\t\tbreak;\n")
-            output_file.write("\t}\n")
-
-
-    output_file.write("#undef IROP_PARSER_SWITCH_HELPERS\n")
-    output_file.write("#endif\n")
-
 def print_ir_dispatcher_defs():
    output_dispatch_file.write("#ifdef IROP_DISPATCH_DEFS\n")
    for op in IROps:
@@ -816,7 +803,6 @@ print_ir_hassideeffects()
 print_ir_gethasdest()
 print_ir_arg_printer()
 print_ir_allocator_helpers()
-print_ir_parser_switch_helper()

 output_file.close()

@@ -67,7 +67,6 @@ set (SRCS
  Common/SoftFloat-3e/s_approxRecipSqrt32_1.c
  Common/SoftFloat-3e/s_approxRecipSqrt_1Ks.c
  Common/SoftFloat-3e/softfloat_raiseFlags.c
-  Common/SoftFloat-3e/softfloat_state.c
  Common/SoftFloat-3e/f64_to_extF80.c
  Common/SoftFloat-3e/s_commonNaNToExtF80UI.c
  Common/SoftFloat-3e/s_normSubnormalF64Sig.c
@@ -91,10 +90,10 @@ set (SRCS
  Interface/Core/CPUBackend.cpp
  Interface/Core/CPUID.cpp
  Interface/Core/Frontend.cpp
-  Interface/Core/HostFeatures.cpp
  Interface/Core/ObjectCache/JobHandling.cpp
  Interface/Core/ObjectCache/NamedRegionObjectHandler.cpp
  Interface/Core/ObjectCache/ObjectCacheService.cpp
+  Interface/Core/OpcodeDispatcher/AVX_128.cpp
  Interface/Core/OpcodeDispatcher/Crypto.cpp
  Interface/Core/OpcodeDispatcher/Flags.cpp
  Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -112,7 +111,6 @@ set (SRCS
  Interface/Core/JIT/Arm64/BranchOps.cpp
  Interface/Core/JIT/Arm64/ConversionOps.cpp
  Interface/Core/JIT/Arm64/EncryptionOps.cpp
-  Interface/Core/JIT/Arm64/FlagOps.cpp
  Interface/Core/JIT/Arm64/MemoryOps.cpp
  Interface/Core/JIT/Arm64/MiscOps.cpp
  Interface/Core/JIT/Arm64/MoveOps.cpp
@@ -134,22 +132,16 @@ set (SRCS
  Interface/GDBJIT/GDBJIT.cpp
  Interface/IR/AOTIR.cpp
  Interface/IR/IRDumper.cpp
-  Interface/IR/IRParser.cpp
  Interface/IR/IREmitter.cpp
  Interface/IR/PassManager.cpp
  Interface/IR/Passes/ConstProp.cpp
-  Interface/IR/Passes/DeadCodeElimination.cpp
-  Interface/IR/Passes/DeadContextStoreElimination.cpp
-  Interface/IR/Passes/IRCompaction.cpp
  Interface/IR/Passes/IRDumperPass.cpp
  Interface/IR/Passes/IRValidation.cpp
  Interface/IR/Passes/RAValidation.cpp
-  Interface/IR/Passes/LongDivideRemovalPass.cpp
-  Interface/IR/Passes/ValueDominanceValidation.cpp
  Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
  Interface/IR/Passes/DeadStoreElimination.cpp
  Interface/IR/Passes/RegisterAllocationPass.cpp
-  Interface/IR/Passes/InlineCallOptimization.cpp
+  Interface/IR/Passes/x87StackOptimizationPass.cpp
  Utils/Telemetry.cpp
  Utils/Threads.cpp
  Utils/Profiler.cpp
@@ -166,7 +158,7 @@ if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
    Utils/AllocatorOverride.cpp)
 endif()

-set(DEFINES -DTHREAD_LOCAL=_Thread_local -DJIT_ARM64)
+set(DEFINES -DJIT_ARM64)

 if (_M_X86_64)
  list(APPEND DEFINES -D_M_X86_64=1)
@@ -176,11 +168,6 @@ if (_M_ARM_64)
  list(APPEND DEFINES -D_M_ARM_64=1)
 endif()

-if (ENABLE_VIXL_SIMULATOR)
-  # We can run the simulator on both x86-64 or AArch64 hosts
-  list(APPEND DEFINES -DVIXL_SIMULATOR=1 -DVIXL_INCLUDE_SIMULATOR_AARCH64=1)
-endif()
-
 if (ENABLE_VIXL_DISASSEMBLER)
  list(APPEND DEFINES -DVIXL_DISASSEMBLER=1)
 endif()
@@ -194,12 +181,15 @@ endif()
 # Some defines for the softfloat library
 list(APPEND DEFINES "-DSOFTFLOAT_BUILTIN_CLZ")

-set (LIBS fmt::fmt vixl xxHash::xxhash FEXHeaderUtils)
+set (LIBS fmt::fmt vixl xxHash::xxhash FEXHeaderUtils CodeEmitter)

 if (NOT MINGW_BUILD)
  list (APPEND LIBS dl)
 else()
  list (APPEND LIBS synchronization)
+  if (_M_ARM_64EC)
+    list (APPEND LIBS kernelbase)
+  endif()
 endif()

 if (ENABLE_JEMALLOC)
@@ -370,16 +360,6 @@ function(AddLibrary Name Type)
  target_link_libraries(${Name} FEXCore_Base)
  target_compile_options(${Name} PRIVATE ${FEX_TUNE_COMPILE_FLAGS})
  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
-  if (MINGW_BUILD)
-    # Mingw build isn't building a linux shared library, so it can't have a SONAME.
-    set_target_properties(${Name} PROPERTIES NO_SONAME ON)
-    # Change the suffixes otherwise cmake continues using .a and .so
-    if (${Type} STREQUAL SHARED)
-      set_target_properties(${Name} PROPERTIES SUFFIX ".dll")
-    elseif(${Type} STREQUAL STATIC)
-      set_target_properties(${Name} PROPERTIES SUFFIX ".lib")
-    endif()
-  endif()

  AddDefaultOptionsToTarget(${Name})
 endfunction()
@@ -18,14 +18,14 @@ struct BitSet final {
  constexpr static size_t MinimumSize = sizeof(ElementType);
  constexpr static size_t MinimumSizeBits = sizeof(ElementType) * 8;

-  ElementType *Memory;
+  ElementType* Memory;
  void Allocate(size_t Elements) {
-    size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
+    size_t AllocateSize = ToBytes(Elements);
    LOGMAN_THROW_AA_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
    Memory = static_cast<ElementType*>(FEXCore::Allocator::malloc(AllocateSize));
  }
  void Realloc(size_t Elements) {
-    size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
+    size_t AllocateSize = ToBytes(Elements);
    LOGMAN_THROW_AA_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
    Memory = static_cast<ElementType*>(FEXCore::Allocator::realloc(Memory, AllocateSize));
  }
@@ -43,10 +43,13 @@ struct BitSet final {
    Memory[Element / MinimumSizeBits] &= (1ULL << (Element % MinimumSizeBits));
  }
  void MemClear(size_t Elements) {
-    memset(Memory, 0, AlignUp(Elements / MinimumSizeBits, MinimumSizeBits));
+    memset(Memory, 0, ToBytes(Elements));
  }
  void MemSet(size_t Elements) {
-    memset(Memory, 0xFF, AlignUp(Elements / MinimumSizeBits, MinimumSizeBits));
+    memset(Memory, 0xFF, ToBytes(Elements));
+  }
+  uint32_t ToBytes(size_t Elements) {
+    return AlignUp(Elements, MinimumSizeBits) / MinimumSize;
  }

  // This very explicitly doesn't let you take an address
@@ -62,11 +65,10 @@ struct BitSetView final {
  constexpr static size_t MinimumSize = sizeof(ElementType);
  constexpr static size_t MinimumSizeBits = sizeof(ElementType) * 8;

-  ElementType *Memory;
+  ElementType* Memory;

-  void GetView(BitSet<T> &Set, uint64_t ElementOffset) {
-    LOGMAN_THROW_AA_FMT((ElementOffset % MinimumSize) == 0,
-                       "Bitset view offset needs to be aligned to size of backing element");
+  void GetView(BitSet<T>& Set, uint64_t ElementOffset) {
+    LOGMAN_THROW_AA_FMT((ElementOffset % MinimumSize) == 0, "Bitset view offset needs to be aligned to size of backing element");
    Memory = &Set.Memory[ElementOffset / MinimumSizeBits];
  }

@@ -7,133 +7,142 @@
 #include <unistd.h>

 namespace FEXCore {
-  JITSymbols::JITSymbols() {
-  }
+JITSymbols::JITSymbols() {}

-  JITSymbols::~JITSymbols() {
-    if (fd != -1) {
-      close(fd);
-    }
+JITSymbols::~JITSymbols() {
+  if (fd != -1) {
+    close(fd);
  }
+}

-  void JITSymbols::InitFile() {
-    // We can't use FILE here since we must be robust against forking processes closing our FD from under us.
+void JITSymbols::InitFile() {
+  // We can't use FILE here since we must be robust against forking processes closing our FD from under us.
 #ifdef __ANDROID__
-    // Android simpleperf looks in /data/local/tmp instead of /tmp
-    const auto PerfMap = fextl::fmt::format("/data/local/tmp/perf-{}.map", getpid());
+  // Android simpleperf looks in /data/local/tmp instead of /tmp
+  const auto PerfMap = fextl::fmt::format("/data/local/tmp/perf-{}.map", getpid());
 #else
-    const auto PerfMap = fextl::fmt::format("/tmp/perf-{}.map", getpid());
+  const auto PerfMap = fextl::fmt::format("/tmp/perf-{}.map", getpid());
 #endif
-    fd = open(PerfMap.c_str(), O_CREAT | O_TRUNC | O_WRONLY | O_APPEND, 0644);
+  fd = open(PerfMap.c_str(), O_CREAT | O_TRUNC | O_WRONLY | O_APPEND, 0644);
+}
+
+void JITSymbols::RegisterNamedRegion(const void* HostAddr, uint32_t CodeSize, std::string_view Name) {
+  if (fd == -1) {
+    return;
  }

-  void JITSymbols::RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
-    if (fd == -1) return;
+  // Linux perf format is very straightforward
+  // `<HostPtr> <Size> <Name>\n`
+  const auto Buffer = fextl::fmt::format("{} {:x} {}\n", HostAddr, CodeSize, Name);
+  auto Result = write(fd, Buffer.c_str(), Buffer.size());
+  if (Result == -1 && errno == EBADF) {
+    fd = -1;
+  }
+}

-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fextl::fmt::format("{} {:x} {}\n", HostAddr, CodeSize, Name);
-    auto Result = write(fd, Buffer.c_str(), Buffer.size());
-    if (Result == -1 && errno == EBADF) {
-      fd = -1;
-    }
+void JITSymbols::RegisterJITSpace(const void* HostAddr, uint32_t CodeSize) {
+  if (fd == -1) {
+    return;
  }

-  void JITSymbols::RegisterJITSpace(const void *HostAddr, uint32_t CodeSize) {
-    if (fd == -1) return;
+  // Linux perf format is very straightforward
+  // `<HostPtr> <Size> <Name>\n`
+  const auto Buffer = fextl::fmt::format("{} {:x} FEXJIT\n", HostAddr, CodeSize);
+  auto Result = write(fd, Buffer.c_str(), Buffer.size());
+  if (Result == -1 && errno == EBADF) {
+    fd = -1;
+  }
+}

-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fextl::fmt::format("{} {:x} FEXJIT\n", HostAddr, CodeSize);
-    auto Result = write(fd, Buffer.c_str(), Buffer.size());
-    if (Result == -1 && errno == EBADF) {
-      fd = -1;
-    }
+// Buffered JIT symbols.
+void JITSymbols::Register(Core::JITSymbolBuffer* Buffer, const void* HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
+  if (fd == -1) {
+    return;
  }

-  // Buffered JIT symbols.
-  void JITSymbols::Register(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
-    if (fd == -1) return;
+  // Calculate remaining sizes.
+  const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
+  const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];

-    // Calculate remaining sizes.
-    const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
-    const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];
+  // Linux perf format is very straightforward
+  // `<HostPtr> <Size> <Name>\n`
+  const auto FMTResult = fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
+  if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
+    // Couldn't fit, need to force a write.
+    WriteBuffer(Buffer, true);
+    // Rerun
+    Register(Buffer, HostAddr, GuestAddr, CodeSize);
+    return;
+  }

-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto FMTResult = fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
-    if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
-      // Couldn't fit, need to force a write.
-      WriteBuffer(Buffer, true);
-      // Rerun
-      Register(Buffer, HostAddr, GuestAddr, CodeSize);
+  Buffer->Offset += FMTResult.size;
+  WriteBuffer(Buffer);
+}
+
+void JITSymbols::Register(Core::JITSymbolBuffer* Buffer, const void* HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset) {
+  if (fd == -1) {
+    return;
+  }
+
+  // Calculate remaining sizes.
+  const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
+  const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];
+
+  // Linux perf format is very straightforward
+  // `<HostPtr> <Size> <Name>\n`
+  const auto FMTResult =
+    fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
+  if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
+    // Couldn't fit, need to force a write.
+    WriteBuffer(Buffer, true);
+    // Rerun
+    Register(Buffer, HostAddr, CodeSize, Name, Offset);
+    return;
+  }
+
+  Buffer->Offset += FMTResult.size;
+  WriteBuffer(Buffer);
+}
+
+void JITSymbols::RegisterNamedRegion(Core::JITSymbolBuffer* Buffer, const void* HostAddr, uint32_t CodeSize, std::string_view Name) {
+  if (fd == -1) {
+    return;
+  }
+
+  // Calculate remaining sizes.
+  const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
+  const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];
+
+  // Linux perf format is very straightforward
+  // `<HostPtr> <Size> <Name>\n`
+  const auto FMTResult = fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} {}\n", HostAddr, CodeSize, Name);
+  if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
+    // Couldn't fit, need to force a write.
+    WriteBuffer(Buffer, true);
+    // Rerun
+    RegisterNamedRegion(Buffer, HostAddr, CodeSize, Name);
+    return;
+  }
+
+  Buffer->Offset += FMTResult.size;
+  WriteBuffer(Buffer);
+}
+
+void JITSymbols::WriteBuffer(Core::JITSymbolBuffer* Buffer, bool ForceWrite) {
+  auto Now = std::chrono::steady_clock::now();
+  if (!ForceWrite) {
+    if (((Buffer->LastWrite - Now) < Buffer->MAXIMUM_THRESHOLD) && Buffer->Offset < Buffer->NEEDS_WRITE_DISTANCE) {
+      // Still buffering, no need to write.
      return;
    }
-
-    Buffer->Offset += FMTResult.size;
-    WriteBuffer(Buffer);
  }

-  void JITSymbols::Register(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset) {
-    if (fd == -1) return;
-
-    // Calculate remaining sizes.
-    const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
-    const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto FMTResult = fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
-    if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
-      // Couldn't fit, need to force a write.
-      WriteBuffer(Buffer, true);
-      // Rerun
-      Register(Buffer, HostAddr, CodeSize, Name, Offset);
-      return;
-    }
-
-    Buffer->Offset += FMTResult.size;
-    WriteBuffer(Buffer);
+  Buffer->LastWrite = Now;
+  auto Result = write(fd, Buffer->Buffer, Buffer->Offset);
+  if (Result == -1 && errno == EBADF) {
+    fd = -1;
  }

-  void JITSymbols::RegisterNamedRegion(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
-    if (fd == -1) return;
-
-    // Calculate remaining sizes.
-    const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
-    const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto FMTResult = fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} {}\n", HostAddr, CodeSize, Name);
-    if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
-      // Couldn't fit, need to force a write.
-      WriteBuffer(Buffer, true);
-      // Rerun
-      RegisterNamedRegion(Buffer, HostAddr, CodeSize, Name);
-      return;
-    }
-
-    Buffer->Offset += FMTResult.size;
-    WriteBuffer(Buffer);
-  }
-
-  void JITSymbols::WriteBuffer(Core::JITSymbolBuffer *Buffer, bool ForceWrite) {
-    auto Now = std::chrono::steady_clock::now();
-    if (!ForceWrite) {
-      if (((Buffer->LastWrite - Now) < Buffer->MAXIMUM_THRESHOLD) &&
-          Buffer->Offset < Buffer->NEEDS_WRITE_DISTANCE) {
-        // Still buffering, no need to write.
-        return;
-      }
-    }
-
-    Buffer->LastWrite = Now;
-    auto Result = write(fd, Buffer->Buffer, Buffer->Offset);
-    if (Result == -1 && errno == EBADF) {
-      fd = -1;
-    }
-
-    Buffer->Offset = 0;
-  }
+  Buffer->Offset = 0;
+}
 } // namespace FEXCore
@@ -17,20 +17,20 @@ public:
  ~JITSymbols();

  void InitFile();
-  void RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
-  void RegisterJITSpace(const void *HostAddr, uint32_t CodeSize);
+  void RegisterNamedRegion(const void* HostAddr, uint32_t CodeSize, std::string_view Name);
+  void RegisterJITSpace(const void* HostAddr, uint32_t CodeSize);

  // Allocate JIT buffer.
  static fextl::unique_ptr<Core::JITSymbolBuffer> AllocateBuffer() {
    return fextl::make_unique<Core::JITSymbolBuffer>();
  }

-  void Register(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
-  void Register(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset);
-  void RegisterNamedRegion(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint32_t CodeSize, std::string_view Name);
+  void Register(Core::JITSymbolBuffer* Buffer, const void* HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
+  void Register(Core::JITSymbolBuffer* Buffer, const void* HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset);
+  void RegisterNamedRegion(Core::JITSymbolBuffer* Buffer, const void* HostAddr, uint32_t CodeSize, std::string_view Name);

 private:
-  int fd{-1};
-  void WriteBuffer(Core::JITSymbolBuffer *Buffer, bool ForceWrite = false);
+  int fd {-1};
+  void WriteBuffer(Core::JITSymbolBuffer* Buffer, bool ForceWrite = false);
 };
-}
+} // namespace FEXCore
@@ -41,7 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_add( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -53,7 +53,7 @@ extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
    bool signB;
    extFloat80_t
        (*magsFuncPtr)(
-            uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+            struct softfloat_state *, uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );

    uA.f = a;
    uiA64 = uA.s.signExp;
@@ -65,6 +65,6 @@ extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
    signB = signExtF80UI64( uiB64 );
    magsFuncPtr =
        (signA == signB) ? softfloat_addMagsExtF80 : softfloat_subMagsExtF80;
-    return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+    return (*magsFuncPtr)( state, uiA64, uiA0, uiB64, uiB0, signA );
 }

@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_div( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -107,7 +107,7 @@ extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
    if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) {
        if ( ! sigB ) {
            if ( ! sigA ) goto invalid;
-            softfloat_raiseFlags( softfloat_flag_infinite );
+            softfloat_raiseFlags( state, softfloat_flag_infinite );
            goto infinity;
        }
        normExpSig = softfloat_normSubnormalExtF80Sig( sigB );
@@ -169,18 +169,18 @@ extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
    sigZExtra = (uint64_t) ((uint_fast64_t) q<<41);
    return
        softfloat_roundPackToExtF80(
-            signZ, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+            state, signZ, expZ, sigZ, sigZExtra, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
    goto uiZ;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    uiZ64 = defaultNaNExtF80UI64;
    uiZ0  = defaultNaNExtF80UI0;
    goto uiZ;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-bool extF80_eq( extFloat80_t a, extFloat80_t b )
+bool extF80_eq( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -62,7 +62,7 @@ bool extF80_eq( extFloat80_t a, extFloat80_t b )
               softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
            || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
        ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
+            softfloat_raiseFlags( state, softfloat_flag_invalid );
        }
        return false;
    }
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-bool extF80_lt( extFloat80_t a, extFloat80_t b )
+bool extF80_lt( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -59,7 +59,7 @@ bool extF80_lt( extFloat80_t a, extFloat80_t b )
    uiB64 = uB.s.signExp;
    uiB0  = uB.s.signif;
    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        return false;
    }
    signA = signExtF80UI64( uiA64 );
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_mul( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -125,11 +125,11 @@ extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
    }
    return
        softfloat_roundPackToExtF80(
-            signZ, expZ, sig128Z.v64, sig128Z.v0, extF80_roundingPrecision );
+            state, signZ, expZ, sig128Z.v64, sig128Z.v0, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
    goto uiZ;
@@ -137,7 +137,7 @@ extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
    *------------------------------------------------------------------------*/
 infArg:
    if ( ! magBits ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        uiZ64 = defaultNaNExtF80UI64;
        uiZ0  = defaultNaNExtF80UI0;
    } else {
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_rem( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -193,18 +193,18 @@ extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b )
    }
    return
        softfloat_normRoundPackToExtF80(
-            signRem, rem.v64 | rem.v0 ? expB + 32 : 0, rem.v64, rem.v0, 80 );
+            state, signRem, rem.v64 | rem.v0 ? expB + 32 : 0, rem.v64, rem.v0, 80 );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
    goto uiZ;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    uiZ64 = defaultNaNExtF80UI64;
    uiZ0  = defaultNaNExtF80UI0;
    goto uiZ;
@@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
- extF80_roundToInt( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+ extF80_roundToInt( struct softfloat_state *state, extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64, signUI64;
@@ -80,7 +80,7 @@ extFloat80_t
    if ( 0x403E <= exp ) {
        if ( exp == 0x7FFF ) {
            if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
-                uiZ = softfloat_propagateNaNExtF80UI( uiA64, sigA, 0, 0 );
+                uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, sigA, 0, 0 );
                uiZ64 = uiZ.v64;
                sigZ  = uiZ.v0;
                goto uiZ;
@@ -93,7 +93,7 @@ extFloat80_t
        goto uiZ;
    }
    if ( exp <= 0x3FFE ) {
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
        switch ( roundingMode ) {
         case softfloat_round_near_even:
            if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break;
@@ -145,7 +145,7 @@ extFloat80_t
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) sigZ |= lastBitMask;
 #endif
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
    }
 uiZ:
    uZ.s.signExp = uiZ64;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_sqrt( extFloat80_t a )
+extFloat80_t extF80_sqrt( struct softfloat_state *state, extFloat80_t a )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -74,7 +74,7 @@ extFloat80_t extF80_sqrt( extFloat80_t a )
    *------------------------------------------------------------------------*/
    if ( expA == 0x7FFF ) {
        if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
-            uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, 0, 0 );
+            uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, 0, 0 );
            uiZ64 = uiZ.v64;
            uiZ0  = uiZ.v0;
            goto uiZ;
@@ -155,11 +155,11 @@ extFloat80_t extF80_sqrt( extFloat80_t a )
    }
    return
        softfloat_roundPackToExtF80(
-            0, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+            state, 0, expZ, sigZ, sigZExtra, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    uiZ64 = defaultNaNExtF80UI64;
    uiZ0  = defaultNaNExtF80UI0;
    goto uiZ;
@@ -41,7 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_sub( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -54,7 +54,7 @@ extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
 #if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
    extFloat80_t
        (*magsFuncPtr)(
-            uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+            struct softfloat_state *, uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
 #endif

    uA.f = a;
@@ -67,14 +67,14 @@ extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
    signB = signExtF80UI64( uiB64 );
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
    if ( signA == signB ) {
-        return softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+        return softfloat_subMagsExtF80( state, uiA64, uiA0, uiB64, uiB0, signA );
    } else {
-        return softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+        return softfloat_addMagsExtF80( state, uiA64, uiA0, uiB64, uiB0, signA );
    }
 #else
    magsFuncPtr =
        (signA == signB) ? softfloat_subMagsExtF80 : softfloat_addMagsExtF80;
-    return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+    return (*magsFuncPtr)( state, uiA64, uiA0, uiB64, uiB0, signA );
 #endif

 }
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-float128_t extF80_to_f128( extFloat80_t a )
+float128_t extF80_to_f128( struct softfloat_state *state, extFloat80_t a )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -61,7 +61,7 @@ float128_t extF80_to_f128( extFloat80_t a )
    exp = expExtF80UI64( uiA64 );
    frac = uiA0 & UINT64_C( 0x7FFFFFFFFFFFFFFF );
    if ( (exp == 0x7FFF) && frac ) {
-        softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+        softfloat_extF80UIToCommonNaN( state, uiA64, uiA0, &commonNaN );
        uiZ = softfloat_commonNaNToF128UI( &commonNaN );
    } else {
        sign = signExtF80UI64( uiA64 );
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-float32_t extF80_to_f32( extFloat80_t a )
+float32_t extF80_to_f32( struct softfloat_state *state, extFloat80_t a )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -66,7 +66,7 @@ float32_t extF80_to_f32( extFloat80_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0x7FFF ) {
        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
-            softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            softfloat_extF80UIToCommonNaN( state, uiA64, uiA0, &commonNaN );
            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
        } else {
            uiZ = packToF32UI( sign, 0xFF, 0 );
@@ -86,7 +86,7 @@ float32_t extF80_to_f32( extFloat80_t a )
    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
        if ( exp < -0x1000 ) exp = -0x1000;
    }
-    return softfloat_roundPackToF32( sign, exp, sig32 );
+    return softfloat_roundPackToF32( state, sign, exp, sig32 );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 uiZ:
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-float64_t extF80_to_f64( extFloat80_t a )
+float64_t extF80_to_f64( struct softfloat_state *state, extFloat80_t a )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -72,7 +72,7 @@ float64_t extF80_to_f64( extFloat80_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0x7FFF ) {
        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
-            softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            softfloat_extF80UIToCommonNaN( state, uiA64, uiA0, &commonNaN );
            uiZ = softfloat_commonNaNToF64UI( &commonNaN );
        } else {
            uiZ = packToF64UI( sign, 0x7FF, 0 );
@@ -86,7 +86,7 @@ float64_t extF80_to_f64( extFloat80_t a )
    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
        if ( exp < -0x1000 ) exp = -0x1000;
    }
-    return softfloat_roundPackToF64( sign, exp, sig );
+    return softfloat_roundPackToF64( state, sign, exp, sig );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 uiZ:
@@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t
- extF80_to_i32( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+ extF80_to_i32( struct softfloat_state *state, extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -68,7 +68,7 @@ int_fast32_t
 #elif (i32_fromNaN == i32_fromNegOverflow)
        sign = 1;
 #else
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        return i32_fromNaN;
 #endif
    }
@@ -78,7 +78,7 @@ int_fast32_t
    shiftDist = 0x4032 - exp;
    if ( shiftDist <= 0 ) shiftDist = 1;
    sig = softfloat_shiftRightJam64( sig, shiftDist );
-    return softfloat_roundToI32( sign, sig, roundingMode, exact );
+    return softfloat_roundToI32( state, sign, sig, roundingMode, exact );

 }

@@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
- extF80_to_i64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+ extF80_to_i64( struct softfloat_state *state, extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -68,7 +68,7 @@ int_fast64_t
        /*--------------------------------------------------------------------
        *--------------------------------------------------------------------*/
        if ( shiftDist ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
+            softfloat_raiseFlags( state, softfloat_flag_invalid );
            return
                (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
                    ? i64_fromNaN
@@ -84,7 +84,7 @@ int_fast64_t
        sig = sig64Extra.v;
        sigExtra = sig64Extra.extra;
    }
-    return softfloat_roundToI64( sign, sig, sigExtra, roundingMode, exact );
+    return softfloat_roundToI64( state, sign, sig, sigExtra, roundingMode, exact );

 }

@@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 uint_fast64_t
- extF80_to_ui64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+ extF80_to_ui64( struct softfloat_state *state, extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -65,7 +65,7 @@ uint_fast64_t
    *------------------------------------------------------------------------*/
    shiftDist = 0x403E - exp;
    if ( shiftDist < 0 ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        return
            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
                ? ui64_fromNaN
@@ -79,7 +79,7 @@ uint_fast64_t
        sig = sig64Extra.v;
        sigExtra = sig64Extra.extra;
    }
-    return softfloat_roundToUI64( sign, sig, sigExtra, roundingMode, exact );
+    return softfloat_roundToUI64( state, sign, sig, sigExtra, roundingMode, exact );

 }

@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f128_to_extF80( float128_t a )
+extFloat80_t f128_to_extF80( struct softfloat_state *state, float128_t a )
 {
    union ui128_f128 uA;
    uint_fast64_t uiA64, uiA0;
@@ -70,7 +70,7 @@ extFloat80_t f128_to_extF80( float128_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0x7FFF ) {
        if ( frac64 | frac0 ) {
-            softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            softfloat_f128UIToCommonNaN( state, uiA64, uiA0, &commonNaN );
            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
            uiZ64 = uiZ.v64;
            uiZ0  = uiZ.v0;
@@ -98,7 +98,7 @@ extFloat80_t f128_to_extF80( float128_t a )
    sig128 =
        softfloat_shortShiftLeft128(
            frac64 | UINT64_C( 0x0001000000000000 ), frac0, 15 );
-    return softfloat_roundPackToExtF80( sign, exp, sig128.v64, sig128.v0, 80 );
+    return softfloat_roundPackToExtF80( state, sign, exp, sig128.v64, sig128.v0, 80 );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 uiZ:
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f32_to_extF80( float32_t a )
+extFloat80_t f32_to_extF80( struct softfloat_state *state, float32_t a )
 {
    union ui32_f32 uA;
    uint_fast32_t uiA;
@@ -67,7 +67,7 @@ extFloat80_t f32_to_extF80( float32_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0xFF ) {
        if ( frac ) {
-            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            softfloat_f32UIToCommonNaN( state, uiA, &commonNaN );
            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
            uiZ64 = uiZ.v64;
            uiZ0  = uiZ.v0;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f64_to_extF80( float64_t a )
+extFloat80_t f64_to_extF80( struct softfloat_state *state, float64_t a )
 {
    union ui64_f64 uA;
    uint_fast64_t uiA;
@@ -67,7 +67,7 @@ extFloat80_t f64_to_extF80( float64_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0x7FF ) {
        if ( frac ) {
-            softfloat_f64UIToCommonNaN( uiA, &commonNaN );
+            softfloat_f64UIToCommonNaN( state, uiA, &commonNaN );
            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
            uiZ64 = uiZ.v64;
            uiZ0  = uiZ.v0;
@@ -63,19 +63,19 @@ uint_fast32_t softfloat_roundToUI32( bool, uint_fast64_t, uint_fast8_t, bool );
 #ifdef SOFTFLOAT_FAST_INT64
 uint_fast64_t
 softfloat_roundToUI64(
-     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+     struct softfloat_state *, bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
 uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif

 FEXCORE_PRESERVE_ALL_ATTR
-int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool );
+int_fast32_t softfloat_roundToI32( struct softfloat_state *, bool, uint_fast64_t, uint_fast8_t, bool );

 #ifdef SOFTFLOAT_FAST_INT64
 FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
 softfloat_roundToI64(
-     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+     struct softfloat_state *, bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
 int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif
@@ -115,7 +115,7 @@ FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );

 FEXCORE_PRESERVE_ALL_ATTR
-float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );
+float32_t softfloat_roundPackToF32( struct softfloat_state *, bool, int_fast16_t, uint_fast32_t );
 float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );

 float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t );
@@ -138,7 +138,7 @@ FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );

 FEXCORE_PRESERVE_ALL_ATTR
-float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );
+float64_t softfloat_roundPackToF64( struct softfloat_state *, bool, int_fast16_t, uint_fast64_t );
 float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );

 float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool );
@@ -167,18 +167,18 @@ struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t );
 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
 softfloat_roundPackToExtF80(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+     struct softfloat_state *, bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
 softfloat_normRoundPackToExtF80(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+     struct softfloat_state *, bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );

 extFloat80_t
 softfloat_addMagsExtF80(
-     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+     struct softfloat_state *, uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
 extFloat80_t
 softfloat_subMagsExtF80(
-     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+     struct softfloat_state *, uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );

 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 extFloat80_t
 softfloat_addMagsExtF80(
+     struct softfloat_state *state,
     uint_fast16_t uiA64,
     uint_fast64_t uiA0,
     uint_fast16_t uiB64,
@@ -140,11 +141,11 @@ extFloat80_t
 roundAndPack:
    return
        softfloat_roundPackToExtF80(
-            signZ, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+            state, signZ, expZ, sigZ, sigZExtra, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
 uiZ:
@@ -49,11 +49,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 void
 softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+     struct softfloat_state *state, uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
 {

    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
    }
    zPtr->sign = uiA64>>15;
    zPtr->v64  = uiA0<<1;
@@ -50,12 +50,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 void
 softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+     struct softfloat_state *state, uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
 {
    struct uint128 NaNSig;

    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
    }
    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
    zPtr->sign = uiA64>>63;
@@ -46,11 +46,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | exception is raised.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
+void softfloat_f32UIToCommonNaN( struct softfloat_state *state, uint_fast32_t uiA, struct commonNaN *zPtr )
 {

    if ( softfloat_isSigNaNF32UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
    }
    zPtr->sign = uiA>>31;
    zPtr->v64  = (uint_fast64_t) uiA<<41;
@@ -46,11 +46,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | exception is raised.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
+void softfloat_f64UIToCommonNaN( struct softfloat_state *state, uint_fast64_t uiA, struct commonNaN *zPtr )
 {

    if ( softfloat_isSigNaNF64UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
    }
    zPtr->sign = uiA>>63;
    zPtr->v64  = uiA<<12;
@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
 softfloat_normRoundPackToExtF80(
+     struct softfloat_state *state,
     bool sign,
     int_fast32_t exp,
     uint_fast64_t sig,
@@ -66,7 +67,7 @@ extFloat80_t
    }
    return
        softfloat_roundPackToExtF80(
-            sign, exp, sig, sigExtra, roundingPrecision );
+            state, sign, exp, sig, sigExtra, roundingPrecision );

 }

@@ -53,6 +53,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
 softfloat_propagateNaNExtF80UI(
+     struct softfloat_state *state,
     uint_fast16_t uiA64,
     uint_fast64_t uiA0,
     uint_fast16_t uiB64,
@@ -76,7 +77,7 @@ struct uint128
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    if ( isSigNaNA | isSigNaNB ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        if ( isSigNaNA ) {
            if ( isSigNaNB ) goto returnLargerMag;
            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto returnB;
@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
 softfloat_roundPackToExtF80(
+     struct softfloat_state *state,
     bool sign,
     int_fast32_t exp,
     uint_fast64_t sig,
@@ -59,7 +60,7 @@ extFloat80_t

    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
-    roundingMode = softfloat_roundingMode;
+    roundingMode = state->roundingMode;
    roundNearEven = (roundingMode == softfloat_round_near_even);
    if ( roundingPrecision == 80 ) goto precision80;
    if ( roundingPrecision == 64 ) {
@@ -87,15 +88,15 @@ extFloat80_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            isTiny =
-                   (softfloat_detectTininess
+                   (state->detectTininess
                        == softfloat_tininess_beforeRounding)
                || (exp < 0)
                || (sig <= (uint64_t) (sig + roundIncrement));
            sig = softfloat_shiftRightJam64( sig, 1 - exp );
            roundBits = sig & roundMask;
            if ( roundBits ) {
-                if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow );
-                softfloat_exceptionFlags |= softfloat_flag_inexact;
+                if ( isTiny ) softfloat_raiseFlags( state, softfloat_flag_underflow );
+                state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
                if ( roundingMode == softfloat_round_odd ) {
                    sig |= roundMask + 1;
@@ -121,7 +122,7 @@ extFloat80_t
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    if ( roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
+        state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) {
            sig = (sig & ~roundMask) | (roundMask + 1);
@@ -157,7 +158,7 @@ extFloat80_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            isTiny =
-                   (softfloat_detectTininess
+                   (state->detectTininess
                        == softfloat_tininess_beforeRounding)
                || (exp < 0)
                || ! doIncrement
@@ -168,8 +169,8 @@ extFloat80_t
            sig = sig64Extra.v;
            sigExtra = sig64Extra.extra;
            if ( sigExtra ) {
-                if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow );
-                softfloat_exceptionFlags |= softfloat_flag_inexact;
+                if ( isTiny ) softfloat_raiseFlags( state, softfloat_flag_underflow );
+                state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
                if ( roundingMode == softfloat_round_odd ) {
                    sig |= 1;
@@ -207,7 +208,7 @@ extFloat80_t
            roundMask = 0;
 overflow:
            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
+                state, softfloat_flag_overflow | softfloat_flag_inexact );
            if (
                   roundNearEven
                || (roundingMode == softfloat_round_near_maxMag)
@@ -226,7 +227,7 @@ extFloat80_t
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    if ( sigExtra ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
+        state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) {
            sig |= 1;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 float32_t
- softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )
+ softfloat_roundPackToF32( struct softfloat_state *state, bool sign, int_fast16_t exp, uint_fast32_t sig )
 {
    uint_fast8_t roundingMode;
    bool roundNearEven;
@@ -53,7 +53,7 @@ float32_t

    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
-    roundingMode = softfloat_roundingMode;
+    roundingMode = state->roundingMode;
    roundNearEven = (roundingMode == softfloat_round_near_even);
    roundIncrement = 0x40;
    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
@@ -71,19 +71,19 @@ float32_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            isTiny =
-                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
+                (state->detectTininess == softfloat_tininess_beforeRounding)
                    || (exp < -1) || (sig + roundIncrement < 0x80000000);
            sig = softfloat_shiftRightJam32( sig, -exp );
            exp = 0;
            roundBits = sig & 0x7F;
            if ( isTiny && roundBits ) {
-                softfloat_raiseFlags( softfloat_flag_underflow );
+                softfloat_raiseFlags( state, softfloat_flag_underflow );
            }
        } else if ( (0xFD < exp) || (0x80000000 <= sig + roundIncrement) ) {
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
+                state, softfloat_flag_overflow | softfloat_flag_inexact );
            uiZ = packToF32UI( sign, 0xFF, 0 ) - ! roundIncrement;
            goto uiZ;
        }
@@ -92,7 +92,7 @@ float32_t
    *------------------------------------------------------------------------*/
    sig = (sig + roundIncrement)>>7;
    if ( roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
+        state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) {
            sig |= 1;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 float64_t
- softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )
+ softfloat_roundPackToF64( struct softfloat_state *state, bool sign, int_fast16_t exp, uint_fast64_t sig )
 {
    uint_fast8_t roundingMode;
    bool roundNearEven;
@@ -53,7 +53,7 @@ float64_t

    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
-    roundingMode = softfloat_roundingMode;
+    roundingMode = state->roundingMode;
    roundNearEven = (roundingMode == softfloat_round_near_even);
    roundIncrement = 0x200;
    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
@@ -71,14 +71,14 @@ float64_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            isTiny =
-                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
+                (state->detectTininess == softfloat_tininess_beforeRounding)
                    || (exp < -1)
                    || (sig + roundIncrement < UINT64_C( 0x8000000000000000 ));
            sig = softfloat_shiftRightJam64( sig, -exp );
            exp = 0;
            roundBits = sig & 0x3FF;
            if ( isTiny && roundBits ) {
-                softfloat_raiseFlags( softfloat_flag_underflow );
+                softfloat_raiseFlags( state, softfloat_flag_underflow );
            }
        } else if (
            (0x7FD < exp)
@@ -87,7 +87,7 @@ float64_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
+                state, softfloat_flag_overflow | softfloat_flag_inexact );
            uiZ = packToF64UI( sign, 0x7FF, 0 ) - ! roundIncrement;
            goto uiZ;
        }
@@ -96,7 +96,7 @@ float64_t
    *------------------------------------------------------------------------*/
    sig = (sig + roundIncrement)>>10;
    if ( roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
+        state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) {
            sig |= 1;
@@ -44,7 +44,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t
 softfloat_roundToI32(
-     bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact )
+     struct softfloat_state *state, bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact )
 {
    uint_fast16_t roundIncrement, roundBits;
    uint_fast32_t sig32;
@@ -86,13 +86,13 @@ int_fast32_t
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) z |= 1;
 #endif
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
    }
    return z;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    return sign ? i32_fromNegOverflow : i32_fromPosOverflow;

 }
@@ -44,6 +44,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
 softfloat_roundToI64(
+     struct softfloat_state *state,
     bool sign,
     uint_fast64_t sig,
     uint_fast64_t sigExtra,
@@ -89,13 +90,13 @@ int_fast64_t
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) z |= 1;
 #endif
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
    }
    return z;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    return sign ? i64_fromNegOverflow : i64_fromPosOverflow;

 }
@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 uint_fast64_t
 softfloat_roundToUI64(
+     struct softfloat_state *state,
     bool sign,
     uint_fast64_t sig,
     uint_fast64_t sigExtra,
@@ -84,13 +85,13 @@ uint_fast64_t
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) sig |= 1;
 #endif
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
    }
    return sig;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;

 }
@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 extFloat80_t
 softfloat_subMagsExtF80(
+     struct softfloat_state *state,
     uint_fast16_t uiA64,
     uint_fast64_t uiA0,
     uint_fast16_t uiB64,
@@ -77,7 +78,7 @@ extFloat80_t
        if ( (sigA | sigB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
            goto propagateNaN;
        }
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        uiZ64 = defaultNaNExtF80UI64;
        uiZ0  = defaultNaNExtF80UI0;
        goto uiZ;
@@ -90,7 +91,7 @@ extFloat80_t
    if ( sigB < sigA ) goto aBigger;
    if ( sigA < sigB ) goto bBigger;
    uiZ64 =
-        packToExtF80UI64( (softfloat_roundingMode == softfloat_round_min), 0 );
+        packToExtF80UI64( (state->roundingMode == softfloat_round_min), 0 );
    uiZ0 = 0;
    goto uiZ;
    /*------------------------------------------------------------------------
@@ -142,11 +143,11 @@ extFloat80_t
 normRoundPack:
    return
        softfloat_normRoundPackToExtF80(
-            signZ, expZ, sig128.v64, sig128.v0, extF80_roundingPrecision );
+            state, signZ, expZ, sig128.v64, sig128.v0, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
 uiZ:
@@ -50,50 +50,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include <stdint.h>
 #include "softfloat_types.h"

-#ifndef THREAD_LOCAL
-#define THREAD_LOCAL
-#endif
-
-/*----------------------------------------------------------------------------
-| Software floating-point underflow tininess-detection mode.
-*----------------------------------------------------------------------------*/
-extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess;
-enum {
-    softfloat_tininess_beforeRounding = 0,
-    softfloat_tininess_afterRounding  = 1
-};
-
-/*----------------------------------------------------------------------------
-| Software floating-point rounding mode.  (Mode "odd" is supported only if
-| SoftFloat is compiled with macro 'SOFTFLOAT_ROUND_ODD' defined.)
-*----------------------------------------------------------------------------*/
-extern THREAD_LOCAL uint_fast8_t softfloat_roundingMode;
-enum {
-    softfloat_round_near_even   = 0,
-    softfloat_round_minMag      = 1,
-    softfloat_round_min         = 2,
-    softfloat_round_max         = 3,
-    softfloat_round_near_maxMag = 4,
-    softfloat_round_odd         = 6
-};
-
-/*----------------------------------------------------------------------------
-| Software floating-point exception flags.
-*----------------------------------------------------------------------------*/
-extern THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags;
-enum {
-    softfloat_flag_inexact   =  1,
-    softfloat_flag_underflow =  2,
-    softfloat_flag_overflow  =  4,
-    softfloat_flag_infinite  =  8,
-    softfloat_flag_invalid   = 16
-};
-
 /*----------------------------------------------------------------------------
 | Routine to raise any or all of the software floating-point exception flags.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_raiseFlags( uint_fast8_t );
+void softfloat_raiseFlags( struct softfloat_state *, uint_fast8_t );

 /*----------------------------------------------------------------------------
 | Integer-to-floating-point conversion routines.
@@ -187,7 +148,7 @@ float16_t f32_to_f16( float32_t );
 float64_t f32_to_f64( float32_t );
 #ifdef SOFTFLOAT_FAST_INT64
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f32_to_extF80( float32_t );
+extFloat80_t f32_to_extF80( struct softfloat_state *, float32_t );
 float128_t f32_to_f128( float32_t );
 #endif
 void f32_to_extF80M( float32_t, extFloat80_t * );
@@ -223,7 +184,7 @@ float16_t f64_to_f16( float64_t );
 float32_t f64_to_f32( float64_t );
 #ifdef SOFTFLOAT_FAST_INT64
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f64_to_extF80( float64_t );
+extFloat80_t f64_to_extF80( struct softfloat_state *, float64_t );
 float128_t f64_to_f128( float64_t );
 #endif
 void f64_to_extF80M( float64_t, extFloat80_t * );
@@ -244,53 +205,47 @@ bool f64_le_quiet( float64_t, float64_t );
 bool f64_lt_quiet( float64_t, float64_t );
 bool f64_isSignalingNaN( float64_t );

-/*----------------------------------------------------------------------------
-| Rounding precision for 80-bit extended double-precision floating-point.
-| Valid values are 32, 64, and 80.
-*----------------------------------------------------------------------------*/
-extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision;
-
 /*----------------------------------------------------------------------------
 | 80-bit extended double-precision floating-point operations.
 *----------------------------------------------------------------------------*/
 #ifdef SOFTFLOAT_FAST_INT64
 uint_fast32_t extF80_to_ui32( extFloat80_t, uint_fast8_t, bool );
 FEXCORE_PRESERVE_ALL_ATTR
-uint_fast64_t extF80_to_ui64( extFloat80_t, uint_fast8_t, bool );
+uint_fast64_t extF80_to_ui64( struct softfloat_state *, extFloat80_t, uint_fast8_t, bool );
 FEXCORE_PRESERVE_ALL_ATTR
-int_fast32_t extF80_to_i32( extFloat80_t, uint_fast8_t, bool );
+int_fast32_t extF80_to_i32( struct softfloat_state *, extFloat80_t, uint_fast8_t, bool );
 FEXCORE_PRESERVE_ALL_ATTR
-int_fast64_t extF80_to_i64( extFloat80_t, uint_fast8_t, bool );
+int_fast64_t extF80_to_i64( struct softfloat_state *, extFloat80_t, uint_fast8_t, bool );
 uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t, bool );
 uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t, bool );
 int_fast32_t extF80_to_i32_r_minMag( extFloat80_t, bool );
 int_fast64_t extF80_to_i64_r_minMag( extFloat80_t, bool );
 float16_t extF80_to_f16( extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-float32_t extF80_to_f32( extFloat80_t );
+float32_t extF80_to_f32( struct softfloat_state *, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-float64_t extF80_to_f64( extFloat80_t );
+float64_t extF80_to_f64( struct softfloat_state *, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-float128_t extF80_to_f128( extFloat80_t );
+float128_t extF80_to_f128( struct softfloat_state *, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_roundToInt( extFloat80_t, uint_fast8_t, bool );
+extFloat80_t extF80_roundToInt( struct softfloat_state *, extFloat80_t, uint_fast8_t, bool );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_add( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_add( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_sub( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_sub( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_mul( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_mul( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_div( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_div( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_rem( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_rem( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_sqrt( extFloat80_t );
+extFloat80_t extF80_sqrt( struct softfloat_state *, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-bool extF80_eq( extFloat80_t, extFloat80_t );
+bool extF80_eq( struct softfloat_state *, extFloat80_t, extFloat80_t );
 bool extF80_le( extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-bool extF80_lt( extFloat80_t, extFloat80_t );
+bool extF80_lt( struct softfloat_state *, extFloat80_t, extFloat80_t );
 bool extF80_eq_signaling( extFloat80_t, extFloat80_t );
 bool extF80_le_quiet( extFloat80_t, extFloat80_t );
 bool extF80_lt_quiet( extFloat80_t, extFloat80_t );
@@ -341,7 +296,7 @@ float16_t f128_to_f16( float128_t );
 float32_t f128_to_f32( float128_t );
 float64_t f128_to_f64( float128_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f128_to_extF80( float128_t );
+extFloat80_t f128_to_extF80( struct softfloat_state *, float128_t );
 float128_t f128_roundToInt( float128_t, uint_fast8_t, bool );
 float128_t f128_add( float128_t, float128_t );
 float128_t f128_sub( float128_t, float128_t );
@@ -44,10 +44,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | should be simply `softfloat_exceptionFlags |= flags;'.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_raiseFlags( uint_fast8_t flags )
+void softfloat_raiseFlags( struct softfloat_state *state, uint_fast8_t flags )
 {

-    softfloat_exceptionFlags |= flags;
+    state->exceptionFlags |= flags;

 }

@@ -1,52 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
-California.  All Rights Reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-#ifndef THREAD_LOCAL
-#define THREAD_LOCAL
-#endif
-
-THREAD_LOCAL uint_fast8_t softfloat_roundingMode = softfloat_round_near_even;
-THREAD_LOCAL uint_fast8_t softfloat_detectTininess = init_detectTininess;
-THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags = 0;
-
-THREAD_LOCAL uint_fast8_t extF80_roundingPrecision = 80;
-
@@ -77,5 +77,50 @@ struct extFloat80M { uint16_t signExp; uint64_t signif; };
 *----------------------------------------------------------------------------*/
 typedef struct extFloat80M extFloat80_t;

+enum {
+    softfloat_tininess_beforeRounding = 0,
+    softfloat_tininess_afterRounding  = 1
+};
+
+enum {
+    softfloat_round_near_even   = 0,
+    softfloat_round_minMag      = 1,
+    softfloat_round_min         = 2,
+    softfloat_round_max         = 3,
+    softfloat_round_near_maxMag = 4,
+    softfloat_round_odd         = 6
+};
+
+enum {
+    softfloat_flag_inexact   =  1,
+    softfloat_flag_underflow =  2,
+    softfloat_flag_overflow  =  4,
+    softfloat_flag_infinite  =  8,
+    softfloat_flag_invalid   = 16
+};
+
+struct softfloat_state {
+/*----------------------------------------------------------------------------
+| Software floating-point underflow tininess-detection mode.
+*----------------------------------------------------------------------------*/
+uint8_t detectTininess; /* = init_detectTininess */
+/*----------------------------------------------------------------------------
+| Software floating-point rounding mode.  (Mode "odd" is supported only if
+| SoftFloat is compiled with macro 'SOFTFLOAT_ROUND_ODD' defined.)
+*----------------------------------------------------------------------------*/
+uint8_t roundingMode; /* = softfloat_round_near_even */
+
+/*----------------------------------------------------------------------------
+| Software floating-point exception flags.
+*----------------------------------------------------------------------------*/
+uint8_t exceptionFlags; /* = 0 */
+
+/*----------------------------------------------------------------------------
+| Rounding precision for 80-bit extended double-precision floating-point.
+| Valid values are 32, 64, and 80.
+*----------------------------------------------------------------------------*/
+uint8_t roundingPrecision; /* = 80 */
+};
+
 #endif

@@ -136,7 +136,7 @@ uint_fast16_t
 | exception is raised.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+void softfloat_f32UIToCommonNaN( struct softfloat_state *, uint_fast32_t uiA, struct commonNaN *zPtr );

 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
@@ -173,7 +173,7 @@ uint_fast32_t
 | exception is raised.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+void softfloat_f64UIToCommonNaN( struct softfloat_state *, uint_fast64_t uiA, struct commonNaN *zPtr );

 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
@@ -222,7 +222,7 @@ uint_fast64_t
 FEXCORE_PRESERVE_ALL_ATTR
 void
 softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+     struct softfloat_state *, uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );

 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -244,6 +244,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
 softfloat_propagateNaNExtF80UI(
+     struct softfloat_state *,
     uint_fast16_t uiA64,
     uint_fast64_t uiA0,
     uint_fast16_t uiB64,
@@ -274,7 +275,7 @@ struct uint128
 FEXCORE_PRESERVE_ALL_ATTR
 void
 softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+     struct softfloat_state *, uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );

 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -45,13 +45,13 @@ struct FEX_PACKED X80SoftFloat {
  uint16_t Exponent    : 15;
  uint16_t Sign        : 1;

-  X80SoftFloat() { memset(this, 0, sizeof(*this)); }
+  X80SoftFloat() {
+    memset(this, 0, sizeof(*this));
+  }
  X80SoftFloat(uint16_t _Sign, uint16_t _Exponent, uint64_t _Significand)
    : Significand {_Significand}
    , Exponent {_Exponent}
-    , Sign {_Sign}
-    {
-  }
+    , Sign {_Sign} {}

  fextl::string str() const {
    fextl::ostringstream string;
@@ -63,99 +63,90 @@ struct FEX_PACKED X80SoftFloat {
  }

  // Ops
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FADD(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FADD(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[rhs]; # st1
    fldt %[lhs]; # st0
    faddp;
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    return extF80_add(lhs, rhs);
+    return extF80_add(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FSUB(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSUB(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[rhs]; # st1
    fldt %[lhs]; # st0
    fsubp;
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    return extF80_sub(lhs, rhs);
+    return extF80_sub(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FMUL(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FMUL(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[rhs]; # st1
    fldt %[lhs]; # st0
    fmulp;
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    return extF80_mul(lhs, rhs);
+    return extF80_mul(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FDIV(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FDIV(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[rhs]; # st1
    fldt %[lhs]; # st0
    fdivp;
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    return extF80_div(lhs, rhs);
+    return extF80_div(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FREM(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #if defined(DEBUG_X86_FLOAT)
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[rhs]; # st1
    fldt %[lhs]; # st0
@@ -163,22 +154,20 @@ struct FEX_PACKED X80SoftFloat {
    fstpt %[result];
    ffreep %%st(0);
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    return extF80_rem(lhs, rhs);
+    return extF80_rem(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FREM1(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM1(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #if defined(DEBUG_X86_FLOAT)
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[rhs]; # st1
    fldt %[lhs]; # st0
@@ -186,41 +175,37 @@ struct FEX_PACKED X80SoftFloat {
    fstpt %[result];
    ffreep %%st(0);
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    return extF80_rem(lhs, rhs);
+    return extF80_rem(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FRNDINT(X80SoftFloat const &lhs) {
-    return extF80_roundToInt(lhs, softfloat_roundingMode, false);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(softfloat_state* state, const X80SoftFloat& lhs) {
+    return extF80_roundToInt(state, lhs, state->roundingMode, false);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FRNDINT(X80SoftFloat const &lhs, uint_fast8_t RoundMode) {
-    return extF80_roundToInt(lhs, RoundMode, false);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(softfloat_state* state, const X80SoftFloat& lhs, uint_fast8_t RoundMode) {
+    return extF80_roundToInt(state, lhs, RoundMode, false);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FXTRACT_SIG(X80SoftFloat const &lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FXTRACT_SIG(const X80SoftFloat& lhs) {
 #if defined(DEBUG_X86_FLOAT)
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[lhs]; # st0
    fxtract;
    fstpt %[result];
    ffreep %%st(0);
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs)
+        : "st", "st(1)");

    return Result;
 #else
@@ -231,20 +216,19 @@ struct FEX_PACKED X80SoftFloat {
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FXTRACT_EXP(X80SoftFloat const &lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FXTRACT_EXP(const X80SoftFloat& lhs) {
 #if defined(DEBUG_X86_FLOAT)
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[lhs]; # st0
    fxtract;
    ffreep %%st(0);
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs)
+        : "st", "st(1)");

    return Result;
 #else
@@ -253,19 +237,18 @@ struct FEX_PACKED X80SoftFloat {
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static void FCMP(X80SoftFloat const &lhs, X80SoftFloat const &rhs, bool *eq, bool *lt, bool *nan) {
-    *eq = extF80_eq(lhs, rhs);
-    *lt = extF80_lt(lhs, rhs);
+  FEXCORE_PRESERVE_ALL_ATTR static void
+  FCMP(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs, bool* eq, bool* lt, bool* nan) {
+    *eq = extF80_eq(state, lhs, rhs);
+    *lt = extF80_lt(state, lhs, rhs);
    *nan = IsNan(lhs) || IsNan(rhs);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FSCALE(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSCALE(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
    WARN_ONCE_FMT("x87: Application used FSCALE which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[rhs]; # st1
    fldt %[lhs]; # st0
@@ -273,240 +256,223 @@ struct FEX_PACKED X80SoftFloat {
    fstpt %[result];
    ffreep %%st(0);
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    X80SoftFloat Int = FRNDINT(rhs, softfloat_round_minMag);
-    LIBRARY_PRECISION Src2_d = Int;
+    X80SoftFloat Int = FRNDINT(state, rhs, softfloat_round_minMag);
+    LIBRARY_PRECISION Src2_d = Int.ToFMax(state);
    Src2_d = exp2l(Src2_d);
-    X80SoftFloat Src2_X80 = Src2_d;
-    X80SoftFloat Result = extF80_mul(lhs, Src2_X80);
+    X80SoftFloat Src2_X80(state, Src2_d);
+    X80SoftFloat Result = extF80_mul(state, lhs, Src2_X80);
    return Result;
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat F2XM1(X80SoftFloat const &lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat F2XM1(softfloat_state* state, const X80SoftFloat& lhs) {
    WARN_ONCE_FMT("x87: Application used F2XM1 which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[lhs]; # st0
    f2xm1; # st0 = 2^st(0) - 1
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    : "st");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs)
+        : "st");

    return Result;
 #else
-    LIBRARY_PRECISION Src1_d = lhs;
+    LIBRARY_PRECISION Src1_d = lhs.ToFMax(state);
    LIBRARY_PRECISION Result = exp2l(Src1_d);
    Result -= 1.0;
-    return Result;
+    return X80SoftFloat(state, Result);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FYL2X(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FYL2X(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
    WARN_ONCE_FMT("x87: Application used FYL2X which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[rhs]; # st(1)
    fldt %[lhs]; # st(0)
    fyl2x; # st(1) * log2l(st(0))
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    LIBRARY_PRECISION Src1_d = lhs;
-    LIBRARY_PRECISION Src2_d = rhs;
+    LIBRARY_PRECISION Src1_d = lhs.ToFMax(state);
+    LIBRARY_PRECISION Src2_d = rhs.ToFMax(state);
    LIBRARY_PRECISION Tmp = Src2_d * log2l(Src1_d);
-    return Tmp;
+    return X80SoftFloat(state, Tmp);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FATAN(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FATAN(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
    WARN_ONCE_FMT("x87: Application used FATAN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[lhs];
    fldt %[rhs];
    fpatan;
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    , [rhs] "m" (rhs)
-    : "st", "st(1)");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs), [rhs] "m"(rhs)
+        : "st", "st(1)");

    return Result;
 #else
-    LIBRARY_PRECISION Src1_d = lhs;
-    LIBRARY_PRECISION Src2_d = rhs;
+    LIBRARY_PRECISION Src1_d = lhs.ToFMax(state);
+    LIBRARY_PRECISION Src2_d = rhs.ToFMax(state);
    LIBRARY_PRECISION Tmp = atan2l(Src1_d, Src2_d);
-    return Tmp;
+    return X80SoftFloat(state, Tmp);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FTAN(X80SoftFloat const &lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FTAN(softfloat_state* state, const X80SoftFloat& lhs) {
    WARN_ONCE_FMT("x87: Application used FTAN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[lhs]; # st0
    fptan;
    ffreep %%st(0);
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    : "st");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs)
+        : "st");

    return Result;
 #else
-    LIBRARY_PRECISION Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs.ToFMax(state);
    Src_d = tanl(Src_d);
-    return Src_d;
+    return X80SoftFloat(state, Src_d);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FSIN(X80SoftFloat const &lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSIN(softfloat_state* state, const X80SoftFloat& lhs) {
    WARN_ONCE_FMT("x87: Application used FSIN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[lhs]; # st0
    fsin;
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    : "st");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs)
+        : "st");

    return Result;
 #else
-    LIBRARY_PRECISION Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs.ToFMax(state);
    Src_d = sinl(Src_d);
-    return Src_d;
+    return X80SoftFloat(state, Src_d);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FCOS(X80SoftFloat const &lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FCOS(softfloat_state* state, const X80SoftFloat& lhs) {
    WARN_ONCE_FMT("x87: Application used FCOS which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[lhs]; # st0
    fcos;
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    : "st");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs)
+        : "st");

    return Result;
 #else
-    LIBRARY_PRECISION Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs.ToFMax(state);
    Src_d = cosl(Src_d);
-    return Src_d;
+    return X80SoftFloat(state, Src_d);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat FSQRT(X80SoftFloat const &lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSQRT(softfloat_state* state, const X80SoftFloat& lhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
-    asm (R"(
+    asm(R"(
    fninit;
    fldt %[lhs]; # st0
    fsqrt;
    fstpt %[result];
    )"
-    : [result] "=m" (Result)
-    : [lhs] "m" (lhs)
-    : "st");
+        : [result] "=m"(Result)
+        : [lhs] "m"(lhs)
+        : "st");

    return Result;
 #else
-    return extF80_sqrt(lhs);
+    return extF80_sqrt(state, lhs);
 #endif
  }

-  operator float() const {
-    const float32_t Result = extF80_to_f32(*this);
+  float ToF32(softfloat_state* state) const {
+    const float32_t Result = extF80_to_f32(state, *this);
    return FEXCore::BitCast<float>(Result);
  }

-  operator double() const {
-    const float64_t Result = extF80_to_f64(*this);
+  double ToF64(softfloat_state* state) const {
+    const float64_t Result = extF80_to_f64(state, *this);
    return FEXCore::BitCast<double>(Result);
  }

-#ifndef _WIN32
-  operator BIGFLOAT() const {
+  LIBRARY_PRECISION ToFMax(softfloat_state* state) const {
+#ifdef _WIN32
+    return ToF64(state);
+#else
 #if BIGFLOATSIZE == 16
-    const float128_t Result = extF80_to_f128(*this);
+    const float128_t Result = extF80_to_f128(state, *this);
    return FEXCore::BitCast<BIGFLOAT>(Result);
 #else
-    BIGFLOAT result{};
+    BIGFLOAT result {};
    memcpy(&result, this, sizeof(result));
    return result;
 #endif
-  }
 #endif
+  }

-  operator int16_t() const {
-    auto rv = extF80_to_i32(*this, softfloat_roundingMode, false);
-    if (rv > INT16_MAX) {
-      return INT16_MAX;
-    } else if (rv < INT16_MIN) {
+  int16_t ToI16(softfloat_state* state) const {
+    auto rv = extF80_to_i32(state, *this, state->roundingMode, false);
+    if (rv > INT16_MAX || rv < INT16_MIN) {
+      ///< Indefinite value for 16-bit conversions.
      return INT16_MIN;
    } else {
      return rv;
    }
  }

-  operator int32_t() const {
-    return extF80_to_i32(*this, softfloat_roundingMode, false);
+  int32_t ToI32(softfloat_state* state) const {
+    return extF80_to_i32(state, *this, state->roundingMode, false);
  }

-  operator int64_t() const {
-    return extF80_to_i64(*this, softfloat_roundingMode, false);
+  int64_t ToI64(softfloat_state* state) const {
+    return extF80_to_i64(state, *this, state->roundingMode, false);
  }

-  operator uint64_t() const {
-    return extF80_to_ui64(*this, softfloat_roundingMode, false);
-  }
-
-  void operator=(const float rhs) {
-    *this = f32_to_extF80(FEXCore::BitCast<float32_t>(rhs));
-  }
-
-  void operator=(const double rhs) {
-    *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
+  uint64_t ToUI64(softfloat_state* state) const {
+    return extF80_to_ui64(state, *this, state->roundingMode, false);
  }

  void operator=(const int16_t rhs) {
@@ -537,18 +503,18 @@ struct FEX_PACKED X80SoftFloat {
    Sign = rhs.signExp >> 15;
  }

-  X80SoftFloat(const float rhs) {
-    *this = f32_to_extF80(FEXCore::BitCast<float32_t>(rhs));
+  X80SoftFloat(softfloat_state* state, const float rhs) {
+    *this = f32_to_extF80(state, FEXCore::BitCast<float32_t>(rhs));
  }

-  X80SoftFloat(const double rhs) {
-    *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
+  X80SoftFloat(softfloat_state* state, const double rhs) {
+    *this = f64_to_extF80(state, FEXCore::BitCast<float64_t>(rhs));
  }

 #ifndef _WIN32
-  X80SoftFloat(BIGFLOAT rhs) {
+  X80SoftFloat(softfloat_state* state, BIGFLOAT rhs) {
 #if BIGFLOATSIZE == 16
-    *this = f128_to_extF80(FEXCore::BitCast<float128_t>(rhs));
+    *this = f128_to_extF80(state, FEXCore::BitCast<float128_t>(rhs));
 #else
    *this = FEXCore::BitCast<long double>(rhs);
 #endif
@@ -570,19 +536,17 @@ struct FEX_PACKED X80SoftFloat {
  }

  operator extFloat80_t() const {
-    extFloat80_t Result{};
+    extFloat80_t Result {};
    Result.signif = Significand;
    Result.signExp = Exponent | (Sign << 15);
    return Result;
  }

-  static bool IsNan(X80SoftFloat const &lhs) {
-    return (lhs.Exponent == 0x7FFF) &&
-      (lhs.Significand & IntegerBit) &&
-      (lhs.Significand & Bottom62Significand);
+  static bool IsNan(const X80SoftFloat& lhs) {
+    return (lhs.Exponent == 0x7FFF) && (lhs.Significand & IntegerBit) && (lhs.Significand & Bottom62Significand);
  }

-  static bool SignBit(X80SoftFloat const &lhs) {
+  static bool SignBit(const X80SoftFloat& lhs) {
    return lhs.Sign;
  }

@@ -7,44 +7,51 @@
 #include <optional>

 namespace FEXCore::StrConv {
-  [[maybe_unused]] static bool Conv(std::string_view Value, bool *Result) {
-    *Result = std::strtoull(Value.data(), nullptr, 0);
-    return true;
-  }
-
-  [[maybe_unused]] static bool Conv(std::string_view Value, uint8_t *Result) {
-    *Result = std::strtoul(Value.data(), nullptr, 0);
-    return true;
-  }
-
-  [[maybe_unused]] static bool Conv(std::string_view Value, uint16_t *Result) {
-    *Result = std::strtoul(Value.data(), nullptr, 0);
-    return true;
-  }
-
-  [[maybe_unused]] static bool Conv(std::string_view Value, uint32_t *Result) {
-    *Result = std::strtoul(Value.data(), nullptr, 0);
-    return true;
-  }
-
-  [[maybe_unused]] static bool Conv(std::string_view Value, int32_t *Result) {
-    *Result = std::strtol(Value.data(), nullptr, 0);
-    return true;
-  }
-
-  [[maybe_unused]] static bool Conv(std::string_view Value, uint64_t *Result) {
-    *Result = std::strtoull(Value.data(), nullptr, 0);
-    return true;
-  }
-  template <typename T,
-    typename = std::enable_if<std::is_enum<T>::value, T>>
-  [[maybe_unused]] static bool Conv(std::string_view Value, T *Result) {
-    *Result = static_cast<T>(std::stoull(Value.data(), nullptr, 0));
-    return true;
-  }
-
-  [[maybe_unused]] static bool Conv(std::string_view Value, fextl::string *Result) {
-    *Result = Value;
-    return true;
-  }
+[[maybe_unused]]
+static bool Conv(std::string_view Value, bool* Result) {
+  *Result = std::strtoull(Value.data(), nullptr, 0);
+  return true;
 }
+
+[[maybe_unused]]
+static bool Conv(std::string_view Value, uint8_t* Result) {
+  *Result = std::strtoul(Value.data(), nullptr, 0);
+  return true;
+}
+
+[[maybe_unused]]
+static bool Conv(std::string_view Value, uint16_t* Result) {
+  *Result = std::strtoul(Value.data(), nullptr, 0);
+  return true;
+}
+
+[[maybe_unused]]
+static bool Conv(std::string_view Value, uint32_t* Result) {
+  *Result = std::strtoul(Value.data(), nullptr, 0);
+  return true;
+}
+
+[[maybe_unused]]
+static bool Conv(std::string_view Value, int32_t* Result) {
+  *Result = std::strtol(Value.data(), nullptr, 0);
+  return true;
+}
+
+[[maybe_unused]]
+static bool Conv(std::string_view Value, uint64_t* Result) {
+  *Result = std::strtoull(Value.data(), nullptr, 0);
+  return true;
+}
+template<typename T, typename = std::enable_if<std::is_enum<T>::value, T>>
+[[maybe_unused]]
+static bool Conv(std::string_view Value, T* Result) {
+  *Result = static_cast<T>(std::stoull(Value.data(), nullptr, 0));
+  return true;
+}
+
+[[maybe_unused]]
+static bool Conv(std::string_view Value, fextl::string* Result) {
+  *Result = Value;
+  return true;
+}
+} // namespace FEXCore::StrConv
@@ -29,7 +29,7 @@
 #include <utility>

 namespace FEXCore::Context {
-  class Context;
+class Context;
 }

 namespace FEXCore::Config {
@@ -40,490 +40,464 @@ namespace DefaultValues {
 #define OPT_STRARRAY(group, enum, json, default) OPT_STR(group, enum, json, default)
 #define OPT_STRENUM(group, enum, json, default) const uint64_t P(enum) = FEXCore::ToUnderlying(P(default));
 #include <FEXCore/Config/ConfigValues.inl>
+} // namespace DefaultValues
+
+enum Paths {
+  PATH_DATA_DIR = 0,
+  PATH_CONFIG_DIR_LOCAL,
+  PATH_CONFIG_DIR_GLOBAL,
+  PATH_CONFIG_FILE_LOCAL,
+  PATH_CONFIG_FILE_GLOBAL,
+  PATH_CONFIG_TELEMETRY_FOLDER,
+  PATH_LAST,
+};
+static std::array<fextl::string, Paths::PATH_LAST> Paths;
+
+void SetDataDirectory(const std::string_view Path) {
+  Paths[PATH_DATA_DIR] = Path;
 }

-  enum Paths {
-    PATH_DATA_DIR = 0,
-    PATH_CONFIG_DIR_LOCAL,
-    PATH_CONFIG_DIR_GLOBAL,
-    PATH_CONFIG_FILE_LOCAL,
-    PATH_CONFIG_FILE_GLOBAL,
-    PATH_CONFIG_TELEMETRY_FOLDER,
-    PATH_LAST,
-  };
-  static std::array<fextl::string, Paths::PATH_LAST> Paths;
+void SetConfigDirectory(const std::string_view Path, bool Global) {
+  Paths[PATH_CONFIG_DIR_LOCAL + Global] = Path;
+}

-  void SetDataDirectory(const std::string_view Path) {
-    Paths[PATH_DATA_DIR] = Path;
+void SetConfigFileLocation(const std::string_view Path, bool Global) {
+  Paths[PATH_CONFIG_FILE_LOCAL + Global] = Path;
+}
+
+const fextl::string& GetTelemetryDirectory() {
+  auto& Path = Paths[PATH_CONFIG_TELEMETRY_FOLDER];
+  if (Path.empty()) {
+    FEX_CONFIG_OPT(TelemetryDirectory, TELEMETRYDIRECTORY);
+    if (!TelemetryDirectory().empty()) {
+      Path = TelemetryDirectory;
+      Path += "/";
+    } else {
+      Path = Config::GetDataDirectory() + "Telemetry/";
+    }
  }

-  void SetConfigDirectory(const std::string_view Path, bool Global) {
-    Paths[PATH_CONFIG_DIR_LOCAL + Global] = Path;
+  return Path;
+}
+
+const fextl::string& GetDataDirectory() {
+  return Paths[PATH_DATA_DIR];
+}
+
+const fextl::string& GetConfigDirectory(bool Global) {
+  return Paths[PATH_CONFIG_DIR_LOCAL + Global];
+}
+
+const fextl::string& GetConfigFileLocation(bool Global) {
+  return Paths[PATH_CONFIG_FILE_LOCAL + Global];
+}
+
+fextl::string GetApplicationConfig(const std::string_view Program, bool Global) {
+  fextl::string ConfigFile = GetConfigDirectory(Global);
+
+  if (!Global && !FHU::Filesystem::Exists(ConfigFile) && !FHU::Filesystem::CreateDirectories(ConfigFile)) {
+    LogMan::Msg::DFmt("Couldn't create config directory: '{}'", ConfigFile);
+    // Let's go local in this case
+    return fextl::fmt::format("./{}.json", Program);
  }

-  void SetConfigFileLocation(const std::string_view Path, bool Global) {
-    Paths[PATH_CONFIG_FILE_LOCAL + Global] = Path;
+  ConfigFile += "AppConfig/";
+
+  // Attempt to create the local folder if it doesn't exist
+  if (!Global && !FHU::Filesystem::Exists(ConfigFile) && !FHU::Filesystem::CreateDirectories(ConfigFile)) {
+    // Let's go local in this case
+    return fextl::fmt::format("./{}.json", Program);
  }

-  fextl::string const& GetTelemetryDirectory() {
-    auto &Path = Paths[PATH_CONFIG_TELEMETRY_FOLDER];
-    if (Path.empty()) {
-      FEX_CONFIG_OPT(TelemetryDirectory, TELEMETRYDIRECTORY);
-      if (!TelemetryDirectory().empty()) {
-        Path = TelemetryDirectory;
-        Path += "/";
-      }
-      else {
-        Path = Config::GetDataDirectory() + "Telemetry/";
+  return fextl::fmt::format("{}{}.json", ConfigFile, Program);
+}
+
+void SetConfig(FEXCore::Context::Context* CTX, ConfigOption Option, uint64_t Config) {}
+
+void SetConfig(FEXCore::Context::Context* CTX, ConfigOption Option, const fextl::string& Config) {}
+
+uint64_t GetConfig(FEXCore::Context::Context* CTX, ConfigOption Option) {
+  return 0;
+}
+
+static fextl::map<FEXCore::Config::LayerType, fextl::unique_ptr<FEXCore::Config::Layer>> ConfigLayers;
+static FEXCore::Config::Layer* Meta {};
+
+constexpr std::array<FEXCore::Config::LayerType, 10> LoadOrder = {
+  FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN,      FEXCore::Config::LayerType::LAYER_MAIN,
+  FEXCore::Config::LayerType::LAYER_GLOBAL_STEAM_APP, FEXCore::Config::LayerType::LAYER_GLOBAL_APP,
+  FEXCore::Config::LayerType::LAYER_LOCAL_STEAM_APP,  FEXCore::Config::LayerType::LAYER_LOCAL_APP,
+  FEXCore::Config::LayerType::LAYER_ARGUMENTS,        FEXCore::Config::LayerType::LAYER_USER_OVERRIDE,
+  FEXCore::Config::LayerType::LAYER_ENVIRONMENT,      FEXCore::Config::LayerType::LAYER_TOP};
+
+Layer::Layer(const LayerType _Type)
+  : Type {_Type} {}
+
+Layer::~Layer() {}
+
+class MetaLayer final : public FEXCore::Config::Layer {
+public:
+  MetaLayer(const LayerType _Type)
+    : FEXCore::Config::Layer(_Type) {}
+  ~MetaLayer() {}
+  void Load();
+
+private:
+  void MergeConfigMap(const LayerOptions& Options);
+  void MergeEnvironmentVariables(const ConfigOption& Option, const LayerValue& Value);
+};
+
+void MetaLayer::Load() {
+  OptionMap.clear();
+
+  for (auto CurrentLayer = LoadOrder.begin(); CurrentLayer != LoadOrder.end(); ++CurrentLayer) {
+    auto it = ConfigLayers.find(*CurrentLayer);
+    if (it != ConfigLayers.end() && *CurrentLayer != Type) {
+      // Merge this layer's options to this layer
+      MergeConfigMap(it->second->GetOptionMap());
+    }
+  }
+}
+
+
+void MetaLayer::MergeEnvironmentVariables(const ConfigOption& Option, const LayerValue& Value) {
+  // Environment variables need a bit of additional work
+  // We want to merge the arrays rather than overwrite entirely
+  auto MetaEnvironment = OptionMap.find(Option);
+  if (MetaEnvironment == OptionMap.end()) {
+    // Doesn't exist, just insert
+    OptionMap.insert_or_assign(Option, Value);
+    return;
+  }
+
+  // If an environment variable exists in both current meta and in the incoming layer then the meta layer value is overwritten
+  fextl::unordered_map<fextl::string, fextl::string> LookupMap;
+  const auto AddToMap = [&LookupMap](const FEXCore::Config::LayerValue& Value) {
+    for (const auto& EnvVar : Value) {
+      const auto ItEq = EnvVar.find_first_of('=');
+      if (ItEq == fextl::string::npos) {
+        // Broken environment variable
+        // Skip
+        continue;
      }
+      auto Key = fextl::string(EnvVar.begin(), EnvVar.begin() + ItEq);
+      auto Value = fextl::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
+
+      // Add the key to the map, overwriting whatever previous value was there
+      LookupMap.insert_or_assign(std::move(Key), std::move(Value));
    }
-
-    return Path;
-  }
-
-  fextl::string const& GetDataDirectory() {
-    return Paths[PATH_DATA_DIR];
-  }
-
-  fextl::string const& GetConfigDirectory(bool Global) {
-    return Paths[PATH_CONFIG_DIR_LOCAL + Global];
-  }
-
-  fextl::string const& GetConfigFileLocation(bool Global) {
-    return Paths[PATH_CONFIG_FILE_LOCAL + Global];
-  }
-
-  fextl::string GetApplicationConfig(const std::string_view Program, bool Global) {
-    fextl::string ConfigFile = GetConfigDirectory(Global);
-
-    if (!Global &&
-        !FHU::Filesystem::Exists(ConfigFile) &&
-        !FHU::Filesystem::CreateDirectories(ConfigFile)) {
-      LogMan::Msg::DFmt("Couldn't create config directory: '{}'", ConfigFile);
-      // Let's go local in this case
-      return fextl::fmt::format("./{}.json", Program);
-    }
-
-    ConfigFile += "AppConfig/";
-
-    // Attempt to create the local folder if it doesn't exist
-    if (!Global &&
-        !FHU::Filesystem::Exists(ConfigFile) &&
-        !FHU::Filesystem::CreateDirectories(ConfigFile)) {
-      // Let's go local in this case
-      return fextl::fmt::format("./{}.json", Program);
-    }
-
-    return fextl::fmt::format("{}{}.json", ConfigFile, Program);
-  }
-
-  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
-  }
-
-  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, fextl::string const &Config) {
-  }
-
-  uint64_t GetConfig(FEXCore::Context::Context *CTX, ConfigOption Option) {
-    return 0;
-  }
-
-  static fextl::map<FEXCore::Config::LayerType, fextl::unique_ptr<FEXCore::Config::Layer>> ConfigLayers;
-  static FEXCore::Config::Layer *Meta{};
-
-  constexpr std::array<FEXCore::Config::LayerType, 10> LoadOrder = {
-    FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN,
-    FEXCore::Config::LayerType::LAYER_MAIN,
-    FEXCore::Config::LayerType::LAYER_GLOBAL_STEAM_APP,
-    FEXCore::Config::LayerType::LAYER_GLOBAL_APP,
-    FEXCore::Config::LayerType::LAYER_LOCAL_STEAM_APP,
-    FEXCore::Config::LayerType::LAYER_LOCAL_APP,
-    FEXCore::Config::LayerType::LAYER_ARGUMENTS,
-    FEXCore::Config::LayerType::LAYER_USER_OVERRIDE,
-    FEXCore::Config::LayerType::LAYER_ENVIRONMENT,
-    FEXCore::Config::LayerType::LAYER_TOP
  };

-  Layer::Layer(const LayerType _Type)
-    : Type {_Type} {
+  AddToMap(MetaEnvironment->second);
+  AddToMap(Value);
+
+  // Now with the two layers merged in the map
+  // Add all the values to the option
+  Erase(Option);
+  for (auto& Val : LookupMap) {
+    // Set will emplace multiple options in to its list
+    Set(Option, Val.first + "=" + Val.second);
  }
+}

-  Layer::~Layer() {
-  }
-
-  class MetaLayer final : public FEXCore::Config::Layer {
-  public:
-    MetaLayer(const LayerType _Type)
-      : FEXCore::Config::Layer (_Type) {
-    }
-    ~MetaLayer() {
-    }
-    void Load();
-
-  private:
-    void MergeConfigMap(const LayerOptions &Options);
-    void MergeEnvironmentVariables(ConfigOption const &Option, LayerValue const &Value);
-  };
-
-  void MetaLayer::Load() {
-    OptionMap.clear();
-
-    for (auto CurrentLayer = LoadOrder.begin(); CurrentLayer != LoadOrder.end(); ++CurrentLayer) {
-      auto it = ConfigLayers.find(*CurrentLayer);
-      if (it != ConfigLayers.end() && *CurrentLayer != Type) {
-        // Merge this layer's options to this layer
-        MergeConfigMap(it->second->GetOptionMap());
-      }
+void MetaLayer::MergeConfigMap(const LayerOptions& Options) {
+  // Insert this layer's options, overlaying previous options that exist here
+  for (auto& it : Options) {
+    if (it.first == FEXCore::Config::ConfigOption::CONFIG_ENV || it.first == FEXCore::Config::ConfigOption::CONFIG_HOSTENV) {
+      MergeEnvironmentVariables(it.first, it.second);
+    } else {
+      OptionMap.insert_or_assign(it.first, it.second);
    }
  }
+}

+void Initialize() {
+  AddLayer(fextl::make_unique<MetaLayer>(FEXCore::Config::LayerType::LAYER_TOP));
+  Meta = ConfigLayers.begin()->second.get();
+}

-  void MetaLayer::MergeEnvironmentVariables(ConfigOption const &Option, LayerValue const &Value) {
-    // Environment variables need a bit of additional work
-    // We want to merge the arrays rather than overwrite entirely
-    auto MetaEnvironment = OptionMap.find(Option);
-    if (MetaEnvironment == OptionMap.end()) {
-      // Doesn't exist, just insert
-      OptionMap.insert_or_assign(Option, Value);
-      return;
-    }
+void Shutdown() {
+  ConfigLayers.clear();
+  Meta = nullptr;
+}

-    // If an environment variable exists in both current meta and in the incoming layer then the meta layer value is overwritten
-    fextl::unordered_map<fextl::string, fextl::string> LookupMap;
-    const auto AddToMap = [&LookupMap](FEXCore::Config::LayerValue const &Value) {
-      for (const auto &EnvVar : Value) {
-        const auto ItEq = EnvVar.find_first_of('=');
-        if (ItEq == fextl::string::npos) {
-          // Broken environment variable
-          // Skip
-          continue;
-        }
-        auto Key = fextl::string(EnvVar.begin(), EnvVar.begin() + ItEq);
-        auto Value = fextl::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
-
-        // Add the key to the map, overwriting whatever previous value was there
-        LookupMap.insert_or_assign(std::move(Key), std::move(Value));
-      }
-    };
-
-    AddToMap(MetaEnvironment->second);
-    AddToMap(Value);
-
-    // Now with the two layers merged in the map
-    // Add all the values to the option
-    Erase(Option);
-    for (auto &Val : LookupMap) {
-      // Set will emplace multiple options in to its list
-      Set(Option, Val.first + "=" + Val.second);
+void Load() {
+  for (auto CurrentLayer = LoadOrder.begin(); CurrentLayer != LoadOrder.end(); ++CurrentLayer) {
+    auto it = ConfigLayers.find(*CurrentLayer);
+    if (it != ConfigLayers.end()) {
+      it->second->Load();
    }
  }
+}

-  void MetaLayer::MergeConfigMap(const LayerOptions &Options) {
-    // Insert this layer's options, overlaying previous options that exist here
-    for (auto &it : Options) {
-      if (it.first == FEXCore::Config::ConfigOption::CONFIG_ENV ||
-          it.first == FEXCore::Config::ConfigOption::CONFIG_HOSTENV) {
-        MergeEnvironmentVariables(it.first, it.second);
-      }
-      else {
-        OptionMap.insert_or_assign(it.first, it.second);
-      }
-    }
-  }
-
-  void Initialize() {
-    AddLayer(fextl::make_unique<MetaLayer>(FEXCore::Config::LayerType::LAYER_TOP));
-    Meta = ConfigLayers.begin()->second.get();
-  }
-
-  void Shutdown() {
-    ConfigLayers.clear();
-    Meta = nullptr;
-  }
-
-  void Load() {
-    for (auto CurrentLayer = LoadOrder.begin(); CurrentLayer != LoadOrder.end(); ++CurrentLayer) {
-      auto it = ConfigLayers.find(*CurrentLayer);
-      if (it != ConfigLayers.end()) {
-        it->second->Load();
-      }
-    }
-  }
-
-  fextl::string ExpandPath(fextl::string const &ContainerPrefix, fextl::string PathName) {
-    if (PathName.empty()) {
-      return {};
-    }
-
-
-    // Expand home if it exists
-    if (FHU::Filesystem::IsRelative(PathName)) {
-      fextl::string Home = getenv("HOME") ?: "";
-      // Home expansion only works if it is the first character
-      // This matches bash behaviour
-      if (PathName.at(0) == '~') {
-        PathName.replace(0, 1, Home);
-        return PathName;
-      }
-
-      // Expand relative path to absolute
-      char ExistsTempPath[PATH_MAX];
-      char *RealPath = FHU::Filesystem::Absolute(PathName.c_str(), ExistsTempPath);
-      if (RealPath) {
-        PathName = RealPath;
-      }
-
-      // Only return if it exists
-      if (FHU::Filesystem::Exists(PathName)) {
-        return PathName;
-      }
-    }
-    else {
-      // If the containerprefix and pathname isn't empty
-      // Then we check if the pathname exists in our current namespace
-      // If the path DOESN'T exist but DOES exist with the prefix applied
-      // then redirect to the prefix
-      //
-      // This might not be expected behaviour for some edge cases but since
-      // all paths aren't mounted inside the container, then it'll be fine
-      //
-      // Main catch case for this is the default thunk install folders
-      // HostThunks: $CMAKE_INSTALL_PREFIX/lib/fex-emu/HostThunks/
-      // GuestThunks: $CMAKE_INSTALL_PREFIX/share/fex-emu/GuestThunks/
-      if (!ContainerPrefix.empty() && !PathName.empty()) {
-        if (!FHU::Filesystem::Exists(PathName)) {
-          auto ContainerPath = ContainerPrefix + PathName;
-          if (FHU::Filesystem::Exists(ContainerPath)) {
-            return ContainerPath;
-          }
-        }
-      }
-    }
+fextl::string ExpandPath(const fextl::string& ContainerPrefix, fextl::string PathName) {
+  if (PathName.empty()) {
    return {};
  }

-  constexpr char ContainerManager[] = "/run/host/container-manager";

-  fextl::string FindContainer() {
-    // We only support pressure-vessel at the moment
-    if (FHU::Filesystem::Exists(ContainerManager)) {
-      fextl::vector<char> Manager{};
-      if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
-        // Trim the whitespace, may contain a newline
-        fextl::string ManagerStr = Manager.data();
-        ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
-        return ManagerStr;
-      }
+  // Expand home if it exists
+  if (FHU::Filesystem::IsRelative(PathName)) {
+    fextl::string Home = getenv("HOME") ?: "";
+    // Home expansion only works if it is the first character
+    // This matches bash behaviour
+    if (PathName.at(0) == '~') {
+      PathName.replace(0, 1, Home);
+      return PathName;
    }
-    return {};
-  }

-  fextl::string FindContainerPrefix() {
-    // We only support pressure-vessel at the moment
-    if (FHU::Filesystem::Exists(ContainerManager)) {
-      fextl::vector<char> Manager{};
-      if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
-        // Trim the whitespace, may contain a newline
-        fextl::string ManagerStr = Manager.data();
-        ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
-        if (strncmp(ManagerStr.data(), "pressure-vessel", Manager.size()) == 0) {
-          // We are running inside of pressure vessel
-          // Our $CMAKE_INSTALL_PREFIX paths are now inside of /run/host/$CMAKE_INSTALL_PREFIX
-          return "/run/host/";
+    // Expand relative path to absolute
+    char ExistsTempPath[PATH_MAX];
+    char* RealPath = FHU::Filesystem::Absolute(PathName.c_str(), ExistsTempPath);
+    if (RealPath) {
+      PathName = RealPath;
+    }
+
+    // Only return if it exists
+    if (FHU::Filesystem::Exists(PathName)) {
+      return PathName;
+    }
+  } else {
+    // If the containerprefix and pathname isn't empty
+    // Then we check if the pathname exists in our current namespace
+    // If the path DOESN'T exist but DOES exist with the prefix applied
+    // then redirect to the prefix
+    //
+    // This might not be expected behaviour for some edge cases but since
+    // all paths aren't mounted inside the container, then it'll be fine
+    //
+    // Main catch case for this is the default thunk install folders
+    // HostThunks: $CMAKE_INSTALL_PREFIX/lib/fex-emu/HostThunks/
+    // GuestThunks: $CMAKE_INSTALL_PREFIX/share/fex-emu/GuestThunks/
+    if (!ContainerPrefix.empty() && !PathName.empty()) {
+      if (!FHU::Filesystem::Exists(PathName)) {
+        auto ContainerPath = ContainerPrefix + PathName;
+        if (FHU::Filesystem::Exists(ContainerPath)) {
+          return ContainerPath;
        }
      }
    }
-    return {};
  }
+  return {};
+}

-  void ReloadMetaLayer() {
-    Meta->Load();
+constexpr char ContainerManager[] = "/run/host/container-manager";

-    // Do configuration option fix ups after everything is reloaded
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_CORE)) {
-      // Sanitize Core option
-      FEX_CONFIG_OPT(Core, CORE);
+fextl::string FindContainer() {
+  // We only support pressure-vessel at the moment
+  if (FHU::Filesystem::Exists(ContainerManager)) {
+    fextl::vector<char> Manager {};
+    if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
+      // Trim the whitespace, may contain a newline
+      fextl::string ManagerStr = Manager.data();
+      ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
+      return ManagerStr;
+    }
+  }
+  return {};
+}
+
+fextl::string FindContainerPrefix() {
+  // We only support pressure-vessel at the moment
+  if (FHU::Filesystem::Exists(ContainerManager)) {
+    fextl::vector<char> Manager {};
+    if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
+      // Trim the whitespace, may contain a newline
+      fextl::string ManagerStr = Manager.data();
+      ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
+      if (strncmp(ManagerStr.data(), "pressure-vessel", Manager.size()) == 0) {
+        // We are running inside of pressure vessel
+        // Our $CMAKE_INSTALL_PREFIX paths are now inside of /run/host/$CMAKE_INSTALL_PREFIX
+        return "/run/host/";
+      }
+    }
+  }
+  return {};
+}
+
+void ReloadMetaLayer() {
+  Meta->Load();
+
+  // Do configuration option fix ups after everything is reloaded
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_CORE)) {
+    // Sanitize Core option
+    FEX_CONFIG_OPT(Core, CORE);
 #if (_M_X86_64)
-      constexpr uint32_t MaxCoreNumber = 1;
+    constexpr uint32_t MaxCoreNumber = 1;
 #else
-      constexpr uint32_t MaxCoreNumber = 0;
+    constexpr uint32_t MaxCoreNumber = 0;
 #endif
-      if (Core > MaxCoreNumber) {
-        // Sanitize the core option by setting the core to the JIT if invalid
-        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, fextl::fmt::format("{}", static_cast<uint32_t>(FEXCore::Config::CONFIG_IRJIT)));
+    if (Core > MaxCoreNumber) {
+      // Sanitize the core option by setting the core to the JIT if invalid
+      FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, fextl::fmt::format("{}", static_cast<uint32_t>(FEXCore::Config::CONFIG_IRJIT)));
+    }
+  }
+
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_CACHEOBJECTCODECOMPILATION)) {
+    FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
+    FEX_CONFIG_OPT(Core, CORE);
+  }
+
+  fextl::string ContainerPrefix {FindContainerPrefix()};
+  auto ExpandPathIfExists = [&ContainerPrefix](FEXCore::Config::ConfigOption Config, fextl::string PathName) {
+    auto NewPath = ExpandPath(ContainerPrefix, PathName);
+    if (!NewPath.empty()) {
+      FEXCore::Config::EraseSet(Config, NewPath);
+    }
+  };
+
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_ROOTFS)) {
+    FEX_CONFIG_OPT(PathName, ROOTFS);
+    auto ExpandedString = ExpandPath(ContainerPrefix, PathName());
+    if (!ExpandedString.empty()) {
+      // Adjust the path if it ended up being relative
+      FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, ExpandedString);
+    } else if (!PathName().empty()) {
+      // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
+      fextl::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
+      if (FHU::Filesystem::Exists(NamedRootFS)) {
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NamedRootFS);
      }
    }
-
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_CACHEOBJECTCODECOMPILATION)) {
-      FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
-      FEX_CONFIG_OPT(Core, CORE);
-    }
-
-    fextl::string ContainerPrefix { FindContainerPrefix() };
-    auto ExpandPathIfExists = [&ContainerPrefix](FEXCore::Config::ConfigOption Config, fextl::string PathName) {
-      auto NewPath = ExpandPath(ContainerPrefix, PathName);
-      if (!NewPath.empty()) {
-        FEXCore::Config::EraseSet(Config, NewPath);
-      }
-    };
-
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_ROOTFS)) {
-      FEX_CONFIG_OPT(PathName, ROOTFS);
-      auto ExpandedString = ExpandPath(ContainerPrefix,PathName());
-      if (!ExpandedString.empty()) {
-        // Adjust the path if it ended up being relative
-        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, ExpandedString);
-      }
-      else if (!PathName().empty()) {
-        // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
-        fextl::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
-        if (FHU::Filesystem::Exists(NamedRootFS)) {
-          FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NamedRootFS);
-        }
+  }
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKHOSTLIBS)) {
+    FEX_CONFIG_OPT(PathName, THUNKHOSTLIBS);
+    ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKHOSTLIBS, PathName());
+  }
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKGUESTLIBS)) {
+    FEX_CONFIG_OPT(PathName, THUNKGUESTLIBS);
+    ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKGUESTLIBS, PathName());
+  }
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKCONFIG)) {
+    FEX_CONFIG_OPT(PathName, THUNKCONFIG);
+    auto ExpandedString = ExpandPath(ContainerPrefix, PathName());
+    if (!ExpandedString.empty()) {
+      // Adjust the path if it ended up being relative
+      FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, ExpandedString);
+    } else if (!PathName().empty()) {
+      // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
+      fextl::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
+      if (FHU::Filesystem::Exists(NamedConfig)) {
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, NamedConfig);
      }
    }
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKHOSTLIBS)) {
-      FEX_CONFIG_OPT(PathName, THUNKHOSTLIBS);
-      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKHOSTLIBS, PathName());
-    }
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKGUESTLIBS)) {
-      FEX_CONFIG_OPT(PathName, THUNKGUESTLIBS);
-      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKGUESTLIBS, PathName());
-    }
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKCONFIG)) {
-      FEX_CONFIG_OPT(PathName, THUNKCONFIG);
-      auto ExpandedString = ExpandPath(ContainerPrefix, PathName());
-      if (!ExpandedString.empty()) {
-        // Adjust the path if it ended up being relative
-        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, ExpandedString);
-      }
-      else if (!PathName().empty()) {
-        // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
-        fextl::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
-        if (FHU::Filesystem::Exists(NamedConfig)) {
-          FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, NamedConfig);
-        }
-      }
-    }
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_OUTPUTLOG)) {
-      FEX_CONFIG_OPT(PathName, OUTPUTLOG);
-      if (PathName() != "stdout" && PathName() != "stderr" && PathName() != "server") {
-        ExpandPathIfExists(FEXCore::Config::CONFIG_OUTPUTLOG, PathName());
-      }
-    }
-
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_DUMPIR) &&
-        !FEXCore::Config::Exists(FEXCore::Config::CONFIG_PASSMANAGERDUMPIR)) {
-      // If DumpIR is set but no PassManagerDumpIR configuration is set, then default to `afteropt`
-      FEX_CONFIG_OPT(PathName, DUMPIR);
-      if (PathName() != "no") {
-        EraseSet(FEXCore::Config::ConfigOption::CONFIG_PASSMANAGERDUMPIR, fextl::fmt::format("{}", static_cast<uint64_t>(FEXCore::Config::PassManagerDumpIR::AFTEROPT)));
-      }
-    }
-
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_SINGLESTEP)) {
-      // Single stepping also enforces single instruction size blocks
-      Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, "1");
+  }
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_OUTPUTLOG)) {
+    FEX_CONFIG_OPT(PathName, OUTPUTLOG);
+    if (PathName() != "stdout" && PathName() != "stderr" && PathName() != "server") {
+      ExpandPathIfExists(FEXCore::Config::CONFIG_OUTPUTLOG, PathName());
    }
  }

-  void AddLayer(fextl::unique_ptr<FEXCore::Config::Layer> _Layer) {
-    ConfigLayers.emplace(_Layer->GetLayerType(), std::move(_Layer));
-  }
-
-  bool Exists(ConfigOption Option) {
-    return Meta->OptionExists(Option);
-  }
-
-  std::optional<LayerValue*> All(ConfigOption Option) {
-    return Meta->All(Option);
-  }
-
-  std::optional<fextl::string*> Get(ConfigOption Option) {
-    return Meta->Get(Option);
-  }
-
-  void Set(ConfigOption Option, std::string_view Data) {
-    Meta->Set(Option, Data);
-  }
-
-  void Erase(ConfigOption Option) {
-    Meta->Erase(Option);
-  }
-
-  void EraseSet(ConfigOption Option, std::string_view Data) {
-    Meta->EraseSet(Option, Data);
-  }
-
-  template<typename T>
-  T Value<T>::Get(FEXCore::Config::ConfigOption Option) {
-    T Result;
-    auto Value = FEXCore::Config::Get(Option);
-
-    if (!FEXCore::StrConv::Conv(**Value, &Result)) {
-      LOGMAN_MSG_A_FMT("Attempted to convert invalid value");
-    }
-    return Result;
-  }
-
-  template<typename T>
-  T Value<T>::GetIfExists(FEXCore::Config::ConfigOption Option, T Default) {
-    T Result;
-    auto Value = FEXCore::Config::Get(Option);
-
-    if (Value && FEXCore::StrConv::Conv(**Value, &Result)) {
-      return Result;
-    }
-    else {
-      return Default;
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_DUMPIR) && !FEXCore::Config::Exists(FEXCore::Config::CONFIG_PASSMANAGERDUMPIR)) {
+    // If DumpIR is set but no PassManagerDumpIR configuration is set, then default to `afteropt`
+    FEX_CONFIG_OPT(PathName, DUMPIR);
+    if (PathName() != "no") {
+      EraseSet(FEXCore::Config::ConfigOption::CONFIG_PASSMANAGERDUMPIR,
+               fextl::fmt::format("{}", static_cast<uint64_t>(FEXCore::Config::PassManagerDumpIR::AFTEROPT)));
    }
  }

-  template<>
-  fextl::string Value<fextl::string>::GetIfExists(FEXCore::Config::ConfigOption Option, fextl::string Default) {
-    auto Value = FEXCore::Config::Get(Option);
-    if (Value) {
-      return **Value;
-    }
-    else {
-      return Default;
-    }
+  if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_SINGLESTEP)) {
+    // Single stepping also enforces single instruction size blocks
+    Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, "1");
  }
-
-  template<>
-  fextl::string Value<fextl::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string_view Default) {
-    auto Value = FEXCore::Config::Get(Option);
-    if (Value) {
-      return **Value;
-    }
-    else {
-      return fextl::string(Default);
-    }
-  }
-
-  template bool     Value<bool>::GetIfExists(FEXCore::Config::ConfigOption Option, bool Default);
-  template int8_t   Value<int8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int8_t Default);
-  template uint8_t  Value<uint8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint8_t Default);
-  template int16_t   Value<int16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int16_t Default);
-  template uint16_t  Value<uint16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint16_t Default);
-  template int32_t  Value<int32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int32_t Default);
-  template uint32_t Value<uint32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint32_t Default);
-  template int64_t  Value<int64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int64_t Default);
-  template uint64_t Value<uint64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint64_t Default);
-
-  // Constructor
-  template Value<fextl::string>::Value(FEXCore::Config::ConfigOption _Option, fextl::string Default);
-  template Value<bool>::Value(FEXCore::Config::ConfigOption _Option, bool Default);
-  template Value<uint8_t>::Value(FEXCore::Config::ConfigOption _Option, uint8_t Default);
-  template Value<uint64_t>::Value(FEXCore::Config::ConfigOption _Option, uint64_t Default);
-
-  template<typename T>
-  void Value<T>::GetListIfExists(FEXCore::Config::ConfigOption Option, fextl::list<fextl::string> *List) {
-    auto Value = FEXCore::Config::All(Option);
-    List->clear();
-    if (Value) {
-      *List = **Value;
-    }
-  }
-  template void Value<fextl::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, fextl::list<fextl::string> *List);
 }

+void AddLayer(fextl::unique_ptr<FEXCore::Config::Layer> _Layer) {
+  ConfigLayers.emplace(_Layer->GetLayerType(), std::move(_Layer));
+}
+
+bool Exists(ConfigOption Option) {
+  return Meta->OptionExists(Option);
+}
+
+std::optional<LayerValue*> All(ConfigOption Option) {
+  return Meta->All(Option);
+}
+
+std::optional<fextl::string*> Get(ConfigOption Option) {
+  return Meta->Get(Option);
+}
+
+void Set(ConfigOption Option, std::string_view Data) {
+  Meta->Set(Option, Data);
+}
+
+void Erase(ConfigOption Option) {
+  Meta->Erase(Option);
+}
+
+void EraseSet(ConfigOption Option, std::string_view Data) {
+  Meta->EraseSet(Option, Data);
+}
+
+template<typename T>
+T Value<T>::Get(FEXCore::Config::ConfigOption Option) {
+  T Result;
+  auto Value = FEXCore::Config::Get(Option);
+
+  if (!FEXCore::StrConv::Conv(**Value, &Result)) {
+    LOGMAN_MSG_A_FMT("Attempted to convert invalid value");
+  }
+  return Result;
+}
+
+template<typename T>
+T Value<T>::GetIfExists(FEXCore::Config::ConfigOption Option, T Default) {
+  T Result;
+  auto Value = FEXCore::Config::Get(Option);
+
+  if (Value && FEXCore::StrConv::Conv(**Value, &Result)) {
+    return Result;
+  } else {
+    return Default;
+  }
+}
+
+template<>
+fextl::string Value<fextl::string>::GetIfExists(FEXCore::Config::ConfigOption Option, fextl::string Default) {
+  auto Value = FEXCore::Config::Get(Option);
+  if (Value) {
+    return **Value;
+  } else {
+    return Default;
+  }
+}
+
+template<>
+fextl::string Value<fextl::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string_view Default) {
+  auto Value = FEXCore::Config::Get(Option);
+  if (Value) {
+    return **Value;
+  } else {
+    return fextl::string(Default);
+  }
+}
+
+template bool Value<bool>::GetIfExists(FEXCore::Config::ConfigOption Option, bool Default);
+template int8_t Value<int8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int8_t Default);
+template uint8_t Value<uint8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint8_t Default);
+template int16_t Value<int16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int16_t Default);
+template uint16_t Value<uint16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint16_t Default);
+template int32_t Value<int32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int32_t Default);
+template uint32_t Value<uint32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint32_t Default);
+template int64_t Value<int64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int64_t Default);
+template uint64_t Value<uint64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint64_t Default);
+
+// Constructor
+template Value<fextl::string>::Value(FEXCore::Config::ConfigOption _Option, fextl::string Default);
+template Value<bool>::Value(FEXCore::Config::ConfigOption _Option, bool Default);
+template Value<uint8_t>::Value(FEXCore::Config::ConfigOption _Option, uint8_t Default);
+template Value<uint64_t>::Value(FEXCore::Config::ConfigOption _Option, uint64_t Default);
+
+template<typename T>
+void Value<T>::GetListIfExists(FEXCore::Config::ConfigOption Option, fextl::list<fextl::string>* List) {
+  auto Value = FEXCore::Config::All(Option);
+  List->clear();
+  if (Value) {
+    *List = **Value;
+  }
+}
+template void Value<fextl::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, fextl::list<fextl::string>* List);
+} // namespace FEXCore::Config
@@ -50,8 +50,6 @@
          "DISABLESVE": "disablesve",
          "ENABLEAVX": "enableavx",
          "DISABLEAVX": "disableavx",
-          "ENABLEAVX2": "enableavx2",
-          "DISABLEAVX2": "disableavx2",
          "ENABLEAFP": "enableafp",
          "DISABLEAFP": "disableafp",
          "ENABLELRCPC": "enablelrcpc",
@@ -78,6 +76,8 @@
          "DISABLECRYPTO": "disablecrypto",
          "ENABLERPRES": "enablerpres",
          "DISABLERPRES": "disablerpres",
+          "ENABLESVEBITPERM": "enablesvebitperm",
+          "DISABLESVEBITPERM": "disablesvebitperm",
          "ENABLEPRESERVEALLABI": "enablepreserveallabi",
          "DISABLEPRESERVEALLABI": "disablepreserveallabi"
        },
@@ -86,7 +86,6 @@
          "\toff: Default CPU features queried from CPU features",
          "\t{enable,disable}sve: Will force enable or disable sve even if the host doesn't support it",
          "\t{enable,disable}avx: Will force enable or disable avx even if the host doesn't support it",
-          "\t{enable,disable}avx2: Will force enable or disable avx2 even if the host doesn't support it",
          "\t{enable,disable}afp: Will force enable or disable afp even if the host doesn't support it",
          "\t{enable,disable}lrcpc: Will force enable or disable lrcpc even if the host doesn't support it",
          "\t{enable,disable}lrcpc2: Will force enable or disable lrcpc2 even if the host doesn't support it",
@@ -100,6 +99,7 @@
          "\t{enable,disable}flagm2: Will force enable or disable flagm2 even if the host doesn't support it",
          "\t{enable,disable}crypto: Will force enable or disable crypto extensions even if the host doesn't support it",
          "\t{enable,disable}rpres: Will force enable or disable rpres even if the host doesn't support it",
+          "\t{enable,disable}svebitperm: Will force enable or disable svebitperm even if the host doesn't support it",
          "\t{enable,disable}preserveallabi: Will force enable or disable preserve_all abi even if the host doesn't support it"
        ]
      },
@@ -401,19 +401,27 @@
      },
      "VectorTSOEnabled": {
        "Type": "bool",
-        "Default": "true",
+        "Default": "false",
        "Desc": [
          "When TSO emulation is enabled, controls if vector loadstores should also be atomic."
        ]
      },
      "MemcpySetTSOEnabled": {
        "Type": "bool",
-        "Default": "true",
+        "Default": "false",
        "Desc": [
          "When TSO emulation is enabled, controls if memcpy and memset should also be atomic.",
          "Only affects REP MOVS and REP STOS instructions"
        ]
      },
+      "HalfBarrierTSOEnabled": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "When TSO emulation is enabled, controls if unaligned loads and stores should be backpatched to half-barrier atomics.",
+          "Can be dangerous due to aligned loadstores through the same code now become non-atomic."
+        ]
+      },
      "TSOAutoMigration": {
        "Type": "bool",
        "Default": "true",
@@ -6,6 +6,7 @@
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Core/HostFeatures.h>
 #include <FEXCore/Core/SignalDelegator.h>
 #include "FEXCore/Debug/InternalThreadState.h"

@@ -13,61 +14,57 @@
 #include <utility>

 namespace FEXCore::Context {
-  void InitializeStaticTables(OperatingMode Mode) {
-    X86Tables::InitializeInfoTables(Mode);
-    IR::InstallOpcodeHandlers(Mode);
-  }
-
-  fextl::unique_ptr<FEXCore::Context::Context> FEXCore::Context::Context::CreateNewContext() {
-    return fextl::make_unique<FEXCore::Context::ContextImpl>();
-  }
-
-  void FEXCore::Context::ContextImpl::SetExitHandler(ExitHandler handler) {
-    CustomExitHandler = std::move(handler);
-  }
-
-  ExitHandler FEXCore::Context::ContextImpl::GetExitHandler() const {
-    return CustomExitHandler;
-  }
-
-  void FEXCore::Context::ContextImpl::CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
-    CompileBlock(Thread->CurrentFrame, GuestRIP);
-  }
-
-  void FEXCore::Context::ContextImpl::CompileRIPCount(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, uint64_t MaxInst) {
-    CompileBlock(Thread->CurrentFrame, GuestRIP, MaxInst);
-  }
-
-  void FEXCore::Context::ContextImpl::SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) {
-    CustomCPUFactory = std::move(Factory);
-  }
-
-  HostFeatures FEXCore::Context::ContextImpl::GetHostFeatures() const {
-    return HostFeatures;
-  }
-
-  void FEXCore::Context::ContextImpl::SetSignalDelegator(FEXCore::SignalDelegator *_SignalDelegation) {
-    SignalDelegation = _SignalDelegation;
-  }
-
-  void FEXCore::Context::ContextImpl::SetSyscallHandler(FEXCore::HLE::SyscallHandler *Handler) {
-    SyscallHandler = Handler;
-    SourcecodeResolver = Handler->GetSourcecodeResolver();
-  }
-
-  FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunction(uint32_t Function, uint32_t Leaf) {
-    return CPUID.RunFunction(Function, Leaf);
-  }
-
-  FEXCore::CPUID::XCRResults FEXCore::Context::ContextImpl::RunXCRFunction(uint32_t Function) {
-    return CPUID.RunXCRFunction(Function);
-  }
-
-  FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
-    return CPUID.RunFunctionName(Function, Leaf, CPU);
-  }
-
-  bool FEXCore::Context::ContextImpl::IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState *Thread, uintptr_t Address) const {
-    return Thread->CPUBackend->IsAddressInCodeBuffer(Address);
-  }
+void InitializeStaticTables(OperatingMode Mode) {
+  X86Tables::InitializeInfoTables(Mode);
+  IR::InstallOpcodeHandlers(Mode);
 }
+
+fextl::unique_ptr<FEXCore::Context::Context> FEXCore::Context::Context::CreateNewContext(const FEXCore::HostFeatures& Features) {
+  return fextl::make_unique<FEXCore::Context::ContextImpl>(Features);
+}
+
+void FEXCore::Context::ContextImpl::SetExitHandler(ExitHandler handler) {
+  CustomExitHandler = std::move(handler);
+}
+
+ExitHandler FEXCore::Context::ContextImpl::GetExitHandler() const {
+  return CustomExitHandler;
+}
+
+void FEXCore::Context::ContextImpl::CompileRIP(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP) {
+  CompileBlock(Thread->CurrentFrame, GuestRIP);
+}
+
+void FEXCore::Context::ContextImpl::CompileRIPCount(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP, uint64_t MaxInst) {
+  CompileBlock(Thread->CurrentFrame, GuestRIP, MaxInst);
+}
+
+void FEXCore::Context::ContextImpl::SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) {
+  CustomCPUFactory = std::move(Factory);
+}
+
+void FEXCore::Context::ContextImpl::SetSignalDelegator(FEXCore::SignalDelegator* _SignalDelegation) {
+  SignalDelegation = _SignalDelegation;
+}
+
+void FEXCore::Context::ContextImpl::SetSyscallHandler(FEXCore::HLE::SyscallHandler* Handler) {
+  SyscallHandler = Handler;
+  SourcecodeResolver = Handler->GetSourcecodeResolver();
+}
+
+FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunction(uint32_t Function, uint32_t Leaf) {
+  return CPUID.RunFunction(Function, Leaf);
+}
+
+FEXCore::CPUID::XCRResults FEXCore::Context::ContextImpl::RunXCRFunction(uint32_t Function) {
+  return CPUID.RunXCRFunction(Function);
+}
+
+FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
+  return CPUID.RunFunctionName(Function, Leaf, CPU);
+}
+
+bool FEXCore::Context::ContextImpl::IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState* Thread, uintptr_t Address) const {
+  return Thread->CPUBackend->IsAddressInCodeBuffer(Address);
+}
+} // namespace FEXCore::Context
@@ -46,362 +46,368 @@ namespace CodeSerialize {
 namespace CPU {
  class Arm64JITCore;
  class Dispatcher;
-}
+} // namespace CPU
 namespace HLE {
-struct SyscallArguments;
-class SyscallHandler;
-class SourcecodeResolver;
-struct SourcecodeMap;
-}
-}
+  struct SyscallArguments;
+  class SyscallHandler;
+  class SourcecodeResolver;
+  struct SourcecodeMap;
+} // namespace HLE
+} // namespace FEXCore

 namespace FEXCore::IR {
-  class RegisterAllocationData;
-  class IRListView;
+class RegisterAllocationData;
+struct IRListCopy;
+class IRListView;
 namespace Validation {
  class IRValidation;
 }
-}
+} // namespace FEXCore::IR

 namespace FEXCore::Context {
-  enum CoreRunningMode {
-    MODE_RUN        = 0,
-    MODE_SINGLESTEP = 1,
-  };
+enum CoreRunningMode {
+  MODE_RUN = 0,
+  MODE_SINGLESTEP = 1,
+};

-  struct ExitFunctionLinkData {
-    uint64_t HostBranch;
-    uint64_t GuestRIP;
-  };
+struct ExitFunctionLinkData {
+  uint64_t HostBranch;
+  uint64_t GuestRIP;
+};

-  using BlockDelinkerFunc = void(*)(FEXCore::Core::CpuStateFrame *Frame, FEXCore::Context::ExitFunctionLinkData *Record);
-  constexpr uint32_t TSC_SCALE = 128;
-  constexpr uint32_t TSC_SCALE_MAXIMUM = 1'000'000'000; ///< 1Ghz
+using BlockDelinkerFunc = void (*)(FEXCore::Core::CpuStateFrame* Frame, FEXCore::Context::ExitFunctionLinkData* Record);
+constexpr uint32_t TSC_SCALE = 128;
+constexpr uint32_t TSC_SCALE_MAXIMUM = 1'000'000'000; ///< 1Ghz

-  class ContextImpl final : public FEXCore::Context::Context {
-    public:
-      // Context base class implementation.
-      bool InitCore() override;
+class ContextImpl final : public FEXCore::Context::Context {
+public:
+  // Context base class implementation.
+  bool InitCore() override;

-      void SetExitHandler(ExitHandler handler) override;
-      ExitHandler GetExitHandler() const override;
+  void SetExitHandler(ExitHandler handler) override;
+  ExitHandler GetExitHandler() const override;

-      ExitReason RunUntilExit(FEXCore::Core::InternalThreadState *Thread) override;
+  ExitReason RunUntilExit(FEXCore::Core::InternalThreadState* Thread) override;

-      void ExecuteThread(FEXCore::Core::InternalThreadState *Thread) override;
+  void ExecuteThread(FEXCore::Core::InternalThreadState* Thread) override;

-      void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) override;
-      void CompileRIPCount(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, uint64_t MaxInst) override;
+  void CompileRIP(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP) override;
+  void CompileRIPCount(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP, uint64_t MaxInst) override;

-      void SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) override;
+  void SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) override;

-      HostFeatures GetHostFeatures() const override;
+  void HandleCallback(FEXCore::Core::InternalThreadState* Thread, uint64_t RIP) override;

-      void HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) override;
+  uint64_t RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState* Thread, uint64_t HostPC) override;
+  uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, bool WasInJIT, uint64_t* HostGPRs, uint64_t PSTATE) override;
+  void SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, uint32_t EFLAGS) override;

-      uint64_t RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState *Thread, uint64_t HostPC) override;
-      uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread, bool WasInJIT, uint64_t *HostGPRs, uint64_t PSTATE) override;
-      void SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState *Thread, uint32_t EFLAGS) override;
+  void ReconstructXMMRegisters(const FEXCore::Core::InternalThreadState* Thread, __uint128_t* XMM_Low, __uint128_t* YMM_High) override;
+  void SetXMMRegistersFromState(FEXCore::Core::InternalThreadState* Thread, const __uint128_t* XMM_Low, const __uint128_t* YMM_High) override;

-      /**
-       * @brief Used to create FEX thread objects in preparation for creating a true OS thread. Does set a TID or PID.
-       *
-       * @param InitialRIP The starting RIP of this thread
-       * @param StackPointer The starting RSP of this thread
-       * @param NewThreadState The initial thread state to setup for our state, if inheriting.
-       * @param ParentTID The PID that was the parent thread that created this
-       *
-       * @return The InternalThreadState object that tracks all of the emulated thread's state
-       *
-       * Usecases:
-       *  Parent thread Creation:
-       *    - Thread = CreateThread(InitialRIP, InitialStack, nullptr, 0);
-       *    - CTX->RunUntilExit(Thread);
-       *  OS thread Creation:
-       *    - Thread = CreateThread(0, 0, NewState, PPID);
-       *    - Thread->ExecutionThread = FEXCore::Threads::Thread::Create(ThreadHandler, Arg);
-       *    - ThreadHandler calls `CTX->ExecutionThread(Thread)`
-       *  OS fork (New thread created with a clone of thread state):
-       *    - clone{2, 3}
-       *    - Thread = CreateThread(0, 0, CopyOfThreadState, PPID);
-       *    - ExecutionThread(Thread); // Starts executing without creating another host thread
-       *  Thunk callback executing guest code from native host thread
-       *    - Thread = CreateThread(0, 0, NewState, PPID);
-       *    - InitializeThreadTLSData(Thread);
-       *    - HandleCallback(Thread, RIP);
-       */
+  /**
+   * @brief Used to create FEX thread objects in preparation for creating a true OS thread. Does set a TID or PID.
+   *
+   * @param InitialRIP The starting RIP of this thread
+   * @param StackPointer The starting RSP of this thread
+   * @param NewThreadState The initial thread state to setup for our state, if inheriting.
+   * @param ParentTID The PID that was the parent thread that created this
+   *
+   * @return The InternalThreadState object that tracks all of the emulated thread's state
+   *
+   * Usecases:
+   *  Parent thread Creation:
+   *    - Thread = CreateThread(InitialRIP, InitialStack, nullptr, 0);
+   *    - CTX->RunUntilExit(Thread);
+   *  OS thread Creation:
+   *    - Thread = CreateThread(0, 0, NewState, PPID);
+   *    - Thread->ExecutionThread = FEXCore::Threads::Thread::Create(ThreadHandler, Arg);
+   *    - ThreadHandler calls `CTX->ExecutionThread(Thread)`
+   *  OS fork (New thread created with a clone of thread state):
+   *    - clone{2, 3}
+   *    - Thread = CreateThread(0, 0, CopyOfThreadState, PPID);
+   *    - ExecutionThread(Thread); // Starts executing without creating another host thread
+   *  Thunk callback executing guest code from native host thread
+   *    - Thread = CreateThread(0, 0, NewState, PPID);
+   *    - InitializeThreadTLSData(Thread);
+   *    - HandleCallback(Thread, RIP);
+   */

-      FEXCore::Core::InternalThreadState* CreateThread(uint64_t InitialRIP, uint64_t StackPointer, FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) override;
+  FEXCore::Core::InternalThreadState*
+  CreateThread(uint64_t InitialRIP, uint64_t StackPointer, FEXCore::Core::CPUState* NewThreadState, uint64_t ParentTID) override;

-      // Public for threading
-      void ExecutionThread(FEXCore::Core::InternalThreadState *Thread) override;
+  // Public for threading
+  void ExecutionThread(FEXCore::Core::InternalThreadState* Thread) override;

-      /**
-       * @brief Destroys this FEX thread object and stops tracking it internally
-       *
-       * @param Thread The internal FEX thread state object
-       */
-      void DestroyThread(FEXCore::Core::InternalThreadState *Thread, bool NeedsTLSUninstall) override;
+  /**
+   * @brief Destroys this FEX thread object and stops tracking it internally
+   *
+   * @param Thread The internal FEX thread state object
+   */
+  void DestroyThread(FEXCore::Core::InternalThreadState* Thread, bool NeedsTLSUninstall) override;

 #ifndef _WIN32
-      void LockBeforeFork(FEXCore::Core::InternalThreadState *Thread) override;
-      void UnlockAfterFork(FEXCore::Core::InternalThreadState *Thread, bool Child) override;
+  void LockBeforeFork(FEXCore::Core::InternalThreadState* Thread) override;
+  void UnlockAfterFork(FEXCore::Core::InternalThreadState* Thread, bool Child) override;
 #endif
-      void SetSignalDelegator(FEXCore::SignalDelegator *SignalDelegation) override;
-      void SetSyscallHandler(FEXCore::HLE::SyscallHandler *Handler) override;
+  void SetSignalDelegator(FEXCore::SignalDelegator* SignalDelegation) override;
+  void SetSyscallHandler(FEXCore::HLE::SyscallHandler* Handler) override;

-      FEXCore::CPUID::FunctionResults RunCPUIDFunction(uint32_t Function, uint32_t Leaf) override;
-      FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) override;
-      FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) override;
+  FEXCore::CPUID::FunctionResults RunCPUIDFunction(uint32_t Function, uint32_t Leaf) override;
+  FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) override;
+  FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) override;

-      FEXCore::IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(const fextl::string& Name) override;
-      void UnloadAOTIRCacheEntry(FEXCore::IR::AOTIRCacheEntry *Entry) override;
+  FEXCore::IR::AOTIRCacheEntry* LoadAOTIRCacheEntry(const fextl::string& Name) override;
+  void UnloadAOTIRCacheEntry(FEXCore::IR::AOTIRCacheEntry* Entry) override;

-      void SetAOTIRLoader(AOTIRLoaderCBFn CacheReader) override {
-        IRCaptureCache.SetAOTIRLoader(std::move(CacheReader));
-      }
-      void SetAOTIRWriter(AOTIRWriterCBFn CacheWriter) override {
-        IRCaptureCache.SetAOTIRWriter(std::move(CacheWriter));
-      }
-      void SetAOTIRRenamer(AOTIRRenamerCBFn CacheRenamer) override {
-        IRCaptureCache.SetAOTIRRenamer(std::move(CacheRenamer));
-      }
+  void SetAOTIRLoader(AOTIRLoaderCBFn CacheReader) override {
+    IRCaptureCache.SetAOTIRLoader(std::move(CacheReader));
+  }
+  void SetAOTIRWriter(AOTIRWriterCBFn CacheWriter) override {
+    IRCaptureCache.SetAOTIRWriter(std::move(CacheWriter));
+  }
+  void SetAOTIRRenamer(AOTIRRenamerCBFn CacheRenamer) override {
+    IRCaptureCache.SetAOTIRRenamer(std::move(CacheRenamer));
+  }

-      void FinalizeAOTIRCache() override {
-        IRCaptureCache.FinalizeAOTIRCache();
-      }
-      void WriteFilesWithCode(AOTIRCodeFileWriterFn Writer) override {
-        IRCaptureCache.WriteFilesWithCode(Writer);
-      }
+  void FinalizeAOTIRCache() override {
+    IRCaptureCache.FinalizeAOTIRCache();
+  }
+  void WriteFilesWithCode(AOTIRCodeFileWriterFn Writer) override {
+    IRCaptureCache.WriteFilesWithCode(Writer);
+  }

-      void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread) override;
-      void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length) override;
-      void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length, CodeRangeInvalidationFn callback) override;
-      FEXCore::ForkableSharedMutex &GetCodeInvalidationMutex() override {
-        return CodeInvalidationMutex;
-      }
+  void ClearCodeCache(FEXCore::Core::InternalThreadState* Thread) override;
+  void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState* Thread, uint64_t Start, uint64_t Length) override;
+  void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState* Thread, uint64_t Start, uint64_t Length, CodeRangeInvalidationFn callback) override;
+  FEXCore::ForkableSharedMutex& GetCodeInvalidationMutex() override {
+    return CodeInvalidationMutex;
+  }

-      void MarkMemoryShared(FEXCore::Core::InternalThreadState *Thread) override;
+  void MarkMemoryShared(FEXCore::Core::InternalThreadState* Thread) override;

-      void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) override;
+  void ConfigureAOTGen(FEXCore::Core::InternalThreadState* Thread, fextl::set<uint64_t>* ExternalBranches, uint64_t SectionMaxAddress) override;

-      bool IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState *Thread, uintptr_t Address) const override;
+  bool IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState* Thread, uintptr_t Address) const override;

-      // returns false if a handler was already registered
-      CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator = nullptr, void *Data = nullptr);
+  // returns false if a handler was already registered
+  CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void* Creator = nullptr, void* Data = nullptr);

-      void AppendThunkDefinitions(fextl::vector<FEXCore::IR::ThunkDefinition> const& Definitions) override;
+  void AppendThunkDefinitions(std::span<const FEXCore::IR::ThunkDefinition> Definitions) override;

-    public:
-    friend class FEXCore::HLE::SyscallHandler;
-  #ifdef JIT_ARM64
-    friend class FEXCore::CPU::Arm64JITCore;
-  #endif
+public:
+  friend class FEXCore::HLE::SyscallHandler;
+#ifdef JIT_ARM64
+  friend class FEXCore::CPU::Arm64JITCore;
+#endif

-    friend class FEXCore::IR::Validation::IRValidation;
+  friend class FEXCore::IR::Validation::IRValidation;

-    struct {
-      CoreRunningMode RunningMode {CoreRunningMode::MODE_RUN};
-      uint64_t VirtualMemSize{1ULL << 36};
+  struct {
+    CoreRunningMode RunningMode {CoreRunningMode::MODE_RUN};
+    uint64_t VirtualMemSize {1ULL << 36};

-      // this is for internal use
-      bool ValidateIRarser { false };
+    // Used if the JIT needs to have its interrupt fault code emitted.
+    bool NeedsPendingInterruptFaultCheck {false};

-      // Used if the JIT needs to have its interrupt fault code emitted.
-      bool NeedsPendingInterruptFaultCheck { false };
-
-      FEX_CONFIG_OPT(Multiblock, MULTIBLOCK);
-      FEX_CONFIG_OPT(SingleStepConfig, SINGLESTEP);
-      FEX_CONFIG_OPT(GdbServer, GDBSERVER);
-      FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
-      FEX_CONFIG_OPT(TSOEnabled, TSOENABLED);
-      FEX_CONFIG_OPT(TSOAutoMigration, TSOAUTOMIGRATION);
-      FEX_CONFIG_OPT(ABILocalFlags, ABILOCALFLAGS);
-      FEX_CONFIG_OPT(AOTIRCapture, AOTIRCAPTURE);
-      FEX_CONFIG_OPT(AOTIRGenerate, AOTIRGENERATE);
-      FEX_CONFIG_OPT(AOTIRLoad, AOTIRLOAD);
-      FEX_CONFIG_OPT(SMCChecks, SMCCHECKS);
-      FEX_CONFIG_OPT(Core, CORE);
-      FEX_CONFIG_OPT(MaxInstPerBlock, MAXINST);
-      FEX_CONFIG_OPT(RootFSPath, ROOTFS);
-      FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
-      FEX_CONFIG_OPT(ThunkHostLibsPath32, THUNKHOSTLIBS32);
-      FEX_CONFIG_OPT(ThunkConfigFile, THUNKCONFIG);
-      FEX_CONFIG_OPT(GlobalJITNaming, GLOBALJITNAMING);
-      FEX_CONFIG_OPT(LibraryJITNaming, LIBRARYJITNAMING);
-      FEX_CONFIG_OPT(BlockJITNaming, BLOCKJITNAMING);
-      FEX_CONFIG_OPT(GDBSymbols, GDBSYMBOLS);
-      FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
-      FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
-      FEX_CONFIG_OPT(x87ReducedPrecision, X87REDUCEDPRECISION);
-      FEX_CONFIG_OPT(DisableTelemetry, DISABLETELEMETRY);
-      FEX_CONFIG_OPT(DisableVixlIndirectCalls, DISABLE_VIXL_INDIRECT_RUNTIME_CALLS);
-      FEX_CONFIG_OPT(SmallTSCScale, SMALLTSCSCALE);
-    } Config;
+    FEX_CONFIG_OPT(Multiblock, MULTIBLOCK);
+    FEX_CONFIG_OPT(SingleStepConfig, SINGLESTEP);
+    FEX_CONFIG_OPT(GdbServer, GDBSERVER);
+    FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
+    FEX_CONFIG_OPT(TSOEnabled, TSOENABLED);
+    FEX_CONFIG_OPT(TSOAutoMigration, TSOAUTOMIGRATION);
+    FEX_CONFIG_OPT(ABILocalFlags, ABILOCALFLAGS);
+    FEX_CONFIG_OPT(AOTIRCapture, AOTIRCAPTURE);
+    FEX_CONFIG_OPT(AOTIRGenerate, AOTIRGENERATE);
+    FEX_CONFIG_OPT(AOTIRLoad, AOTIRLOAD);
+    FEX_CONFIG_OPT(SMCChecks, SMCCHECKS);
+    FEX_CONFIG_OPT(Core, CORE);
+    FEX_CONFIG_OPT(MaxInstPerBlock, MAXINST);
+    FEX_CONFIG_OPT(RootFSPath, ROOTFS);
+    FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
+    FEX_CONFIG_OPT(ThunkHostLibsPath32, THUNKHOSTLIBS32);
+    FEX_CONFIG_OPT(ThunkConfigFile, THUNKCONFIG);
+    FEX_CONFIG_OPT(GlobalJITNaming, GLOBALJITNAMING);
+    FEX_CONFIG_OPT(LibraryJITNaming, LIBRARYJITNAMING);
+    FEX_CONFIG_OPT(BlockJITNaming, BLOCKJITNAMING);
+    FEX_CONFIG_OPT(GDBSymbols, GDBSYMBOLS);
+    FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
+    FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
+    FEX_CONFIG_OPT(x87ReducedPrecision, X87REDUCEDPRECISION);
+    FEX_CONFIG_OPT(DisableTelemetry, DISABLETELEMETRY);
+    FEX_CONFIG_OPT(DisableVixlIndirectCalls, DISABLE_VIXL_INDIRECT_RUNTIME_CALLS);
+    FEX_CONFIG_OPT(SmallTSCScale, SMALLTSCSCALE);
+  } Config;


-    std::atomic_bool CoreShuttingDown{false};
+  std::atomic_bool CoreShuttingDown {false};

-    FEXCore::ForkableSharedMutex CodeInvalidationMutex;
+  FEXCore::ForkableSharedMutex CodeInvalidationMutex;

-    FEXCore::HostFeatures HostFeatures;
-    // CPUID depends on HostFeatures so needs to be initialized after that.
-    FEXCore::CPUIDEmu CPUID;
-    FEXCore::HLE::SyscallHandler *SyscallHandler{};
-    FEXCore::HLE::SourcecodeResolver *SourcecodeResolver{};
-    fextl::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
-    fextl::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
+  FEXCore::HostFeatures HostFeatures;
+  // CPUID depends on HostFeatures so needs to be initialized after that.
+  FEXCore::CPUIDEmu CPUID;
+  FEXCore::HLE::SyscallHandler* SyscallHandler {};
+  FEXCore::HLE::SourcecodeResolver* SourcecodeResolver {};
+  fextl::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
+  fextl::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;

-    CustomCPUFactoryType CustomCPUFactory;
-    FEXCore::Context::ExitHandler CustomExitHandler;
+  CustomCPUFactoryType CustomCPUFactory;
+  FEXCore::Context::ExitHandler CustomExitHandler;

 #ifdef BLOCKSTATS
-    fextl::unique_ptr<FEXCore::BlockSamplingData> BlockData;
+  fextl::unique_ptr<FEXCore::BlockSamplingData> BlockData;
 #endif

-    SignalDelegator *SignalDelegation{};
-    X86GeneratedCode X86CodeGen;
+  SignalDelegator* SignalDelegation {};
+  X86GeneratedCode X86CodeGen;

-    ContextImpl();
-    ~ContextImpl();
+  ContextImpl(const FEXCore::HostFeatures& Features);
+  ~ContextImpl();

-    static void ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-    static void ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, FEXCore::Context::ExitFunctionLinkData *HostLink, const BlockDelinkerFunc &delinker);
+  static void ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP);
+  static void ThreadAddBlockLink(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestDestination,
+                                 FEXCore::Context::ExitFunctionLinkData* HostLink, const BlockDelinkerFunc& delinker);

-    template<auto Fn>
-    static uint64_t ThreadExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, ExitFunctionLinkData *Record) {
-      auto Thread = Frame->Thread;
-      auto lk = GuardSignalDeferringSection<std::shared_lock>(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
+  template<auto Fn>
+  static uint64_t ThreadExitFunctionLink(FEXCore::Core::CpuStateFrame* Frame, ExitFunctionLinkData* Record) {
+    auto Thread = Frame->Thread;
+    auto lk = GuardSignalDeferringSection<std::shared_lock>(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);

-      return Fn(Frame, Record);
-    }
+    return Fn(Frame, Record);
+  }

-    // Wrapper which takes CpuStateFrame instead of InternalThreadState and unique_locks CodeInvalidationMutex
-    // Must be called from owning thread
-    static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
-      auto Thread = Frame->Thread;
+  // Wrapper which takes CpuStateFrame instead of InternalThreadState and unique_locks CodeInvalidationMutex
+  // Must be called from owning thread
+  static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame* Frame, uint64_t GuestRIP) {
+    auto Thread = Frame->Thread;
+    auto lk = GuardSignalDeferringSection(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);

-      LOGMAN_THROW_A_FMT(Thread->ThreadManager.GetTID() == FHU::Syscalls::gettid(), "Must be called from owning thread {}, not {}", Thread->ThreadManager.GetTID(), FHU::Syscalls::gettid());
-      auto lk = GuardSignalDeferringSection(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
+    ThreadRemoveCodeEntry(Thread, GuestRIP);
+  }

-      ThreadRemoveCodeEntry(Thread, GuestRIP);
-    }
+  void RemoveCustomIREntrypoint(uintptr_t Entrypoint);

-    void RemoveCustomIREntrypoint(uintptr_t Entrypoint);
-
-    struct GenerateIRResult {
-      FEXCore::IR::IRListView* IRList;
-      FEXCore::IR::RegisterAllocationData::UniquePtr RAData;
-      uint64_t TotalInstructions;
-      uint64_t TotalInstructionsLength;
-      uint64_t StartAddr;
-      uint64_t Length;
-    };
-    [[nodiscard]] GenerateIRResult GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, bool ExtendedDebugInfo, uint64_t MaxInst);
-
-    struct CompileCodeResult {
-      void* CompiledCode;
-      FEXCore::IR::IRListView* IRData;
-      FEXCore::Core::DebugData* DebugData;
-      FEXCore::IR::RegisterAllocationData::UniquePtr RAData;
-      bool GeneratedIR;
-      uint64_t StartAddr;
-      uint64_t Length;
-    };
-    [[nodiscard]] CompileCodeResult CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, uint64_t MaxInst = 0);
-    uintptr_t CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP, uint64_t MaxInst = 0);
-
-    // Used for thread creation from syscalls
-    /**
-     * @brief Initializes TID, PID and TLS data for a thread
-     *
-     * @param Thread The internal FEX thread state object
-     */
-    void InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread);
-
-    void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread);
-
-    uint8_t GetGPRSize() const { return Config.Is64BitMode ? 8 : 4; }
-
-    FEXCore::JITSymbols Symbols;
-
-    void GetVDSOSigReturn(VDSOSigReturn *VDSOPointers) override {
-      if (VDSOPointers->VDSO_kernel_sigreturn == nullptr) {
-        VDSOPointers->VDSO_kernel_sigreturn = reinterpret_cast<void*>(X86CodeGen.sigreturn_32);
-      }
-
-      if (VDSOPointers->VDSO_kernel_rt_sigreturn == nullptr) {
-        VDSOPointers->VDSO_kernel_rt_sigreturn = reinterpret_cast<void*>(X86CodeGen.rt_sigreturn_32);
-      }
-    }
-
-    FEXCore::Utils::PooledAllocatorVirtual OpDispatcherAllocator;
-    FEXCore::Utils::PooledAllocatorVirtual FrontendAllocator;
-
-    // If Atomic-based TSO emulation is enabled or not.
-    bool IsAtomicTSOEnabled() const { return AtomicTSOEmulationEnabled; }
-
-    void SetHardwareTSOSupport(bool HardwareTSOSupported) override {
-      SupportsHardwareTSO = HardwareTSOSupported;
-      UpdateAtomicTSOEmulationConfig();
-    }
-
-    // Returns if Software TSO emulation is required.
-    // NOTE: This doesn't necessary return if Atomic-based TSO is currently enabled.
-    // This will still return true if on a single thread and TSO is currently disabled.
-    //
-    // This is to ensure that if early initialization checks CPU features and TSO /could/ be enabled, that
-    // we return consistent results.
-    //
-    // To check if Atomic TSO is currently enabled in the JIT, use `IsAtomicTSOEnabled` instead.
-    bool SoftwareTSORequired() const {
-      if (SupportsHardwareTSO) return false;
-
-      return Config.TSOEnabled;
-    }
-
-    void EnableExitOnHLT() override { ExitOnHLT = true; }
-
-    bool ExitOnHLTEnabled() const { return ExitOnHLT; }
-
-    FEXCore::CPU::CPUBackendFeatures BackendFeatures;
-
-  protected:
-    void UpdateAtomicTSOEmulationConfig() {
-      if (SupportsHardwareTSO) {
-        // If the hardware supports TSO then we don't need to emulate it through atomics.
-        AtomicTSOEmulationEnabled = false;
-      }
-      else {
-        // Atomic TSO emulation only enabled if the config option is enabled.
-        AtomicTSOEmulationEnabled = (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled;
-      }
-    }
-
-  private:
-    /**
-     * @brief Initializes the JIT compilers for the thread
-     *
-     * @param State The internal FEX thread state object
-     *
-     * InitializeCompiler is called inside of CreateThread, so you likely don't need this
-     */
-    void InitializeCompiler(FEXCore::Core::InternalThreadState* Thread);
-
-    void AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr);
-
-    IR::AOTIRCaptureCache IRCaptureCache;
-    fextl::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;
-
-    bool StartPaused = false;
-    bool IsMemoryShared = false;
-    bool SupportsHardwareTSO = false;
-    bool AtomicTSOEmulationEnabled = true;
-    bool ExitOnHLT = false;
-    FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
-
-    std::shared_mutex CustomIRMutex;
-    std::atomic<bool> HasCustomIRHandlers{};
-    fextl::unordered_map<uint64_t, std::tuple<CustomIREntrypointHandler, void *, void *>> CustomIRHandlers;
+  struct GenerateIRResult {
+    fextl::unique_ptr<FEXCore::IR::IRStorageBase> IR;
+    uint64_t TotalInstructions;
+    uint64_t TotalInstructionsLength;
+    uint64_t StartAddr;
+    uint64_t Length;
  };
-}
+  [[nodiscard]]
+  GenerateIRResult GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP, bool ExtendedDebugInfo, uint64_t MaxInst);
+
+  struct CompileCodeResult {
+    void* CompiledCode;
+    fextl::unique_ptr<FEXCore::IR::IRStorageBase> IR;
+    FEXCore::Core::DebugData* DebugData;
+    bool GeneratedIR;
+    uint64_t StartAddr;
+    uint64_t Length;
+  };
+  [[nodiscard]]
+  CompileCodeResult CompileCode(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP, uint64_t MaxInst = 0);
+  uintptr_t CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_t GuestRIP, uint64_t MaxInst = 0);
+
+  // Used for thread creation from syscalls
+  /**
+   * @brief Initializes TID, PID and TLS data for a thread
+   *
+   * @param Thread The internal FEX thread state object
+   */
+  void InitializeThreadTLSData(FEXCore::Core::InternalThreadState* Thread);
+
+  void CopyMemoryMapping(FEXCore::Core::InternalThreadState* ParentThread, FEXCore::Core::InternalThreadState* ChildThread);
+
+  uint8_t GetGPRSize() const {
+    return Config.Is64BitMode ? 8 : 4;
+  }
+
+  FEXCore::JITSymbols Symbols;
+
+  void GetVDSOSigReturn(VDSOSigReturn* VDSOPointers) override {
+    if (VDSOPointers->VDSO_kernel_sigreturn == nullptr) {
+      VDSOPointers->VDSO_kernel_sigreturn = reinterpret_cast<void*>(X86CodeGen.sigreturn_32);
+    }
+
+    if (VDSOPointers->VDSO_kernel_rt_sigreturn == nullptr) {
+      VDSOPointers->VDSO_kernel_rt_sigreturn = reinterpret_cast<void*>(X86CodeGen.rt_sigreturn_32);
+    }
+  }
+
+  FEXCore::Utils::PooledAllocatorVirtual OpDispatcherAllocator;
+  FEXCore::Utils::PooledAllocatorVirtual FrontendAllocator;
+
+  // If Atomic-based TSO emulation is enabled or not.
+  bool IsAtomicTSOEnabled() const {
+    return AtomicTSOEmulationEnabled;
+  }
+
+  void SetHardwareTSOSupport(bool HardwareTSOSupported) override {
+    SupportsHardwareTSO = HardwareTSOSupported;
+    UpdateAtomicTSOEmulationConfig();
+  }
+
+  // Returns if Software TSO emulation is required.
+  // NOTE: This doesn't necessary return if Atomic-based TSO is currently enabled.
+  // This will still return true if on a single thread and TSO is currently disabled.
+  //
+  // This is to ensure that if early initialization checks CPU features and TSO /could/ be enabled, that
+  // we return consistent results.
+  //
+  // To check if Atomic TSO is currently enabled in the JIT, use `IsAtomicTSOEnabled` instead.
+  bool SoftwareTSORequired() const {
+    if (SupportsHardwareTSO) {
+      return false;
+    }
+
+    return Config.TSOEnabled;
+  }
+
+  void EnableExitOnHLT() override {
+    ExitOnHLT = true;
+  }
+
+  bool ExitOnHLTEnabled() const {
+    return ExitOnHLT;
+  }
+
+protected:
+  void UpdateAtomicTSOEmulationConfig() {
+    if (SupportsHardwareTSO) {
+      // If the hardware supports TSO then we don't need to emulate it through atomics.
+      AtomicTSOEmulationEnabled = false;
+    } else {
+      // Atomic TSO emulation only enabled if the config option is enabled.
+      AtomicTSOEmulationEnabled = (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled;
+    }
+  }
+
+private:
+  /**
+   * @brief Initializes the JIT compilers for the thread
+   *
+   * @param State The internal FEX thread state object
+   *
+   * InitializeCompiler is called inside of CreateThread, so you likely don't need this
+   */
+  void InitializeCompiler(FEXCore::Core::InternalThreadState* Thread);
+
+  void AddBlockMapping(FEXCore::Core::InternalThreadState* Thread, uint64_t Address, void* Ptr);
+
+  IR::AOTIRCaptureCache IRCaptureCache;
+  fextl::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;
+
+  bool StartPaused = false;
+  bool IsMemoryShared = false;
+  bool SupportsHardwareTSO = false;
+  bool AtomicTSOEmulationEnabled = true;
+  bool ExitOnHLT = false;
+  FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
+
+  std::shared_mutex CustomIRMutex;
+  std::atomic<bool> HasCustomIRHandlers {};
+  fextl::unordered_map<uint64_t, std::tuple<CustomIREntrypointHandler, void*, void*>> CustomIRHandlers;
+};
+} // namespace FEXCore::Context
@@ -2,9 +2,6 @@
 #pragma once

 #include "FEXCore/Utils/EnumUtils.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
-
 #include "Interface/Core/ObjectCache/Relocations.h"

 #include <aarch64/assembler-aarch64.h>
@@ -22,6 +19,8 @@

 #include <FEXCore/Config/Config.h>
 #include <FEXCore/fextl/vector.h>
+#include <CodeEmitter/Emitter.h>
+#include <CodeEmitter/Registers.h>

 #include <array>
 #include <cstddef>
@@ -35,86 +34,85 @@ class ContextImpl;

 namespace FEXCore::CPU {
 // Contains the address to the currently available CPU state
-constexpr auto STATE = FEXCore::ARMEmitter::XReg::x28;
+constexpr auto STATE = ARMEmitter::XReg::x28;

 #ifndef _M_ARM_64EC
 // GPR temporaries. Only x3 can be used across spill boundaries
 // so if these ever need to change, be very careful about that.
-constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x0;
-constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x1;
-constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x2;
-constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x3;
+constexpr auto TMP1 = ARMEmitter::XReg::x0;
+constexpr auto TMP2 = ARMEmitter::XReg::x1;
+constexpr auto TMP3 = ARMEmitter::XReg::x2;
+constexpr auto TMP4 = ARMEmitter::XReg::x3;
 constexpr bool TMP_ABIARGS = true;

 // We pin r26/r27 as PF/AF respectively, this is internal FEX ABI.
-constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r26;
-constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r27;
+constexpr auto REG_PF = ARMEmitter::Reg::r26;
+constexpr auto REG_AF = ARMEmitter::Reg::r27;

 // Vector temporaries
-constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v0;
-constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1;
+constexpr auto VTMP1 = ARMEmitter::VReg::v0;
+constexpr auto VTMP2 = ARMEmitter::VReg::v1;
 #else
-constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x10;
-constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x11;
-constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x12;
-constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x13;
+constexpr auto TMP1 = ARMEmitter::XReg::x10;
+constexpr auto TMP2 = ARMEmitter::XReg::x11;
+constexpr auto TMP3 = ARMEmitter::XReg::x12;
+constexpr auto TMP4 = ARMEmitter::XReg::x13;
 constexpr bool TMP_ABIARGS = false;

 // We pin r11/r12 as PF/AF respectively for arm64ec, as r26/r27 are used for SRA.
-constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r9;
-constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r24;
+constexpr auto REG_PF = ARMEmitter::Reg::r9;
+constexpr auto REG_AF = ARMEmitter::Reg::r24;

 // Vector temporaries
-constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v16;
-constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v17;
+constexpr auto VTMP1 = ARMEmitter::VReg::v16;
+constexpr auto VTMP2 = ARMEmitter::VReg::v17;
+
+// Entry/Exit ABI
+constexpr auto EC_CALL_CHECKER_PC_REG = ARMEmitter::XReg::x9;
+constexpr auto EC_ENTRY_CPUAREA_REG = ARMEmitter::XReg::x17;
+
+// These structures are not included in the standard Windows headers, define the offsets of members we care about for EC here.
+constexpr size_t TEB_CPU_AREA_OFFSET = 0x1788;
+constexpr size_t TEB_PEB_OFFSET = 0x60;
+constexpr size_t PEB_EC_CODE_BITMAP_OFFSET = 0x368;
+constexpr size_t CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET = 0x1;
+constexpr size_t CPU_AREA_EMULATOR_STACK_BASE_OFFSET = 0x8;
+constexpr size_t CPU_AREA_EMULATOR_DATA_OFFSET = 0x30;
 #endif

 // Predicate register temporaries (used when AVX support is enabled)
 // PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1.
 // PRED_TMP_32B indicates a predicate register that indicates the first 32 bytes set to 1.
-constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_16B = FEXCore::ARMEmitter::PReg::p6;
-constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_32B = FEXCore::ARMEmitter::PReg::p7;
+constexpr ARMEmitter::PRegister PRED_TMP_16B = ARMEmitter::PReg::p6;
+constexpr ARMEmitter::PRegister PRED_TMP_32B = ARMEmitter::PReg::p7;


 // This class contains common emitter utility functions that can
 // be used by both Arm64 JIT and ARM64 Dispatcher
-class Arm64Emitter : public FEXCore::ARMEmitter::Emitter {
+class Arm64Emitter : public ARMEmitter::Emitter {
 protected:
-  Arm64Emitter(FEXCore::Context::ContextImpl *ctx, void* EmissionPtr = nullptr, size_t size = 0);
+  Arm64Emitter(FEXCore::Context::ContextImpl* ctx, void* EmissionPtr = nullptr, size_t size = 0);

-  FEXCore::Context::ContextImpl *EmitterCTX;
-  vixl::aarch64::CPU CPU;
+  FEXCore::Context::ContextImpl* EmitterCTX;

-  std::span<const FEXCore::ARMEmitter::Register> ConfiguredDynamicRegisterBase{};
-  std::span<const FEXCore::ARMEmitter::Register> StaticRegisters{};
-  std::span<const FEXCore::ARMEmitter::Register> GeneralRegisters{};
-  std::span<const std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>> GeneralPairRegisters{};
-  std::span<const FEXCore::ARMEmitter::VRegister> StaticFPRegisters{};
-  std::span<const FEXCore::ARMEmitter::VRegister> GeneralFPRegisters{};
+  std::span<const ARMEmitter::Register> ConfiguredDynamicRegisterBase {};
+  std::span<const ARMEmitter::Register> StaticRegisters {};
+  std::span<const ARMEmitter::Register> GeneralRegisters {};
+  std::span<const ARMEmitter::VRegister> StaticFPRegisters {};
+  std::span<const ARMEmitter::VRegister> GeneralFPRegisters {};
+  uint32_t PairRegisters = 0;

-  /**
-   * @name Register Allocation
-   * @{ */
-  constexpr static uint32_t RegisterClasses = 6;
-
-  constexpr static uint64_t GPRBase = (0ULL << 32);
-  constexpr static uint64_t FPRBase = (1ULL << 32);
-  constexpr static uint64_t GPRPairBase = (2ULL << 32);
-
-  /**  @} */
-
-  constexpr static uint8_t RA_32 = 0;
-  constexpr static uint8_t RA_64 = 1;
-  constexpr static uint8_t RA_FPR = 2;
-
-  void LoadConstant(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false);
+  void LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false);

+  void FillSpecialRegs(ARMEmitter::Register TmpReg, ARMEmitter::Register TmpReg2, bool SetFIZ, bool SetPredRegs);

  // NOTE: These functions WILL clobber the register TMP4 if AVX support is enabled
  //       and FPRs are being spilled or filled. If only GPRs are spilled/filled, then
  //       TMP4 is left alone.
-  void SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
-  void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U);
+  void SpillStaticRegs(ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
+  void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U,
+                      std::optional<ARMEmitter::Register> OptionalReg = std::nullopt,
+                      std::optional<ARMEmitter::Register> OptionalReg2 = std::nullopt);

  // Register 0-18 + 29 + 30 are caller saved
  static constexpr uint32_t CALLER_GPR_MASK = 0b0110'0000'0000'0111'1111'1111'1111'1111U;
@@ -124,13 +122,13 @@ protected:
  static constexpr uint32_t CALLER_FPR_MASK = ~0U;

  // Generic push and pop vector registers.
-  void PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs);
-  void PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span<const FEXCore::ARMEmitter::Register> Regs);
+  void PushVectorRegisters(ARMEmitter::Register TmpReg, bool SVERegs, std::span<const ARMEmitter::VRegister> VRegs);
+  void PushGeneralRegisters(ARMEmitter::Register TmpReg, std::span<const ARMEmitter::Register> Regs);

-  void PopVectorRegisters(bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs);
-  void PopGeneralRegisters(std::span<const FEXCore::ARMEmitter::Register> Regs);
+  void PopVectorRegisters(bool SVERegs, std::span<const ARMEmitter::VRegister> VRegs);
+  void PopGeneralRegisters(std::span<const ARMEmitter::Register> Regs);

-  void PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg);
+  void PushDynamicRegsAndLR(ARMEmitter::Register TmpReg);
  void PopDynamicRegsAndLR();

  void PushCalleeSavedRegisters();
@@ -146,14 +144,13 @@ protected:
  // Callee Saved:
  // - X9-X15, X19-X31
  // - Low 128-bits of v8-v31
-  void SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true);
+  void SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs = true);
  void FillForPreserveAllABICall(bool FPRs = true);

-  void SpillForABICall(bool SupportsPreserveAllABI, FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true) {
+  void SpillForABICall(bool SupportsPreserveAllABI, ARMEmitter::Register TmpReg, bool FPRs = true) {
    if (SupportsPreserveAllABI) {
      SpillForPreserveAllABICall(TmpReg, FPRs);
-    }
-    else {
+    } else {
      SpillStaticRegs(TmpReg, FPRs);
      PushDynamicRegsAndLR(TmpReg);
    }
@@ -162,8 +159,7 @@ protected:
  void FillForABICall(bool SupportsPreserveAllABI, bool FPRs = true) {
    if (SupportsPreserveAllABI) {
      FillForPreserveAllABICall(FPRs);
-    }
-    else {
+    } else {
      PopDynamicRegsAndLR();
      FillStaticRegs(FPRs);
    }
@@ -185,8 +181,7 @@ protected:

  template<typename R, typename... P>
  void GenerateRuntimeCall(R (*Function)(P...)) {
-    uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(vixl::aarch64::Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));
+    uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(&(vixl::aarch64::Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));

    uintptr_t FunctionAddress = reinterpret_cast<uintptr_t>(Function);

@@ -204,8 +199,7 @@ protected:

  template<typename R, typename... P>
  void GenerateIndirectRuntimeCall(ARMEmitter::Register Reg) {
-    uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(vixl::aarch64::Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));
+    uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(&(vixl::aarch64::Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));

    hlt(vixl::aarch64::kIndirectRuntimeCallOpcode);

@@ -221,8 +215,8 @@ protected:

  template<>
  void GenerateIndirectRuntimeCall<float, __uint128_t>(ARMEmitter::Register Reg) {
-    uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(vixl::aarch64::Simulator::RuntimeCallStructHelper<float, __uint128_t>::Wrapper));
+    uintptr_t SimulatorWrapperAddress =
+      reinterpret_cast<uintptr_t>(&(vixl::aarch64::Simulator::RuntimeCallStructHelper<float, __uint128_t>::Wrapper));

    hlt(vixl::aarch64::kIndirectRuntimeCallOpcode);

@@ -262,4 +256,4 @@ protected:
 #endif
 };

-}
+} // namespace FEXCore::CPU
@@ -1,106 +0,0 @@
-// SPDX-License-Identifier: MIT
-#pragma once
-#include <cstddef>
-#include <cstdint>
-#include <cstring>
-
-namespace FEXCore::ARMEmitter {
-  class Buffer {
-    public:
-      Buffer() {
-        SetBuffer(nullptr, 0);
-      }
-
-      Buffer(uint8_t* Base, uint64_t BaseSize) {
-        SetBuffer(Base, BaseSize);
-      }
-
-      void SetBuffer(uint8_t* Base, uint64_t BaseSize) {
-        BufferBase = Base;
-        CurrentOffset = BufferBase;
-        Size = BaseSize;
-      }
-
-      void dc8(uint8_t Data) {
-        decltype(Data) *Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
-        *Memory = Data;
-        CurrentOffset += sizeof(Data);
-      }
-
-      void dc16(uint16_t Data) {
-        decltype(Data) *Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
-        *Memory = Data;
-        CurrentOffset += sizeof(Data);
-      }
-
-      void dc32(uint32_t Data) {
-        decltype(Data) *Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
-        *Memory = Data;
-        CurrentOffset += sizeof(Data);
-      }
-
-      void dc64(uint64_t Data) {
-        decltype(Data) *Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
-        *Memory = Data;
-        CurrentOffset += sizeof(Data);
-      }
-      void EmitString(const char *String) {
-        const auto StringLength = strlen(String);
-        memcpy(CurrentOffset, String, StringLength);
-        CurrentOffset += StringLength;
-      }
-
-      void Align() {
-        // Align the buffer to instruction size
-        auto CurrentAlignment = reinterpret_cast<uint64_t>(CurrentOffset) & 0b11;
-        if (!CurrentAlignment) {
-          return;
-        }
-        CurrentOffset += 4 - CurrentAlignment;
-      }
-
-      template<typename T>
-      T GetCursorAddress() const {
-        return reinterpret_cast<T>(CurrentOffset);
-      }
-
-      static void ClearICache(void* Begin, std::size_t Length) {
-        __builtin___clear_cache(static_cast<char*>(Begin), static_cast<char*>(Begin) + Length);
-      }
-
-      size_t GetCursorOffset() const {
-        return static_cast<size_t>(CurrentOffset - BufferBase);
-      }
-
-      uint8_t *GetBufferBase() const {
-        return BufferBase;
-      }
-
-      void CursorIncrement(size_t Size) {
-        CurrentOffset += Size;
-      }
-
-      void SetCursorOffset(size_t Offset) {
-        CurrentOffset = BufferBase + Offset;
-      }
-
-      uint64_t GetBufferSize() const {
-        return Size;
-      }
-
-      template<typename T>
-      size_t GetCursorOffsetFromAddress(const T* Address) const {
-        return static_cast<size_t>(reinterpret_cast<const uint8_t*>(Address) - BufferBase);
-      }
-
-    protected:
-
-      void ResetBuffer() {
-        CurrentOffset = BufferBase;
-      }
-
-      uint8_t* BufferBase;
-      uint8_t* CurrentOffset;
-      uint64_t Size;
-  };
-}
@@ -1,850 +0,0 @@
-// SPDX-License-Identifier: MIT
-#pragma once
-
-#include "Interface/Core/ArchHelpers/CodeEmitter/Buffer.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
-
-#include <FEXCore/Utils/CompilerDefs.h>
-#include <FEXCore/Utils/EnumUtils.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/MathUtils.h>
-#include <FEXCore/fextl/vector.h>
-
-#include <FEXHeaderUtils/BitUtils.h>
-
-#include <aarch64/assembler-aarch64.h>
-
-#include <array>
-#include <cstdint>
-#include <utility>
-#include <type_traits>
-
-/*
- * Welcome to FEX-Emu's custom AArch64 emitter.
- * This was written specifically to avoid the performance cost of the vixl emitter.
- *
- * There are some specific design constraints in this design to target a couple features:
- *   - High performance
- *   - Low CPU cache performance hit
- *   - Significantly reduced code footprint
- *   - Low number of branches
- *
- * These requirements are mostly achieved by removing a bunch of developer conveniences
- * that vixl provides. The developer needs to take a lot of care to not shoot themselves in the foot.
- *
- * Misc design decisions:
- * - Registers are encoded as basic uint32_t enums.
- *   - Converting between different registers is zero-cost.
- *   - Passing around as arguments are as cheap as registers
- *     - Contrast to vixl where every register requires living on the stack.
- *   - Registers can get encoded in to instructions with a simple `BFM` instruction.
- *
- * - Instructions are very simply emitted, allowing direct inlining most of the time.
- *   - These are simple enough that multiple back-to-back instructions get optimized to 128-bit load-store operations.
- *     - Contrast to vixl where pretty much no instruction emitter gets inlined.
- *
- * - Instruction emitters are /mostly/ unsized. Most instructions take a size argument first, which gets encoded
- *   directly in to the instruction.
- *   - Contrast to vixl where the register arguments are how the instructions determine operating size.
- *   - Size argument allows FEX to use `CSEL` to select a size at runtime, instead of branching.
- *   - Some instructions are explicitly sized based on register type. Read comments in the respective `inl` files to
- *     see why.
- *     Some scalar/vector operations are an example of this.
- *
- * - Almost zero helper functions.
- *   - Primary exception to this rule is load-store operations. These will use a helper to make
- *     it easier to select the correct load-store instruction. Mostly because these are a nightmare selecting
- *     the right instruction.
- */
-namespace FEXCore::ARMEmitter {
-  /*
-   * This `Size` enum is used for most ALU operations.
-   * These follow the AArch64 encoding style in most cases.
-   */
-  enum class Size : uint32_t {
-    i32Bit = 0,
-    i64Bit,
-  };
-
-  // This allows us to get the `Size` enum in bits.
-  [[nodiscard]]
-  constexpr size_t RegSizeInBits(Size size) {
-    return size_t{32} << FEXCore::ToUnderlying(size);
-  }
-
-  /* This `SubRegSize` enum is used for most ASIMD operations.
-   * These follow the AArch64 encoding style in most cases.
-   */
-  enum class SubRegSize : uint32_t {
-    i8Bit   = 0b00,
-    i16Bit  = 0b01,
-    i32Bit  = 0b10,
-    i64Bit  = 0b11,
-    i128Bit = 0b100,
-  };
-
-  // This allows us to get the `SubRegSize` in bits.
-  [[nodiscard]]
-  constexpr size_t SubRegSizeInBits(SubRegSize size) {
-    return size_t{8} << FEXCore::ToUnderlying(size);
-  }
-
-  /* This `ScalarRegSize` enum is used for most scalar float
-   * operations.
-   *
-   * This is specifically duplicated from `SubRegSize` to have strongly
-   * typed functions.
-   *
-   * `ScalarRegSize` specifically doesn't have `i128Bit` because scalar operations
-   * can't operate at 128-bit.
-   */
-  enum class ScalarRegSize : uint32_t {
-    i8Bit   = 0b00,
-    i16Bit  = 0b01,
-    i32Bit  = 0b10,
-    i64Bit  = 0b11,
-  };
-
-  // This allows us to get the `ScalarRegSize` in bits.
-  [[nodiscard]]
-  constexpr size_t ScalarRegSizeInBits(ScalarRegSize size) {
-    return size_t{8} << FEXCore::ToUnderlying(size);
-  }
-
-  /* This `VectorRegSizePair` union allows us to have an overlapping type
-   * to select a scalar operation or a vector depending on which operation
-   * we pass in.
-   * Useful in FEX's vector operations that behave as scalar or vector
-   * depending on various factors. But since the operation will have the sa,e
-   * element size, we want to choose the operation more easily
-   */
-  union VectorRegSizePair {
-    ScalarRegSize Scalar;
-    SubRegSize Vector;
-  };
-
-  // This allows us to create a `VectorRegSizePair` union.
-  [[nodiscard]]
-  constexpr VectorRegSizePair ToVectorSizePair(SubRegSize size) {
-    return VectorRegSizePair {.Vector = size};
-  }
-  [[nodiscard]]
-  constexpr VectorRegSizePair ToVectorSizePair(ScalarRegSize size) {
-    return VectorRegSizePair {.Scalar = size};
-  }
-
-  // This `ShiftType` enum is used for ALU shift-register encoded instructions.
-  enum class ShiftType : uint32_t {
-    LSL = 0,
-    LSR,
-    ASR,
-    ROR,
-  };
-
-  // This `ExtendedType` enum is used for ALU extended-register encoded instructions.
-  enum class ExtendedType : uint32_t {
-    UXTB = 0b000,
-    UXTH = 0b001,
-    UXTW = 0b010,
-    UXTX = 0b011,
-    SXTB = 0b100,
-    SXTH = 0b101,
-    SXTW = 0b110,
-    SXTX = 0b111,
-    LSL_32 = UXTW,
-    LSL_64 = UXTX,
-  };
-
-  // This `Condition` enum is used for various conditional instructions.
-  enum class Condition : uint32_t {
-    // Meaning:   Int                    - Float
-    CC_EQ = 0, // Equal                  - Equal
-    CC_NE,     // Not Eq                 - Not Eq or unordered
-    CC_CS,     // Carry set              - Greater than, equal, or unordered
-    CC_CC,     // Carry clear            - Less than
-    CC_MI,     // Minus/Negative         - Less than
-    CC_PL,     // Plus, positive or zero - GT, equal, or unordered
-    CC_VS,     // Overflow               - Unordered
-    CC_VC,     // No Overflow            - Ordered
-    CC_HI,     // Unsigned higher        - GT, or unordered
-    CC_LS,     // Unsigned lower or same - LT or EQ
-    CC_GE,     // Signed GT or EQ        - GT or EQ
-    CC_LT,     // Signed LT              - LT or Unordered
-    CC_GT,     // Signed GT              - GT
-    CC_LE,     // Signed LT or EQ        - LT, EQ, or Unordered
-    CC_AL,     // Always                 - Always
-    CC_NV,     // Always                 - Always
-
-    // Aliases
-    CC_HS = CC_CS,
-    CC_LO = CC_CC,
-  };
-
-  /*
-   * This `StatusFlags` enum is used for conditional compare encoded instructions.
-   * These directly encode to the `nzcv` flags.
-   */
-  enum class StatusFlags : uint32_t {
-    None = 0,
-    Flag_V = 0b0001,
-    Flag_C = 0b0010,
-    Flag_Z = 0b0100,
-    Flag_N = 0b1000,
-
-    Flag_NZCV = Flag_N | Flag_Z | Flag_C | Flag_V,
-  };
-
-
-  /*
-   * This `IndexType` enum is used for load-store instructions.
-   * Not all load-store instructions use this, so the user needs to be careful.
-   */
-  enum class IndexType {
-    POST,
-    OFFSET,
-    PRE,
-
-    UNPRIVILEGED,
-  };
-
-  // Used with adr and scalar + vector load/store variants to denote
-  // a modifier operation.
-  enum class SVEModType : uint8_t {
-    MOD_UXTW,
-    MOD_SXTW,
-    MOD_LSL,
-    MOD_NONE,
-  };
-
-  /* This `SVEMemOperand` class is used for the helper SVE load-store instructions.
-   * Load-store instructions are quite expressive, so having a helper that handles these differences is worth it.
-   */
-  class SVEMemOperand final {
-    public:
-      enum class Type {
-        ScalarPlusScalar,
-        ScalarPlusImm,
-        ScalarPlusVector,
-        VectorPlusImm,
-      };
-
-      SVEMemOperand(XRegister rn, XRegister rm = XReg::zr)
-        : rn {rn}
-        , MemType{Type::ScalarPlusScalar}
-        , MetaType {
-          .ScalarScalarType {
-            .rm = rm,
-          }
-        } {}
-      SVEMemOperand(XRegister rn, int32_t imm = 0)
-        : rn {rn}
-        , MemType{Type::ScalarPlusImm}
-        , MetaType {
-          .ScalarImmType {
-            .Imm = imm,
-          }
-        } {}
-      SVEMemOperand(XRegister rn, ZRegister zm, SVEModType mod = SVEModType::MOD_NONE, uint8_t scale = 0)
-        : rn{rn}
-        , MemType{Type::ScalarPlusVector}
-        , MetaType {
-          .ScalarVectorType {
-            .zm = zm,
-            .mod = mod,
-            .scale = scale,
-          }
-        } {}
-      SVEMemOperand(ZRegister zn, uint32_t imm)
-        : rn{Register{zn.Idx()}}
-        , MemType{Type::VectorPlusImm}
-        , MetaType {
-          .VectorImmType{
-            .Imm = imm,
-          }
-        } {}
-
-      [[nodiscard]] bool IsScalarPlusScalar() const {
-        return MemType == Type::ScalarPlusScalar;
-      }
-      [[nodiscard]] bool IsScalarPlusImm() const {
-        return MemType == Type::ScalarPlusImm;
-      }
-      [[nodiscard]] bool IsScalarPlusVector() const {
-        return MemType == Type::ScalarPlusVector;
-      }
-      [[nodiscard]] bool IsVectorPlusImm() const {
-        return MemType == Type::VectorPlusImm;
-      }
-
-      union Data {
-        struct {
-          Register rm;
-        } ScalarScalarType;
-
-        struct {
-          int32_t Imm;
-        } ScalarImmType;
-
-        struct {
-          ZRegister zm;
-          SVEModType mod;
-          uint8_t scale;
-        } ScalarVectorType;
-
-        struct {
-          // rn will be a ZRegister
-          uint32_t Imm;
-        } VectorImmType;
-      };
-
-      Register rn;
-      Type MemType;
-      Data MetaType;
-  };
-
-  /* This `ExtendedMemOperand` class is used for the helper load-store instructions.
-   * Load-store instructions are quite expressive, so having a helper that handles these differences is worth it.
-   */
-  class ExtendedMemOperand final {
-    public:
-      ExtendedMemOperand(XRegister rn, XRegister rm = XReg::zr, ExtendedType Option = ExtendedType::LSL_64, uint32_t Shift = 0)
-        : rn {rn}
-        , MetaType {
-          .ExtendedType {
-            .Header = { .MemType = TYPE_EXTENDED },
-            .rm = rm,
-            .Option = Option,
-            .Shift = Shift,
-          }
-        } {}
-      ExtendedMemOperand(XRegister rn, IndexType Index = IndexType::OFFSET, int32_t Imm = 0)
-        : rn {rn}
-        , MetaType {
-          .ImmType {
-            .Header = { .MemType = TYPE_IMM },
-            .Index = Index,
-            .Imm = Imm,
-          }
-        } {}
-
-      Register rn;
-      enum Type {
-        TYPE_EXTENDED,
-        TYPE_IMM,
-      };
-      struct HeaderStruct {
-        Type MemType;
-      };
-      union {
-        HeaderStruct Header;
-        struct {
-          HeaderStruct Header;
-          Register rm;
-          ExtendedType Option;
-          uint32_t Shift;
-        } ExtendedType;
-        struct {
-          HeaderStruct Header;
-          IndexType Index;
-          int32_t Imm;
-        } ImmType;
-      } MetaType;
-  };
-
-  template<uint32_t op0, uint32_t op1, uint32_t CRn, uint32_t CRm, uint32_t op2>
-  constexpr uint32_t GenSystemReg() {
-    return op0 << 19 |
-      op1 << 16 |
-      CRn << 12 |
-      CRm << 8 |
-      op2 << 5;
-  };
-
-  // This `SystemRegister` enum is used for the mrs/msr instructions.
-  enum class SystemRegister : uint32_t {
-    CTR_EL0    = GenSystemReg<0b11, 0b011, 0b0000, 0b0000, 0b001>(),
-    DCZID_EL0  = GenSystemReg<0b11, 0b011, 0b0000, 0b0000, 0b111>(),
-    TPIDR_EL0  = GenSystemReg<0b11, 0b011, 0b1101, 0b0000, 0b010>(),
-    RNDR       = GenSystemReg<0b11, 0b011, 0b0010, 0b0100, 0b000>(),
-    RNDRRS     = GenSystemReg<0b11, 0b011, 0b0010, 0b0100, 0b001>(),
-    NZCV       = GenSystemReg<0b11, 0b011, 0b0100, 0b0010, 0b000>(),
-    FPCR       = GenSystemReg<0b11, 0b011, 0b0100, 0b0100, 0b000>(),
-    CNTFRQ_EL0 = GenSystemReg<0b11, 0b011, 0b1110, 0b0000, 0b000>(),
-    CNTVCT_EL0 = GenSystemReg<0b11, 0b011, 0b1110, 0b0000, 0b010>(),
-  };
-
-  template<uint32_t op1, uint32_t CRm, uint32_t op2>
-  constexpr uint32_t GenDCReg() {
-    return op1 << 16 |
-      CRm << 8 |
-      op2 << 5;
-  };
-
-  // This `DataCacheOperation` enum is used for the dc instruction.
-  enum class DataCacheOperation : uint32_t {
-    IVAC  = GenDCReg<0b000, 0b0110, 0b001>(),
-    ISW   = GenDCReg<0b000, 0b0110, 0b010>(),
-    CSW   = GenDCReg<0b000, 0b1010, 0b010>(),
-    CISW  = GenDCReg<0b000, 0b1110, 0b010>(),
-    ZVA   = GenDCReg<0b011, 0b0100, 0b001>(),
-    CVAC  = GenDCReg<0b011, 0b1010, 0b001>(),
-    CVAU  = GenDCReg<0b011, 0b1011, 0b001>(),
-    CIVAC = GenDCReg<0b011, 0b1110, 0b001>(),
-
-    // MTE2
-    IGVAC  = GenDCReg<0b000, 0b0110, 0b011>(),
-    IGSW   = GenDCReg<0b000, 0b0110, 0b100>(),
-    IGDVAC = GenDCReg<0b000, 0b0110, 0b101>(),
-    IGDSW  = GenDCReg<0b000, 0b0110, 0b110>(),
-    CGSW   = GenDCReg<0b000, 0b1010, 0b100>(),
-    CGDSW  = GenDCReg<0b000, 0b1010, 0b110>(),
-    CIGSW  = GenDCReg<0b000, 0b1110, 0b100>(),
-    CIGDSW = GenDCReg<0b000, 0b1110, 0b110>(),
-
-    // MTE
-    GVA      = GenDCReg<0b011, 0b0100, 0b011>(),
-    GZVA     = GenDCReg<0b011, 0b0100, 0b100>(),
-    CGVAC    = GenDCReg<0b011, 0b1010, 0b011>(),
-    CGDVAC   = GenDCReg<0b011, 0b1010, 0b101>(),
-    CGVAP    = GenDCReg<0b011, 0b1100, 0b011>(),
-    CGDVAP   = GenDCReg<0b011, 0b1100, 0b101>(),
-    CGVADP   = GenDCReg<0b011, 0b1101, 0b011>(),
-    CGDVADP  = GenDCReg<0b011, 0b1101, 0b101>(),
-    CIGVAC   = GenDCReg<0b011, 0b1110, 0b011>(),
-    CIGDVAC  = GenDCReg<0b011, 0b1110, 0b101>(),
-
-    // DPB
-    CVAP = GenDCReg<0b011, 0b1100, 0b001>(),
-
-    // DPB2
-    CVADP = GenDCReg<0b011, 0b1101, 0b001>(),
-  };
-
-  template<uint32_t CRm, uint32_t op2>
-  constexpr uint32_t GenHintBarrierReg() {
-    return CRm << 8 |
-      op2 << 5;
-  }
-
-  // This `HintRegister` enum is used for the hint instruction.
-  enum class HintRegister : uint32_t {
-    NOP   = GenHintBarrierReg<0b0000, 0b000>(),
-    YIELD = GenHintBarrierReg<0b0000, 0b001>(),
-    WFE   = GenHintBarrierReg<0b0000, 0b010>(),
-    WFI   = GenHintBarrierReg<0b0000, 0b011>(),
-    SEV   = GenHintBarrierReg<0b0000, 0b100>(),
-    SEVL  = GenHintBarrierReg<0b0000, 0b101>(),
-    DGH   = GenHintBarrierReg<0b0000, 0b110>(),
-    CSDB  = GenHintBarrierReg<0b0010, 0b100>(),
-  };
-
-  // This `BarrierRegister` enum is used for the various barrier instructions.
-  enum class BarrierRegister : uint32_t {
-    CLREX   = GenHintBarrierReg<0b0000, 0b010>(),
-    TCOMMIT = GenHintBarrierReg<0b0000, 0b011>(),
-    DSB     = GenHintBarrierReg<0b0000, 0b100>(),
-    DMB     = GenHintBarrierReg<0b0000, 0b101>(),
-    ISB     = GenHintBarrierReg<0b0000, 0b110>(),
-    SB      = GenHintBarrierReg<0b0000, 0b111>(),
-  };
-
-  // This `BarrierScope` enum is used for the dsb/dmb instructions.
-  enum class BarrierScope : uint32_t {
-    // Outer shareable
-    OSHLD  = 0b0001,
-    OSHST  = 0b0010,
-    OSH    = 0b0011,
-    // Non shareable
-    NSHLD  = 0b0101,
-    NSHST  = 0b0110,
-    NSH    = 0b0111,
-    // Inner shareable
-    ISHLD  = 0b1001,
-    ISHST  = 0b1010,
-    ISH    = 0b1011,
-    // Full System visibility
-    LD     = 0b1101,
-    ST     = 0b1110,
-    SY     = 0b1111,
-  };
-
-  // This `Prefetch` enum is used for prefetch instructions.
-  enum class Prefetch : uint32_t {
-    // Prefetch for load
-    PLDL1KEEP = 0b00000,
-    PLDL1STRM = 0b00001,
-    PLDL2KEEP = 0b00010,
-    PLDL2STRM = 0b00011,
-    PLDL3KEEP = 0b00100,
-    PLDL3STRM = 0b00101,
-
-    // Preload instructions
-    PLIL1KEEP = 0b01000,
-    PLIL1STRM = 0b01001,
-    PLIL2KEEP = 0b01010,
-    PLIL2STRM = 0b01011,
-    PLIL3KEEP = 0b01100,
-    PLIL3STRM = 0b01101,
-
-    // Preload for store
-    PSTL1KEEP = 0b10000,
-    PSTL1STRM = 0b10001,
-    PSTL2KEEP = 0b10010,
-    PSTL2STRM = 0b10011,
-    PSTL3KEEP = 0b10100,
-    PSTL3STRM = 0b10101,
-  };
-
-  // This `PredicatePattern` enun is used for some SVE instructions.
-  enum class PredicatePattern : uint32_t {
-    SVE_POW2  = 0b00000,
-    SVE_VL1   = 0b00001,
-    SVE_VL2   = 0b00010,
-    SVE_VL3   = 0b00011,
-    SVE_VL4   = 0b00100,
-    SVE_VL5   = 0b00101,
-    SVE_VL6   = 0b00110,
-    SVE_VL7   = 0b00111,
-    SVE_VL8   = 0b01000,
-    SVE_VL16  = 0b01001,
-    SVE_VL32  = 0b01010,
-    SVE_VL64  = 0b01011,
-    SVE_VL128 = 0b01100,
-    SVE_VL256 = 0b01101,
-    SVE_MUL4  = 0b11101,
-    SVE_MUL3  = 0b11110,
-    SVE_ALL   = 0b11111,
-  };
-
-  // Used with SVE FP immediate arithmetic instructions
-  enum class SVEFAddSubImm : uint32_t {
-    _0_5,
-    _1_0,
-  };
-  enum class SVEFMulImm : uint32_t {
-    _0_5,
-    _2_0,
-  };
-  enum class SVEFMaxMinImm : uint32_t {
-    _0_0,
-    _1_0,
-  };
-
-  /* This `BackwardLabel` struct used for retaining a location for PC-Relative instructions.
-   * This is specifically a label for a target that is logically `below` an instruction that uses it.
-   * Which means that a branch would jump backwards.
-   */
-  struct BackwardLabel {
-    uint8_t *Location{};
-  };
-
-  /* This `SingleUseForwardLabel` struct used for retaining a location for PC-Relative instructions.
-   * This is specifically a label for a target that is logically `above` an instruction that uses it.
-   * Which means that a branch would jump forwards.
-   *
-   * The `ForwardLabel` struct can be bound to multiple instructions, so it needs a vector for each bind instruction type.
-   */
-  struct SingleUseForwardLabel {
-    enum class InstType {
-      UNKNOWN,
-      ADR,
-      ADRP,
-      B,
-      BC,
-      TEST_BRANCH,
-      RELATIVE_LOAD,
-      LONG_ADDRESS_GEN,
-    };
-    uint8_t *Location{};
-    InstType Type = InstType::UNKNOWN;
-  };
-
-  struct ForwardLabel {
-    fextl::vector<SingleUseForwardLabel> Insts{};
-  };
-
-  /* This `BiDirectionalLabel` struct used for retaining a location for PC-Relative instructions.
-   * This is specifically a label for a target that is in either direction of an instruction that uses it.
-   * Which means a branch could jump backwards or forwards depending on situation.
-   */
-  struct BiDirectionalLabel {
-    BackwardLabel Backward;
-    ForwardLabel Forward;
-  };
-
-  static inline void AddLocationToLabel(SingleUseForwardLabel *Label, SingleUseForwardLabel&& Location) {
-    LOGMAN_THROW_A_FMT(Label->Type == SingleUseForwardLabel::InstType::UNKNOWN, "Trying to bind a SingleUseForwardLabel to multiple locations. Use ForwardLabel instead.");
-    *Label = std::move(Location);
-  }
-
-  static inline void AddLocationToLabel(ForwardLabel *Label, SingleUseForwardLabel&& Location) {
-    Label->Insts.emplace_back(std::move(Location));
-  }
-
-  // Some FCMA ASIMD instructions support a rotation argument.
-  enum class Rotation : uint32_t {
-    ROTATE_0   = 0b00,
-    ROTATE_90  = 0b01,
-    ROTATE_180 = 0b10,
-    ROTATE_270 = 0b11,
-  };
-
-  // Concept for contraining some instructions to accept only an XRegister or WRegister.
-  // Particularly for operations that differ encodings depending on which one is used.
-  template <typename T>
-  concept IsXOrWRegister = std::is_same_v<T, XRegister> || std::is_same_v<T, WRegister>;
-
-  // Whether or not a given set of vector registers are sequential
-  // in increasing order as far as the register file is concerned (modulo its size)
-  //
-  // For example, a set of registers like:
-  //
-  // v1,  v2, v3 and
-  // v31, v0, v1
-  //
-  // would both be considered sequential sequences, and some instructions in particular
-  // limit register lists to these kind of sequences.
-  //
-  template <typename T, typename... Args>
-  constexpr bool AreVectorsSequential(T first, const Args&... args) {
-    // Ensure we always have a pair of registers to compare against.
-    static_assert(sizeof...(args) >= 1, "Number of arguments must be greater than 1");
-
-    const auto fn = [](auto& lhs, const auto& rhs) {
-      const auto result = ((lhs.Idx() + 1) % 32) == rhs.Idx();
-      lhs = rhs;
-      return result;
-    };
-
-    return (fn(first, args) && ...);
-  }
-
-  // This is an emitter that is designed around the smallest code bloat as possible.
-  // Eschewing most developer convenience in order to keep code as small as possible.
-
-  // Choices:
-  // - Size of ops passed as an argument rather than template to let the compiler use csel instead of branching.
-  // - Registers are unsized so they can be passed in a GPR and not need conversion operations
-  class Emitter : public FEXCore::ARMEmitter::Buffer {
-  public:
-    Emitter() = default;
-
-    Emitter(uint8_t* Base, uint64_t BaseSize)
-      : Buffer (Base, BaseSize) {
-    }
-
-    // Bind a backward label to an address.
-    // Address that is bound is the current emitter location.
-    void Bind(BackwardLabel *Label) {
-      LOGMAN_THROW_AA_FMT(Label->Location == nullptr, "Trying to bind a label twice");
-      Label->Location = GetCursorAddress<uint8_t*>();
-    }
-
-    void Bind(const SingleUseForwardLabel *Label) {
-      uint8_t *CurrentAddress = GetCursorAddress<uint8_t*>();
-      // Patch up the instructions
-      switch (Label->Type) {
-        case SingleUseForwardLabel::InstType::ADR: {
-          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
-          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-          LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large");
-          uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
-          uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
-          uint32_t Inst = *Instruction & ~InstMask;
-          Inst |= (Offset & 0b11) << 29;
-          Inst |= (Offset >> 2) << 5;
-          *Instruction = Inst;
-          break;
-        }
-        case SingleUseForwardLabel::InstType::ADRP: {
-          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
-          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-          LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large");
-          Imm >>= 12;
-          uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
-          uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
-          uint32_t Inst = *Instruction & ~InstMask;
-          Inst |= (Offset & 0b11) << 29;
-          Inst |= (Offset >> 2) << 5;
-          *Instruction = Inst;
-          break;
-        }
-
-        case SingleUseForwardLabel::InstType::B: {
-          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
-          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-          LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
-          Imm >>= 2;
-          uint32_t InstMask = 0x3FF'FFFF;
-          uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
-          uint32_t Inst = *Instruction & ~InstMask;
-          Inst |= Offset;
-          *Instruction = Inst;
-
-          break;
-        }
-
-        case SingleUseForwardLabel::InstType::TEST_BRANCH: {
-          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
-          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-          LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
-          Imm >>= 2;
-          uint32_t InstMask = 0x3FFF;
-          uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
-          uint32_t Inst = *Instruction & ~(InstMask << 5);
-          Inst |= Offset << 5;
-          *Instruction = Inst;
-
-          break;
-        }
-        case SingleUseForwardLabel::InstType::BC:
-        case SingleUseForwardLabel::InstType::RELATIVE_LOAD: {
-          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
-          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-          LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
-          Imm >>= 2;
-          uint32_t InstMask = 0x7'FFFF;
-          uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
-          uint32_t Inst = *Instruction & ~(InstMask << 5);
-          Inst |= Offset << 5;
-          *Instruction = Inst;
-          break;
-        }
-        case SingleUseForwardLabel::InstType::LONG_ADDRESS_GEN: {
-          uint32_t *Instructions = reinterpret_cast<uint32_t*>(Label->Location);
-          int64_t ImmInstOne = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[0]);
-          int64_t ImmInstTwo = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[1]);
-          auto OriginalOffset = GetCursorOffset();
-
-          auto InstOffset = GetCursorOffsetFromAddress(Instructions);
-          SetCursorOffset(InstOffset);
-
-          // We encoded the destination register in to the first instruction space.
-          // Read it back.
-          ARMEmitter::Register DestReg(Instructions[0]);
-
-          if (IsADRRange(ImmInstTwo)) {
-            // If within ADR range from the second instruction, then we can emit NOP+ADR
-            nop();
-            adr(DestReg, static_cast<uint32_t>(ImmInstTwo) & 0x7FFF);
-          }
-          else if (IsADRPRange(ImmInstOne)) {
-
-            // If within ADRP range from the first instruction, then we are /definitely/ in range for the second instruction.
-            // First check if we are in non-offset range for second instruction.
-            if (IsADRPAligned(reinterpret_cast<uint64_t>(CurrentAddress))) {
-              // We can emit nop + adrp
-              nop();
-              adrp(DestReg, static_cast<uint32_t>(ImmInstTwo >> 12) & 0x7FFF);
-            }
-            else {
-              // Not aligned, need adrp + add
-              adrp(DestReg, static_cast<uint32_t>(ImmInstOne >> 12) & 0x7FFF);
-              add(ARMEmitter::Size::i64Bit, DestReg, DestReg, ImmInstOne & 0xFFF);
-            }
-          }
-          else {
-            LOGMAN_MSG_A_FMT("Unscaled offset is too large");
-            FEX_UNREACHABLE;
-          }
-
-          SetCursorOffset(OriginalOffset);
-          break;
-        }
-        default: LOGMAN_MSG_A_FMT("Unexpected inst type in label fixup");
-      }
-    }
-
-    // Bind a forward label to a location.
-    // This walks all the instructions in the label's vector.
-    // Then backpatching all instructions that have used the label.
-    template<bool WarnAboutEmpty = false>
-    void Bind(ForwardLabel *Label) {
-      if constexpr (WarnAboutEmpty) {
-        LOGMAN_THROW_A_FMT(Label->Insts.empty() == false, "Binding forward label that didn't have any instructions using it");
-      }
-      for (auto &Inst : Label->Insts) {
-        Bind(&Inst);
-      }
-    }
-
-    // Bind a bidirectional location to a location.
-    // Binds both forwards and backwards depending on how the label was used.
-    void Bind(BiDirectionalLabel *Label) {
-      if (!Label->Backward.Location) {
-        Bind(&Label->Backward);
-      }
-      Bind<false>(&Label->Forward);
-    }
-
-  public:
-  // TODO: Implement SME when it matters.
-#include "Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/BranchOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/LoadstoreOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/SystemOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/ScalarOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/ASIMDOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl"
-
-  private:
-    template<typename T>
-    uint32_t Encode_ra(T Reg) const {
-      return Reg.Idx() << 10;
-    }
-    uint32_t Encode_ra(uint32_t Reg) const {
-      return Reg << 10;
-    }
-    template<typename T>
-    uint32_t Encode_rt2(T Reg) const {
-      return Reg.Idx() << 10;
-    }
-    template<>
-    uint32_t Encode_rt2(uint32_t Reg) const {
-      return Reg << 10;
-    }
-    template<typename T>
-    uint32_t Encode_rm(T Reg) const {
-      return Reg.Idx() << 16;
-    }
-    uint32_t Encode_rm(uint32_t Reg) const {
-      return Reg << 16;
-    }
-    template<typename T>
-    uint32_t Encode_rs(T Reg) const {
-      return Reg.Idx() << 16;
-    }
-    uint32_t Encode_rs(uint32_t Reg) const {
-      return Reg << 16;
-    }
-    template<typename T>
-    uint32_t Encode_rn(T Reg) const {
-      return Reg.Idx() << 5;
-    }
-    uint32_t Encode_rn(uint32_t Reg) const {
-      return Reg << 5;
-    }
-    template<typename T>
-    uint32_t Encode_rd(T Reg) const {
-      return Reg.Idx();
-    }
-    uint32_t Encode_rd(uint32_t Reg) const {
-      return Reg;
-    }
-    template<typename T>
-    uint32_t Encode_rt(T Reg) const {
-      return Reg.Idx();
-    }
-    template<>
-    uint32_t Encode_rt(Prefetch Reg) const {
-      return FEXCore::ToUnderlying(Reg);
-    }
-    uint32_t Encode_rt(uint32_t Reg) const {
-      return Reg;
-    }
-    template<typename T>
-    uint32_t Encode_pd(T Reg) const {
-      return FEXCore::ToUnderlying(Reg);
-    }
-  };
-}
@@ -6,48 +6,46 @@
 #include <utility>

 namespace FEXCore {
-  void BlockSamplingData::DumpBlockData() {
-    std::fstream Output;
-    Output.open("output.csv", std::fstream::out | std::fstream::binary);
+void BlockSamplingData::DumpBlockData() {
+  std::fstream Output;
+  Output.open("output.csv", std::fstream::out | std::fstream::binary);

-    if (!Output.is_open())
-      return;
-
-    Output << "Entry, Min, Max, Total, Calls, Average" << std::endl;
-
-    for (auto it : SamplingMap) {
-      if (!it.second->TotalCalls)
-        continue;
-
-      Output << "0x" << std::hex << it.first
-             << ", " << std::dec << it.second->Min
-             << ", " << std::dec << it.second->Max
-             << ", " << std::dec << it.second->TotalTime
-             << ", " << std::dec << it.second->TotalCalls
-             << ", " << std::dec << ((double)it.second->TotalTime / (double)it.second->TotalCalls)
-             << std::endl;
-    }
-    Output.close();
-    LogMan::Msg::DFmt("Dumped {} blocks of sampling data", SamplingMap.size());
+  if (!Output.is_open()) {
+    return;
  }

-  BlockSamplingData::BlockData *BlockSamplingData::GetBlockData(uint64_t RIP) {
-    auto it = SamplingMap.find(RIP);
-    if (it != SamplingMap.end()) {
-      return it->second;
-    }
-    BlockData *NewData = new BlockData{};
-    memset(NewData, 0, sizeof(BlockData));
-    NewData->Min = ~0ULL;
-    SamplingMap[RIP] = NewData;
-    return NewData;
-  }
+  Output << "Entry, Min, Max, Total, Calls, Average" << std::endl;

-  BlockSamplingData::~BlockSamplingData() {
-    DumpBlockData();
-    for (auto it : SamplingMap) {
-      delete it.second;
+  for (auto it : SamplingMap) {
+    if (!it.second->TotalCalls) {
+      continue;
    }
-    SamplingMap.clear();
+
+    Output << "0x" << std::hex << it.first << ", " << std::dec << it.second->Min << ", " << std::dec << it.second->Max << ", " << std::dec
+           << it.second->TotalTime << ", " << std::dec << it.second->TotalCalls << ", " << std::dec
+           << ((double)it.second->TotalTime / (double)it.second->TotalCalls) << std::endl;
  }
+  Output.close();
+  LogMan::Msg::DFmt("Dumped {} blocks of sampling data", SamplingMap.size());
 }
+
+BlockSamplingData::BlockData* BlockSamplingData::GetBlockData(uint64_t RIP) {
+  auto it = SamplingMap.find(RIP);
+  if (it != SamplingMap.end()) {
+    return it->second;
+  }
+  BlockData* NewData = new BlockData {};
+  memset(NewData, 0, sizeof(BlockData));
+  NewData->Min = ~0ULL;
+  SamplingMap[RIP] = NewData;
+  return NewData;
+}
+
+BlockSamplingData::~BlockSamplingData() {
+  DumpBlockData();
+  for (auto it : SamplingMap) {
+    delete it.second;
+  }
+  SamplingMap.clear();
+}
+} // namespace FEXCore
@@ -14,7 +14,7 @@ public:
    uint64_t TotalCalls;
  };

-  BlockData *GetBlockData(uint64_t RIP);
+  BlockData* GetBlockData(uint64_t RIP);
  ~BlockSamplingData();

  void DumpBlockData();
@@ -22,4 +22,4 @@ public:
 private:
  std::unordered_map<uint64_t, BlockData*> SamplingMap;
 };
-}
+} // namespace FEXCore
@@ -12,349 +12,330 @@
 namespace FEXCore {
 namespace CPU {

-constexpr static uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX][2] = {
-  {0x0003'0002'0001'0000ULL, 0x0007'0006'0005'0004ULL}, // NAMED_VECTOR_INCREMENTAL_U16_INDEX
-  {0x000B'000A'0009'0008ULL, 0x000F'000E'000D'000CULL}, // NAMED_VECTOR_INCREMENTAL_U16_INDEX_UPPER
-  {0x0000'0000'8000'0000ULL, 0x0000'0000'8000'0000ULL}, // NAMED_VECTOR_PADDSUBPS_INVERT
-  {0x0000'0000'8000'0000ULL, 0x0000'0000'8000'0000ULL}, // NAMED_VECTOR_PADDSUBPS_INVERT_UPPER
-  {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT
-  {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT_UPPER
-  {0x0000'0001'0000'0000ULL, 0x0000'0003'0000'0002ULL}, // NAMED_VECTOR_MOVMSKPS_SHIFT
-  {0x040B'0E01'0B0E'0104ULL, 0x0C03'0609'0306'090CULL}, // NAMED_VECTOR_AESKEYGENASSIST_SWIZZLE
-  {0x0706'0504'FFFF'FFFFULL, 0xFFFF'FFFF'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_0110B
-  {0x0706'0504'0302'0100ULL, 0xFFFF'FFFF'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_0111B
-  {0xFFFF'FFFF'0302'0100ULL, 0x0F0E'0D0C'FFFF'FFFFULL}, // NAMED_VECTOR_BLENDPS_1001B
-  {0x0706'0504'0302'0100ULL, 0x0F0E'0D0C'FFFF'FFFFULL}, // NAMED_VECTOR_BLENDPS_1011B
-  {0xFFFF'FFFF'0302'0100ULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1101B
-  {0x0706'0504'FFFF'FFFFULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1110B
-  {0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB
-  {0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB_UPPER
-};
-
-constexpr static auto PSHUFLW_LUT {
-[]() consteval {
-  struct LUTType {
-    uint64_t Val[2];
-  };
-  // Expectation for this LUT is to simulate PSHUFLW with ARM's TBL (single register) instruction
-  // PSHUFLW behaviour:
-  // 16-bit words in [63:48], [47:32], [31:16], [15:0] are selected using the 8-bit Index.
-  // For 128-bit PSHUFLW, bits [127:64] are identity copied.
-  constexpr uint64_t IdentityCopyUpper = 0x0f'0e'0d'0c'0b'0a'09'08;
-  std::array<LUTType, 256> TotalLUT{};
-  uint64_t WordSelection[4] = {
-    0x01'00,
-    0x03'02,
-    0x05'04,
-    0x07'06,
-  };
-  for (size_t i = 0; i < 256; ++i) {
-    auto &LUT = TotalLUT[i];
-    const auto Word0 = (i >> 0) & 0b11;
-    const auto Word1 = (i >> 2) & 0b11;
-    const auto Word2 = (i >> 4) & 0b11;
-    const auto Word3 = (i >> 6) & 0b11;
-
-    LUT.Val[0] =
-      (WordSelection[Word0] << 0) |
-      (WordSelection[Word1] << 16) |
-      (WordSelection[Word2] << 32) |
-      (WordSelection[Word3] << 48);
-
-    LUT.Val[1] = IdentityCopyUpper;
-  }
-  return TotalLUT;
-}()
-};
-
-constexpr static auto PSHUFHW_LUT {
-[]() consteval {
-  struct LUTType {
-    uint64_t Val[2];
-  };
-  // Expectation for this LUT is to simulate PSHUFHW with ARM's TBL (single register) instruction
-  // PSHUFHW behaviour:
-  // 16-bit words in [127:112], [111:96], [95:80], [79:64] are selected using the 8-bit Index.
-  // Incoming words come from bits [127:64] of the source.
-  // Bits [63:0] are identity copied.
-  constexpr uint64_t IdentityCopyLower = 0x07'06'05'04'03'02'01'00;
-  std::array<LUTType, 256> TotalLUT{};
-  uint64_t WordSelection[4] = {
-    0x09'08,
-    0x0b'0a,
-    0x0d'0c,
-    0x0f'0e,
-  };
-  for (size_t i = 0; i < 256; ++i) {
-    auto &LUT = TotalLUT[i];
-    const auto Word0 = (i >> 0) & 0b11;
-    const auto Word1 = (i >> 2) & 0b11;
-    const auto Word2 = (i >> 4) & 0b11;
-    const auto Word3 = (i >> 6) & 0b11;
-
-    LUT.Val[0] = IdentityCopyLower;
-
-    LUT.Val[1] =
-      (WordSelection[Word0] << 0) |
-      (WordSelection[Word1] << 16) |
-      (WordSelection[Word2] << 32) |
-      (WordSelection[Word3] << 48);
-
-  }
-  return TotalLUT;
-}()
-};
-
-constexpr static auto PSHUFD_LUT {
-[]() consteval {
-  struct LUTType {
-    uint64_t Val[2];
-  };
-  // Expectation for this LUT is to simulate PSHUFD with ARM's TBL (single register) instruction
-  // PSHUFD behaviour:
-  // 32-bit words in [127:96], [95:64], [63:32], [31:0] are selected using the 8-bit Index.
-  std::array<LUTType, 256> TotalLUT{};
-  uint64_t WordSelection[4] = {
-    0x03'02'01'00,
-    0x07'06'05'04,
-    0x0b'0a'09'08,
-    0x0f'0e'0d'0c,
-  };
-  for (size_t i = 0; i < 256; ++i) {
-    auto &LUT = TotalLUT[i];
-    const auto Word0 = (i >> 0) & 0b11;
-    const auto Word1 = (i >> 2) & 0b11;
-    const auto Word2 = (i >> 4) & 0b11;
-    const auto Word3 = (i >> 6) & 0b11;
-
-    LUT.Val[0] =
-      (WordSelection[Word0] << 0) |
-      (WordSelection[Word1] << 32);
-
-    LUT.Val[1] =
-      (WordSelection[Word2] << 0) |
-      (WordSelection[Word3] << 32);
-  }
-  return TotalLUT;
-}()
-};
-
-constexpr static auto SHUFPS_LUT {
-[]() consteval {
-  struct LUTType {
-    uint64_t Val[2];
-  };
-  // 32-bit words in [127:96], [95:64], [63:32], [31:0] are selected using the 8-bit Index.
-  // Expectation for this LUT is to simulate SHUFPS with ARM's TBL (two register) instruction.
-  // SHUFPS behaviour:
-  // Two 32-bits words from each source are selected from each source in the lower and upper halves of the 128-bit destination.
-  // Dest[31:0]   = Src1[<Word0>]
-  // Dest[63:32]  = Src1[<Word1>]
-  // Dest[95:64]  = Src2[<Word2>]
-  // Dest[127:96] = Src2[<Word3>]
-
-  std::array<LUTType, 256> TotalLUT{};
-  const uint64_t WordSelectionSrc1[4] = {
-    0x03'02'01'00,
-    0x07'06'05'04,
-    0x0b'0a'09'08,
-    0x0f'0e'0d'0c,
+  constexpr static uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX][2] = {
+    {0x0003'0002'0001'0000ULL, 0x0007'0006'0005'0004ULL}, // NAMED_VECTOR_INCREMENTAL_U16_INDEX
+    {0x000B'000A'0009'0008ULL, 0x000F'000E'000D'000CULL}, // NAMED_VECTOR_INCREMENTAL_U16_INDEX_UPPER
+    {0x0000'0000'8000'0000ULL, 0x0000'0000'8000'0000ULL}, // NAMED_VECTOR_PADDSUBPS_INVERT
+    {0x0000'0000'8000'0000ULL, 0x0000'0000'8000'0000ULL}, // NAMED_VECTOR_PADDSUBPS_INVERT_UPPER
+    {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT
+    {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT_UPPER
+    {0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPS_INVERT
+    {0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPS_INVERT_UPPER
+    {0x0000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPD_INVERT
+    {0x0000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPD_INVERT_UPPER
+    {0x0000'0001'0000'0000ULL, 0x0000'0003'0000'0002ULL}, // NAMED_VECTOR_MOVMSKPS_SHIFT
+    {0x040B'0E01'0B0E'0104ULL, 0x0C03'0609'0306'090CULL}, // NAMED_VECTOR_AESKEYGENASSIST_SWIZZLE
+    {0x0706'0504'FFFF'FFFFULL, 0xFFFF'FFFF'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_0110B
+    {0x0706'0504'0302'0100ULL, 0xFFFF'FFFF'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_0111B
+    {0xFFFF'FFFF'0302'0100ULL, 0x0F0E'0D0C'FFFF'FFFFULL}, // NAMED_VECTOR_BLENDPS_1001B
+    {0x0706'0504'0302'0100ULL, 0x0F0E'0D0C'FFFF'FFFFULL}, // NAMED_VECTOR_BLENDPS_1011B
+    {0xFFFF'FFFF'0302'0100ULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1101B
+    {0x0706'0504'FFFF'FFFFULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1110B
+    {0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB
+    {0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB_UPPER
+    {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'3FFFULL}, // NAMED_VECTOR_X87_ONE
+    {0xD49A'784B'CD1B'8AFEULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_LOG2_10
+    {0xB8AA'3B29'5C17'F0BCULL, 0x0000'0000'0000'3FFFULL}, // NAMED_VECTOR_X87_LOG2_E
+    {0xC90F'DAA2'2168'C235ULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_PI
+    {0x9A20'9A84'FBCF'F799ULL, 0x0000'0000'0000'3FFDULL}, // NAMED_VECTOR_X87_LOG10_2
+    {0xB172'17F7'D1CF'79ACULL, 0x0000'0000'0000'3FFEULL}, // NAMED_VECTOR_X87_LOG_2
  };

-  // Src2 needs to offset each byte index by 16-bytes to pull from the second source.
-  const uint64_t WordSelectionSrc2[4] = {
-    0x03'02'01'00 + (0x10101010),
-    0x07'06'05'04 + (0x10101010),
-    0x0b'0a'09'08 + (0x10101010),
-    0x0f'0e'0d'0c + (0x10101010),
-  };
-
-  for (size_t i = 0; i < 256; ++i) {
-    auto &LUT = TotalLUT[i];
-    const auto Word0 = (i >> 0) & 0b11;
-    const auto Word1 = (i >> 2) & 0b11;
-    const auto Word2 = (i >> 4) & 0b11;
-    const auto Word3 = (i >> 6) & 0b11;
-
-    LUT.Val[0] =
-      (WordSelectionSrc1[Word0] << 0) |
-      (WordSelectionSrc1[Word1] << 32);
-
-    LUT.Val[1] =
-      (WordSelectionSrc2[Word2] << 0) |
-      (WordSelectionSrc2[Word3] << 32);
-  }
-  return TotalLUT;
-}()
-};
-
-constexpr static auto DPPS_MASK {
-[]() consteval {
-  struct LUTType {
-    uint32_t Val[4];
-  };
-
-  std::array<LUTType, 16> TotalLUT{};
-  for (size_t i = 0; i < TotalLUT.size(); ++i) {
-    auto &LUT = TotalLUT[i];
-    constexpr auto GetLUT = [](size_t i, size_t Index) {
-      if (i & (1U << Index)) {
-        return -1U;
-      }
-      return 0U;
+  constexpr static auto PSHUFLW_LUT {[]() consteval {
+    struct LUTType {
+      uint64_t Val[2];
    };
-
-    LUT.Val[0] = GetLUT(i, 0);
-    LUT.Val[1] = GetLUT(i, 1);
-    LUT.Val[2] = GetLUT(i, 2);
-    LUT.Val[3] = GetLUT(i, 3);
-  }
-  return TotalLUT;
-}()
-};
-
-constexpr static auto DPPD_MASK {
-[]() consteval {
-  struct LUTType {
-    uint64_t Val[2];
-  };
-
-  std::array<LUTType, 4> TotalLUT{};
-  for (size_t i = 0; i < TotalLUT.size(); ++i) {
-    auto &LUT = TotalLUT[i];
-    constexpr auto GetLUT = [](size_t i, size_t Index) {
-      if (i & (1U << Index)) {
-        return -1ULL;
-      }
-      return 0ULL;
+    // Expectation for this LUT is to simulate PSHUFLW with ARM's TBL (single register) instruction
+    // PSHUFLW behaviour:
+    // 16-bit words in [63:48], [47:32], [31:16], [15:0] are selected using the 8-bit Index.
+    // For 128-bit PSHUFLW, bits [127:64] are identity copied.
+    constexpr uint64_t IdentityCopyUpper = 0x0f'0e'0d'0c'0b'0a'09'08;
+    std::array<LUTType, 256> TotalLUT {};
+    uint64_t WordSelection[4] = {
+      0x01'00,
+      0x03'02,
+      0x05'04,
+      0x07'06,
    };
+    for (size_t i = 0; i < 256; ++i) {
+      auto& LUT = TotalLUT[i];
+      const auto Word0 = (i >> 0) & 0b11;
+      const auto Word1 = (i >> 2) & 0b11;
+      const auto Word2 = (i >> 4) & 0b11;
+      const auto Word3 = (i >> 6) & 0b11;

-    LUT.Val[0] = GetLUT(i, 0);
-    LUT.Val[1] = GetLUT(i, 1);
-  }
-  return TotalLUT;
-}()
-};
+      LUT.Val[0] = (WordSelection[Word0] << 0) | (WordSelection[Word1] << 16) | (WordSelection[Word2] << 32) | (WordSelection[Word3] << 48);

-constexpr static auto PBLENDW_LUT {
-[]() consteval {
-  struct LUTType {
-    uint16_t Val[8];
-  };
-  // 16-bit words in [127:112], [111:96], [95:80], [79:64], [63:48], [47:32], [31:16], [15:0] are selected using 8-bit swizzle.
-  // Expectation for this LUT is to simulate PBLENDW with ARM's TBX (one register) instruction.
-  // PBLENDW behaviour:
-  // 16-bit words from the source is moved in to the destination based on the bit in the swizzle.
-  // Dest[15:0]    = Swizzle[0] ? Src[15:0] : Dest[15:0]
-  // Dest[31:16]   = Swizzle[1] ? Src[31:16] : Dest[31:16]
-  // Dest[47:32]   = Swizzle[2] ? Src[47:32] : Dest[47:32]
-  // Dest[63:48]   = Swizzle[3] ? Src[63:48] : Dest[63:48]
-  // Dest[79:64]   = Swizzle[4] ? Src[79:64] : Dest[79:64]
-  // Dest[95:80]   = Swizzle[5] ? Src[95:80] : Dest[95:80]
-  // Dest[111:96]  = Swizzle[6] ? Src[111:96] : Dest[111:96]
-  // Dest[127:112] = Swizzle[7] ? Src[127:112] : Dest[127:112]
-
-  std::array<LUTType, 256> TotalLUT{};
-  const uint16_t WordSelectionSrc[8] = {
-    0x01'00,
-    0x03'02,
-    0x05'04,
-    0x07'06,
-    0x09'08,
-    0x0B'0A,
-    0x0D'0C,
-    0x0F'0E,
-  };
-
-  constexpr uint16_t OriginalDest = 0xFF'FF;
-
-  for (size_t i = 0; i < 256; ++i) {
-    auto &LUT = TotalLUT[i];
-    for (size_t j = 0; j < 8; ++j) {
-      LUT.Val[j] = ((i >> j) & 1) ? WordSelectionSrc[j] : OriginalDest;
+      LUT.Val[1] = IdentityCopyUpper;
    }
-  }
-  return TotalLUT;
-}()
-};
+    return TotalLUT;
+  }()};

-CPUBackend::CPUBackend(FEXCore::Core::InternalThreadState *ThreadState, size_t InitialCodeSize, size_t MaxCodeSize)
-    : ThreadState(ThreadState), InitialCodeSize(InitialCodeSize), MaxCodeSize(MaxCodeSize) {
+  constexpr static auto PSHUFHW_LUT {[]() consteval {
+    struct LUTType {
+      uint64_t Val[2];
+    };
+    // Expectation for this LUT is to simulate PSHUFHW with ARM's TBL (single register) instruction
+    // PSHUFHW behaviour:
+    // 16-bit words in [127:112], [111:96], [95:80], [79:64] are selected using the 8-bit Index.
+    // Incoming words come from bits [127:64] of the source.
+    // Bits [63:0] are identity copied.
+    constexpr uint64_t IdentityCopyLower = 0x07'06'05'04'03'02'01'00;
+    std::array<LUTType, 256> TotalLUT {};
+    uint64_t WordSelection[4] = {
+      0x09'08,
+      0x0b'0a,
+      0x0d'0c,
+      0x0f'0e,
+    };
+    for (size_t i = 0; i < 256; ++i) {
+      auto& LUT = TotalLUT[i];
+      const auto Word0 = (i >> 0) & 0b11;
+      const auto Word1 = (i >> 2) & 0b11;
+      const auto Word2 = (i >> 4) & 0b11;
+      const auto Word3 = (i >> 6) & 0b11;

-  auto &Common = ThreadState->CurrentFrame->Pointers.Common;
+      LUT.Val[0] = IdentityCopyLower;

-  // Initialize named vector constants.
-  for (size_t i = 0; i < FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX; ++i) {
-    Common.NamedVectorConstantPointers[i] = reinterpret_cast<uint64_t>(NamedVectorConstants[i]);
-  }
+      LUT.Val[1] = (WordSelection[Word0] << 0) | (WordSelection[Word1] << 16) | (WordSelection[Word2] << 32) | (WordSelection[Word3] << 48);
+    }
+    return TotalLUT;
+  }()};

-  // Copy named vector constants.
-  memcpy(Common.NamedVectorConstants, NamedVectorConstants, sizeof(NamedVectorConstants));
+  constexpr static auto PSHUFD_LUT {[]() consteval {
+    struct LUTType {
+      uint64_t Val[2];
+    };
+    // Expectation for this LUT is to simulate PSHUFD with ARM's TBL (single register) instruction
+    // PSHUFD behaviour:
+    // 32-bit words in [127:96], [95:64], [63:32], [31:0] are selected using the 8-bit Index.
+    std::array<LUTType, 256> TotalLUT {};
+    uint64_t WordSelection[4] = {
+      0x03'02'01'00,
+      0x07'06'05'04,
+      0x0b'0a'09'08,
+      0x0f'0e'0d'0c,
+    };
+    for (size_t i = 0; i < 256; ++i) {
+      auto& LUT = TotalLUT[i];
+      const auto Word0 = (i >> 0) & 0b11;
+      const auto Word1 = (i >> 2) & 0b11;
+      const auto Word2 = (i >> 4) & 0b11;
+      const auto Word3 = (i >> 6) & 0b11;

-  // Initialize Indexed named vector constants.
-  Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW] = reinterpret_cast<uint64_t>(PSHUFLW_LUT.data());
-  Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW] = reinterpret_cast<uint64_t>(PSHUFHW_LUT.data());
-  Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFD] = reinterpret_cast<uint64_t>(PSHUFD_LUT.data());
-  Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_SHUFPS] = reinterpret_cast<uint64_t>(SHUFPS_LUT.data());
-  Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPS_MASK] = reinterpret_cast<uint64_t>(DPPS_MASK.data());
-  Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPD_MASK] = reinterpret_cast<uint64_t>(DPPD_MASK.data());
-  Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PBLENDW] = reinterpret_cast<uint64_t>(PBLENDW_LUT.data());
+      LUT.Val[0] = (WordSelection[Word0] << 0) | (WordSelection[Word1] << 32);
+
+      LUT.Val[1] = (WordSelection[Word2] << 0) | (WordSelection[Word3] << 32);
+    }
+    return TotalLUT;
+  }()};
+
+  constexpr static auto SHUFPS_LUT {[]() consteval {
+    struct LUTType {
+      uint64_t Val[2];
+    };
+    // 32-bit words in [127:96], [95:64], [63:32], [31:0] are selected using the 8-bit Index.
+    // Expectation for this LUT is to simulate SHUFPS with ARM's TBL (two register) instruction.
+    // SHUFPS behaviour:
+    // Two 32-bits words from each source are selected from each source in the lower and upper halves of the 128-bit destination.
+    // Dest[31:0]   = Src1[<Word0>]
+    // Dest[63:32]  = Src1[<Word1>]
+    // Dest[95:64]  = Src2[<Word2>]
+    // Dest[127:96] = Src2[<Word3>]
+
+    std::array<LUTType, 256> TotalLUT {};
+    const uint64_t WordSelectionSrc1[4] = {
+      0x03'02'01'00,
+      0x07'06'05'04,
+      0x0b'0a'09'08,
+      0x0f'0e'0d'0c,
+    };
+
+    // Src2 needs to offset each byte index by 16-bytes to pull from the second source.
+    const uint64_t WordSelectionSrc2[4] = {
+      0x03'02'01'00 + (0x10101010),
+      0x07'06'05'04 + (0x10101010),
+      0x0b'0a'09'08 + (0x10101010),
+      0x0f'0e'0d'0c + (0x10101010),
+    };
+
+    for (size_t i = 0; i < 256; ++i) {
+      auto& LUT = TotalLUT[i];
+      const auto Word0 = (i >> 0) & 0b11;
+      const auto Word1 = (i >> 2) & 0b11;
+      const auto Word2 = (i >> 4) & 0b11;
+      const auto Word3 = (i >> 6) & 0b11;
+
+      LUT.Val[0] = (WordSelectionSrc1[Word0] << 0) | (WordSelectionSrc1[Word1] << 32);
+
+      LUT.Val[1] = (WordSelectionSrc2[Word2] << 0) | (WordSelectionSrc2[Word3] << 32);
+    }
+    return TotalLUT;
+  }()};
+
+  constexpr static auto DPPS_MASK {[]() consteval {
+    struct LUTType {
+      uint32_t Val[4];
+    };
+
+    std::array<LUTType, 16> TotalLUT {};
+    for (size_t i = 0; i < TotalLUT.size(); ++i) {
+      auto& LUT = TotalLUT[i];
+      constexpr auto GetLUT = [](size_t i, size_t Index) {
+        if (i & (1U << Index)) {
+          return -1U;
+        }
+        return 0U;
+      };
+
+      LUT.Val[0] = GetLUT(i, 0);
+      LUT.Val[1] = GetLUT(i, 1);
+      LUT.Val[2] = GetLUT(i, 2);
+      LUT.Val[3] = GetLUT(i, 3);
+    }
+    return TotalLUT;
+  }()};
+
+  constexpr static auto DPPD_MASK {[]() consteval {
+    struct LUTType {
+      uint64_t Val[2];
+    };
+
+    std::array<LUTType, 4> TotalLUT {};
+    for (size_t i = 0; i < TotalLUT.size(); ++i) {
+      auto& LUT = TotalLUT[i];
+      constexpr auto GetLUT = [](size_t i, size_t Index) {
+        if (i & (1U << Index)) {
+          return -1ULL;
+        }
+        return 0ULL;
+      };
+
+      LUT.Val[0] = GetLUT(i, 0);
+      LUT.Val[1] = GetLUT(i, 1);
+    }
+    return TotalLUT;
+  }()};
+
+  constexpr static auto PBLENDW_LUT {[]() consteval {
+    struct LUTType {
+      uint16_t Val[8];
+    };
+    // 16-bit words in [127:112], [111:96], [95:80], [79:64], [63:48], [47:32], [31:16], [15:0] are selected using 8-bit swizzle.
+    // Expectation for this LUT is to simulate PBLENDW with ARM's TBX (one register) instruction.
+    // PBLENDW behaviour:
+    // 16-bit words from the source is moved in to the destination based on the bit in the swizzle.
+    // Dest[15:0]    = Swizzle[0] ? Src[15:0] : Dest[15:0]
+    // Dest[31:16]   = Swizzle[1] ? Src[31:16] : Dest[31:16]
+    // Dest[47:32]   = Swizzle[2] ? Src[47:32] : Dest[47:32]
+    // Dest[63:48]   = Swizzle[3] ? Src[63:48] : Dest[63:48]
+    // Dest[79:64]   = Swizzle[4] ? Src[79:64] : Dest[79:64]
+    // Dest[95:80]   = Swizzle[5] ? Src[95:80] : Dest[95:80]
+    // Dest[111:96]  = Swizzle[6] ? Src[111:96] : Dest[111:96]
+    // Dest[127:112] = Swizzle[7] ? Src[127:112] : Dest[127:112]
+
+    std::array<LUTType, 256> TotalLUT {};
+    const uint16_t WordSelectionSrc[8] = {
+      0x01'00, 0x03'02, 0x05'04, 0x07'06, 0x09'08, 0x0B'0A, 0x0D'0C, 0x0F'0E,
+    };
+
+    constexpr uint16_t OriginalDest = 0xFF'FF;
+
+    for (size_t i = 0; i < 256; ++i) {
+      auto& LUT = TotalLUT[i];
+      for (size_t j = 0; j < 8; ++j) {
+        LUT.Val[j] = ((i >> j) & 1) ? WordSelectionSrc[j] : OriginalDest;
+      }
+    }
+    return TotalLUT;
+  }()};
+
+  CPUBackend::CPUBackend(FEXCore::Core::InternalThreadState* ThreadState, size_t InitialCodeSize, size_t MaxCodeSize)
+    : ThreadState(ThreadState)
+    , InitialCodeSize(InitialCodeSize)
+    , MaxCodeSize(MaxCodeSize) {
+
+    auto& Common = ThreadState->CurrentFrame->Pointers.Common;
+
+    // Initialize named vector constants.
+    for (size_t i = 0; i < FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX; ++i) {
+      Common.NamedVectorConstantPointers[i] = reinterpret_cast<uint64_t>(NamedVectorConstants[i]);
+    }
+
+    // Copy named vector constants.
+    memcpy(Common.NamedVectorConstants, NamedVectorConstants, sizeof(NamedVectorConstants));
+
+    // Initialize Indexed named vector constants.
+    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW] =
+      reinterpret_cast<uint64_t>(PSHUFLW_LUT.data());
+    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW] =
+      reinterpret_cast<uint64_t>(PSHUFHW_LUT.data());
+    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFD] =
+      reinterpret_cast<uint64_t>(PSHUFD_LUT.data());
+    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_SHUFPS] =
+      reinterpret_cast<uint64_t>(SHUFPS_LUT.data());
+    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPS_MASK] =
+      reinterpret_cast<uint64_t>(DPPS_MASK.data());
+    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPD_MASK] =
+      reinterpret_cast<uint64_t>(DPPD_MASK.data());
+    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PBLENDW] =
+      reinterpret_cast<uint64_t>(PBLENDW_LUT.data());

 #ifndef FEX_DISABLE_TELEMETRY
-  // Fill in telemetry values
-  for (size_t i = 0; i < FEXCore::Telemetry::TYPE_LAST; ++i) {
-    auto &Telem = FEXCore::Telemetry::GetTelemetryValue(static_cast<FEXCore::Telemetry::TelemetryType>(i));
-    Common.TelemetryValueAddresses[i] = reinterpret_cast<uint64_t>(Telem.GetAddr());
-  }
+    // Fill in telemetry values
+    for (size_t i = 0; i < FEXCore::Telemetry::TYPE_LAST; ++i) {
+      auto& Telem = FEXCore::Telemetry::GetTelemetryValue(static_cast<FEXCore::Telemetry::TelemetryType>(i));
+      Common.TelemetryValueAddresses[i] = reinterpret_cast<uint64_t>(Telem.GetAddr());
+    }
 #endif
-}
-
-CPUBackend::~CPUBackend() {
-  for (auto CodeBuffer : CodeBuffers) {
-    FreeCodeBuffer(CodeBuffer);
  }
-  CodeBuffers.clear();
-}

-auto CPUBackend::GetEmptyCodeBuffer() -> CodeBuffer * {
-  if (ThreadState->CurrentFrame->SignalHandlerRefCounter == 0) {
-    if (CodeBuffers.empty()) {
+  CPUBackend::~CPUBackend() {
+    for (auto CodeBuffer : CodeBuffers) {
+      FreeCodeBuffer(CodeBuffer);
+    }
+    CodeBuffers.clear();
+  }
+
+  auto CPUBackend::GetEmptyCodeBuffer() -> CodeBuffer* {
+    if (ThreadState->CurrentFrame->SignalHandlerRefCounter == 0) {
+      if (CodeBuffers.empty()) {
+        auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
+        EmplaceNewCodeBuffer(NewCodeBuffer);
+      } else {
+        if (CodeBuffers.size() > 1) {
+          // If we have more than one code buffer we are tracking then walk them and delete
+          // This is a cleanup step
+          for (size_t i = 1; i < CodeBuffers.size(); i++) {
+            FreeCodeBuffer(CodeBuffers[i]);
+          }
+          CodeBuffers.resize(1);
+        }
+        // Set the current code buffer to the initial
+        CurrentCodeBuffer = &CodeBuffers[0];
+
+        if (CurrentCodeBuffer->Size != MaxCodeSize) {
+          FreeCodeBuffer(*CurrentCodeBuffer);
+
+          // Resize the code buffer and reallocate our code size
+          CurrentCodeBuffer->Size *= 1.5;
+          CurrentCodeBuffer->Size = std::min(CurrentCodeBuffer->Size, MaxCodeSize);
+
+          *CurrentCodeBuffer = AllocateNewCodeBuffer(CurrentCodeBuffer->Size);
+        }
+      }
+    } else {
+      // We have signal handlers that have generated code
+      // This means that we can not safely clear the code at this point in time
+      // Allocate some new code buffers that we can switch over to instead
      auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
      EmplaceNewCodeBuffer(NewCodeBuffer);
-    } else {
-      if (CodeBuffers.size() > 1) {
-        // If we have more than one code buffer we are tracking then walk them and delete
-        // This is a cleanup step
-        for (size_t i = 1; i < CodeBuffers.size(); i++) {
-          FreeCodeBuffer(CodeBuffers[i]);
-        }
-        CodeBuffers.resize(1);
-      }
-      // Set the current code buffer to the initial
-      CurrentCodeBuffer = &CodeBuffers[0];
-
-      if (CurrentCodeBuffer->Size != MaxCodeSize) {
-        FreeCodeBuffer(*CurrentCodeBuffer);
-
-        // Resize the code buffer and reallocate our code size
-        CurrentCodeBuffer->Size *= 1.5;
-        CurrentCodeBuffer->Size = std::min(CurrentCodeBuffer->Size, MaxCodeSize);
-
-        *CurrentCodeBuffer = AllocateNewCodeBuffer(CurrentCodeBuffer->Size);
-      }
    }
-  } else {
-    // We have signal handlers that have generated code
-    // This means that we can not safely clear the code at this point in time
-    // Allocate some new code buffers that we can switch over to instead
-    auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
-    EmplaceNewCodeBuffer(NewCodeBuffer);
+
+    return CurrentCodeBuffer;
  }

-  return CurrentCodeBuffer;
-}
-
-auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
+  auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
 #ifndef _WIN32
 // MDWE (Memory-Deny-Write-Execute) is a new Linux 6.3 feature.
 // It's equivalent to systemd's `MemoryDenyWriteExecute` but implemented entirely in the kernel.
@@ -374,40 +355,39 @@ auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
 #ifndef PR_GET_MDWE
 #define PR_GET_MDWE 66
 #endif
-  int MDWE = ::prctl(PR_GET_MDWE, 0, 0, 0, 0);
-  if (MDWE != -1 && MDWE != 0) {
-    LogMan::Msg::EFmt("MDWE was set to 0x{:x} which means FEX can't allocate executable memory", MDWE);
-  }
+    int MDWE = ::prctl(PR_GET_MDWE, 0, 0, 0, 0);
+    if (MDWE != -1 && MDWE != 0) {
+      LogMan::Msg::EFmt("MDWE was set to 0x{:x} which means FEX can't allocate executable memory", MDWE);
+    }
 #endif

-  CodeBuffer Buffer;
-  Buffer.Size = Size;
-  Buffer.Ptr = static_cast<uint8_t *>(
-      FEXCore::Allocator::VirtualAlloc(Buffer.Size, true));
-  LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
+    CodeBuffer Buffer;
+    Buffer.Size = Size;
+    Buffer.Ptr = static_cast<uint8_t*>(FEXCore::Allocator::VirtualAlloc(Buffer.Size, true));
+    LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");

-  if (static_cast<Context::ContextImpl*>(ThreadState->CTX)->Config.GlobalJITNaming()) {
-    static_cast<Context::ContextImpl*>(ThreadState->CTX)->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size);
-  }
-  return Buffer;
-}
-
-void CPUBackend::FreeCodeBuffer(CodeBuffer Buffer) {
-  FEXCore::Allocator::VirtualFree(Buffer.Ptr, Buffer.Size);
-}
-
-bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {
-  for (auto &Buffer: CodeBuffers) {
-    auto start = (uintptr_t)Buffer.Ptr;
-    auto end = start + Buffer.Size;
-
-    if (Address >= start && Address < end) {
-      return true;
+    if (static_cast<Context::ContextImpl*>(ThreadState->CTX)->Config.GlobalJITNaming()) {
+      static_cast<Context::ContextImpl*>(ThreadState->CTX)->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size);
    }
+    return Buffer;
  }

-  return false;
-}
+  void CPUBackend::FreeCodeBuffer(CodeBuffer Buffer) {
+    FEXCore::Allocator::VirtualFree(Buffer.Ptr, Buffer.Size);
+  }

-}
-}
+  bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {
+    for (auto& Buffer : CodeBuffers) {
+      auto start = (uintptr_t)Buffer.Ptr;
+      auto end = start + Buffer.Size;
+
+      if (Address >= start && Address < end) {
+        return true;
+      }
+    }
+
+    return false;
+  }
+
+} // namespace CPU
+} // namespace FEXCore
@@ -20,44 +20,39 @@ namespace FEXCore {
 namespace IR {
  class IRListView;
  class RegisterAllocationData;
-}
+} // namespace IR

 namespace Core {
  struct DebugData;
  struct ThreadState;
  struct CpuStateFrame;
  struct InternalThreadState;
-}
+} // namespace Core

 namespace CodeSerialize {
  struct CodeObjectFileSection;
 }

 namespace CPU {
-  struct CPUBackendFeatures {
-    bool SupportsFlags = false;
-    bool SupportsSaturatingRoundingShifts = false;
-    bool SupportsVTBL2 = false;
-  };
-
  class CPUBackend {
  public:
    struct CodeBuffer {
-      uint8_t *Ptr;
+      uint8_t* Ptr;
      size_t Size;
    };

    /**
     * @param InitialCodeSize - Initial size for the code buffers
     * @param MaxCodeSize - Max size for the code buffers
-    */
-    CPUBackend(FEXCore::Core::InternalThreadState *ThreadState, size_t InitialCodeSize, size_t MaxCodeSize);
+     */
+    CPUBackend(FEXCore::Core::InternalThreadState* ThreadState, size_t InitialCodeSize, size_t MaxCodeSize);

    virtual ~CPUBackend();
    /**
     * @return The name of this backend
     */
-    [[nodiscard]] virtual fextl::string GetName() = 0;
+    [[nodiscard]]
+    virtual fextl::string GetName() = 0;

    struct CompiledCode {
      // Where this code block begins.
@@ -137,10 +132,9 @@ namespace CPU {
     *
     * @return Information about the compiled code block.
     */
-    [[nodiscard]] virtual CompiledCode CompileCode(uint64_t Entry,
-                                            FEXCore::IR::IRListView const *IR,
-                                            FEXCore::Core::DebugData *DebugData,
-                                            FEXCore::IR::RegisterAllocationData *RAData) = 0;
+    [[nodiscard]]
+    virtual CompiledCode CompileCode(uint64_t Entry, const FEXCore::IR::IRListView* IR, FEXCore::Core::DebugData* DebugData,
+                                     const FEXCore::IR::RegisterAllocationData* RAData) = 0;

    /**
     * @brief Relocates a block of code from the JIT code object cache
@@ -150,14 +144,18 @@ namespace CPU {
     *
     * @return An executable function pointer relocated from the cache object
     */
-    [[nodiscard]] virtual void *RelocateJITObjectCode(uint64_t Entry, CodeSerialize::CodeObjectFileSection const *SerializationData) { return nullptr; }
+    [[nodiscard]]
+    virtual void* RelocateJITObjectCode(uint64_t Entry, const CodeSerialize::CodeObjectFileSection* SerializationData) {
+      return nullptr;
+    }

    /**
     * @brief Function for mapping memory in to the CPUBackend's visible space. Allows setting up virtual mappings if required
     *
     * @return Currently unused
     */
-    [[nodiscard]] virtual void *MapRegion(void *HostPtr, uint64_t GuestPtr, uint64_t Size) = 0;
+    [[nodiscard]]
+    virtual void* MapRegion(void* HostPtr, uint64_t GuestPtr, uint64_t Size) = 0;

    /**
     * @brief Lets FEXCore know if this CPUBackend needs IR and DebugData for CompileCode
@@ -168,7 +166,8 @@ namespace CPU {
     *
     * @return true if it needs the IR
     */
-    [[nodiscard]] virtual bool NeedsOpDispatch() = 0;
+    [[nodiscard]]
+    virtual bool NeedsOpDispatch() = 0;

    virtual void ClearCache() {}

@@ -184,13 +183,14 @@ namespace CPU {
    // to be able to handle a 256-bit vector store to a slot.
    constexpr static uint32_t MaxSpillSlotSize = 32;

-    FEXCore::Core::InternalThreadState *ThreadState;
+    FEXCore::Core::InternalThreadState* ThreadState;

    size_t InitialCodeSize, MaxCodeSize;
-    [[nodiscard]] CodeBuffer *GetEmptyCodeBuffer();
+    [[nodiscard]]
+    CodeBuffer* GetEmptyCodeBuffer();

    // This is the current code buffer that we are tracking
-    CodeBuffer *CurrentCodeBuffer{};
+    CodeBuffer* CurrentCodeBuffer {};

  private:
    CodeBuffer AllocateNewCodeBuffer(size_t Size);
@@ -202,8 +202,8 @@ namespace CPU {

    // This is the array of code buffers. Unless signals force us to keep more than
    // buffer, there will be only one entry here
-    fextl::vector<CodeBuffer> CodeBuffers{};
+    fextl::vector<CodeBuffer> CodeBuffers {};
  };

-}
-}
+} // namespace CPU
+} // namespace FEXCore
@@ -30,7 +30,7 @@ private:
  constexpr static uint32_t CPUID_VENDOR_AMD3 = 0x444D4163; // "cAMD"

 public:
-  CPUIDEmu(FEXCore::Context::ContextImpl const *ctx);
+  CPUIDEmu(const FEXCore::Context::ContextImpl* ctx);

  // X86 cacheline size effectively has to be hardcoded to 64
  // if we report anything differently then applications are likely to break
@@ -58,12 +58,13 @@ public:
  }

  FEXCore::CPUID::FunctionResults RunFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) const {
-    if (Function == 0x8000'0002U)
+    if (Function == 0x8000'0002U) {
      return Function_8000_0002h(Leaf, CPU % PerCPUData.size());
-    else if (Function == 0x8000'0003U)
+    } else if (Function == 0x8000'0003U) {
      return Function_8000_0003h(Leaf, CPU % PerCPUData.size());
-    else
+    } else {
      return Function_8000_0004h(Leaf, CPU % PerCPUData.size());
+    }
  }

  FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) const {
@@ -113,11 +114,12 @@ public:
  }

 private:
-  FEXCore::Context::ContextImpl const *CTX;
-  bool Hybrid{};
-  uint32_t Cores{};
+  const FEXCore::Context::ContextImpl* CTX;
+  bool Hybrid {};
+  uint32_t Cores {};
  FEX_CONFIG_OPT(HideHypervisorBit, HIDEHYPERVISORBIT);
  FEX_CONFIG_OPT(SmallTSCScale, SMALLTSCSCALE);
+  FEX_CONFIG_OPT(MemcpySetTSOEnabled, MEMCPYSETTSOENABLED);

  // XFEATURE_ENABLED_MASK
  // Mask that configures what features are enabled on the CPU.
@@ -148,10 +150,7 @@ private:
    .SHA = 1,
  };

-  uint64_t XCR0 {
-    XCR0_X87 |
-    XCR0_SSE
-  };
+  uint64_t XCR0 {XCR0_X87 | XCR0_SSE};

  uint32_t SupportsAVX() const {
    return (XCR0 & XCR0_AVX) ? 1 : 0;
@@ -160,13 +159,13 @@ private:
  using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf) const;

  struct CPUData {
-    const char *ProductName{};
+    const char* ProductName {};
 #ifdef _M_ARM_64
-    uint32_t MIDR{};
+    uint32_t MIDR {};
 #endif
-    bool IsBig{};
+    bool IsBig {};
  };
-  fextl::vector<CPUData> PerCPUData{};
+  fextl::vector<CPUData> PerCPUData {};

  // Functions
  FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf) const;
@@ -277,74 +276,74 @@ private:

  static constexpr std::array<FunctionConstant, PRIMARY_FUNCTION_COUNT> Primary_Constant = {{
    // 0: Highest function parameter and ID
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 1: Processor info
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 2: Cache and TLB info
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 3: Serial Number(previously), now reserved
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #ifndef CPUID_AMD
    // 4: Deterministic cache parameters for each level
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
 #else
    // 4: Reserved
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #endif
    // 5: Monitor/mwait
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 6: Thermal and power management
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 7: Extended feature flags
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
    // 0x08: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 9: Direct Cache Access information
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x0A: Architectural performance monitoring
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x0B: Extended topology enumeration
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x0C: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x0D: Processor extended state enumeration
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
    // 0x0E: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x0F: Intel RDT monitoring
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x10: Intel RDT allocation enumeration
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x12: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x12: Intel SGX capability enumeration
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x13: Reserved
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x14: Intel Processor trace
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #ifndef CPUID_AMD
    // 0x15: Timestamp counter information
    // Doesn't exist on AMD hardware
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #else
    // 0x15: Reserved
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #endif
    // 0x16: Processor frequency information
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x17: SoC vendor attribute enumeration
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x18: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x19: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #ifndef CPUID_AMD
    // 0x1A: Hybrid Information Sub-leaf
-    { SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #else
    // 0x1A: Reserved
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #endif
  }};

@@ -357,9 +356,9 @@ private:

  static constexpr std::array<FunctionConstant, HYPERVISOR_FUNCTION_COUNT> Hypervisor_Constant = {{
    // Hypervisor CPUID information leaf
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // FEX-Emu specific leaf
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
  }};

  static constexpr std::array<FunctionHandler, EXTENDED_FUNCTION_COUNT> Extended = {
@@ -439,79 +438,79 @@ private:

  static constexpr std::array<FunctionConstant, EXTENDED_FUNCTION_COUNT> Extended_Constant = {{
    // Largest extended function number
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // Processor vendor
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // Processor brand string
-    { SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // Processor brand string continued
-    { SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // Processor brand string continued
-    { SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #ifdef CPUID_AMD
    // 0x8000'0005: L1 Cache and TLB identifiers
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #else
    // 0x8000'0005: Reserved
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #endif
    // 0x8000'0006: L2 Cache identifiers
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0007: Advanced power management information
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0008: Virtual and physical address sizes
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0009: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'000A: SVM Revision
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'000B: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'000C: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'000D: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'000E: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'000F: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0010: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0011: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0012: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0013: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0014: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0015: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0016: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0017: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0018: Reserved?
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'0019: TLB 1GB page identifiers
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'001A: Performance optimization identifiers
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'001B: Instruction based sampling identifiers
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'001C: Lightweight profiling capabilities
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #ifdef CPUID_AMD
    // 0x8000'001D: Cache properties
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
 #else
    // 0x8000'001D: Reserved
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
 #endif
    // 0x8000'001E: Extended APIC ID
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
    // 0x8000'001F: AMD Secure Encryption
-    { SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT },
+    {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
  }};
 };
-}
+} // namespace FEXCore
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: MIT
-#pragma once
-#include <stdint.h>
-
-namespace FEXCore::CPU {
-}
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: MIT

 #include "Interface/Context/Context.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/X86HelperGen.h"
@@ -17,6 +16,8 @@
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>

+#include <CodeEmitter/Emitter.h>
+
 #include <atomic>
 #include <condition_variable>
 #include <csignal>
@@ -25,13 +26,13 @@

 namespace FEXCore::CPU {

-static void SleepThread(FEXCore::Context::ContextImpl *CTX, FEXCore::Core::CpuStateFrame *Frame) {
+static void SleepThread(FEXCore::Context::ContextImpl* CTX, FEXCore::Core::CpuStateFrame* Frame) {
  CTX->SyscallHandler->SleepThread(CTX, Frame);
 }

 constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 2;

-Dispatcher::Dispatcher(FEXCore::Context::ContextImpl *ctx)
+Dispatcher::Dispatcher(FEXCore::Context::ContextImpl* ctx)
  : Arm64Emitter(ctx, FEXCore::Allocator::VirtualAlloc(MAX_DISPATCHER_CODE_SIZE, true), MAX_DISPATCHER_CODE_SIZE)
  , CTX {ctx} {
  EmitDispatcher();
@@ -79,19 +80,43 @@ void Dispatcher::EmitDispatcher() {
  AbsoluteLoopTopAddressFillSRA = GetCursorAddress<uint64_t>();

  FillStaticRegs();
+  ARMEmitter::BiDirectionalLabel LoopTop {};
+
+#ifdef _M_ARM_64EC
+  b(&LoopTop);
+
+  AbsoluteLoopTopAddressEnterECFillSRA = GetCursorAddress<uint64_t>();
+  ldr(STATE, EC_ENTRY_CPUAREA_REG, CPU_AREA_EMULATOR_DATA_OFFSET);
+  FillStaticRegs();
+
+  // Enter JIT
+  b(&LoopTop);
+
+  AbsoluteLoopTopAddressEnterEC = GetCursorAddress<uint64_t>();
+  // Load ThreadState and write the target PC there
+  ldr(STATE, EC_ENTRY_CPUAREA_REG, CPU_AREA_EMULATOR_DATA_OFFSET);
+  str(EC_CALL_CHECKER_PC_REG, STATE_PTR(CpuStateFrame, State.rip));
+
+  // Swap stacks to the emulator stack
+  ldr(TMP1, EC_ENTRY_CPUAREA_REG, CPU_AREA_EMULATOR_STACK_BASE_OFFSET);
+  add(ARMEmitter::Size::i64Bit, StaticRegisters[X86State::REG_RSP], ARMEmitter::Reg::rsp, 0);
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, TMP1, 0);
+
+  FillSpecialRegs(TMP1, TMP2, false, true);
+
+  // Enter JIT
+#endif

  // We want to ensure that we are 16 byte aligned at the top of this loop
  Align16B();
-  ARMEmitter::BiDirectionalLabel FullLookup{};
-  ARMEmitter::BiDirectionalLabel CallBlock{};
-  ARMEmitter::BackwardLabel LoopTop{};
+  ARMEmitter::BiDirectionalLabel FullLookup {};
+  ARMEmitter::BiDirectionalLabel CallBlock {};

  Bind(&LoopTop);
  AbsoluteLoopTopAddress = GetCursorAddress<uint64_t>();

  // Load in our RIP
  // Don't modify TMP3 since it contains our RIP once the block doesn't exist
-
  auto RipReg = TMP3;
  ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));

@@ -99,7 +124,7 @@ void Dispatcher::EmitDispatcher() {
  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));

  and_(ARMEmitter::Size::i64Bit, TMP4, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
-  add(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP4, ARMEmitter::ShiftType::LSL , 4);
+  add(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP4, ARMEmitter::ShiftType::LSL, 4);
  ldp<ARMEmitter::IndexType::OFFSET>(TMP4, TMP1, TMP1, 0);
  sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, RipReg);
  cbnz(ARMEmitter::Size::i64Bit, TMP1, &FullLookup);
@@ -117,8 +142,7 @@ void Dispatcher::EmitDispatcher() {
  uint64_t VirtualMemorySize = CTX->Config.VirtualMemSize;
  if (std::popcount(VirtualMemorySize) == 1) {
    and_(ARMEmitter::Size::i64Bit, TMP4, RipReg.R(), VirtualMemorySize - 1);
-  }
-  else {
+  } else {
    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, VirtualMemorySize);
    and_(ARMEmitter::Size::i64Bit, TMP4, RipReg.R(), TMP4);
  }
@@ -160,7 +184,7 @@ void Dispatcher::EmitDispatcher() {

      and_(ARMEmitter::Size::i64Bit, TMP2, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
      add(TMP1, TMP1, TMP2, ARMEmitter::ShiftType::LSL, 4);
-      stp<ARMEmitter::IndexType::OFFSET>(TMP4, TMP3, TMP1);
+      stp<ARMEmitter::IndexType::OFFSET>(TMP4, RipReg, TMP1);

      // Jump to the block
      br(TMP4);
@@ -184,18 +208,25 @@ void Dispatcher::EmitDispatcher() {
    ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
    SpillStaticRegs(TMP1);

+#ifndef _WIN32
    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+#endif
+
+#ifdef _M_ARM_64EC
+    ldr(ARMEmitter::XReg::x0, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
+    LoadConstant(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, 1);
+    strb(ARMEmitter::WReg::w1, ARMEmitter::XReg::x0, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
+#endif

    mov(ARMEmitter::XReg::x0, STATE);
    mov(ARMEmitter::XReg::x1, ARMEmitter::XReg::lr);

    ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink));
    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<uintptr_t, void *, void *>(ARMEmitter::Reg::r2);
-    }
-    else {
+      GenerateIndirectRuntimeCall<uintptr_t, void*, void*>(ARMEmitter::Reg::r2);
+    } else {
      blr(ARMEmitter::Reg::r2);
    }

@@ -205,13 +236,20 @@ void Dispatcher::EmitDispatcher() {

    FillStaticRegs();

+#ifdef _M_ARM_64EC
+    ldr(TMP2, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
+    strb(ARMEmitter::WReg::zr, TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
+#endif
+
+#ifndef _WIN32
    ldr(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, 1);
    str(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));

    // Trigger segfault if any deferred signals are pending
-    ldr(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
-    str(ARMEmitter::XReg::zr, TMP2, 0);
+    strb(ARMEmitter::XReg::zr, STATE,
+         offsetof(FEXCore::Core::InternalThreadState, InterruptFaultPage) - offsetof(FEXCore::Core::InternalThreadState, BaseFrameState));
+#endif

    br(TMP1);
  }
@@ -220,15 +258,44 @@ void Dispatcher::EmitDispatcher() {
  {
    Bind(&NoBlock);

+#ifdef _M_ARM_64EC
+    // Check the EC code bitmap incase we need to exit the JIT to call into native code.
+    ARMEmitter::SingleUseForwardLabel l_NotECCode;
+    ldr(TMP1, ARMEmitter::XReg::x18, TEB_PEB_OFFSET);
+    ldr(TMP1, TMP1, PEB_EC_CODE_BITMAP_OFFSET);
+
+    lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 15);
+    and_(ARMEmitter::Size::i64Bit, TMP2, TMP2, 0x1fffffffffff8);
+    ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 0);
+    lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 12);
+    lsrv(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP2);
+    tbz(TMP1, 0, &l_NotECCode);
+
+    add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0);
+    mov(EC_CALL_CHECKER_PC_REG, RipReg);
+    ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
+    br(TMP2);
+
+    Bind(&l_NotECCode);
+#endif
+
    SpillStaticRegs(TMP1);

    if (!TMP_ABIARGS) {
-      mov(ARMEmitter::XReg::x2, TMP3);
+      mov(ARMEmitter::XReg::x2, RipReg);
    }

+#ifndef _WIN32
    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+#endif
+
+#ifdef _M_ARM_64EC
+    ldr(ARMEmitter::XReg::x0, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
+    LoadConstant(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, 1);
+    strb(ARMEmitter::WReg::w1, ARMEmitter::XReg::x0, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
+#endif

    ldr(ARMEmitter::XReg::x0, &l_CTX);
    mov(ARMEmitter::XReg::x1, STATE);
@@ -237,21 +304,27 @@ void Dispatcher::EmitDispatcher() {
    ldr(ARMEmitter::XReg::x4, &l_CompileBlock);

    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<uintptr_t, void *, void*, uint64_t, uint64_t>(ARMEmitter::Reg::r4);
-    }
-    else {
+      GenerateIndirectRuntimeCall<uintptr_t, void*, void*, uint64_t, uint64_t>(ARMEmitter::Reg::r4);
+    } else {
      blr(ARMEmitter::Reg::r4); // { CTX, Frame, RIP, MaxInst }
    }

    FillStaticRegs();

+#ifdef _M_ARM_64EC
+    ldr(TMP1, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
+    strb(ARMEmitter::WReg::zr, TMP1, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
+#endif
+
+#ifndef _WIN32
    ldr(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1);
    str(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));

    // Trigger segfault if any deferred signals are pending
-    ldr(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
-    str(ARMEmitter::XReg::zr, TMP1, 0);
+    strb(ARMEmitter::XReg::zr, STATE,
+         offsetof(FEXCore::Core::InternalThreadState, InterruptFaultPage) - offsetof(FEXCore::Core::InternalThreadState, BaseFrameState));
+#endif

    b(&LoopTop);
  }
@@ -285,7 +358,7 @@ void Dispatcher::EmitDispatcher() {
  {
    // Guest SIGTRAP handler
    // Needs to be distinct from the SignalHandlerReturnAddress
-    GuestSignal_SIGTRAP  = GetCursorAddress<uint64_t>();
+    GuestSignal_SIGTRAP = GetCursorAddress<uint64_t>();

    SpillStaticRegs(TMP1);

@@ -308,8 +381,7 @@ void Dispatcher::EmitDispatcher() {
      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::r0, 0);
      PopCalleeSavedRegisters();
      ret();
-    }
-    else {
+    } else {
      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, 0);
      ldr(ARMEmitter::XReg::x1, ARMEmitter::Reg::r1);
    }
@@ -328,9 +400,8 @@ void Dispatcher::EmitDispatcher() {
    mov(ARMEmitter::XReg::x1, STATE);
    ldr(ARMEmitter::XReg::x2, &l_Sleep);
    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<void, void *, void *>(ARMEmitter::Reg::r2);
-    }
-    else {
+      GenerateIndirectRuntimeCall<void, void*, void*>(ARMEmitter::Reg::r2);
+    } else {
      blr(ARMEmitter::Reg::r2);
    }

@@ -405,8 +476,7 @@ void Dispatcher::EmitDispatcher() {
    ldr(ARMEmitter::XReg::x3, R, Offset);
    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
      GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
-    }
-    else {
+    } else {
      blr(ARMEmitter::Reg::r3);
    }
    // Result is now in x0
@@ -463,26 +533,28 @@ void Dispatcher::EmitDispatcher() {
 }

 #ifdef VIXL_SIMULATOR
-void Dispatcher::ExecuteDispatch(FEXCore::Core::CpuStateFrame *Frame) {
+void Dispatcher::ExecuteDispatch(FEXCore::Core::CpuStateFrame* Frame) {
  Simulator.WriteXRegister(0, reinterpret_cast<int64_t>(Frame));
-  Simulator.RunFrom(reinterpret_cast<vixl::aarch64::Instruction const*>(DispatchPtr));
+  Simulator.RunFrom(reinterpret_cast< const vixl::aarch64::Instruction*>(DispatchPtr));
 }

-void Dispatcher::ExecuteJITCallback(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP) {
+void Dispatcher::ExecuteJITCallback(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP) {
  Simulator.WriteXRegister(0, reinterpret_cast<int64_t>(Frame));
  Simulator.WriteXRegister(1, RIP);
-  Simulator.RunFrom(reinterpret_cast<vixl::aarch64::Instruction const*>(CallbackPtr));
+  Simulator.RunFrom(reinterpret_cast< const vixl::aarch64::Instruction*>(CallbackPtr));
 }

 #endif

-void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) {
+void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread) {
  // Setup dispatcher specific pointers that need to be accessed from JIT code
  {
-    auto &Common = Thread->CurrentFrame->Pointers.Common;
+    auto& Common = Thread->CurrentFrame->Pointers.Common;

    Common.DispatcherLoopTop = AbsoluteLoopTopAddress;
    Common.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
+    Common.DispatcherLoopTopEnterEC = AbsoluteLoopTopAddressEnterEC;
+    Common.DispatcherLoopTopEnterECFillSRA = AbsoluteLoopTopAddressEnterECFillSRA;
    Common.ExitFunctionLinker = ExitFunctionLinkerAddress;
    Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
    Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
@@ -492,7 +564,7 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread)
    Common.SignalReturnHandler = SignalHandlerReturnAddress;
    Common.SignalReturnHandlerRT = SignalHandlerReturnAddressRT;

-    auto &AArch64 = Thread->CurrentFrame->Pointers.AArch64;
+    auto& AArch64 = Thread->CurrentFrame->Pointers.AArch64;
    AArch64.LUDIVHandler = LUDIVHandlerAddress;
    AArch64.LDIVHandler = LDIVHandlerAddress;
    AArch64.LUREMHandler = LUREMHandlerAddress;
@@ -500,8 +572,8 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread)
  }
 }

-fextl::unique_ptr<Dispatcher> Dispatcher::Create(FEXCore::Context::ContextImpl *CTX) {
+fextl::unique_ptr<Dispatcher> Dispatcher::Create(FEXCore::Context::ContextImpl* CTX) {
  return fextl::make_unique<Dispatcher>(CTX);
 }

-}
+} // namespace FEXCore::CPU
@@ -23,7 +23,7 @@ struct GuestSigAction;
 namespace FEXCore::Core {
 struct CpuStateFrame;
 struct InternalThreadState;
-}
+} // namespace FEXCore::Core

 namespace FEXCore::Context {
 class ContextImpl;
@@ -31,51 +31,52 @@ class ContextImpl;

 namespace FEXCore::CPU {

-#define STATE_PTR(STATE_TYPE, FIELD) \
-  STATE.R(), offsetof(FEXCore::Core::STATE_TYPE, FIELD)
+#define STATE_PTR(STATE_TYPE, FIELD) STATE.R(), offsetof(FEXCore::Core::STATE_TYPE, FIELD)

 class Dispatcher final : public Arm64Emitter {
 public:
-  static fextl::unique_ptr<Dispatcher> Create(FEXCore::Context::ContextImpl *CTX);
+  static fextl::unique_ptr<Dispatcher> Create(FEXCore::Context::ContextImpl* CTX);

-  Dispatcher(FEXCore::Context::ContextImpl *ctx);
+  Dispatcher(FEXCore::Context::ContextImpl* ctx);
  ~Dispatcher();

  /**
   * @name Dispatch Helper functions
   * @{ */
-  uint64_t ThreadStopHandlerAddress{};
-  uint64_t ThreadStopHandlerAddressSpillSRA{};
-  uint64_t AbsoluteLoopTopAddress{};
-  uint64_t AbsoluteLoopTopAddressFillSRA{};
-  uint64_t ThreadPauseHandlerAddress{};
-  uint64_t ThreadPauseHandlerAddressSpillSRA{};
-  uint64_t ExitFunctionLinkerAddress{};
-  uint64_t SignalHandlerReturnAddress{};
-  uint64_t SignalHandlerReturnAddressRT{};
-  uint64_t GuestSignal_SIGILL{};
-  uint64_t GuestSignal_SIGTRAP{};
-  uint64_t GuestSignal_SIGSEGV{};
-  uint64_t IntCallbackReturnAddress{};
+  uint64_t ThreadStopHandlerAddress {};
+  uint64_t ThreadStopHandlerAddressSpillSRA {};
+  uint64_t AbsoluteLoopTopAddress {};
+  uint64_t AbsoluteLoopTopAddressFillSRA {};
+  uint64_t AbsoluteLoopTopAddressEnterEC {};
+  uint64_t AbsoluteLoopTopAddressEnterECFillSRA {};
+  uint64_t ThreadPauseHandlerAddress {};
+  uint64_t ThreadPauseHandlerAddressSpillSRA {};
+  uint64_t ExitFunctionLinkerAddress {};
+  uint64_t SignalHandlerReturnAddress {};
+  uint64_t SignalHandlerReturnAddressRT {};
+  uint64_t GuestSignal_SIGILL {};
+  uint64_t GuestSignal_SIGTRAP {};
+  uint64_t GuestSignal_SIGSEGV {};
+  uint64_t IntCallbackReturnAddress {};

-  uint64_t PauseReturnInstruction{};
+  uint64_t PauseReturnInstruction {};

  /**  @} */

-  uint64_t Start{};
-  uint64_t End{};
+  uint64_t Start {};
+  uint64_t End {};

-  void InitThreadPointers(FEXCore::Core::InternalThreadState *Thread);
+  void InitThreadPointers(FEXCore::Core::InternalThreadState* Thread);

 #ifdef VIXL_SIMULATOR
-  void ExecuteDispatch(FEXCore::Core::CpuStateFrame *Frame) ;
-  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP);
+  void ExecuteDispatch(FEXCore::Core::CpuStateFrame* Frame);
+  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP);
 #else
-  void ExecuteDispatch(FEXCore::Core::CpuStateFrame *Frame) {
+  void ExecuteDispatch(FEXCore::Core::CpuStateFrame* Frame) {
    DispatchPtr(Frame);
  }

-  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP) {
+  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP) {
    CallbackPtr(Frame, RIP);
  }
 #endif
@@ -103,21 +104,21 @@ public:
  }

 protected:
-  FEXCore::Context::ContextImpl *CTX;
+  FEXCore::Context::ContextImpl* CTX;

-  using AsmDispatch = void(*)(FEXCore::Core::CpuStateFrame *Frame);
-  using JITCallback = void(*)(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP);
+  using AsmDispatch = void (*)(FEXCore::Core::CpuStateFrame* Frame);
+  using JITCallback = void (*)(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP);

  AsmDispatch DispatchPtr;
  JITCallback CallbackPtr;
 private:
  // Long division helpers
-  uint64_t LUDIVHandlerAddress{};
-  uint64_t LDIVHandlerAddress{};
-  uint64_t LUREMHandlerAddress{};
-  uint64_t LREMHandlerAddress{};
+  uint64_t LUDIVHandlerAddress {};
+  uint64_t LDIVHandlerAddress {};
+  uint64_t LUREMHandlerAddress {};
+  uint64_t LREMHandlerAddress {};

  void EmitDispatcher();
 };

-}
+} // namespace FEXCore::CPU
@@ -21,10 +21,10 @@ class Decoder final {
 public:
  // New Frontend decoding
  struct DecodedBlocks final {
-    uint64_t Entry{};
-    uint64_t NumInstructions{};
-    FEXCore::X86Tables::DecodedInst *DecodedInstructions;
-    bool HasInvalidInstruction{};
+    uint64_t Entry {};
+    uint64_t NumInstructions {};
+    FEXCore::X86Tables::DecodedInst* DecodedInstructions;
+    bool HasInvalidInstruction {};
  };

  struct DecodedBlockInformation final {
@@ -32,19 +32,24 @@ public:
    fextl::vector<DecodedBlocks> Blocks;
  };

-  Decoder(FEXCore::Context::ContextImpl *ctx);
+  Decoder(FEXCore::Context::ContextImpl* ctx);
  ~Decoder();
-  void DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC, uint64_t MaxInst, std::function<void(uint64_t BlockEntry, uint64_t Start, uint64_t Length)> AddContainedCodePage);
+  void DecodeInstructionsAtEntry(const uint8_t* InstStream, uint64_t PC, uint64_t MaxInst,
+                                 std::function<void(uint64_t BlockEntry, uint64_t Start, uint64_t Length)> AddContainedCodePage);

-  DecodedBlockInformation const *GetDecodedBlockInfo() const {
+  const DecodedBlockInformation* GetDecodedBlockInfo() const {
    return &BlockInfo;
  }

  uint64_t DecodedMinAddress {};
  uint64_t DecodedMaxAddress {~0ULL};

-  void SetSectionMaxAddress(uint64_t v) { SectionMaxAddress = v; }
-  void SetExternalBranches(fextl::set<uint64_t> *v) { ExternalBranches = v; }
+  void SetSectionMaxAddress(uint64_t v) {
+    SectionMaxAddress = v;
+  }
+  void SetExternalBranches(fextl::set<uint64_t>* v) {
+    ExternalBranches = v;
+  }

  void DelayedDisownBuffer() {
    PoolObject.DelayedDisownBuffer();
@@ -59,8 +64,8 @@ private:
    bool L;       // VEX.L bit (if set then 256 bit operation, if unset then scalar or 128-bit operation)
  };

-  FEXCore::Context::ContextImpl *CTX;
-  const FEXCore::HLE::SyscallOSABI OSABI{};
+  FEXCore::Context::ContextImpl* CTX;
+  const FEXCore::HLE::SyscallOSABI OSABI {};

  bool DecodeInstruction(uint64_t PC);

@@ -70,22 +75,24 @@ private:
  uint8_t ReadByte();
  uint8_t PeekByte(uint8_t Offset) const;
  uint64_t ReadData(uint8_t Size);
-  void SkipBytes(uint8_t Size) { InstructionSize += Size; }
+  void SkipBytes(uint8_t Size) {
+    InstructionSize += Size;
+  }

-  bool NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, DecodedHeader Options = {});
-  bool NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op);
+  bool NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op, DecodedHeader Options = {});
+  bool NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op);

  static constexpr size_t DefaultDecodedBufferSize = 0x10000;
-  FEXCore::X86Tables::DecodedInst *DecodedBuffer{};
+  FEXCore::X86Tables::DecodedInst* DecodedBuffer {};
  Utils::FixedSizePooledAllocation<FEXCore::X86Tables::DecodedInst*, 5000, 500> PoolObject;
  size_t DecodedSize {};

-  uint8_t const *InstStream;
+  const uint8_t* InstStream;

  static constexpr size_t MAX_INST_SIZE = 15;
  uint8_t InstructionSize;
  std::array<uint8_t, MAX_INST_SIZE> Instruction;
-  FEXCore::X86Tables::DecodedInst *DecodeInst;
+  FEXCore::X86Tables::DecodedInst* DecodeInst;

  // This is for multiblock data tracking
  bool SymbolAvailable {false};
@@ -99,21 +106,20 @@ private:
  DecodedBlockInformation BlockInfo;
  fextl::set<uint64_t> BlocksToDecode;
  fextl::set<uint64_t> HasBlocks;
-  fextl::set<uint64_t> *ExternalBranches {nullptr};
+  fextl::set<uint64_t>* ExternalBranches {nullptr};

  // ModRM rm decoding
-  using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
-  void DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
-  void DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
+  using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand* Operand, X86Tables::ModRMDecoded ModRM);
+  void DecodeModRM_16(X86Tables::DecodedOperand* Operand, X86Tables::ModRMDecoded ModRM);
+  void DecodeModRM_64(X86Tables::DecodedOperand* Operand, X86Tables::ModRMDecoded ModRM);

-  static constexpr std::array<DecodeModRMPtr, 2> DecodeModRMs_Disp{
+  static constexpr std::array<DecodeModRMPtr, 2> DecodeModRMs_Disp {
    &FEXCore::Frontend::Decoder::DecodeModRM_64,
    &FEXCore::Frontend::Decoder::DecodeModRM_16,
  };

-  const uint8_t *AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP);
+  const uint8_t* AdjustAddrForSpecialRegion(const uint8_t* _InstStream, uint64_t EntryPoint, uint64_t RIP);

-  FEXCORE_TELEMETRY_INIT(VEXOpTelem, TYPE_USES_VEX_OPS);
  FEXCORE_TELEMETRY_INIT(EVEXOpTelem, TYPE_USES_EVEX_OPS);
 };
-}
+} // namespace FEXCore::Frontend
@@ -1,259 +0,0 @@
-// SPDX-License-Identifier: MIT
-#include "Interface/Core/CPUID.h"
-#include <FEXCore/Core/HostFeatures.h>
-
-#include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
-#include "aarch64/disasm-aarch64.h"
-#include "aarch64/assembler-aarch64.h"
-
-#ifdef _M_X86_64
-#define XBYAK64
-#define XBYAK_NO_EXCEPTION
-#include <FEXCore/fextl/list.h>
-#include <FEXCore/fextl/unordered_map.h>
-#include <FEXCore/fextl/unordered_set.h>
-
-#include <xbyak/xbyak.h>
-#include <xbyak/xbyak_util.h>
-#endif
-
-namespace FEXCore {
-
-// Data Zero Prohibited flag
-// 0b0 = ZVA/GVA/GZVA permitted
-// 0b1 = ZVA/GVA/GZVA prohibited
-[[maybe_unused]] constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
-// Log2 of the blocksize in 32-bit words
-[[maybe_unused]] constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
-
-#ifdef _M_ARM_64
-[[maybe_unused]] static uint32_t GetDCZID() {
-  uint64_t Result{};
-  __asm("mrs %[Res], DCZID_EL0"
-      : [Res] "=r" (Result));
-  return Result;
-}
-
-static uint32_t GetFPCR() {
-  uint64_t Result{};
-  __asm ("mrs %[Res], FPCR"
-    : [Res] "=r" (Result));
-  return Result;
-}
-
-static void SetFPCR(uint64_t Value) {
-  __asm ("msr FPCR, %[Value]"
-    :: [Value] "r" (Value));
-}
-#else
-static uint32_t GetDCZID() {
-  // Return unsupported
-  return DCZID_DZP_MASK;
-}
-#endif
-
-static void OverrideFeatures(HostFeatures *Features) {
-  // Override features if the user has specifically called for it.
-  FEX_CONFIG_OPT(HostFeatures, HOSTFEATURES);
-  if (!HostFeatures()) {
-    // Early exit if no features are overriden.
-    return;
-  }
-
-#define ENABLE_DISABLE_OPTION(FeatureName, name, enum_name) \
-    do { \
-      const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
-      const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0;   \
-      LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive"); \
-      const bool AlreadyEnabled = Features->FeatureName; \
-      const bool Result = (AlreadyEnabled | Enable##name) & !Disable##name; \
-      Features->FeatureName = Result; \
-    } while (0)
-
-#define GET_SINGLE_OPTION(name, enum_name) \
-    const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
-    const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0;   \
-    LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive");
-
-  ENABLE_DISABLE_OPTION(SupportsAVX, AVX, AVX);
-  ENABLE_DISABLE_OPTION(SupportsAVX2, AVX2, AVX2);
-  ENABLE_DISABLE_OPTION(SupportsSVE, SVE, SVE);
-  ENABLE_DISABLE_OPTION(SupportsAFP, AFP, AFP);
-  ENABLE_DISABLE_OPTION(SupportsRCPC, LRCPC, LRCPC);
-  ENABLE_DISABLE_OPTION(SupportsTSOImm9, LRCPC2, LRCPC2);
-  ENABLE_DISABLE_OPTION(SupportsCSSC, CSSC, CSSC);
-  ENABLE_DISABLE_OPTION(SupportsPMULL_128Bit, PMULL128, PMULL128);
-  ENABLE_DISABLE_OPTION(SupportsRAND, RNG, RNG);
-  ENABLE_DISABLE_OPTION(SupportsCLZERO, CLZERO, CLZERO);
-  ENABLE_DISABLE_OPTION(SupportsAtomics, Atomics, ATOMICS);
-  ENABLE_DISABLE_OPTION(SupportsFCMA, FCMA, FCMA);
-  ENABLE_DISABLE_OPTION(SupportsFlagM, FlagM, FLAGM);
-  ENABLE_DISABLE_OPTION(SupportsFlagM2, FlagM2, FLAGM2);
-  ENABLE_DISABLE_OPTION(SupportsRPRES, RPRES, RPRES);
-  ENABLE_DISABLE_OPTION(SupportsPreserveAllABI, PRESERVEALLABI, PRESERVEALLABI);
-  GET_SINGLE_OPTION(Crypto, CRYPTO);
-
-#undef ENABLE_DISABLE_OPTION
-#undef GET_SINGLE_OPTION
-
-  if (EnableCrypto) {
-    Features->SupportsAES = true;
-    Features->SupportsCRC = true;
-    Features->SupportsSHA = true;
-    Features->SupportsPMULL_128Bit = true;
-  }
-  else if (DisableCrypto) {
-    Features->SupportsAES = false;
-    Features->SupportsCRC = false;
-    Features->SupportsSHA = false;
-    Features->SupportsPMULL_128Bit = false;
-  }
-}
-
-HostFeatures::HostFeatures() {
-#ifdef VIXL_SIMULATOR
-  auto Features = vixl::CPUFeatures::All();
-  // Vixl simulator doesn't support AFP.
-  Features.Remove(vixl::CPUFeatures::Feature::kAFP);
-  // Vixl simulator doesn't support RPRES.
-  Features.Remove(vixl::CPUFeatures::Feature::kRPRES);
-#elif !defined(_WIN32)
-  auto Features = vixl::CPUFeatures::InferFromOS();
-#else
-  // Need to use ID registers in WINE.
-  auto Features = vixl::CPUFeatures::InferFromIDRegisters();
-#endif
-
-  SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
-  SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
-  SupportsSHA = Features.Has(vixl::CPUFeatures::Feature::kSHA1) &&
-                Features.Has(vixl::CPUFeatures::Feature::kSHA2);
-  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
-  SupportsRAND = Features.Has(vixl::CPUFeatures::Feature::kRNG);
-
-  // Only supported when FEAT_AFP is supported
-  SupportsAFP = Features.Has(vixl::CPUFeatures::Feature::kAFP);
-  SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
-  SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
-  SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
-  SupportsCSSC = Features.Has(vixl::CPUFeatures::Feature::kCSSC);
-  SupportsFCMA = Features.Has(vixl::CPUFeatures::Feature::kFcma);
-  SupportsFlagM = Features.Has(vixl::CPUFeatures::Feature::kFlagM);
-  SupportsFlagM2 = Features.Has(vixl::CPUFeatures::Feature::kAXFlag);
-  SupportsRPRES = Features.Has(vixl::CPUFeatures::Feature::kRPRES);
-
-  Supports3DNow = true;
-  SupportsSSE4A = true;
-#ifdef VIXL_SIMULATOR
-  // Hardcode enable SVE with 256-bit wide registers.
-  SupportsSVE = true;
-  SupportsAVX = true;
-#else
-  SupportsSVE = Features.Has(vixl::CPUFeatures::Feature::kSVE);
-  SupportsAVX = Features.Has(vixl::CPUFeatures::Feature::kSVE2) &&
-                vixl::aarch64::CPU::ReadSVEVectorLengthInBits() >= 256;
-#endif
-  // TODO: AVX2 is currently unsupported. Disable until the remaining features are implemented.
-  SupportsAVX2 = false;
-  SupportsBMI1 = true;
-  SupportsBMI2 = true;
-  SupportsCLWB = true;
-
-  // TODO: AFP is disabled until the scalar usage in the codebase can be audited to be working as expected.
-  SupportsAFP = false;
-  // RPRES has a dependency on AFP. Disable it until AFP is enabled.
-  SupportsRPRES = false;
-
-  if (!SupportsAtomics) {
-    WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
-  }
-
-#ifdef _M_ARM_64
-  // We need to get the CPU's cache line size
-  // We expect sane targets that have correct cacheline sizes across clusters
-  uint64_t CTR;
-  __asm volatile ("mrs %[ctr], ctr_el0"
-    : [ctr] "=r"(CTR));
-
-  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
-  ICacheLineSize = 4 << (CTR & 0xF);
-
-  // Test if this CPU supports float exception trapping by attempting to enable
-  // On unsupported these bits are architecturally defined as RAZ/WI
-  constexpr uint32_t ExceptionEnableTraps =
-    (1U << 8) |  // Invalid Operation float exception trap enable
-    (1U << 9) |  // Divide by zero float exception trap enable
-    (1U << 10) | // Overflow float exception trap enable
-    (1U << 11) | // Underflow float exception trap enable
-    (1U << 12) | // Inexact float exception trap enable
-    (1U << 15);  // Input Denormal float exception trap enable
-
-  uint32_t OriginalFPCR = GetFPCR();
-  uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
-  SetFPCR(FPCR);
-  FPCR = GetFPCR();
-  SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
-
-  // Set FPCR back to original just in case anything changed
-  SetFPCR(OriginalFPCR);
-#endif
-
-#ifdef VIXL_SIMULATOR
-  // simulator doesn't support dc(ZVA)
-  SupportsCLZERO = false;
-  // Simulator doesn't support SHA
-  SupportsSHA = false;
-#else
-  // Check if we can support cacheline clears
-  uint32_t DCZID = GetDCZID();
-  if ((DCZID & DCZID_DZP_MASK) == 0) {
-    uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
-    uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
-    // If the DC ZVA size matches the emulated cache line size
-    // This means we can use the instruction
-    SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
-  }
-#endif
-
-#if defined(_M_X86_64)
-  // Hardcoded cacheline size.
-  DCacheLineSize = 64U;
-  ICacheLineSize = 64U;
-
-#if !defined(VIXL_SIMULATOR)
-  Xbyak::util::Cpu X86Features{};
-  SupportsAES = X86Features.has(Xbyak::util::Cpu::tAESNI);
-  SupportsCRC = X86Features.has(Xbyak::util::Cpu::tSSE42);
-  SupportsRAND = X86Features.has(Xbyak::util::Cpu::tRDRAND) && X86Features.has(Xbyak::util::Cpu::tRDSEED);
-  SupportsRCPC = true;
-  SupportsTSOImm9 = true;
-  Supports3DNow = X86Features.has(Xbyak::util::Cpu::t3DN) && X86Features.has(Xbyak::util::Cpu::tE3DN);
-  SupportsSSE4A = X86Features.has(Xbyak::util::Cpu::tSSE4a);
-  SupportsAVX = true;
-  SupportsAVX2 = true;
-  SupportsSHA = X86Features.has(Xbyak::util::Cpu::tSHA);
-  SupportsBMI1 = X86Features.has(Xbyak::util::Cpu::tBMI1);
-  SupportsBMI2 = X86Features.has(Xbyak::util::Cpu::tBMI2);
-  SupportsCLWB = X86Features.has(Xbyak::util::Cpu::tCLWB);
-  SupportsPMULL_128Bit = X86Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
-
-  // xbyak doesn't know how to check for CLZero
-  // First ensure we support a new enough extended CPUID function range
-
-  uint32_t data[4];
-  Xbyak::util::Cpu::getCpuid(0x8000'0000, data);
-  if (data[0] >= 0x8000'0008U) {
-    // CLZero defined in 8000_00008_EBX[bit 0]
-    Xbyak::util::Cpu::getCpuid(0x8000'0008, data);
-    SupportsCLZERO = data[1] & 1;
-  }
-
-  SupportsAFP = true;
-  SupportsFloatExceptions = true;
-#endif
-#endif
-  SupportsPreserveAllABI = FEXCORE_HAS_PRESERVE_ALL_ATTR;
-  OverrideFeatures(this);
-}
-}
@@ -6,69 +6,59 @@
 #include "Interface/IR/IR.h"

 namespace FEXCore::CPU {
-FEXCORE_PRESERVE_ALL_ATTR
-static void LoadDeferredFCW(uint16_t NewFCW) {
-  auto PC = (NewFCW >> 8) & 3;
-  switch(PC) {
-    case 0: extF80_roundingPrecision = 32; break;
-    case 2: extF80_roundingPrecision = 64; break;
-    case 3: extF80_roundingPrecision = 80; break;
-    case 1: LOGMAN_MSG_A_FMT("Invalid x87 precision mode, {}", PC);
+FEXCORE_PRESERVE_ALL_ATTR static softfloat_state SoftFloatStateFromFCW(uint16_t FCW) {
+  softfloat_state State;
+  State.detectTininess = softfloat_tininess_afterRounding;
+  State.exceptionFlags = 0;
+
+  auto PC = (FCW >> 8) & 3;
+  switch (PC) {
+  case 0: State.roundingPrecision = 32; break;
+  case 2: State.roundingPrecision = 64; break;
+  case 3: State.roundingPrecision = 80; break;
+  case 1: LOGMAN_MSG_A_FMT("Invalid x87 precision mode, {}", PC);
  }

-  auto RC = (NewFCW >> 10) & 3;
-  switch(RC) {
-    case 0:
-      softfloat_roundingMode = softfloat_round_near_even;
-      break;
-    case 1:
-      softfloat_roundingMode = softfloat_round_min;
-      break;
-    case 2:
-      softfloat_roundingMode = softfloat_round_max;
-      break;
-    case 3:
-      softfloat_roundingMode = softfloat_round_minMag;
-    break;
+  auto RC = (FCW >> 10) & 3;
+  switch (RC) {
+  case 0: State.roundingMode = softfloat_round_near_even; break;
+  case 1: State.roundingMode = softfloat_round_min; break;
+  case 2: State.roundingMode = softfloat_round_max; break;
+  case 3: State.roundingMode = softfloat_round_minMag; break;
  }
+
+  return State;
 }

 template<>
 struct OpHandlers<IR::OP_F80CVTTO> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle4(uint16_t NewFCW, float src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle4(uint16_t FCW, float src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat(&State, src);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle8(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle8(uint16_t FCW, double src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat(&State, src);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80CMP> {
-  template<uint32_t Flags>
-  FEXCORE_PRESERVE_ALL_ATTR
-  static uint64_t handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static uint64_t handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);

    bool eq, lt, nan;
    uint64_t ResultFlags = 0;

-    X80SoftFloat::FCMP(Src1, Src2, &eq, &lt, &nan);
-    if (Flags & (1 << IR::FCMP_FLAG_LT) &&
-        lt) {
+    X80SoftFloat::FCMP(&State, Src1, Src2, &eq, &lt, &nan);
+    if (lt) {
      ResultFlags |= (1 << IR::FCMP_FLAG_LT);
    }
-    if (Flags & (1 << IR::FCMP_FLAG_UNORDERED) &&
-        nan) {
+    if (nan) {
      ResultFlags |= (1 << IR::FCMP_FLAG_UNORDERED);
    }
-    if (Flags & (1 << IR::FCMP_FLAG_EQ) &&
-        eq) {
+    if (eq) {
      ResultFlags |= (1 << IR::FCMP_FLAG_EQ);
    }
    return ResultFlags;
@@ -77,322 +67,280 @@ struct OpHandlers<IR::OP_F80CMP> {

 template<>
 struct OpHandlers<IR::OP_F80CVT> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static float handle4(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static float handle4(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToF32(&State);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static double handle8(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static double handle8(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToF64(&State);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80CVTINT> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static int16_t handle2(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static int16_t handle2(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToI16(&State);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static int32_t handle4(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static int32_t handle4(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToI32(&State);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static int64_t handle8(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToI64(&State);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static int16_t handle2t(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    auto rv = extF80_to_i32(src, softfloat_round_minMag, false);
+  FEXCORE_PRESERVE_ALL_ATTR static int16_t handle2t(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    auto rv = extF80_to_i32(&State, src, softfloat_round_minMag, false);

-    if (rv > INT16_MAX) {
-      return INT16_MAX;
-    } else if (rv < INT16_MIN) {
+    if (rv > INT16_MAX || rv < INT16_MIN) {
+      ///< Indefinite value for 16-bit conversions.
      return INT16_MIN;
    } else {
      return rv;
    }
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static int32_t handle4t(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return extF80_to_i32(src, softfloat_round_minMag, false);
+  FEXCORE_PRESERVE_ALL_ATTR static int32_t handle4t(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return extF80_to_i32(&State, src, softfloat_round_minMag, false);
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static int64_t handle8t(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return extF80_to_i64(src, softfloat_round_minMag, false);
+  FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8t(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return extF80_to_i64(&State, src, softfloat_round_minMag, false);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80CVTTOINT> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle2(uint16_t NewFCW, int16_t src) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle2(uint16_t FCW, int16_t src) {
    return src;
  }

-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle4(uint16_t NewFCW, int32_t src) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle4(uint16_t FCW, int32_t src) {
    return src;
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80ROUND> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FRNDINT(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FRNDINT(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80F2XM1> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::F2XM1(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::F2XM1(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80TAN> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FTAN(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FTAN(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80SQRT> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FSQRT(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FSQRT(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80SIN> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FSIN(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FSIN(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80COS> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FCOS(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FCOS(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80XTRACT_EXP> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
    return X80SoftFloat::FXTRACT_EXP(Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80XTRACT_SIG> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
    return X80SoftFloat::FXTRACT_SIG(Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80ADD> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FADD(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FADD(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80SUB> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FSUB(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FSUB(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80MUL> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FMUL(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FMUL(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80DIV> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FDIV(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FDIV(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80FYL2X> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FYL2X(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FYL2X(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80ATAN> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FATAN(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FATAN(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80FPREM1> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FREM1(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FREM1(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80FPREM> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FREM(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FREM(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80SCALE> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FSCALE(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FSCALE(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64SIN> {
-  static double handle(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src) {
    return sin(src);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64COS> {
-  static double handle(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src) {
    return cos(src);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64TAN> {
-  static double handle(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src) {
    return tan(src);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64F2XM1> {
-  static double handle(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src) {
    return exp2(src) - 1.0;
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64ATAN> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    return atan2(src1, src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64FPREM> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    return fmod(src1, src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64FPREM1> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    return remainder(src1, src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64FYL2X> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    return src2 * log2(src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64SCALE> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
-    double trunc = (double)(int64_t)(src2); //truncate
+  static double handle(uint16_t FCW, double src1, double src2) {
+    double trunc = (double)(int64_t)(src2); // truncate
    return src1 * exp2(trunc);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80BCDSTORE> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
    bool Negative = Src1.Sign;

-    Src1 = X80SoftFloat::FRNDINT(Src1);
+    Src1 = X80SoftFloat::FRNDINT(&State, Src1);

    // Clear the Sign bit
    Src1.Sign = 0;

-    uint64_t Tmp = Src1;
+    uint64_t Tmp = Src1.ToI64(&State);
    X80SoftFloat Rv;
-    uint8_t *BCD = reinterpret_cast<uint8_t*>(&Rv);
+    uint8_t* BCD = reinterpret_cast<uint8_t*>(&Rv);
    memset(BCD, 0, 10);

    for (size_t i = 0; i < 9; ++i) {
@@ -422,11 +370,9 @@ struct OpHandlers<IR::OP_F80BCDSTORE> {

 template<>
 struct OpHandlers<IR::OP_F80BCDLOAD> {
-  FEXCORE_PRESERVE_ALL_ATTR
-  static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src) {
-    LoadDeferredFCW(NewFCW);
-    uint8_t *Src1 = reinterpret_cast<uint8_t *>(&Src);
-    uint64_t BCD{};
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src) {
+    uint8_t* Src1 = reinterpret_cast<uint8_t*>(&Src);
+    uint64_t BCD {};
    // We walk through each uint8_t and pull out the BCD encoding
    // Each 4bit split is a digit
    // Only 0-9 is supported, A-F results in undefined data