Docs: Update for release FEX-2202

FEXCore: Defer a significant number of ALU flag calculation

.github/ISSUE_TEMPLATE/potential-game-bug.md

@@ -0,0 +1,45 @@
+---
+name: Potential Game Bug
+about: A bug in FEX-Emu that causes a problem in a game
+title: "[Game]: [Short Problem Description]"
+labels: Game related
+assignees: ''
+
+---
+
+**What Game**
+The game name.
+A link to the storefront where to get the game. GOG, Steam, Itch.io, etc
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**To Reproduce**
+Steps to reproduce the behavior:
+1. Go to '...'
+2. Click on '....'
+3. Scroll down to '....'
+4. See error
+
+**Expected behavior**
+A clear and concise description of what you expected to happen.
+
+**Screenshots and Video**
+If applicable, add screenshots and video to help explain your problem.
+
+**System information:**
+ - OS: [eg: Ubuntu 21.10]
+ - CPU/SoC: [eg: Snapdragon 888, Intel Core i8-12900k]
+ - Video driver version: [eg: OpenGL ES 3.2 Mesa 22.0.0-devel (git-9ff086052a)]
+ - RootFS used: [eg: Ubuntu 21.10 Official Rootfs]
+ - FEX version: (FEXGetConfig --version) [eg: FEX-2112-155-gc691d709]
+ - Thunks Enabled: [Yes/No]
+
+**Additional context**
+ - Is this an x86 or x86-64 game: [x86/x86-64/Both]
+ - Does this reproduce on x86-64 host with FEX: [Yes/No/Untested]
+ - Does this reproduce on AArch64 with Radeon/Intel/Nvidia: [Yes/No/Untested]
+ - Is this a Vulkan game: [Yes/No/Unknown]
+   - If Yes, What is your Vulkan driver:
+
+Add any other context about the problem here.

.github/workflows/ccpp.yml

@@ -13,21 +13,27 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
+  FEX_FORCE32BITALLOCATOR: 1
 
 jobs:
   build:
     runs-on: ${{ matrix.arch }}
     strategy:
       matrix:
-        arch: [[self-hosted, x64], [self-hosted, ARMv8.0], [self-hosted, ARMv8.2]]
+        arch: [[self-hosted, x64], [self-hosted, ARMv8.0], [self-hosted, ARMv8.2], [self-hosted, ARMv8.4]]
       fail-fast: false
 
     steps:
     - uses: actions/checkout@v2
 
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
     - name : submodule checkout
       # Need to update submodules
-      run: git submodule update --init --depth 1
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
 
     - name: Clean Build Environment
       run: rm -Rf ${{runner.workspace}}/build
@@ -45,7 +51,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True
 
     - name: Build
       working-directory: ${{runner.workspace}}/build
@@ -113,13 +119,47 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC64.log || true
 
+    - name: gcc target tests 32
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_32
+
+    - name: GCC32 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC32.log || true
+
+    - name: Struct verifier tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target struct_verifier
+
+    - name: Struct verifier Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_StructVerifier.log || true
+
+    - name: APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target api_tests
+
+    - name: APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_APITests.log || true
+
     - name: Truncate test results
       if: ${{ always() }}
       shell: bash
       working-directory: ${{runner.workspace}}/build
       # Cap out the log files at 20M in case something crash spins and dumps fault text
       # ASM tests get quite close to 10MB
-      run: truncate --size=20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
 
     - name: Set runner name
       if: ${{ always() }}

.gitmodules

@@ -1,7 +1,7 @@
 [submodule "External/vixl"]
 	shallow = true
 	path = External/vixl
-	url = https://github.com/Sonicadvance1/vixl.git
+	url = https://github.com/FEX-Emu/vixl.git
 [submodule "External/cpp-optparse"]
 	path = External/cpp-optparse
 	url = https://github.com/Sonicadvance1/cpp-optparse
@@ -30,3 +30,18 @@
         shallow = true
 	path = External/fex-gcc-target-tests-bins
 	url = https://github.com/FEX-Emu/fex-gcc-target-tests-bins.git
+[submodule "External/jemalloc"]
+	path = External/jemalloc
+	url = https://github.com/FEX-Emu/jemalloc.git
+[submodule "External/fmt"]
+	path = External/fmt
+	url = https://github.com/fmtlib/fmt.git
+[submodule "External/drm-headers"]
+	path = External/drm-headers
+	url = https://github.com/FEX-Emu/drm-headers.git
+[submodule "External/xxhash"]
+	path = External/xxhash
+	url = https://github.com/FEX-Emu/xxHash.git
+[submodule "External/Catch2"]
+	path = External/Catch2
+	url = https://github.com/catchorg/Catch2.git

CMakeLists.txt

@@ -12,11 +12,24 @@ option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
 option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
 option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_VISUAL_DEBUGGER "Enables the visual debugger for compiling" FALSE)
+option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
+option(ENABLE_WERROR "Enables -Werror" FALSE)
+option(ENABLE_STATIC_PIE "Enables static-pie build" FALSE)
+option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
+option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
+option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
+option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
+option(ENABLE_INTERPRETER "Enables FEX's Interpreter" FALSE)
 
 set (X86_C_COMPILER "x86_64-linux-gnu-gcc" CACHE STRING "c compiler for compiling x86 guest libs")
 set (X86_CXX_COMPILER "x86_64-linux-gnu-g++" CACHE STRING "c++ compiler for compiling x86 guest libs")
 set (DATA_DIRECTORY "${CMAKE_INSTALL_PREFIX}/share/fex-emu" CACHE PATH "global data directory")
 
+# These options are meant for package management
+set (TUNE_CPU "native" CACHE STRING "Override the CPU the build is tuned for")
+set (TUNE_ARCH "generic" CACHE STRING "Override the Arch the build is tuned for")
+set (OVERRIDE_VERSION "detect" CACHE STRING "Override the FEX version in the format of <MMYY>{.<REV>}")
+
 string(TOUPPER "${CMAKE_BUILD_TYPE}" CMAKE_BUILD_TYPE)
 if (CMAKE_BUILD_TYPE MATCHES "DEBUG")
   set(ENABLE_ASSERTIONS TRUE)
@@ -27,12 +40,9 @@ if (ENABLE_ASSERTIONS)
   add_definitions(-DASSERTIONS_ENABLED=1)
 endif()
 
-if (ENABLE_IWYU)
-  find_program(IWYU_EXE "iwyu")
-  if (IWYU_EXE)
-    message(STATUS "IWYU enabled")
-    set(CMAKE_CXX_INCLUDE_WHAT_YOU_USE "${IWYU_EXE}")
-  endif()
+if (ENABLE_INTERPRETER)
+  message(STATUS "Interpreter enabled")
+  add_definitions(-DINTERPRETER_ENABLED=1)
 endif()
 
 set(CMAKE_CXX_STANDARD 20)
@@ -50,6 +60,25 @@ else()
   set(CMAKE_INTERPROCEDURAL_OPTIMIZATION FALSE)
 endif()
 
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+  option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
+  if (NOT ENABLE_X86_HOST_DEBUG)
+    message(FATAL_ERROR
+      " Be warned: FEX isn't optimized for x86_64 hosts!\n"
+      " Support for x86_64 hosts is only for debugging and convenience!\n"
+      " Don't expect amazing performance or optimal code generation!\n"
+      " Pass -DENABLE_X86_HOST_DEBUG=True to bypass this message!")
+  endif()
+  set(_M_X86_64 1)
+  add_definitions(-D_M_X86_64=1)
+  set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
+endif()
+
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
+  set(_M_ARM_64 1)
+  add_definitions(-D_M_ARM_64=1)
+endif()
+
 find_program(CCACHE_PROGRAM ccache)
 if(CCACHE_PROGRAM)
   message(STATUS "CCache enabled")
@@ -61,14 +90,156 @@ if (ENABLE_XRAY)
   link_libraries(-fxray-instrument)
 endif()
 
+if (ENABLE_COMPILE_TIME_TRACE)
+  add_compile_options(-ftime-trace)
+  link_libraries(-ftime-trace)
+endif()
+
+set (PTHREAD_LIB pthread)
 if (ENABLE_LLD)
-  link_libraries(-fuse-ld=lld)
+  set (LD_OVERRIDE "-fuse-ld=lld")
+  link_libraries(${LD_OVERRIDE})
+endif()
+
+if (ENABLE_LIBCXX)
+  message(WARNING "This is an unsupported configuration and should only be used for testing")
+  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11 -stdlib=libc++")
+  set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -stdlib=libc++ -lc++abi")
+endif()
+
+if (NOT ENABLE_OFFLINE_TELEMETRY)
+  # Disable FEX offline telemetry entirely if asked
+  add_definitions(-DFEX_DISABLE_TELEMETRY=1)
+endif()
+
+if (ENABLE_STATIC_PIE)
+  if (_M_ARM_64 AND ENABLE_LLD)
+    message (FATAL_ERROR "Static linking does not currently work with AArch64+LLD. Use GNU ld for now.")
+  endif()
+
+  file(WRITE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt.c
+    "int main(int argc, char* argv[])
+      {
+        return 0;
+      }")
+
+  # Compile the test application with our LD_OVERRIDE and static-pie options
+  try_compile(
+    COMPILE_RESULT
+    ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp
+    ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt.c
+    COMPILE_DEFINITIONS "-fPIE ${LD_OVERRIDE}"
+    LINK_LIBRARIES "-static-pie ${LD_OVERRIDE}"
+    COPY_FILE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt
+  )
+
+  if (${COMPILE_RESULT})
+    # Read the symbols from the elf
+    execute_process(COMMAND
+      readelf -s ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt
+      OUTPUT_FILE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/plt_out.txt
+      OUTPUT_VARIABLE PLT_SYMBOLS)
+
+    # Pull out the __rela_iplt_{start,end} symbols if they exist
+    execute_process(COMMAND
+      "grep" "__rela_iplt" ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/plt_out.txt
+      OUTPUT_VARIABLE PLT_SYMBOLS)
+
+    set (SYMBOLS_FINE TRUE)
+    set (HAS_IPLT -1)
+    # Check if we have any symbols in our grep output
+    # The symbols must either not exist at all OR the symbols are zero
+    if (PLT_SYMBOLS)
+      string(FIND ${PLT_SYMBOLS} "__rela_iplt_start" HAS_IPLT)
+    endif()
+
+    if (NOT HAS_IPLT EQUAL -1)
+      # We have some symbols from readelf. Let's parse the results to check if they are zero
+      # Format: '35: 0000000000000000     0 NOTYPE  LOCAL  HIDDEN   UND __rela_iplt_start'
+      string(REPLACE "\n" ";" SYMBOL_LIST ${PLT_SYMBOLS})
+      foreach (SYMBOL ${SYMBOL_LIST})
+        # strip any leading and trailing whitespace
+        string (STRIP ${SYMBOL} SYMBOL)
+        # Convert string to a list
+        string(REPLACE " " ";" SYMBOL_VALUES ${SYMBOL}})
+        # Pull out the address argument
+        list(GET SYMBOL_VALUES 1 OFFSET)
+
+        # Check against integer zero
+        if (NOT ${OFFSET} EQUAL 0)
+          # Symbol wasn't zero, this now fails
+          set (SYMBOLS_FINE FALSE)
+        endif()
+      endforeach()
+    endif()
+
+    if (SYMBOLS_FINE)
+      # We can now exnable static-pie
+      set (STATIC_PIE_OPTIONS "-static-pie")
+      # Pthreads has an issue with exposing symbols
+      # We need to make some concessions to the pthread gods
+      if (ENABLE_LLD)
+        set (PTHREAD_LIB
+          -Wl,--undefined-glob=pthread_*
+          -Wl,--undefined=__cxa_finalize
+          -Wl,--undefined=_pthread_cleanup_push_defer
+          -Wl,--undefined=_pthread_cleanup_pop_restore
+          -Wl,--undefined=__pthread_cleanup_upto
+          pthread)
+      else()
+        set (PTHREAD_LIB
+          -Wl,--undefined=pthread_join
+          -Wl,--undefined=pthread_attr_getdetachstate
+          -Wl,--undefined=pthread_sigmask
+          -Wl,--undefined=pthread_mutex_lock
+          -Wl,--undefined=pthread_cond_init
+          -Wl,--undefined=pthread_attr_init
+          -Wl,--undefined=pthread_mutex_unlock
+          -Wl,--undefined=pthread_mutexattr_destroy
+          -Wl,--undefined=pthread_detach
+          -Wl,--undefined=pthread_mutex_init
+          -Wl,--undefined=pthread_getattr_np
+          -Wl,--undefined=pthread_cond_timedwait
+          -Wl,--undefined=pthread_attr_destroy
+          -Wl,--undefined=pthread_mutexattr_settype
+          -Wl,--undefined=pthread_rwlock_unlock
+          -Wl,--undefined=pthread_rwlock_wrlock
+          -Wl,--undefined=pthread_setspecific
+          -Wl,--undefined=pthread_create
+          -Wl,--undefined=pthread_cond_clockwait
+          -Wl,--undefined=pthread_key_create
+          -Wl,--undefined=pthread_rwlock_rdlock
+          -Wl,--undefined=pthread_setname_np
+          -Wl,--undefined=pthread_cond_signal
+          -Wl,--undefined=pthread_mutexattr_init
+          -Wl,--undefined=pthread_attr_setstack
+          -Wl,--undefined=pthread_self
+          -Wl,--undefined=pthread_getaffinity_np
+          -Wl,--undefined=pthread_cond_wait
+          -Wl,--undefined=pthread_mutex_trylock
+          -Wl,--undefined=pthread_cond_broadcast
+          -Wl,--undefined=pthread_cond_destroy
+          -Wl,--undefined=pthread_getspecific
+          -Wl,--undefined=pthread_key_delete
+          -Wl,--undefined=pthread_once
+          -Wl,--undefined=__cxa_finalize
+          -Wl,--undefined=_pthread_cleanup_push_defer
+          -Wl,--undefined=_pthread_cleanup_pop_restore
+          -Wl,--undefined=__pthread_cleanup_upto
+          pthread)
+      endif()
+    else()
+      message (FATAL_ERROR "Application has __rela_iplt_{start,end} symbols. Which means static-pie can't be enabled")
+    endif()
+  else()
+    message (FATAL_ERROR "Couldn't compile static-pie test. Static-pie can't be enabled! Is your glibc compiled without static-pie?")
+  endif()
 endif()
 
 if (ENABLE_ASAN)
   add_definitions(-DENABLE_ASAN=1)
-  add_compile_options(-fno-omit-frame-pointer -fsanitize=address)
-  link_libraries(-fno-omit-frame-pointer -fsanitize=address)
+  add_compile_options(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
+  link_libraries(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
 endif()
 
 if (ENABLE_TSAN)
@@ -76,41 +247,56 @@ if (ENABLE_TSAN)
   link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
 endif()
 
+if (ENABLE_JEMALLOC)
+  add_definitions(-DENABLE_JEMALLOC=1)
+  add_subdirectory(External/jemalloc/)
+  include_directories(External/jemalloc/pregen/include/)
+else()
+  message (STATUS
+    " jemalloc disabled!\n"
+    " This is not a recommended configuration!\n"
+    " This will very explicitly break 32-bit application execution!\n"
+    " Use at your own risk!")
+endif()
+
 set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
 set (CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
 
 set (CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
 set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
-  set(_M_X86_64 1)
-  add_definitions(-D_M_X86_64=1)
-  set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
-endif()
-
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
-  set(_M_ARM_64 1)
-  add_definitions(-D_M_ARM_64=1)
-  add_subdirectory(External/vixl/)
-  include_directories(External/vixl/src/)
-  if(CMAKE_BUILD_TYPE MATCHES DEBUG)
-    add_definitions(-DVIXL_DEBUG=1)
-  endif()
-endif()
+add_subdirectory(External/vixl/)
+include_directories(External/vixl/src/)
 
 if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
   # This means we were attempted to get compiled with GCC
   message(FATAL_ERROR "FEX doesn't support getting compiled with GCC!")
 endif()
 
-find_package(Python 3.0 REQUIRED COMPONENTS Interpreter Development)
+find_package(PkgConfig REQUIRED)
+find_package(Python 3.0 REQUIRED COMPONENTS Interpreter)
+
+add_subdirectory(External/xxhash/)
+include_directories(External/xxhash/)
 
 add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")
 
+if (BUILD_TESTS)
+  option(CATCH_BUILD_STATIC_LIBRARY "" ON)
+  set(CATCH_BUILD_STATIC_LIBRARY ON)
+  add_subdirectory(External/Catch2/)
+
+  # Pull in catch_discover_tests definition
+  list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/External/Catch2/contrib/")
+  include(Catch)
+endif()
+
 add_subdirectory(External/cpp-optparse/)
 include_directories(External/cpp-optparse/)
 
+add_subdirectory(External/fmt/)
+
 add_subdirectory(External/imgui/)
 include_directories(External/imgui/)
 
@@ -144,57 +330,277 @@ if(ENUM_ENUM_WARNING)
   add_compile_options(-Wno-deprecated-enum-enum-conversion)
 endif()
 
-check_cxx_compiler_flag("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE)
-if(COMPILER_SUPPORTS_MARCH_NATIVE)
-  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native")
+if(ENABLE_WERROR OR ENABLE_STRICT_WERROR)
+  add_compile_options(-Werror)
+  if (NOT ENABLE_STRICT_WERROR)
+    # Disable some Werror that can add frustration when developing
+    add_compile_options(-Wno-error=unused-variable)
+  endif()
 endif()
 
-if(_M_ARM_64)
-  # Due to an oversight in llvm, it declares any reasonably new Kryo CPU to only be ARMv8.0
-  # Manually detect newer CPU revisions until clang and llvm fixes their bug
-  # This script will either provide a supported CPU or 'native'
-  # Additionally -march doesn't work under AArch64+Clang, so you have to use -mcpu or -mtune
-  execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo"
-    OUTPUT_VARIABLE AARCH64_CPU)
-
-  string(STRIP ${AARCH64_CPU} AARCH64_CPU)
-
-  check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
-  if(COMPILER_SUPPORTS_CPU_TYPE)
-    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=${AARCH64_CPU}")
+if (NOT TUNE_ARCH STREQUAL "generic")
+  check_cxx_compiler_flag("-march=${TUNE_ARCH}" COMPILER_SUPPORTS_ARCH_TYPE)
+  if(COMPILER_SUPPORTS_ARCH_TYPE)
+    add_compile_options("-march=${TUNE_ARCH}")
+  else()
+    message(FATAL_ERROR "Trying to compile arch type '${TUNE_ARCH}' but the compiler doesn't support this")
   endif()
 endif()
 
+if (TUNE_CPU STREQUAL "native")
+  if(_M_ARM_64)
+    if (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL 999999.0)
+      # Clang 12.0 fixed the -mcpu=native bug with mixed big.little implementers
+      # Clang can not currently check for native Apple M1 type in hypervisor. Currently disabled
+      check_cxx_compiler_flag("-mcpu=native" COMPILER_SUPPORTS_CPU_TYPE)
+      if(COMPILER_SUPPORTS_CPU_TYPE)
+        add_compile_options("-mcpu=native")
+      endif()
+    else()
+      # Due to an oversight in llvm, it declares any reasonably new Kryo CPU to only be ARMv8.0
+      # Manually detect newer CPU revisions until clang and llvm fixes their bug
+      # This script will either provide a supported CPU or 'native'
+      # Additionally -march doesn't work under AArch64+Clang, so you have to use -mcpu or -mtune
+      execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo" "${CMAKE_CXX_COMPILER_VERSION}"
+        OUTPUT_VARIABLE AARCH64_CPU)
+
+      string(STRIP ${AARCH64_CPU} AARCH64_CPU)
+
+      check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
+      if(COMPILER_SUPPORTS_CPU_TYPE)
+        add_compile_options("-mcpu=${AARCH64_CPU}")
+      endif()
+    endif()
+  else()
+    check_cxx_compiler_flag("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE)
+    if(COMPILER_SUPPORTS_MARCH_NATIVE)
+      add_compile_options("-march=native")
+    endif()
+  endif()
+else()
+  check_cxx_compiler_flag("-mcpu=${TUNE_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
+  if(COMPILER_SUPPORTS_CPU_TYPE)
+    add_compile_options("-mcpu=${TUNE_CPU}")
+  else()
+    message(FATAL_ERROR "Trying to compile cpu type '${TUNE_CPU}' but the compiler doesn't support this")
+  endif()
+endif()
+
+if (ENABLE_IWYU)
+  find_program(IWYU_EXE "iwyu")
+  if (IWYU_EXE)
+    message(STATUS "IWYU enabled")
+    set(CMAKE_CXX_INCLUDE_WHAT_YOU_USE "${IWYU_EXE}")
+  endif()
+endif()
+
+if (ENABLE_CLANG_FORMAT)
+  find_program(CLANG_TIDY_EXE "clang-tidy")
+  if (NOT CLANG_TIDY_EXE)
+    message(FATAL_ERROR "Couldn't find clang-tidy")
+  endif()
+
+  set(CLANG_TIDY_FLAGS
+    "-checks=*"
+    "-fuchsia*"
+    "-bugprone-macro-parentheses"
+    "-clang-analyzer-core.*"
+    "-cppcoreguidelines-pro-type-*"
+    "-cppcoreguidelines-pro-bounds-array-to-pointer-decay"
+    "-cppcoreguidelines-pro-bounds-pointer-arithmetic"
+    "-cppcoreguidelines-avoid-c-arrays"
+    "-cppcoreguidelines-avoid-magic-numbers"
+    "-cppcoreguidelines-pro-bounds-constant-array-index"
+    "-cppcoreguidelines-no-malloc"
+    "-cppcoreguidelines-special-member-functions"
+    "-cppcoreguidelines-owning-memory"
+    "-cppcoreguidelines-macro-usage"
+    "-cppcoreguidelines-avoid-goto"
+    "-google-readability-function-size"
+    "-google-readability-namespace-comments"
+    "-google-readability-braces-around-statements"
+    "-google-build-using-namespace"
+    "-hicpp-*"
+    "-llvm-namespace-comment"
+    "-llvm-include-order" # Messes up with case sensitivity
+    "-llvmlibc-*"
+    "-misc-unused-parameters"
+    "-modernize-loop-convert"
+    "-modernize-use-auto"
+    "-modernize-avoid-c-arrays"
+    "-modernize-use-nodiscard"
+    "readability-*"
+    "-readability-function-size"
+    "-readability-implicit-bool-conversion"
+    "-readability-braces-around-statements"
+    "-readability-else-after-return"
+    "-readability-magic-numbers"
+    "-readability-named-parameter"
+    "-readability-uppercase-literal-suffix"
+    "-cert-err34-c"
+    "-cert-err58-cpp"
+    "-bugprone-exception-escape"
+    )
+  string(REPLACE ";" "," CLANG_TIDY_FLAGS "${CLANG_TIDY_FLAGS}")
+  set(CMAKE_CXX_CLANG_TIDY ${CLANG_TIDY_EXE} "${CLANG_TIDY_FLAGS}")
+endif()
+
 add_compile_options(-Wall)
 
-add_subdirectory(External/FEXCore)
-
-add_subdirectory(Source/)
+configure_file(
+  ${CMAKE_CURRENT_SOURCE_DIR}/include/Config.h.in
+  ${CMAKE_BINARY_DIR}/generated/ConfigDefines.h)
 
 if (BUILD_TESTS)
   include(CTest)
   enable_testing()
   message(STATUS "Unit tests are enabled")
+endif()
+
+add_subdirectory(FEXHeaderUtils/)
+include_directories(FEXHeaderUtils/)
+
+add_subdirectory(External/FEXCore)
+
+# Binfmt_misc files must be installed prior to Source/ installs
+add_subdirectory(Data/binfmts/)
+
+add_subdirectory(Source/)
+add_subdirectory(Data/AppConfig/)
+
+# Install the ThunksDB file
+install(
+  FILES ${CMAKE_CURRENT_SOURCE_DIR}/Data/ThunksDB.json
+  DESTINATION ${DATA_DIRECTORY}/)
+
+if (BUILD_TESTS)
   add_subdirectory(unittests/)
 endif()
 
 if (BUILD_THUNKS)
+  add_subdirectory(ThunkLibs/Generator)
+
   include(ExternalProject)
 
   ExternalProject_Add(host-libs
     PREFIX host-libs
     SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/HostLibs"
     BINARY_DIR "Host"
+    CMAKE_ARGS
+      "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}"
+      "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
+      "-DGENERATOR_EXE=$<TARGET_FILE:thunkgen>"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
+    DEPENDS thunkgen
+  )
+
+  install(
+    CODE "MESSAGE(\"-- Installing: host-libs\")"
+    CODE "
+    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target ThunkHostsInstall
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Host
+    )"
+    DEPENDS host-libs
   )
 
   ExternalProject_Add(guest-libs
     PREFIX guest-libs
     SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/GuestLibs"
     BINARY_DIR "Guest"
-    CMAKE_ARGS "-DX86_C_COMPILER:STRING=${X86_C_COMPILER}" "-DX86_CXX_COMPILER:STRING=${X86_CXX_COMPILER}"
+    CMAKE_ARGS
+      "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}"
+      "-DX86_C_COMPILER:STRING=${X86_C_COMPILER}"
+      "-DX86_CXX_COMPILER:STRING=${X86_CXX_COMPILER}"
+      "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
+      "-DSTRUCT_VERIFIER=${CMAKE_SOURCE_DIR}/Scripts/StructPackVerifier.py"
+      "-DGENERATOR_EXE=$<TARGET_FILE:thunkgen>"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
+    DEPENDS thunkgen
+  )
+
+  install(
+    CODE "MESSAGE(\"-- Installing: guest-libs\")"
+    CODE "
+    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target ThunkGuestsInstall
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest
+    )"
+    DEPENDS guest-libs
   )
 endif()
+
+set(FEX_VERSION_MAJOR "0")
+set(FEX_VERSION_MINOR "0")
+set(FEX_VERSION_PATCH "0")
+
+if (OVERRIDE_VERSION STREQUAL "detect")
+  find_package(Git)
+  if (GIT_FOUND)
+    execute_process(
+      COMMAND ${GIT_EXECUTABLE} describe --abbrev=0
+      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+      OUTPUT_VARIABLE GIT_DESCRIBE_STRING
+      RESULT_VARIABLE GIT_ERROR
+      ERROR_QUIET
+      OUTPUT_STRIP_TRAILING_WHITESPACE
+    )
+
+    if (NOT ${GIT_ERROR} EQUAL 0)
+      # Likely built in a way that doesn't have tags
+      # Setup a version tag that is unknown
+      set(GIT_DESCRIBE_STRING "FEX-0000")
+    endif()
+  endif()
+else()
+  set(GIT_DESCRIBE_STRING "FEX-${OVERRIDE_VERSION}")
+endif()
+
+# Parse the version here
+# Change something like `FEX-2106.1-76-<hash>` in to a list
+string(REPLACE "-" ";" DESCRIBE_LIST ${GIT_DESCRIBE_STRING})
+
+# Extract the `2106.1` element
+list(GET DESCRIBE_LIST 1 DESCRIBE_LIST)
+
+# Change `2106.1` in to a list
+string(REPLACE "." ";" DESCRIBE_LIST ${DESCRIBE_LIST})
+
+# Calculate list size
+list(LENGTH DESCRIBE_LIST LIST_SIZE)
+
+# Pull out the major version
+list(GET DESCRIBE_LIST 0 FEX_VERSION_MAJOR)
+
+# Minor version only exists if there is a .1 at the end
+# eg: 2106 versus 2106.1
+if (LIST_SIZE GREATER 1)
+  list(GET DESCRIBE_LIST 1 FEX_VERSION_MINOR)
+endif()
+
+# Package creation
+set (CPACK_GENERATOR "DEB")
+if (ENABLE_STATIC_PIE)
+  set (CPACK_PACKAGE_NAME fex-emu-static)
+  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "fex-emu")
+else()
+  set (CPACK_PACKAGE_NAME fex-emu)
+  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "fex-emu-static")
+endif()
+set (CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${GIT_DESCRIBE_STRING}_${CMAKE_SYSTEM_PROCESSOR}")
+set (CPACK_PACKAGE_CONTACT "FEX-Emu Maintainers <team@fex-emu.org>")
+set (CPACK_PACKAGE_VERSION_MAJOR "${FEX_VERSION_MAJOR}")
+set (CPACK_PACKAGE_VERSION_MINOR "${FEX_VERSION_MINOR}")
+set (CPACK_PACKAGE_VERSION_PATCH "${FEX_VERSION_PATCH}")
+set (CPACK_PACKAGE_DESCRIPTION_FILE "${CMAKE_CURRENT_SOURCE_DIR}/CPack/Description.txt")
+
+# Debian defines
+set (CPACK_DEBIAN_PACKAGE_DEPENDS "libc6, libstdc++6, libepoxy0, libsdl2-2.0-0, libegl1, libx11-6, squashfuse")
+set (CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA
+  "${CMAKE_CURRENT_SOURCE_DIR}/CPack/postinst;${CMAKE_CURRENT_SOURCE_DIR}/CPack/prerm;${CMAKE_CURRENT_SOURCE_DIR}/CPack/triggers")
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
+  # binfmt_misc conflicts with qemu-user-static
+  # We also only install binfmt_misc on aarch64 hosts
+  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "${CPACK_DEBIAN_PACKAGE_CONFLICTS}, qemu-user-static")
+endif()
+include (CPack)

CPack/Description.txt

@@ -0,0 +1,3 @@
+x86 and x86-64 Linux emulator
+
+FEX is very much work in progress, so expect things to change.

CPack/postinst

@@ -0,0 +1,18 @@
+#!/bin/sh
+set -e
+update_binfmt() {
+  # Check for update-binfmts
+  command -v update-binfmts >/dev/null || return 0
+
+  # Setup binfmt_misc
+  update-binfmts --import FEX-x86
+  update-binfmts --import FEX-x86_64
+}
+
+# Install FEXInterpreter hardlink
+# Needs to be done before setting up binfmt_misc
+ln -f /usr/bin/FEXLoader /usr/bin/FEXInterpreter
+
+if [ $(uname -m) = 'aarch64' ]; then
+  update_binfmt
+fi

CPack/prerm

@@ -0,0 +1,17 @@
+#!/bin/sh
+set -e
+update_binfmt() {
+  # Check for update-binfmts
+  command -v update-binfmts >/dev/null || return 0
+
+  # Uninstall
+  update-binfmts --unimport FEX-x86
+  update-binfmts --unimport FEX-x86_64
+}
+
+if [ $(uname -m) = 'aarch64' ]; then
+  update_binfmt
+fi
+
+# Remove FEXInterpreter hardlink
+unlink /usr/bin/FEXInterpreter

CPack/triggers

@@ -0,0 +1 @@
+activate-noawait ldconfig

Data/AppConfig/CMakeLists.txt

@@ -0,0 +1,25 @@
+file(GLOB CONFIG_SOURCES CONFIGURE_DEPENDS *.json)
+file(GLOB GEN_CONFIG_SOURCES CONFIGURE_DEPENDS *.json.in)
+
+# Any application configuration json file gets installed
+foreach(CONFIG_SRC ${CONFIG_SOURCES})
+  install(FILES ${CONFIG_SRC}
+    DESTINATION ${DATA_DIRECTORY}/AppConfig/)
+endforeach()
+
+# Any configuration file json file that needs to be generated
+# First generate then install it
+foreach(GEN_CONFIG_SRC ${GEN_CONFIG_SOURCES})
+  # Get the filename only component
+  get_filename_component(CONFIG_NAME ${GEN_CONFIG_SRC} NAME_WE)
+
+  # Configure it
+  configure_file(
+    ${GEN_CONFIG_SRC}
+    ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}.json)
+
+  # Then install the configured json
+  install(
+    FILES ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}.json
+    DESTINATION ${DATA_DIRECTORY}/AppConfig/)
+endforeach()

Data/AppConfig/steam.json.in

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "Env": "STEAM_GAME_LAUNCH_SHELL=@CMAKE_INSTALL_PREFIX@/bin/FEXBash"
+  }
+}

Data/ThunksDB.json

@@ -0,0 +1,349 @@
+{
+  "DB": {
+    "GL": {
+      "Library" : "libGL-guest.so",
+      "Depends": [
+        "X11"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libGL.so",
+        "/usr/lib/x86_64-linux-gnu/libGL.so.1",
+        "/usr/lib/x86_64-linux-gnu/libGL.so.1.2.0",
+        "/usr/lib/x86_64-linux-gnu/libGL.so.1.7.0",
+        "/usr/local/lib/x86_64-linux-gnu/libGL.so",
+        "/usr/local/lib/x86_64-linux-gnu/libGL.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libGL.so.1.2.0",
+        "/usr/local/lib/x86_64-linux-gnu/libGL.so.1.7.0",
+        "/lib/x86_64-linux-gnu/libGL.so",
+        "/lib/x86_64-linux-gnu/libGL.so.1",
+        "/lib/x86_64-linux-gnu/libGL.so.1.2.0",
+        "/lib/x86_64-linux-gnu/libGL.so.1.7.0"
+      ]
+    },
+    "GLESv2": {
+      "Library": "libGLESv2-guest.so",
+      "Depends": [
+        "X11"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libGLESv2.so",
+        "/usr/lib/x86_64-linux-gnu/libGLESv2.so.2",
+        "/usr/lib/x86_64-linux-gnu/libGLESv2.so.2.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libGLESv2.so",
+        "/usr/local/lib/x86_64-linux-gnu/libGLESv2.so.2",
+        "/usr/local/lib/x86_64-linux-gnu/libGLESv2.so.2.0.0",
+        "/lib/x86_64-linux-gnu/libGLESv2.so",
+        "/lib/x86_64-linux-gnu/libGLESv2.so.2",
+        "/lib/x86_64-linux-gnu/libGLESv2.so.2.0.0"
+      ]
+    },
+    "X11": {
+      "Library": "libX11-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libX11.so",
+        "/usr/lib/x86_64-linux-gnu/libX11.so.6",
+        "/usr/lib/x86_64-linux-gnu/libX11.so.6.4.0",
+        "/usr/local/lib/x86_64-linux-gnu/libX11.so",
+        "/usr/local/lib/x86_64-linux-gnu/libX11.so.6",
+        "/usr/local/lib/x86_64-linux-gnu/libX11.so.6.4.0",
+        "/lib/x86_64-linux-gnu/libX11.so",
+        "/lib/x86_64-linux-gnu/libX11.so.6",
+        "/lib/x86_64-linux-gnu/libX11.so.6.4.0"
+      ]
+    },
+    "Vulkan-radeon": {
+      "Library": "libvulkan_radeon-guest.so",
+      "Depends": [
+        "xcb"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libvulkan_radeon.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_radeon.so",
+        "/lib/x86_64-linux-gnu/libvulkan_radeon.so"
+      ],
+      "Comment": [
+        "Vulkan library relies on xcb, otherwise it crashes with jemalloc"
+      ]
+    },
+    "Vulkan-lavapipe": {
+      "Library": "libvulkan_lvp-guest.so",
+      "Depends": [
+        "xcb"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libvulkan_lvp.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_lvp.so",
+        "/lib/x86_64-linux-gnu/libvulkan_lvp.so"
+      ]
+    },
+    "Vulkan-freedreno": {
+      "Library": "libvulkan_freedreno-guest.so",
+      "Depends": [
+        "xcb"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libvulkan_freedreno.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_freedreno.so",
+        "/lib/x86_64-linux-gnu/libvulkan_freedreno.so"
+      ]
+    },
+    "Vulkan-intel": {
+      "Library": "libvulkan_intel-guest.so",
+      "Depends": [
+        "xcb"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libvulkan_intel.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_intel.so",
+        "/lib/x86_64-linux-gnu/libvulkan_intel.so"
+      ]
+    },
+    "Vulkan-panfrost": {
+      "Library": "libvulkan_panfrost-guest.so",
+      "Depends": [
+        "xcb"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libvulkan_panfrost.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_panfrost.so",
+        "/lib/x86_64-linux-gnu/libvulkan_panfrost.so"
+      ]
+    },
+    "Vulkan-nvidia": {
+      "Library": "libvulkan_nvidia-guest.so",
+      "Depends": [
+        "xcb"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libGLX_nvidia.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libGLX_nvidia.so.0",
+        "/lib/x86_64-linux-gnu/libGLX_nvidia.so.0"
+      ],
+      "Comment": [
+        "Not currently wired up"
+      ]
+    },
+    "Vulkan-virtio": {
+      "Library": "libvulkan_virtio-guest.so",
+      "Depends": [
+        "xcb"
+      ],
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libvulkan_virtio.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_virtio.so",
+        "/lib/x86_64-linux-gnu/libvulkan_virtio.so"
+      ]
+    },
+    "xcb": {
+      "Library": "libxcb-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb.so.1",
+        "/usr/lib/x86_64-linux-gnu/libxcb.so.1.1.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb.so.1.1.0",
+        "/lib/x86_64-linux-gnu/libxcb.so",
+        "/lib/x86_64-linux-gnu/libxcb.so.1",
+        "/lib/x86_64-linux-gnu/libxcb.so.1.1.0"
+      ]
+    },
+    "xcb-dri2": {
+      "Library": "libxcb_dri2-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb-dri2.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb-dri2.so.0",
+        "/usr/lib/x86_64-linux-gnu/libxcb-dri2.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri2.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri2.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri2.so.0.0.0",
+        "/lib/x86_64-linux-gnu/libxcb-dri2.so",
+        "/lib/x86_64-linux-gnu/libxcb-dri2.so.0",
+        "/lib/x86_64-linux-gnu/libxcb-dri2.so.0.0.0"
+      ]
+    },
+    "xcb-dri3": {
+      "Library": "libxcb_dri3-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb-dri3.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb-dri3.so.0",
+        "/usr/lib/x86_64-linux-gnu/libxcb-dri3.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri3.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri3.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri3.so.0.0.0",
+        "/lib/x86_64-linux-gnu/libxcb-dri3.so",
+        "/lib/x86_64-linux-gnu/libxcb-dri3.so.0",
+        "/lib/x86_64-linux-gnu/libxcb-dri3.so.0.0.0"
+      ]
+    },
+    "xcb-xfixes": {
+      "Library": "libxcb_xfixes-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb-xfixes.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb-xfixes.so.0",
+        "/usr/lib/x86_64-linux-gnu/libxcb-xfixes.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-xfixes.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-xfixes.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-xfixes.so.0.0.0",
+        "/lib/x86_64-linux-gnu/libxcb-xfixes.so",
+        "/lib/x86_64-linux-gnu/libxcb-xfixes.so.0",
+        "/lib/x86_64-linux-gnu/libxcb-xfixes.so.0.0.0"
+      ]
+    },
+    "xcb-shm": {
+      "Library": "libxcb_shm-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb-shm.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb-shm.so.0",
+        "/usr/lib/x86_64-linux-gnu/libxcb-shm.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-shm.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-shm.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-shm.so.0.0.0",
+        "/lib/x86_64-linux-gnu/libxcb-shm.so",
+        "/lib/x86_64-linux-gnu/libxcb-shm.so.0",
+        "/lib/x86_64-linux-gnu/libxcb-shm.so.0.0.0"
+      ]
+    },
+    "xcb-sync": {
+      "Library": "libxcb_sync-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb-sync.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb-sync.so.1",
+        "/usr/lib/x86_64-linux-gnu/libxcb-sync.so.1.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-sync.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-sync.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-sync.so.1.0.0",
+        "/lib/x86_64-linux-gnu/libxcb-sync.so",
+        "/lib/x86_64-linux-gnu/libxcb-sync.so.1",
+        "/lib/x86_64-linux-gnu/libxcb-sync.so.1.0.0"
+      ]
+    },
+    "xcb-randr": {
+      "Library": "libxcb_randr-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb-randr.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb-randr.so.0",
+        "/usr/lib/x86_64-linux-gnu/libxcb-randr.so.0.1.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-randr.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-randr.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-randr.so.0.1.0",
+        "/lib/x86_64-linux-gnu/libxcb-randr.so",
+        "/lib/x86_64-linux-gnu/libxcb-randr.so.0",
+        "/lib/x86_64-linux-gnu/libxcb-randr.so.0.1.0"
+      ]
+    },
+    "xcb-present": {
+      "Library": "libxcb_present-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb-present.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb-present.so.0",
+        "/usr/lib/x86_64-linux-gnu/libxcb-present.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-present.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-present.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-present.so.0.0.0",
+        "/lib/x86_64-linux-gnu/libxcb-present.so",
+        "/lib/x86_64-linux-gnu/libxcb-present.so.0",
+        "/lib/x86_64-linux-gnu/libxcb-present.so.0.0.0"
+      ]
+    },
+    "xcb-glx": {
+      "Library": "libxcb_glx-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxcb-glx.so",
+        "/usr/lib/x86_64-linux-gnu/libxcb-glx.so.0",
+        "/usr/lib/x86_64-linux-gnu/libxcb-glx.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-glx.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-glx.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-glx.so.0.0.0",
+        "/lib/x86_64-linux-gnu/libxcb-glx.so",
+        "/lib/x86_64-linux-gnu/libxcb-glx.so.0",
+        "/lib/x86_64-linux-gnu/libxcb-glx.so.0.0.0"
+      ]
+    },
+    "xshmfence": {
+      "Library": "libshmfence-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libxshmfence.so",
+        "/usr/lib/x86_64-linux-gnu/libxshmfence.so.1",
+        "/usr/lib/x86_64-linux-gnu/libxshmfence.so.1.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxshmfence.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxshmfence.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libxshmfence.so.1.0.0",
+        "/lib/x86_64-linux-gnu/libxshmfence.so",
+        "/lib/x86_64-linux-gnu/libxshmfence.so.1",
+        "/lib/x86_64-linux-gnu/libxshmfence.so.1.0.0"
+      ]
+    },
+    "drm": {
+      "Library": "libdrm-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libdrm.so",
+        "/usr/lib/x86_64-linux-gnu/libdrm.so.2",
+        "/usr/lib/x86_64-linux-gnu/libdrm.so.2.4.0",
+        "/usr/local/lib/x86_64-linux-gnu/libdrm.so",
+        "/usr/local/lib/x86_64-linux-gnu/libdrm.so.2",
+        "/usr/local/lib/x86_64-linux-gnu/libdrm.so.2.4.0",
+        "/lib/x86_64-linux-gnu/libdrm.so",
+        "/lib/x86_64-linux-gnu/libdrm.so.2",
+        "/lib/x86_64-linux-gnu/libdrm.so.2.4.0"
+      ]
+    },
+    "asound": {
+      "Library": "libasound-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libasound.so",
+        "/usr/lib/x86_64-linux-gnu/libasound.so.2",
+        "/usr/lib/x86_64-linux-gnu/libasound.so.2.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libasound.so",
+        "/usr/local/lib/x86_64-linux-gnu/libasound.so.2",
+        "/usr/local/lib/x86_64-linux-gnu/libasound.so.2.0.0",
+        "/lib/x86_64-linux-gnu/libasound.so",
+        "/lib/x86_64-linux-gnu/libasound.so.2",
+        "/lib/x86_64-linux-gnu/libasound.so.2.0.0"
+      ]
+    },
+    "Xrender": {
+      "Library": "libXrender-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libXrender.so",
+        "/usr/lib/x86_64-linux-gnu/libXrender.so.1",
+        "/usr/lib/x86_64-linux-gnu/libXrender.so.1.3.0",
+        "/usr/local/lib/x86_64-linux-gnu/libXrender.so",
+        "/usr/local/lib/x86_64-linux-gnu/libXrender.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libXrender.so.1.3.0",
+        "/lib/x86_64-linux-gnu/libXrender.so",
+        "/lib/x86_64-linux-gnu/libXrender.so.1",
+        "/lib/x86_64-linux-gnu/libXrender.so.1.3.0"
+      ]
+    },
+    "Xext": {
+      "Library": "libXext-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libXext.so",
+        "/usr/lib/x86_64-linux-gnu/libXext.so.6",
+        "/usr/lib/x86_64-linux-gnu/libXext.so.6.4.0",
+        "/usr/local/lib/x86_64-linux-gnu/libXext.so",
+        "/usr/local/lib/x86_64-linux-gnu/libXext.so.6",
+        "/usr/local/lib/x86_64-linux-gnu/libXext.so.6.4.0",
+        "/lib/x86_64-linux-gnu/libXext.so",
+        "/lib/x86_64-linux-gnu/libXext.so.6",
+        "/lib/x86_64-linux-gnu/libXext.so.6.4.0"
+      ]
+    },
+    "Xfixes": {
+      "Library": "libXfixes-guest.so",
+      "Overlay": [
+        "/usr/lib/x86_64-linux-gnu/libXfixes.so",
+        "/usr/lib/x86_64-linux-gnu/libXfixes.so.3",
+        "/usr/lib/x86_64-linux-gnu/libXfixes.so.3.1.0",
+        "/usr/local/lib/x86_64-linux-gnu/libXfixes.so",
+        "/usr/local/lib/x86_64-linux-gnu/libXfixes.so.3",
+        "/usr/local/lib/x86_64-linux-gnu/libXfixes.so.3.1.0",
+        "/lib/x86_64-linux-gnu/libXfixes.so",
+        "/lib/x86_64-linux-gnu/libXfixes.so.3",
+        "/lib/x86_64-linux-gnu/libXfixes.so.3.1.0"
+      ]
+    },
+    "":{}
+  }
+}

Data/binfmts/CMakeLists.txt

@@ -0,0 +1,17 @@
+function(GenBinFmt Name)
+  # Get the filename only component
+  get_filename_component(FMT_NAME ${Name} NAME_WE)
+
+  # Configure it
+  configure_file(
+    ${Name}
+    ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME})
+
+  # Then install the configured binfmt
+  install(
+    FILES ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME}
+    DESTINATION ${CMAKE_INSTALL_PREFIX}/share/binfmts/)
+endfunction()
+
+GenBinFmt(FEX-x86.in)
+GenBinFmt(FEX-x86_64.in)

Data/binfmts/FEX-x86.in

@@ -0,0 +1,8 @@
+package fex
+interpreter @CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter
+magic \x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00
+offset 0
+mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff
+credentials yes
+fix_binary yes
+preserve yes

Data/binfmts/FEX-x86_64.in

@@ -0,0 +1,8 @@
+package fex
+interpreter @CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter
+magic \x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x3e\x00
+offset 0
+mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff
+credentials yes
+fix_binary yes
+preserve yes

Dockerfile

@@ -3,8 +3,9 @@ FROM ubuntu:20.04 as builder
 
 RUN DEBIAN_FRONTEND="noninteractive" apt-get update
 RUN DEBIAN_FRONTEND="noninteractive" apt install -y cmake \
-clang-10 llvm-10 nasm ninja-build libnuma-dev \
-libcap-dev libglfw3-dev libepoxy-dev
+clang-10 llvm-10 nasm ninja-build \
+libcap-dev libglfw3-dev libepoxy-dev python3-dev \
+python3 linux-headers-generic
 
 COPY . /opt/FEX
 
@@ -22,7 +23,7 @@ FROM ubuntu:20.04
 
 RUN DEBIAN_FRONTEND="noninteractive" apt-get update
 RUN DEBIAN_FRONTEND="noninteractive" apt install -y \
-libnuma-dev libcap-dev libglfw3-dev libepoxy-dev
+libcap-dev libglfw3-dev libepoxy-dev
 
 COPY --from=builder /opt/FEX/build/Bin/* /usr/bin/
 

External/FEXCore/CMakeLists.txt

@@ -4,8 +4,18 @@ project(${PROJECT_NAME}
   VERSION 0.01
   LANGUAGES CXX)
 
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+  set(_M_X86_64 1)
+  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
+endif()
+
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
+  set(_M_ARM_64 1)
+endif()
+
+set(ENABLE_JIT_X86_64 ${_M_X86_64} CACHE BOOL "Enable the x86_64 JIT")
+set(ENABLE_JIT_ARM64 ${_M_ARM_64} CACHE BOOL "Enable the ARM64 JIT")
 option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
-option(ENABLE_JITSYMBOLS "Enable visibility of JITSymbols in profiling tools" FALSE)
 
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
 cmake_policy(SET CMP0083 NEW) # Follow new PIE policy
@@ -17,48 +27,42 @@ set(CMAKE_INCLUDE_CURRENT_DIR ON)
 include(CheckCXXCompilerFlag)
 include(CheckIncludeFileCXX)
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
-  set(_M_X86_64 1)
-  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
-  message(STATUS "Enabling x86-64 JIT")
-  set(ENABLE_JIT 1)
-endif()
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
-  message(STATUS "Enabling AArch64 JIT")
-  set(_M_ARM_64 1)
-  set(ENABLE_JIT 1)
-  if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
+if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
     # Useful to have for freestanding libFEXCore
     add_subdirectory(External/vixl/)
     include_directories(External/vixl/src/)
-  endif()
 endif()
 
 set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 
-# Find our git hash
-find_package(Git)
-
 set(GIT_SHORT_HASH "Unknown")
 set(GIT_DESCRIBE_STRING "FEX-Unknown")
 
-if (GIT_FOUND)
-  execute_process(
-    COMMAND ${GIT_EXECUTABLE} rev-parse --short HEAD
-    WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
-    OUTPUT_VARIABLE GIT_SHORT_HASH
-    ERROR_QUIET
-    OUTPUT_STRIP_TRAILING_WHITESPACE
-  )
-  execute_process(
-    COMMAND ${GIT_EXECUTABLE} describe
-    WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
-    OUTPUT_VARIABLE GIT_DESCRIBE_STRING
-    ERROR_QUIET
-    OUTPUT_STRIP_TRAILING_WHITESPACE
-  )
+if (OVERRIDE_VERSION STREQUAL "detect")
+# Find our git hash
+  find_package(Git)
+
+  if (GIT_FOUND)
+    execute_process(
+      COMMAND ${GIT_EXECUTABLE} rev-parse --short HEAD
+      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+      OUTPUT_VARIABLE GIT_SHORT_HASH
+      ERROR_QUIET
+      OUTPUT_STRIP_TRAILING_WHITESPACE
+    )
+    execute_process(
+      COMMAND ${GIT_EXECUTABLE} describe
+      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+      OUTPUT_VARIABLE GIT_DESCRIBE_STRING
+      ERROR_QUIET
+      OUTPUT_STRIP_TRAILING_WHITESPACE
+    )
+  endif()
+else()
+  set(GIT_SHORT_HASH "${OVERRIDE_VERSION}")
+  set(GIT_DESCRIBE_STRING "FEX-${OVERRIDE_VERSION}")
 endif()
 
 configure_file(

External/FEXCore/Scripts/config_generator.py

@@ -0,0 +1,492 @@
+import datetime
+import json
+import sys
+
+def print_header():
+    header = '''#ifndef OPT_BASE
+#define OPT_BASE(type, group, enum, json, default)
+#endif
+#ifndef OPT_BOOL
+#define OPT_BOOL(group, enum, json, default) OPT_BASE(bool, group, enum, json, default)
+#endif
+#ifndef OPT_UINT8
+#define OPT_UINT8(group, enum, json, default) OPT_BASE(uint8_t, group, enum, json, default)
+#endif
+#ifndef OPT_INT32
+#define OPT_INT32(group, enum, json, default) OPT_BASE(int32_t, group, enum, json, default)
+#endif
+#ifndef OPT_UINT32
+#define OPT_UINT32(group, enum, json, default) OPT_BASE(uint32_t, group, enum, json, default)
+#endif
+#ifndef OPT_UINT64
+#define OPT_UINT64(group, enum, json, default) OPT_BASE(uint64_t, group, enum, json, default)
+#endif
+#ifndef OPT_STR
+#define OPT_STR(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#endif
+#ifndef OPT_STRARRAY
+#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#endif
+
+'''
+    output_file.write(header)
+
+def print_tail():
+    tail = '''#undef OPT_BASE
+#undef OPT_BOOL
+#undef OPT_UINT8
+#undef OPT_INT32
+#undef OPT_UINT32
+#undef OPT_UINT64
+#undef OPT_STR
+#undef OPT_STRARRAY
+'''
+    output_file.write(tail)
+
+def print_config(type, group_name, json_name, default_value):
+    output_file.write("OPT_{0} ({1}, {2}, {3}, {4})\n".format(type.upper(), group_name.upper(), json_name.upper(), json_name, default_value))
+
+def print_options(options):
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            print_config(
+                op_vals["Type"],
+                op_group,
+                op_key,
+                default)
+
+        output_file.write("\n")
+
+def print_unnamed_options(options):
+    output_file.write("// Unnamed configuration options\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            print_config(
+                op_vals["Type"],
+                op_group,
+                op_key.upper(), # KEY is the enum here, there is no json configuration for these
+                default)
+
+        output_file.write("\n")
+
+def print_man_option(short, long, desc, default):
+    if (short != None):
+        output_man.write(".It Fl {0} , ".format(short))
+    else:
+        output_man.write(".It ")
+
+    output_man.write("Fl Fl {0}=".format(long))
+
+    output_man.write("\n");
+
+    # Print description
+    for line in desc:
+        output_man.write(".Pp\n")
+        output_man.write("{0}\n".format(line))
+
+    output_man.write(".Pp\n")
+    output_man.write("\\fBdefault:\\fR {0}\n".format(default))
+    output_man.write(".Pp\n\n")
+
+def print_man_env_option(name, desc, default, no_json_key):
+    output_man.write("\\fBFEX_{0}\\fR\n".format(name.upper()))
+
+    # Print description
+    for line in desc:
+        output_man.write(".Pp\n")
+        output_man.write("{0}\n".format(line))
+
+    if (not no_json_key):
+        output_man.write(".Pp\n")
+        output_man.write("\\fBJSON key:\\fR '{0}'\n".format(name))
+        output_man.write(".Pp\n\n")
+
+    output_man.write(".Pp\n")
+    output_man.write("\\fBdefault:\\fR {0}\n".format(default))
+    output_man.write(".Pp\n\n")
+
+def print_man_options(options):
+    output_man.write(".Sh OPTIONS\n")
+    output_man.write(".Bl -tag -width -indent\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            short = None
+            long = op_key.lower()
+
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+
+            default = op_vals["Default"]
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = op_vals["TextDefault"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "'" + default + "'"
+            print_man_option(
+                short,
+                long,
+                op_vals["Desc"],
+                default
+            )
+
+    output_man.write(".El\n")
+
+def print_man_environment(options):
+    output_man.write(".Sh ENVIRONMENT\n")
+    output_man.write(".Bl -tag -width -indent\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = op_vals["TextDefault"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "'" + default + "'"
+            print_man_env_option(
+                op_key,
+                op_vals["Desc"],
+                default,
+                False
+            )
+
+    print_man_environment_tail()
+    output_man.write(".El\n")
+
+def print_man_environment_tail():
+
+    # Additional environment variables that live outside of the normal loop
+    print_man_env_option(
+    "FEX_APP_CONFIG_LOCATION",
+    [
+    "Allows the user to override where FEX looks for configuration files",
+    "By default FEX will look in {$HOME, $XDG_CONFIG_HOME}/.fex-emu/",
+    "This will override the full path",
+    ],
+    "''", True)
+
+    print_man_env_option(
+    "FEX_APP_CONFIG",
+    [
+    "Allows the user to override where FEX looks for only the application config file",
+    "By default FEX will look in {$HOME, $XDG_CONFIG_HOME}/.fex-emu/Config.json",
+    "This will override this file location",
+    "One must be careful with this option as it will override any applications that load with execve as well"
+    "If you need to support applications that execve then use FEX_APP_CONFIG_LOCATION instead"
+    ],
+    "''", True)
+
+    print_man_env_option(
+    "FEX_APP_DATA_LOCATION",
+    [
+    "Allows the user to override where FEX looks for data files",
+    "By default FEX will look in {$HOME, $XDG_DATA_HOME}/.fex-emu/",
+    "This will override the full path",
+    "This is the folder where FEX stores generated files like IR cache"
+    ],
+    "''", True)
+
+def print_man_header():
+    header ='''.Dd {0}
+.Dt FEX
+.Os Linux
+.Sh NAME
+.Nm FEXLoader
+.Nm FEXInterpreter
+.Nm FEXBash
+.Nd Fast x86-64 and x86 emulation.
+.Sh SYNOPSIS
+.Nm
+.Op options
+.Op Ar --
+.Ar Application
+<args> ...
+.Pp
+.Nm FEXInterpreter
+.Ar Application
+<args> ...
+.Pp
+.Nm FEXBash
+.Ar <args> ...
+.Sh DESCRIPTION
+FEX allows you to run x86 and x86-64 binaries on an AArch64 host, similar to qemu-user and box86.
+It has native support for a rootfs overlay, so you don't need to chroot, as well as some thunklibs so it can forward things like GL to the host.
+FEX presents a Linux 5.0 interface to the guest, and supports both AArch64 and x86-64 as hosts.
+FEX is very much work in progress, so expect things to change.
+'''
+    output_man.write(header.format(datetime.datetime.now().strftime("%d-%m-%Y")))
+
+def print_man_tail():
+    tail ='''.Sh FILES
+.Bl -tag -width "$prefix/share/fex-emu/GuestThunks" -compact
+.It Pa $XDG_HOME_DIR/.fex-emu
+Default FEX user configuration directory
+.It Pa $prefix/share/fex-emu/AppConfig
+System level application configuration files
+.It Pa $prefix/share/fex-emu/GuestThunks
+guest-side thunk data libraries
+.It Pa $prefix/lib/fex-emu/HostThunks
+host-side thunks for guest communication
+.El
+'''
+    output_man.write(tail)
+
+def print_config_option(type, group_name, json_name, default_value, short, choices, desc):
+    if (type == "bool"):
+        # Bool gets some special handling to add an inverted case
+        output_argloader.write("{0}Group".format(group_name))
+
+        options = ""
+        AddedArg = False
+        if (short != None):
+            AddedArg = True
+            options += "\"-{0}\"".format(short)
+
+        if (AddedArg):
+            options += ", "
+        options += "\"--{0}\"".format(json_name.lower())
+
+        output_argloader.write(".add_option({0})".format(options))
+
+        output_argloader.write("\n")
+
+        output_argloader.write("\t.action(\"store_true\")\n")
+
+        output_argloader.write("\t.dest(\"{0}\")\n".format(json_name));
+
+        # help
+        output_argloader.write("\t.help(\n")
+        desc_line_ender = ""
+        if (len(desc) > 1):
+            desc_line_ender = "\\n"
+
+        for line in desc:
+            output_argloader.write("\t\t\"{0}{1}\"\n".format(line, desc_line_ender))
+        output_argloader.write("\t)\n")
+
+        output_argloader.write("\t.set_default({0});\n\n".format(default_value));
+
+        output_argloader.write("{0}Group".format(group_name))
+        output_argloader.write(".add_option(\"--no-{0}\")\n".format(json_name.lower()))
+
+        # Inverted case sets the bool to false
+        output_argloader.write("\t.action(\"store_false\")\n")
+
+        output_argloader.write("\t.dest(\"{0}\");\n".format(json_name));
+    else:
+        output_argloader.write("{0}Group".format(group_name))
+        options = ""
+        AddedArg = False
+        if (short != None):
+            AddedArg = True
+            options += "\"-{0}\"".format(short)
+
+        if (AddedArg):
+            options += ", "
+        options += "\"--{0}\"".format(json_name.lower())
+
+        output_argloader.write(".add_option({0})".format(options))
+
+        output_argloader.write("\n")
+
+        output_argloader.write("\t.dest(\"{0}\")\n".format(json_name));
+
+        if (choices != None):
+            output_argloader.write("\t.choices({\n")
+            for choice in choices:
+                output_argloader.write("\t\t\"{0}\",\n".format(choice))
+            output_argloader.write("\t})\n")
+
+
+        # help
+        output_argloader.write("\t.help(\n")
+        desc_line_ender = ""
+        if (len(desc) > 1):
+            desc_line_ender = "\\n"
+
+        for line in desc:
+            output_argloader.write("\t\t\"{0}{1}\"\n".format(line, desc_line_ender))
+        output_argloader.write("\t)\n")
+
+        output_argloader.write("\t.set_default({0});\n".format(default_value));
+
+    output_argloader.write("\n");
+
+def print_argloader_options(options):
+    output_argloader.write("#ifdef BEFORE_PARSE\n")
+    output_argloader.write("#undef BEFORE_PARSE\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = "\"" + op_vals["TextDefault"] + "\""
+
+            short = None
+            choices = None
+
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+            if ("Choices" in op_vals):
+                choices = op_vals["Choices"]
+
+            print_config_option(
+                op_vals["Type"],
+                op_group,
+                op_key,
+                default,
+                short,
+                choices,
+                op_vals["Desc"])
+
+        output_argloader.write("\n")
+    output_argloader.write("#endif\n")
+
+def print_parse_argloader_options(options):
+    output_argloader.write("#ifdef AFTER_PARSE\n")
+    output_argloader.write("#undef AFTER_PARSE\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            output_argloader.write("if (Options.is_set_by_user(\"{0}\")) {{\n".format(op_key))
+
+            value_type = op_vals["Type"]
+            NeedsString = False
+            conversion_func = "std::to_string"
+            if ("ArgumentHandler" in op_vals):
+                NeedsString = True
+                conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
+            if (value_type == "str"):
+                NeedsString = True
+                conversion_func = ""
+
+            if (value_type == "strarray"):
+                # these need a bit more help
+                output_argloader.write("\tauto Array = Options.all(\"{0}\");\n".format(op_key))
+                output_argloader.write("\tfor (auto iter = Array.begin(); iter != Array.end(); ++iter) {\n")
+                output_argloader.write("\t\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, *iter);\n".format(op_key.upper()))
+                output_argloader.write("\t}\n")
+            else:
+                if (NeedsString):
+                    output_argloader.write("\tstd::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                else:
+                    output_argloader.write("\t{0} UserValue = Options.get(\"{1}\");\n".format(value_type, op_key))
+
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}(UserValue));\n".format(op_key.upper(), conversion_func))
+            output_argloader.write("}\n")
+
+    output_argloader.write("#endif\n")
+
+
+def print_parse_envloader_options(options):
+    output_argloader.write("#ifdef ENVLOADER\n")
+    output_argloader.write("#undef ENVLOADER\n")
+    output_argloader.write("if (false) {}\n")
+
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            if ("ArgumentHandler" in op_vals):
+                conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
+                output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
+                output_argloader.write("Value = {0}(Value);\n".format(conversion_func))
+                output_argloader.write("}\n")
+    output_argloader.write("#endif\n")
+
+def check_for_duplicate_options(options):
+    short_map = []
+    long_map = []
+
+    # Spin through all the items and see if we have a duplicate option
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            short = None
+            long = op_key.lower()
+            long_invert = None
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+            if (op_vals["Type"] == "bool"):
+                long_invert = "no-" + long
+
+            # Check for short key duplication
+            if (short != None):
+                if (short in short_map):
+                    raise Exception("Short config '{0}' for option '{1}' has duplicate entry!".format(short, op_key))
+                else:
+                    short_map.append(short)
+
+            # Check for long key duplication
+            if (long in long_map):
+                raise Exception("Long config '{0}' has duplicate entry!".format(long))
+            else:
+                long_map.append(long)
+
+            # Check for long key duplication
+            if (long_invert != None):
+                if (long_invert in long_map):
+                    raise Exception("Long config '{0}' has duplicate entry!".format(long_invert))
+                else:
+                    long_map.append(long_invert)
+
+if (len(sys.argv) < 5):
+    sys.exit()
+
+output_filename = sys.argv[2]
+output_man_page = sys.argv[3]
+output_argumentloader_filename = sys.argv[4]
+
+json_file = open(sys.argv[1], "r")
+json_text = json_file.read()
+json_file.close()
+
+json_object = json.loads(json_text)
+
+options = json_object["Options"]
+unnamed_options = json_object["UnnamedOptions"]
+
+check_for_duplicate_options(options)
+
+# Generate config include file
+output_file = open(output_filename, "w")
+print_header()
+print_options(options)
+print_unnamed_options(unnamed_options)
+print_tail()
+output_file.close()
+
+# Generate man file
+output_man = open(output_man_page, "w")
+print_man_header()
+print_man_options(options)
+print_man_environment(options)
+print_man_tail()
+
+output_man.close()
+
+# Generate argument loader code
+output_argloader = open(output_argumentloader_filename, "w")
+print_argloader_options(options);
+print_parse_argloader_options(options);
+
+# Generate environment loader code
+print_parse_envloader_options(options);
+
+output_argloader.close()

External/FEXCore/Scripts/json_ir_generator.py

@@ -7,7 +7,7 @@ def print_enums(ops, defines):
     output_file.write("enum IROps : uint8_t {\n")
 
     for op_key, op_vals in ops.items():
-        output_file.write("\t\tOP_%s,\n" % op_key.upper())
+        output_file.write("\tOP_%s,\n" % op_key.upper())
 
     output_file.write("};\n")
 
@@ -20,7 +20,10 @@ def print_ir_structs(ops, defines):
 
     # Print out defines here
     for op_val in defines:
-        output_file.write("\t%s;\n" % op_val)
+        if op_val:
+            output_file.write("\t%s;\n" % op_val)
+        else:
+            output_file.write("\n")
 
     output_file.write("// Default structs\n")
     output_file.write("struct __attribute__((packed)) IROp_Header {\n")
@@ -81,11 +84,21 @@ def print_ir_structs(ops, defines):
 
         output_file.write("\tstatic constexpr IROps OPCODE = OP_%s;\n" % op_key.upper())
 
+        if (SSAArgs > 0):
+            # Add helpers for accessing SSA arguments, given how frequently they're accessed
+            output_file.write("\n")
+            output_file.write("\t[[nodiscard]] OrderedNodeWrapper& Args(size_t Index) {\n")
+            output_file.write("\t\treturn Header.Args[Index];\n")
+            output_file.write("\t}\n")
+            output_file.write("\t[[nodiscard]] const OrderedNodeWrapper& Args(size_t Index) const {\n")
+            output_file.write("\t\treturn Header.Args[Index];\n")
+            output_file.write("\t}\n")
+
         output_file.write("};\n")
 
         # Add a static assert that the IR ops must be pod
-        output_file.write("static_assert(std::is_trivial<IROp_%s>::value);\n\n" % op_key)
-        output_file.write("static_assert(std::is_standard_layout<IROp_%s>::value);\n\n" % op_key)
+        output_file.write("static_assert(std::is_trivial_v<IROp_%s>);\n" % op_key)
+        output_file.write("static_assert(std::is_standard_layout_v<IROp_%s>);\n\n" % op_key)
 
     output_file.write("#undef IROP_STRUCTS\n")
     output_file.write("#endif\n\n")
@@ -106,12 +119,12 @@ def print_ir_sizes(ops, defines):
     output_file.write("// Make sure our array maps directly to the IROps enum\n")
     output_file.write("static_assert(IRSizes[IROps::OP_LAST] == -1ULL);\n\n")
 
-    output_file.write("[[maybe_unused]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }\n\n")
+    output_file.write("[[maybe_unused, nodiscard]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }\n\n")
 
-    output_file.write("std::string_view const& GetName(IROps Op);\n")
-    output_file.write("uint8_t GetArgs(IROps Op);\n")
-    output_file.write("FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
-    output_file.write("bool HasSideEffects(IROps Op);\n")
+    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] std::string_view const& GetName(IROps Op);\n")
+    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetArgs(IROps Op);\n")
+    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
+    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool HasSideEffects(IROps Op);\n")
 
     output_file.write("#undef IROP_SIZES\n")
     output_file.write("#endif\n\n")
@@ -270,14 +283,15 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\t\t\n")
     output_file.write("\t\toperator Wrapper<IROp_Header>() const { return Wrapper<IROp_Header> {reinterpret_cast<IROp_Header*>(first), Node}; }\n")
     output_file.write("\t\toperator OrderedNode *() { return Node; }\n")
-    output_file.write("\t\toperator OpNodeWrapper () { return Node->Header.Value; }\n")
+    output_file.write("\t\toperator const OrderedNode *() const { return Node; }\n")
+    output_file.write("\t\toperator OpNodeWrapper () const { return Node->Header.Value; }\n")
     output_file.write("\t};\n")
 
     output_file.write("\ttemplate <class T>\n")
     output_file.write("\tusing IRPair = Wrapper<T>;\n\n")
 
     output_file.write("\tIRPair<IROp_Header> AllocateRawOp(size_t HeaderSize) {\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<IROp_Header*>(Data.Allocate(HeaderSize));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<IROp_Header*>(DualListData.DataAllocate(HeaderSize));\n")
     output_file.write("\t\tmemset(Op, 0, HeaderSize);\n")
     output_file.write("\t\tOp->Op = IROps::OP_DUMMY;\n")
     output_file.write("\t\treturn IRPair<IROp_Header>{Op, CreateNode(Op)};\n")
@@ -286,7 +300,7 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\ttemplate<class T, IROps T2>\n")
     output_file.write("\tT *AllocateOrphanOp() {\n")
     output_file.write("\t\tsize_t Size = FEXCore::IR::GetSize(T2);\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<T*>(Data.Allocate(Size));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<T*>(DualListData.DataAllocate(Size));\n")
     output_file.write("\t\tmemset(Op, 0, Size);\n")
     output_file.write("\t\tOp->Header.Op = T2;\n")
     output_file.write("\t\treturn Op;\n")
@@ -295,25 +309,25 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\ttemplate<class T, IROps T2>\n")
     output_file.write("\tIRPair<T> AllocateOp() {\n")
     output_file.write("\t\tsize_t Size = FEXCore::IR::GetSize(T2);\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<T*>(Data.Allocate(Size));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<T*>(DualListData.DataAllocate(Size));\n")
     output_file.write("\t\tmemset(Op, 0, Size);\n")
     output_file.write("\t\tOp->Header.Op = T2;\n")
     output_file.write("\t\treturn IRPair<T>{Op, CreateNode(&Op->Header)};\n")
     output_file.write("\t}\n\n")
 
-    output_file.write("\tuint8_t GetOpSize(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
+    output_file.write("\tuint8_t GetOpSize(const OrderedNode *Op) const {\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
     output_file.write("\t\treturn HeaderOp->Size;\n")
     output_file.write("\t}\n\n")
 
-    output_file.write("\tuint8_t GetOpElements(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
-    output_file.write("\t\tLogMan::Throw::A(HeaderOp->HasDest, \"Op %s has no dest\\n\", GetName(HeaderOp->Op));\n")
+    output_file.write("\tuint8_t GetOpElements(const OrderedNode *Op) const {\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
+    output_file.write("\t\tLOGMAN_THROW_A_FMT(HeaderOp->HasDest, \"Op {} has no dest\\n\", GetName(HeaderOp->Op));\n")
     output_file.write("\t\treturn HeaderOp->Size / HeaderOp->ElementSize;\n")
     output_file.write("\t}\n\n")
 
-    output_file.write("\tbool OpHasDest(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
+    output_file.write("\tbool OpHasDest(const OrderedNode *Op) const {\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
     output_file.write("\t\treturn HeaderOp->HasDest;\n")
     output_file.write("\t}\n\n")
 
@@ -387,11 +401,14 @@ def print_ir_allocator_helpers(ops, defines):
             output_file.write(") {\n")
 
             output_file.write("\t\tauto Op = AllocateOp<IROp_%s, IROps::OP_%s>();\n" % (op_key, op_key.upper()))
-            output_file.write("\t\tOp.first->Header.NumArgs = %d;\n" % (SSAArgs))
+
+            if (SSAArgs != 0):
+                output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n")
+                for i in range(0, SSAArgs):
+                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListDataBegin);\n" % (i, i))
 
             if (SSAArgs != 0):
                 for i in range(0, SSAArgs):
-                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListData.Begin());\n" % (i, i))
                     output_file.write("\t\tssa%d->AddUse();\n" % (i))
 
             if (HasArgs):
@@ -399,11 +416,6 @@ def print_ir_allocator_helpers(ops, defines):
                     data_name = op_vals["Args"][i]
                     output_file.write("\t\tOp.first->%s = %s;\n" % (data_name, data_name))
 
-            if (HasFixedDestSize):
-                output_file.write("\t\tOp.first->Header.Size = %d;\n" % FixedDestSize)
-            if (HasDestSize):
-                output_file.write("\t\tOp.first->Header.Size = %s;\n" % DestSize)
-
             if (HasDest):
                 # We can only infer a size if we have arguments
                 if not (HasFixedDestSize or HasDestSize):
@@ -412,10 +424,18 @@ def print_ir_allocator_helpers(ops, defines):
                     if (SSAArgs != 0):
                         for i in range(0, SSAArgs):
                             output_file.write("\t\tuint8_t Size%d = GetOpSize(ssa%s);\n" % (i, i))
+                        for i in range(0, SSAArgs):
                             output_file.write("\t\tInferSize = std::max(InferSize, Size%d);\n" % (i))
 
                     output_file.write("\t\tOp.first->Header.Size = InferSize;\n")
 
+            output_file.write("\t\tOp.first->Header.NumArgs = %d;\n" % (SSAArgs))
+
+            if (HasFixedDestSize):
+                output_file.write("\t\tOp.first->Header.Size = %d;\n" % FixedDestSize)
+            if (HasDestSize):
+                output_file.write("\t\tOp.first->Header.Size = %s;\n" % DestSize)
+
             output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / (%s);\n" % NumElements)
 
             if (HasDest):
@@ -499,7 +519,7 @@ def print_ir_parser_allocator_helpers(ops, defines):
 
             if (SSAArgs != 0):
                 for i in range(0, SSAArgs):
-                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListData.Begin());\n" % (i, i))
+                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(DualListData.ListBegin());\n" % (i, i))
                     output_file.write("\t\tssa%d->AddUse();\n" % (i))
 
             if (HasArgs):

External/FEXCore/Source/CMakeLists.txt

@@ -1,54 +1,15 @@
-if (ENABLE_CLANG_FORMAT)
-  find_program(CLANG_TIDY_EXE "clang-tidy")
-  set(CLANG_TIDY_FLAGS
-    "-checks=*"
-    "-fuchsia*"
-    "-bugprone-macro-parentheses"
-    "-clang-analyzer-core.*"
-    "-cppcoreguidelines-pro-type-*"
-    "-cppcoreguidelines-pro-bounds-array-to-pointer-decay"
-    "-cppcoreguidelines-pro-bounds-pointer-arithmetic"
-    "-cppcoreguidelines-avoid-c-arrays"
-    "-cppcoreguidelines-avoid-magic-numbers"
-    "-cppcoreguidelines-pro-bounds-constant-array-index"
-    "-cppcoreguidelines-no-malloc"
-    "-cppcoreguidelines-special-member-functions"
-    "-cppcoreguidelines-owning-memory"
-    "-cppcoreguidelines-macro-usage"
-    "-cppcoreguidelines-avoid-goto"
-    "-google-readability-function-size"
-    "-google-readability-namespace-comments"
-    "-google-readability-braces-around-statements"
-    "-google-build-using-namespace"
-    "-hicpp-*"
-    "-llvm-namespace-comment"
-    "-llvm-include-order" # Messes up with case sensitivity
-    "-misc-unused-parameters"
-    "-modernize-loop-convert"
-    "-modernize-use-auto"
-    "-modernize-avoid-c-arrays"
-    "-modernize-use-nodiscard"
-    "readability-*"
-    "-readability-function-size"
-    "-readability-implicit-bool-conversion"
-    "-readability-braces-around-statements"
-    "-readability-else-after-return"
-    "-readability-magic-numbers"
-    "-readability-named-parameter"
-    "-readability-uppercase-literal-suffix"
-    "-cert-err34-c"
-    "-cert-err58-cpp"
-    "-bugprone-exception-escape"
-    )
-  string(REPLACE ";" "," CLANG_TIDY_FLAGS "${CLANG_TIDY_FLAGS}")
+set (MAN_DIR ${CMAKE_INSTALL_PREFIX}/share/man CACHE PATH "MAN_DIR")
 
-  set(CMAKE_CXX_CLANG_TIDY ${CLANG_TIDY_EXE} "${CLANG_TIDY_FLAGS}")
-endif()
+set (FEXCORE_BASE_SRCS
+  Common/Paths.cpp
+  Interface/Config/Config.cpp
+  Utils/FileLoading.cpp
+  Utils/ForcedAssert.cpp
+  Utils/LogManager.cpp
+  )
 
 set (SRCS
-  Common/Paths.cpp
   Common/JitSymbols.cpp
-  Common/NetStream.cpp
   Common/SoftFloat-3e/extF80_add.c
   Common/SoftFloat-3e/extF80_div.c
   Common/SoftFloat-3e/extF80_sub.c
@@ -116,7 +77,6 @@ set (SRCS
   Common/SoftFloat-3e/f32_to_extF80.c
   Common/SoftFloat-3e/s_normSubnormalF32Sig.c
   Common/SoftFloat-3e/s_f32UIToCommonNaN.c
-  Interface/Config/Config.cpp
   Interface/Context/Context.cpp
   Interface/Core/LookupCache.cpp
   Interface/Core/BlockSamplingData.cpp
@@ -126,12 +86,21 @@ set (SRCS
   Interface/Core/Frontend.cpp
   Interface/Core/GdbServer.cpp
   Interface/Core/HostFeatures.cpp
+  Interface/Core/OpcodeDispatcher/Crypto.cpp
+  Interface/Core/OpcodeDispatcher/Flags.cpp
+  Interface/Core/OpcodeDispatcher/Vector.cpp
+  Interface/Core/OpcodeDispatcher/X87.cpp
   Interface/Core/OpcodeDispatcher.cpp
+  Interface/Core/SignalDelegator.cpp
   Interface/Core/X86Tables.cpp
   Interface/Core/X86DebugInfo.cpp
   Interface/Core/X86HelperGen.cpp
-  Interface/Core/Interpreter/InterpreterCore.cpp
-  Interface/Core/Interpreter/InterpreterOps.cpp
+  Interface/Core/ArchHelpers/Arm64_stubs.cpp
+  Interface/Core/ArchHelpers/Arm64Emitter.cpp
+  Interface/Core/Dispatcher/Dispatcher.cpp
+  Interface/Core/Dispatcher/X86Dispatcher.cpp
+  Interface/Core/Dispatcher/Arm64Dispatcher.cpp
+  Interface/Core/Interpreter/InterpreterFallbacks.cpp
   Interface/Core/X86Tables/BaseTables.cpp
   Interface/Core/X86Tables/DDDTables.cpp
   Interface/Core/X86Tables/EVEXTables.cpp
@@ -145,6 +114,7 @@ set (SRCS
   Interface/Core/X86Tables/X87Tables.cpp
   Interface/Core/X86Tables/XOPTables.cpp
   Interface/HLE/Thunks/Thunks.cpp
+  Interface/IR/AOTIR.cpp
   Interface/IR/IRDumper.cpp
   Interface/IR/IRParser.cpp
   Interface/IR/IREmitter.cpp
@@ -154,6 +124,8 @@ set (SRCS
   Interface/IR/Passes/DeadContextStoreElimination.cpp
   Interface/IR/Passes/IRCompaction.cpp
   Interface/IR/Passes/IRValidation.cpp
+  Interface/IR/Passes/RAValidation.cpp
+  Interface/IR/Passes/LongDivideRemovalPass.cpp
   Interface/IR/Passes/ValueDominanceValidation.cpp
   Interface/IR/Passes/PhiValidation.cpp
   Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
@@ -161,63 +133,87 @@ set (SRCS
   Interface/IR/Passes/StaticRegisterAllocationPass.cpp
   Interface/IR/Passes/RegisterAllocationPass.cpp
   Interface/IR/Passes/SyscallOptimization.cpp
-  Utils/ELFLoader.cpp
-  Utils/ELFSymbolDatabase.cpp
-  Utils/LogManager.cpp
+  Utils/Allocator.cpp
+  Utils/Allocator/64BitAllocator.cpp
+  Utils/NetStream.cpp
+  Utils/Telemetry.cpp
+  Utils/Threads.cpp
   )
 
-if (_M_X86_64)
-  list(APPEND SRCS Interface/Core/Interpreter/x86_64Dispatcher.cpp)
+if (ENABLE_INTERPRETER)
+  list(APPEND SRCS
+    Interface/Core/Interpreter/InterpreterCore.cpp
+    Interface/Core/Interpreter/InterpreterOps.cpp
+    Interface/Core/Interpreter/ALUOps.cpp
+    Interface/Core/Interpreter/AtomicOps.cpp
+    Interface/Core/Interpreter/BranchOps.cpp
+    Interface/Core/Interpreter/ConversionOps.cpp
+    Interface/Core/Interpreter/EncryptionOps.cpp
+    Interface/Core/Interpreter/F80Ops.cpp
+    Interface/Core/Interpreter/FlagOps.cpp
+    Interface/Core/Interpreter/MemoryOps.cpp
+    Interface/Core/Interpreter/MiscOps.cpp
+    Interface/Core/Interpreter/MoveOps.cpp
+    Interface/Core/Interpreter/VectorOps.cpp)
 endif()
+
 if(_M_ARM_64)
   list(APPEND SRCS
-    Interface/Core/ArchHelpers/Arm64.cpp
-    Interface/Core/Interpreter/Arm64Dispatcher.cpp)
+    Interface/Core/ArchHelpers/Arm64.cpp)
 endif()
 
-set (JIT_LIBS )
-if (ENABLE_JIT)
-  if (_M_X86_64)
-    add_definitions(-D_M_X86_64=1)
-    if (NOT FORCE_AARCH64)
-      list(APPEND SRCS
-        Interface/Core/JIT/x86_64/JIT.cpp
-        Interface/Core/JIT/x86_64/ALUOps.cpp
-        Interface/Core/JIT/x86_64/AtomicOps.cpp
-        Interface/Core/JIT/x86_64/BranchOps.cpp
-        Interface/Core/JIT/x86_64/ConversionOps.cpp
-        Interface/Core/JIT/x86_64/EncryptionOps.cpp
-        Interface/Core/JIT/x86_64/FlagOps.cpp
-        Interface/Core/JIT/x86_64/MemoryOps.cpp
-        Interface/Core/JIT/x86_64/MiscOps.cpp
-        Interface/Core/JIT/x86_64/MoveOps.cpp
-        Interface/Core/JIT/x86_64/VectorOps.cpp)
-    endif()
-  endif()
-  if(_M_ARM_64)
-    add_definitions(-D_M_ARM_64=1)
-    add_definitions(-DVIXL_INCLUDE_TARGET_AARCH64=1)
-    add_definitions(-DVIXL_CODE_BUFFER_MMAP=1)
-    list(APPEND SRCS
-      Interface/Core/JIT/Arm64/JIT.cpp
-      Interface/Core/JIT/Arm64/ALUOps.cpp
-      Interface/Core/JIT/Arm64/AtomicOps.cpp
-      Interface/Core/JIT/Arm64/BranchOps.cpp
-      Interface/Core/JIT/Arm64/ConversionOps.cpp
-      Interface/Core/JIT/Arm64/EncryptionOps.cpp
-      Interface/Core/JIT/Arm64/FlagOps.cpp
-      Interface/Core/JIT/Arm64/MemoryOps.cpp
-      Interface/Core/JIT/Arm64/MiscOps.cpp
-      Interface/Core/JIT/Arm64/MoveOps.cpp
-      Interface/Core/JIT/Arm64/VectorOps.cpp)
-    list(APPEND JIT_LIBS vixl)
-  endif()
+set(DEFINES -DTHREAD_LOCAL=_Thread_local)
+
+if (_M_X86_64)
+  list(APPEND DEFINES -D_M_X86_64=1)
 endif()
 
-if (ENABLE_JITSYMBOLS)
-  add_definitions(-DENABLE_JITSYMBOLS=1)
+if (_M_ARM_64)
+  list(APPEND DEFINES -D_M_ARM_64=1)
 endif()
 
+if (ENABLE_JIT_X86_64)
+  list(APPEND SRCS
+    Interface/Core/JIT/x86_64/JIT.cpp
+    Interface/Core/JIT/x86_64/ALUOps.cpp
+    Interface/Core/JIT/x86_64/AtomicOps.cpp
+    Interface/Core/JIT/x86_64/BranchOps.cpp
+    Interface/Core/JIT/x86_64/ConversionOps.cpp
+    Interface/Core/JIT/x86_64/EncryptionOps.cpp
+    Interface/Core/JIT/x86_64/FlagOps.cpp
+    Interface/Core/JIT/x86_64/MemoryOps.cpp
+    Interface/Core/JIT/x86_64/MiscOps.cpp
+    Interface/Core/JIT/x86_64/MoveOps.cpp
+    Interface/Core/JIT/x86_64/VectorOps.cpp)
+  list(APPEND DEFINES -DJIT_X86_64)
+endif()
+
+if (ENABLE_JIT_ARM64)
+  list(APPEND DEFINES -DJIT_ARM64)
+  list(APPEND SRCS
+    Interface/Core/JIT/Arm64/JIT.cpp
+    Interface/Core/JIT/Arm64/ALUOps.cpp
+    Interface/Core/JIT/Arm64/AtomicOps.cpp
+    Interface/Core/JIT/Arm64/BranchOps.cpp
+    Interface/Core/JIT/Arm64/ConversionOps.cpp
+    Interface/Core/JIT/Arm64/EncryptionOps.cpp
+    Interface/Core/JIT/Arm64/FlagOps.cpp
+    Interface/Core/JIT/Arm64/MemoryOps.cpp
+    Interface/Core/JIT/Arm64/MiscOps.cpp
+    Interface/Core/JIT/Arm64/MoveOps.cpp
+    Interface/Core/JIT/Arm64/VectorOps.cpp)
+endif()
+
+set (LIBS vixl dl xxhash tiny-json)
+if (ENABLE_JEMALLOC)
+  list (APPEND LIBS FEX_jemalloc)
+endif()
+
+# Generate config
+configure_file(
+  ${CMAKE_CURRENT_SOURCE_DIR}/Interface/Config/Config.json.in
+  ${CMAKE_BINARY_DIR}/generated/Config/Config.json)
+
 # Generate IR include file
 set(OUTPUT_IR_FOLDER "${CMAKE_BINARY_DIR}/include/FEXCore/IR")
 set(OUTPUT_NAME "${OUTPUT_IR_FOLDER}/IRDefines.inc")
@@ -251,22 +247,68 @@ add_custom_command(
 set_source_files_properties(${OUTPUT_IR_NAME} PROPERTIES
   GENERATED TRUE)
 
-# Create teh target
+# Create the target
 add_custom_target(IR_INC
   DEPENDS "${OUTPUT_NAME}"
   DEPENDS "${OUTPUT_IR_DOC}")
 
+# Generate the configuration include file
+set(OUTPUT_CONFIG_FOLDER "${CMAKE_BINARY_DIR}/include/FEXCore/Config")
+set(OUTPUT_CONFIG_NAME "${OUTPUT_CONFIG_FOLDER}/ConfigValues.inl")
+set(OUTPUT_CONFIG_OPTION_NAME "${OUTPUT_CONFIG_FOLDER}/ConfigOptions.inl")
+set(INPUT_CONFIG_NAME "${CMAKE_BINARY_DIR}/generated/Config/Config.json")
+set(OUTPUT_MAN_NAME "${CMAKE_BINARY_DIR}/generated/FEX.1")
+set(OUTPUT_MAN_NAME_COMPRESS "${CMAKE_BINARY_DIR}/generated/FEX.1.gz")
+
+add_custom_target(CREATE_CONFIG_FOLDER ALL
+  COMMAND ${CMAKE_COMMAND} -E make_directory "${OUTPUT_CONFIG_FOLDER}")
+
+add_custom_command(
+  OUTPUT "${OUTPUT_CONFIG_NAME}"
+  OUTPUT "${OUTPUT_CONFIG_OPTION_NAME}"
+  OUTPUT "${OUTPUT_MAN_NAME}"
+  DEPENDS "${INPUT_CONFIG_NAME}"
+  DEPENDS CREATE_CONFIG_FOLDER
+  DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/config_generator.py"
+  COMMAND "python3" "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/config_generator.py" "${INPUT_CONFIG_NAME}" "${OUTPUT_CONFIG_NAME}" "${OUTPUT_MAN_NAME}"
+  "${OUTPUT_CONFIG_OPTION_NAME}"
+  )
+
+add_custom_command(
+  OUTPUT "${OUTPUT_MAN_NAME_COMPRESS}"
+  DEPENDS "${OUTPUT_MAN_NAME}"
+  COMMAND "gzip" "-kf9n" "${OUTPUT_MAN_NAME}"
+  )
+
+set_source_files_properties(${OUTPUT_CONFIG_NAME} PROPERTIES
+  GENERATED TRUE)
+set_source_files_properties(${OUTPUT_CONFIG_OPTION_NAME} PROPERTIES
+  GENERATED TRUE)
+
+set_source_files_properties(${OUTPUT_MAN_NAME} PROPERTIES
+  GENERATED TRUE)
+set_source_files_properties(${OUTPUT_MAN_NAME_COMPRESS} PROPERTIES
+  GENERATED TRUE)
+
+# Create the target
+add_custom_target(CONFIG_INC
+  DEPENDS "${OUTPUT_CONFIG_NAME}"
+  DEPENDS "${OUTPUT_CONFIG_OPTION_NAME}"
+  DEPENDS "${OUTPUT_MAN_NAME}"
+  DEPENDS "${OUTPUT_MAN_NAME_COMPRESS}")
+
+# Install the compressed man page
+install(FILES ${OUTPUT_MAN_NAME_COMPRESS} DESTINATION ${MAN_DIR}/man1)
+
 # Add in diagnostic colours if the option is available.
 # Ninja code generator will kill colours if this isn't here
 check_cxx_compiler_flag(-fdiagnostics-color=always GCC_COLOR)
 check_cxx_compiler_flag(-fcolor-diagnostics CLANG_COLOR)
 
-function(AddLibrary Name Type)
-  add_library(${Name} ${Type} ${SRCS})
-  add_dependencies(${Name} IR_INC)
-  target_link_libraries(${Name} pthread rt ${JIT_LIBS} ${LINUX_LIBS} dl)
-  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
-
+function(AddDefaultOptionsToTarget Name)
+  set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES VISIBILITY_INLINES_HIDDEN TRUE)
   target_include_directories(${Name} PUBLIC "${CMAKE_CURRENT_BINARY_DIR}")
 
   target_include_directories(${Name} PRIVATE IncludePrivate/)
@@ -275,9 +317,19 @@ function(AddLibrary Name Type)
   target_include_directories(${Name} PUBLIC "${PROJECT_SOURCE_DIR}/include/")
   target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")
 
+  target_compile_definitions(${Name} PRIVATE ${DEFINES})
+  add_dependencies(${Name} CONFIG_INC)
+
   target_compile_options(${Name}
     PRIVATE
-    -Wno-trigraphs -Wall)
+    -Wall
+    -Werror=cast-qual
+    -Werror=ignored-qualifiers
+    -Werror=implicit-fallthrough
+
+    -Wno-trigraphs
+    -ffunction-sections
+  )
 
   if (GCC_COLOR)
     target_compile_options(${Name}
@@ -289,8 +341,41 @@ function(AddLibrary Name Type)
       PRIVATE
       "-fcolor-diagnostics")
   endif()
+
+  if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
+    target_link_options(${Name}
+      PRIVATE
+      "LINKER:--gc-sections"
+      "LINKER:--strip-all"
+      "LINKER:--as-needed"
+    )
+  endif()
 endfunction()
 
+# Build FEXCore_Config static library
+add_library(FEXCore_Base STATIC ${FEXCORE_BASE_SRCS})
+target_link_libraries(FEXCore_Base fmt::fmt tiny-json)
+AddDefaultOptionsToTarget(FEXCore_Base)
+
+function(AddObject Name Type)
+  add_library(${Name} ${Type} ${SRCS})
+  add_dependencies(${Name} IR_INC)
+
+  target_link_libraries(${Name} FEXCore_Base ${LIBS})
+  AddDefaultOptionsToTarget(${Name})
+
+  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+endfunction()
+
+function(AddLibrary Name Type)
+  add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
+  target_link_libraries(${Name} FEXCore_Base ${LIBS})
+  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+
+  AddDefaultOptionsToTarget(${Name})
+endfunction()
+
+AddObject(${PROJECT_NAME}_object OBJECT)
 AddLibrary(${PROJECT_NAME} STATIC)
 AddLibrary(${PROJECT_NAME}_shared SHARED)
 

External/FEXCore/Source/Common/BitSet.h

@@ -1,12 +1,16 @@
 #pragma once
-#include "Common/MathUtils.h"
+
+#include <FEXCore/Utils/Allocator.h>
+#include <FEXCore/Utils/MathUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 
+#include <cstdint>
+#include <cstdlib>
 #include <cstring>
-#include <stdint.h>
-#include <stdlib.h>
 #include <type_traits>
 
+namespace FEXCore {
+
 template<typename T>
 struct BitSet final {
   using ElementType = T;
@@ -16,16 +20,16 @@ struct BitSet final {
   ElementType *Memory;
   void Allocate(size_t Elements) {
     size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LogMan::Throw::A((AllocateSize * MinimumSize) >= Elements, "Fail");
-    Memory = static_cast<ElementType*>(malloc(AllocateSize));
+    LOGMAN_THROW_A_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
+    Memory = static_cast<ElementType*>(FEXCore::Allocator::malloc(AllocateSize));
   }
   void Realloc(size_t Elements) {
     size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LogMan::Throw::A((AllocateSize * MinimumSize) >= Elements, "Fail");
-    Memory = static_cast<ElementType*>(realloc(Memory, AllocateSize));
+    LOGMAN_THROW_A_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
+    Memory = static_cast<ElementType*>(FEXCore::Allocator::realloc(Memory, AllocateSize));
   }
   void Free() {
-    free(Memory);
+    FEXCore::Allocator::free(Memory);
     Memory = nullptr;
   }
   bool Get(T Element) {
@@ -60,8 +64,8 @@ struct BitSetView final {
   ElementType *Memory;
 
   void GetView(BitSet<T> &Set, uint64_t ElementOffset) {
-    LogMan::Throw::A((ElementOffset % MinimumSize) == 0,
-        "Bitset view offset needs to be aligned to size of backing element");
+    LOGMAN_THROW_A_FMT((ElementOffset % MinimumSize) == 0,
+                       "Bitset view offset needs to be aligned to size of backing element");
     Memory = &Set.Memory[ElementOffset / MinimumSizeBits];
   }
 
@@ -86,11 +90,12 @@ struct BitSetView final {
   bool operator[](T Element) {
     return Get(Element);
   }
-
 };
 
 static_assert(sizeof(BitSet<uint32_t>) == sizeof(uintptr_t), "Needs to just be a pointer");
-static_assert(std::is_trivially_copyable<BitSet<uint32_t>>::value, "Needs to trivially copyable");
+static_assert(std::is_trivially_copyable_v<BitSet<uint32_t>>, "Needs to trivially copyable");
 
 static_assert(sizeof(BitSetView<uint32_t>) == sizeof(uintptr_t), "Needs to just be a pointer");
-static_assert(std::is_trivially_copyable<BitSetView<uint32_t>>::value, "Needs to trivially copyable");
+static_assert(std::is_trivially_copyable_v<BitSetView<uint32_t>>, "Needs to trivially copyable");
+
+} // namespace FEXCore

External/FEXCore/Source/Common/JitSymbols.cpp

@@ -1,45 +1,53 @@
 #include "Common/JitSymbols.h"
 
 #include <string>
-#include <sstream>
 #include <unistd.h>
 
-namespace FEXCore {
-  JITSymbols::JITSymbols() {
-    std::stringstream PerfMap;
-    PerfMap << "/tmp/perf-" << getpid() << ".map";
+#include <fmt/format.h>
 
-    fp = fopen(PerfMap.str().c_str(), "wb");
+namespace FEXCore {
+  JITSymbols::JITSymbols() : fp{nullptr, std::fclose} {
+    const auto PerfMap = fmt::format("/tmp/perf-{}.map", getpid());
+
+    fp.reset(fopen(PerfMap.c_str(), "wb"));
     if (fp) {
       // Disable buffering on this file
-      setvbuf(fp, nullptr, _IONBF, 0);
+      setvbuf(fp.get(), nullptr, _IONBF, 0);
     }
   }
 
-  JITSymbols::~JITSymbols() {
-    if (fp) {
-      fclose(fp);
-    }
-  }
+  JITSymbols::~JITSymbols() = default;
 
-  void JITSymbols::Register(void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
+  void JITSymbols::Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
     if (!fp) return;
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    std::stringstream String;
-    String << std::hex << HostAddr << " " << CodeSize << " " << "JIT_0x" << GuestAddr << "_" << HostAddr << std::endl;
-    fwrite(String.str().c_str(), 1, String.str().size(), fp);
+    fmt::print(fp.get(), "{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
   }
 
-  void JITSymbols::Register(void *HostAddr, uint32_t CodeSize, std::string const &Name) {
+  void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
     if (!fp) return;
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    std::stringstream String;
-    String << std::hex << HostAddr << " " << CodeSize << " " << Name << "_" << HostAddr << std::endl;
-    fwrite(String.str().c_str(), 1, String.str().size(), fp);
+    fmt::print(fp.get(), "{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
   }
-}
 
+  void JITSymbols::RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
+    if (!fp) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    fmt::print(fp.get(), "{} {:x} {}\n", HostAddr, CodeSize, Name);
+  }
+
+  void JITSymbols::RegisterJITSpace(const void *HostAddr, uint32_t CodeSize) {
+    if (!fp) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    fmt::print(fp.get(), "{} {:x} FEXJIT\n", HostAddr, CodeSize);
+  }
+
+} // namespace FEXCore

External/FEXCore/Source/Common/JitSymbols.h

@@ -1,17 +1,24 @@
 #pragma once
+
 #include <cstdint>
 #include <cstdio>
-#include <string>
+#include <memory>
+#include <string_view>
 
 namespace FEXCore {
 class JITSymbols final {
 public:
   JITSymbols();
   ~JITSymbols();
-  void Register(void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
-  void Register(void *HostAddr, uint32_t CodeSize, std::string const &Name);
+
+  void Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
+  void Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
+  void RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
+  void RegisterJITSpace(const void *HostAddr, uint32_t CodeSize);
 
 private:
-  FILE* fp{};
+  using FILEPtr = std::unique_ptr<FILE, decltype(&std::fclose)>;
+
+  FILEPtr fp;
 };
 }

External/FEXCore/Source/Common/MathUtils.h

@@ -1,13 +0,0 @@
-#pragma once
-
-#include <stdint.h>
-
-static inline uint64_t AlignUp(uint64_t value, uint64_t size) {
-  return value + (size - value % size) % size;
-};
-
-static inline uint64_t AlignDown(uint64_t value, uint64_t size) {
-  return value - value % size;
-};
-
-

External/FEXCore/Source/Common/NetStream.h

@@ -1,41 +0,0 @@
-#pragma once
-
-#include <array>
-#include <iostream>
-#include <string.h>
-
-class NetStream : public std::iostream {
-public:
-    NetStream(int socketfd) : std::iostream(new NetBuf(socketfd)) {}
-    virtual ~NetStream();
-
-private:
-    class NetBuf : public std::streambuf {
-
-    public:
-        NetBuf(int socketfd) {
-            socket = socketfd;
-            reset_output_buffer();
-        }
-        virtual ~NetBuf();
-
-    protected:
-        virtual std::streamsize xsputn(const char* buffer, std::streamsize size);
-
-        virtual std::streambuf::int_type underflow();
-        virtual std::streambuf::int_type overflow(std::streambuf::int_type ch);
-        virtual int sync();
-
-    private:
-        void reset_output_buffer() {
-            // we always leave room for one extra char
-            setp(std::begin(output_buffer), std::end(output_buffer) -1);
-        }
-
-        int flushBuffer(const char *buffer, size_t size);
-
-        int socket;
-        std::array<char, 1400> output_buffer;
-        std::array<char, 1500> input_buffer; // enough for a typical packet
-    };
-};

External/FEXCore/Source/Common/Paths.cpp

@@ -3,13 +3,48 @@
 
 #include <cstdlib>
 #include <filesystem>
-#include <sys/stat.h>
+#include <memory>
+#include <pwd.h>
+#include <system_error>
+#include <unistd.h>
 
 namespace FEXCore::Paths {
-  std::string CachePath;
-  std::string EntryCache;
+  std::unique_ptr<std::string> CachePath;
+  std::unique_ptr<std::string> EntryCache;
+
+  char const* FindUserHomeThroughUID() {
+    auto passwd = getpwuid(geteuid());
+    if (passwd) {
+      return passwd->pw_dir;
+    }
+    return nullptr;
+  }
+
+  const char *GetHomeDirectory() {
+    char const *HomeDir = getenv("HOME");
+
+    // Try to get home directory from uid
+    if (!HomeDir) {
+      HomeDir = FindUserHomeThroughUID();
+    }
+
+    // try the PWD
+    if (!HomeDir) {
+      HomeDir = getenv("PWD");
+    }
+
+    // Still doesn't exit? You get local
+    if (!HomeDir) {
+      HomeDir = ".";
+    }
+
+    return HomeDir;
+  }
 
   void InitializePaths() {
+    CachePath = std::make_unique<std::string>();
+    EntryCache = std::make_unique<std::string>();
+
     char const *HomeDir = getenv("HOME");
 
     if (!HomeDir) {
@@ -22,29 +57,35 @@ namespace FEXCore::Paths {
 
     char *XDGDataDir = getenv("XDG_DATA_DIR");
     if (XDGDataDir) {
-      CachePath = XDGDataDir;
+      *CachePath = XDGDataDir;
     }
     else {
       if (HomeDir) {
-        CachePath = HomeDir;
+        *CachePath = HomeDir;
       }
     }
 
-    CachePath += "/.fex-emu/";
-    EntryCache = CachePath + "/EntryCache/";
+    *CachePath += "/.fex-emu/";
+    *EntryCache = *CachePath + "/EntryCache/";
 
+    std::error_code ec{};
     // Ensure the folder structure is created for our Data
-    if (!std::filesystem::exists(EntryCache) &&
-        !std::filesystem::create_directories(EntryCache)) {
-      LogMan::Msg::D("Couldn't create EntryCache directory: '%s'", EntryCache.c_str());
+    if (!std::filesystem::exists(*EntryCache, ec) &&
+        !std::filesystem::create_directories(*EntryCache, ec)) {
+      LogMan::Msg::DFmt("Couldn't create EntryCache directory: '{}'", *EntryCache);
     }
   }
 
+  void ShutdownPaths() {
+    CachePath.reset();
+    EntryCache.reset();
+  }
+
   std::string GetCachePath() {
-    return CachePath;
+    return *CachePath;
   }
 
   std::string GetEntryCachePath() {
-    return EntryCache;
+    return *EntryCache;
   }
 }

External/FEXCore/Source/Common/Paths.h

@@ -3,6 +3,10 @@
 
 namespace FEXCore::Paths {
   void InitializePaths();
+  void ShutdownPaths();
+
+  const char *GetHomeDirectory();
+
   std::string GetCachePath();
   std::string GetEntryCachePath();
 }

External/FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c

@@ -96,6 +96,7 @@ extFloat80_t
         switch ( roundingMode ) {
          case softfloat_round_near_even:
             if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break;
+            __attribute__((fallthrough));
          case softfloat_round_near_maxMag:
             if ( exp == 0x3FFE ) goto mag1;
             break;

External/FEXCore/Source/Common/SoftFloat.h

@@ -1,4 +1,6 @@
 #pragma once
+
+#include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <cmath>
@@ -14,9 +16,19 @@ extern "C" {
 
 struct X80SoftFloat {
 #ifdef _M_X86_64
+// Define this to push some operations to x87
+// Only useful to see if precision loss is killing something
+// #define DEBUG_X86_FLOAT
+#ifdef DEBUG_X86_FLOAT
+#define BIGFLOAT long double
+#define BIGFLOATSIZE 10
+#else
 #define BIGFLOAT __float128
+#define BIGFLOATSIZE 16
+#endif
 #elif defined(_M_ARM_64)
 #define BIGFLOAT long double
+#define BIGFLOATSIZE 16
 #else
 #error No 128bit float for this target!
 #endif
@@ -45,35 +57,131 @@ struct X80SoftFloat {
 
   // Ops
   static X80SoftFloat FADD(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    faddp;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     return extF80_add(lhs, rhs);
+#endif
   }
 
   static X80SoftFloat FSUB(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fsubp;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     return extF80_sub(lhs, rhs);
+#endif
   }
 
   static X80SoftFloat FMUL(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fmulp;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     return extF80_mul(lhs, rhs);
+#endif
   }
 
   static X80SoftFloat FDIV(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fdivp;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     return extF80_div(lhs, rhs);
+#endif
   }
 
   static X80SoftFloat FREM(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
-    X80SoftFloat Rem = extF80_rem(lhs, rhs);
-    if (SignBit(Rem)) {
-      Rem = extF80_add(Rem, rhs);
-    }
-    else {
-      Rem.Sign = SignBit(lhs);
-    }
+#if defined(DEBUG_X86_FLOAT)
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fprem;
+    fstpt %[result];
+    ffreep %%st(0);
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
 
-    return Rem;
+    return Result;
+#else
+    return extF80_rem(lhs, rhs);
+#endif
   }
 
   static X80SoftFloat FREM1(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#if defined(DEBUG_X86_FLOAT)
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fprem1;
+    fstpt %[result];
+    ffreep %%st(0);
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     return extF80_rem(lhs, rhs);
+#endif
   }
 
   static X80SoftFloat FRNDINT(X80SoftFloat const &lhs) {
@@ -81,15 +189,47 @@ struct X80SoftFloat {
   }
 
   static X80SoftFloat FXTRACT_SIG(X80SoftFloat const &lhs) {
+#if defined(DEBUG_X86_FLOAT)
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fxtract;
+    fstpt %[result];
+    ffreep %%st(0);
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     X80SoftFloat Tmp = lhs;
     Tmp.Exponent = 0x3FFF;
     Tmp.Sign = lhs.Sign;
     return Tmp;
+#endif
   }
 
   static X80SoftFloat FXTRACT_EXP(X80SoftFloat const &lhs) {
+#if defined(DEBUG_X86_FLOAT)
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fxtract;
+    ffreep %%st(0);
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     int32_t TrueExp = lhs.Exponent - ExponentBias;
     return i32_to_extF80(TrueExp);
+#endif
   }
 
   static void FCMP(X80SoftFloat const &lhs, X80SoftFloat const &rhs, bool *eq, bool *lt, bool *nan) {
@@ -99,77 +239,211 @@ struct X80SoftFloat {
   }
 
   static X80SoftFloat FSCALE(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
-    WARN_ONCE("x87: Application used FSCALE which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FSCALE which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fscale; # st0 = st0 * 2^(rdint(st1))
+    fstpt %[result];
+    ffreep %%st(0);
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     X80SoftFloat Int = FRNDINT(rhs);
     BIGFLOAT Src2_d = Int;
     Src2_d = exp2l(Src2_d);
     X80SoftFloat Src2_X80 = Src2_d;
     X80SoftFloat Result = extF80_mul(lhs, Src2_X80);
     return Result;
+#endif
   }
 
   static X80SoftFloat F2XM1(X80SoftFloat const &lhs) {
-    WARN_ONCE("x87: Application used F2XM1 which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used F2XM1 which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    f2xm1; # st0 = 2^st(0) - 1
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
     BIGFLOAT Src1_d = lhs;
     BIGFLOAT Result = exp2l(Src1_d);
     Result -= 1.0;
     return Result;
+#endif
   }
 
   static X80SoftFloat FYL2X(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
-    WARN_ONCE("x87: Application used FYL2X which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FYL2X which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st(1)
+    fldt %[lhs]; # st(0)
+    fyl2x; # st(1) * log2l(st(0))
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     BIGFLOAT Src1_d = lhs;
     BIGFLOAT Src2_d = rhs;
     BIGFLOAT Tmp = Src2_d * log2l(Src1_d);
     return Tmp;
+#endif
   }
 
   static X80SoftFloat FATAN(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
-    WARN_ONCE("x87: Application used FATAN which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FATAN which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs];
+    fldt %[rhs];
+    fpatan;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
     BIGFLOAT Src1_d = lhs;
     BIGFLOAT Src2_d = rhs;
     BIGFLOAT Tmp = atan2l(Src1_d, Src2_d);
     return Tmp;
+#endif
   }
 
   static X80SoftFloat FTAN(X80SoftFloat const &lhs) {
-    WARN_ONCE("x87: Application used FTAN which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FTAN which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fptan;
+    ffreep %%st(0);
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
     BIGFLOAT Src_d = lhs;
     Src_d = tanl(Src_d);
     return Src_d;
+#endif
   }
 
   static X80SoftFloat FSIN(X80SoftFloat const &lhs) {
-    WARN_ONCE("x87: Application used FSIN which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FSIN which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fsin;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
     BIGFLOAT Src_d = lhs;
     Src_d = sinl(Src_d);
     return Src_d;
+#endif
   }
 
   static X80SoftFloat FCOS(X80SoftFloat const &lhs) {
-    WARN_ONCE("x87: Application used FCOS which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FCOS which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fcos;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
     BIGFLOAT Src_d = lhs;
     Src_d = cosl(Src_d);
     return Src_d;
+#endif
   }
 
   static X80SoftFloat FSQRT(X80SoftFloat const &lhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fsqrt;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
     return extF80_sqrt(lhs);
+#endif
   }
 
   operator float() const {
-    float32_t Result = extF80_to_f32(*this);
-    return *(float*)&Result;
+    const float32_t Result = extF80_to_f32(*this);
+    return FEXCore::BitCast<float>(Result);
   }
 
   operator double() const {
-    float64_t Result = extF80_to_f64(*this);
-    return *(double*)&Result;
+    const float64_t Result = extF80_to_f64(*this);
+    return FEXCore::BitCast<double>(Result);
   }
 
   operator BIGFLOAT() const {
-    float128_t Result = extF80_to_f128(*this);
-    return *(BIGFLOAT*)&Result;
+#if BIGFLOATSIZE == 16
+    const float128_t Result = extF80_to_f128(*this);
+    return FEXCore::BitCast<BIGFLOAT>(Result);
+#else
+    BIGFLOAT result{};
+    memcpy(&result, this, sizeof(result));
+    return result;
+#endif
   }
 
   operator int16_t() const {
@@ -196,11 +470,11 @@ struct X80SoftFloat {
   }
 
   void operator=(const float rhs) {
-    *this = f32_to_extF80(*(float32_t*)&rhs);
+    *this = f32_to_extF80(FEXCore::BitCast<float32_t>(rhs));
   }
 
   void operator=(const double rhs) {
-    *this = f64_to_extF80(*(float64_t*)&rhs);
+    *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
   }
 
   void operator=(const int16_t rhs) {
@@ -215,6 +489,12 @@ struct X80SoftFloat {
     *this = ui64_to_extF80(rhs);
   }
 
+#if BIGFLOATSIZE == 10
+  void operator=(const long double rhs) {
+    memcpy(this, &rhs, sizeof(rhs));
+  }
+#endif
+
   operator void*() {
     return reinterpret_cast<void*>(this);
   }
@@ -226,15 +506,19 @@ struct X80SoftFloat {
   }
 
   X80SoftFloat(const float rhs) {
-    *this = f32_to_extF80(*(float32_t*)&rhs);
+    *this = f32_to_extF80(FEXCore::BitCast<float32_t>(rhs));
   }
 
   X80SoftFloat(const double rhs) {
-    *this = f64_to_extF80(*(float64_t*)&rhs);
+    *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
   }
 
   X80SoftFloat(BIGFLOAT rhs) {
-    *this = f128_to_extF80(*(float128_t*)&rhs);
+#if BIGFLOATSIZE == 16
+    *this = f128_to_extF80(FEXCore::BitCast<float128_t>(rhs));
+#else
+    *this = FEXCore::BitCast<long double>(rhs);
+#endif
   }
 
   X80SoftFloat(const int16_t rhs) {

External/FEXCore/Source/Common/StringConv.h

@@ -38,4 +38,11 @@ namespace FEXCore::StrConv {
     *Result = Value;
     return true;
   }
+  template <typename T,
+    typename = std::enable_if<std::is_enum<T>::value, T>>
+  [[maybe_unused]] static bool Conv(std::string_view Value, T *Result) {
+    *Result = static_cast<T>(std::stoull(std::string(Value), nullptr, 0));
+    return true;
+  }
+
 }

External/FEXCore/Source/Interface/Config/Config.cpp

@@ -1,121 +1,204 @@
 #include "Common/StringConv.h"
-
-#include <FEXCore/Utils/LogManager.h>
-#include "Interface/Context/Context.h"
+#include "Common/Paths.h"
+#include "Utils/FileLoading.h"
 
 #include <FEXCore/Config/Config.h>
+#include <FEXCore/Utils/LogManager.h>
+
+#include <array>
+#include <assert.h>
+#include <cstdlib>
+#include <filesystem>
+#include <fstream>
+#include <functional>
 #include <map>
+#include <memory>
+#include <list>
+#include <optional>
+#include <stddef.h>
+#include <stdint.h>
+#include <string>
+#include <string_view>
+#include <sys/sysinfo.h>
+#include <system_error>
+#include <type_traits>
+#include <unordered_map>
+#include <utility>
+#include <vector>
+
+#include <tiny-json.h>
+
+namespace FEXCore::Context {
+  struct Context;
+}
 
 namespace FEXCore::Config {
-  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
-    switch (Option) {
-    case FEXCore::Config::CONFIG_MULTIBLOCK:
-      CTX->Config.Multiblock = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_MAXBLOCKINST:
-      CTX->Config.MaxInstPerBlock = Config;
-    break;
-    case FEXCore::Config::CONFIG_DEFAULTCORE:
-      CTX->Config.Core = static_cast<FEXCore::Config::ConfigCore>(Config);
-    break;
-    case FEXCore::Config::CONFIG_VIRTUALMEMSIZE:
-      CTX->Config.VirtualMemSize = Config;
-    break;
-    case FEXCore::Config::CONFIG_SINGLESTEP:
-      CTX->Config.RunningMode = Config != 0 ? FEXCore::Context::CoreRunningMode::MODE_SINGLESTEP : FEXCore::Context::CoreRunningMode::MODE_RUN;
-    break;
-    case FEXCore::Config::CONFIG_GDBSERVER:
-      Config != 0 ? CTX->StartGdbServer() : CTX->StopGdbServer();
-    break;
-    case FEXCore::Config::CONFIG_IS64BIT_MODE:
-      CTX->Config.Is64BitMode = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_TSO_ENABLED:
-      CTX->Config.TSOEnabled = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_SMC_CHECKS:
-      CTX->Config.SMCChecks = static_cast<FEXCore::Config::ConfigSMCChecks>(Config);
-    break;
-    case FEXCore::Config::CONFIG_ABI_LOCAL_FLAGS:
-      CTX->Config.ABILocalFlags = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_ABI_NO_PF:
-      CTX->Config.ABINoPF = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_VALIDATE_IR_PARSER:
-      CTX->Config.ValidateIRarser = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_AOTIR_GENERATE:
-      CTX->Config.AOTIRCapture = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_AOTIR_LOAD:
-      CTX->Config.AOTIRLoad = Config != 0;
-    break;
-    default: LogMan::Msg::A("Unknown configuration option");
+namespace DefaultValues {
+#define P(x) x
+#define OPT_BASE(type, group, enum, json, default) const P(type) P(enum) = P(default);
+#define OPT_STR(group, enum, json, default) const std::string_view P(enum) = P(default);
+#define OPT_STRARRAY(group, enum, json, default) OPT_STR(group, enum, json, default)
+#include <FEXCore/Config/ConfigValues.inl>
+}
+
+namespace JSON {
+  struct JsonAllocator {
+    jsonPool_t PoolObject;
+    std::unique_ptr<std::list<json_t>> json_objects;
+  };
+  static_assert(offsetof(JsonAllocator, PoolObject) == 0, "This needs to be at offset zero");
+
+  json_t* PoolInit(jsonPool_t* Pool) {
+    JsonAllocator* alloc = reinterpret_cast<JsonAllocator*>(Pool);
+    alloc->json_objects = std::make_unique<std::list<json_t>>();
+    return &*alloc->json_objects->emplace(alloc->json_objects->end());
+  }
+
+  json_t* PoolAlloc(jsonPool_t* Pool) {
+    JsonAllocator* alloc = reinterpret_cast<JsonAllocator*>(Pool);
+    return &*alloc->json_objects->emplace(alloc->json_objects->end());
+  }
+
+  static void LoadJSonConfig(const std::string &Config, std::function<void(const char *Name, const char *ConfigSring)> Func) {
+    std::vector<char> Data;
+    if (!FEXCore::FileLoading::LoadFile(Data, Config)) {
+      return;
     }
+
+    JsonAllocator Pool {
+      .PoolObject = {
+        .init = PoolInit,
+        .alloc = PoolAlloc,
+      },
+    };
+
+    json_t const *json = json_createWithPool(&Data.at(0), &Pool.PoolObject);
+    if (!json) {
+      LogMan::Msg::EFmt("Couldn't create json");
+      return;
+    }
+
+    json_t const* ConfigList = json_getProperty(json, "Config");
+
+    if (!ConfigList) {
+      LogMan::Msg::EFmt("Couldn't get config list");
+      return;
+    }
+
+    for (json_t const* ConfigItem = json_getChild(ConfigList);
+      ConfigItem != nullptr;
+      ConfigItem = json_getSibling(ConfigItem)) {
+      const char* ConfigName = json_getName(ConfigItem);
+      const char* ConfigString = json_getValue(ConfigItem);
+
+      if (!ConfigName) {
+        LogMan::Msg::EFmt("Couldn't get config name");
+        return;
+      }
+
+      if (!ConfigString) {
+        LogMan::Msg::EFmt("Couldn't get ConfigString for '{}'", ConfigName);
+        return;
+      }
+
+      Func(ConfigName, ConfigString);
+    }
+  }
+}
+
+  std::string GetDataDirectory() {
+    std::string DataDir{};
+
+    char const *HomeDir = Paths::GetHomeDirectory();
+    char const *DataXDG = getenv("XDG_DATA_HOME");
+    char const *DataOverride = getenv("FEX_APP_DATA_LOCATION");
+    if (DataOverride) {
+      // Data override will override the complete directory
+      DataDir = DataOverride;
+    }
+    else {
+      DataDir = DataXDG ?: HomeDir;
+      DataDir += "/.fex-emu/";
+    }
+    return DataDir;
+  }
+
+  std::string GetConfigDirectory(bool Global) {
+    std::string ConfigDir;
+    if (Global) {
+      ConfigDir = GLOBAL_DATA_DIRECTORY;
+    }
+    else {
+      char const *HomeDir = Paths::GetHomeDirectory();
+      char const *ConfigXDG = getenv("XDG_CONFIG_HOME");
+      char const *ConfigOverride = getenv("FEX_APP_CONFIG_LOCATION");
+      if (ConfigOverride) {
+        // Config override completely overrides the config directory
+        ConfigDir = ConfigOverride;
+      }
+      else {
+        ConfigDir = ConfigXDG ? ConfigXDG : HomeDir;
+        ConfigDir += "/.fex-emu/";
+      }
+
+      // Ensure the folder structure is created for our configuration
+      std::error_code ec{};
+      if (!std::filesystem::exists(ConfigDir, ec) &&
+          !std::filesystem::create_directories(ConfigDir, ec)) {
+        // Let's go local in this case
+        return "./";
+      }
+    }
+
+    return ConfigDir;
+  }
+
+  std::string GetConfigFileLocation() {
+    std::string ConfigFile{};
+    const char *AppConfig = getenv("FEX_APP_CONFIG");
+    if (AppConfig) {
+      // App config environment variable overwrites only the config file
+      ConfigFile = AppConfig;
+    }
+    else {
+      ConfigFile = GetConfigDirectory(false) + "Config.json";
+    }
+    return ConfigFile;
+  }
+
+  std::string GetApplicationConfig(const std::string &Filename, bool Global) {
+    std::string ConfigFile = GetConfigDirectory(Global);
+
+    std::error_code ec{};
+    if (!Global &&
+        !std::filesystem::exists(ConfigFile, ec) &&
+        !std::filesystem::create_directories(ConfigFile, ec)) {
+      LogMan::Msg::DFmt("Couldn't create config directory: '{}'", ConfigFile);
+      // Let's go local in this case
+      return "./" + Filename + ".json";
+    }
+
+    ConfigFile += "AppConfig/";
+
+    // Attempt to create the local folder if it doesn't exist
+    if (!Global &&
+        !std::filesystem::exists(ConfigFile, ec) &&
+        !std::filesystem::create_directories(ConfigFile, ec)) {
+      // Let's go local in this case
+      return "./" + Filename + ".json";
+    }
+
+    ConfigFile += Filename + ".json";
+    return ConfigFile;
+  }
+
+  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
   }
 
   void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, std::string const &Config) {
-    switch (Option) {
-    case CONFIG_ROOTFSPATH:
-      CTX->Config.RootFSPath = Config;
-      break;
-    case CONFIG_THUNKLIBSPATH:
-      CTX->Config.ThunkLibsPath = Config;
-      break;
-    case FEXCore::Config::CONFIG_DUMPIR:
-      CTX->Config.DumpIR = Config;
-      break;
-    default: LogMan::Msg::A("Unknown configuration option");
-    }
   }
 
   uint64_t GetConfig(FEXCore::Context::Context *CTX, ConfigOption Option) {
-    switch (Option) {
-    case FEXCore::Config::CONFIG_MULTIBLOCK:
-      return CTX->Config.Multiblock;
-    break;
-    case FEXCore::Config::CONFIG_MAXBLOCKINST:
-      return CTX->Config.MaxInstPerBlock;
-    break;
-    case FEXCore::Config::CONFIG_DEFAULTCORE:
-      return CTX->Config.Core;
-    break;
-    case FEXCore::Config::CONFIG_VIRTUALMEMSIZE:
-      return CTX->Config.VirtualMemSize;
-    break;
-    case FEXCore::Config::CONFIG_SINGLESTEP:
-      return CTX->Config.RunningMode == FEXCore::Context::CoreRunningMode::MODE_SINGLESTEP ? 1 : 0;
-    case FEXCore::Config::CONFIG_GDBSERVER:
-      return CTX->GetGdbServerStatus();
-    break;
-    case FEXCore::Config::CONFIG_IS64BIT_MODE:
-      return CTX->Config.Is64BitMode;
-    break;
-    case FEXCore::Config::CONFIG_TSO_ENABLED:
-      return CTX->Config.TSOEnabled;
-    break;
-    case FEXCore::Config::CONFIG_SMC_CHECKS:
-      return CTX->Config.SMCChecks;
-    break;
-    case FEXCore::Config::CONFIG_ABI_LOCAL_FLAGS:
-      return CTX->Config.ABILocalFlags;
-    break;
-    case FEXCore::Config::CONFIG_ABI_NO_PF:
-      return CTX->Config.ABINoPF;
-    break;
-    case FEXCore::Config::CONFIG_VALIDATE_IR_PARSER:
-      return CTX->Config.ValidateIRarser;
-    break;
-    case FEXCore::Config::CONFIG_AOTIR_GENERATE:
-      return CTX->Config.AOTIRCapture;
-    break;
-    case FEXCore::Config::CONFIG_AOTIR_LOAD:
-      return CTX->Config.AOTIRLoad;
-    break;
-    default: LogMan::Msg::A("Unknown configuration option");
-    }
-
     return 0;
   }
 
@@ -149,6 +232,7 @@ namespace FEXCore::Config {
 
   private:
     void MergeConfigMap(const LayerOptions &Options);
+    void MergeEnvironmentVariables(ConfigOption const &Option, LayerValue const &Value);
   };
 
   void MetaLayer::Load() {
@@ -163,10 +247,57 @@ namespace FEXCore::Config {
     }
   }
 
+
+  void MetaLayer::MergeEnvironmentVariables(ConfigOption const &Option, LayerValue const &Value) {
+    // Environment variables need a bit of additional work
+    // We want to merge the arrays rather than overwrite entirely
+    auto MetaEnvironment = OptionMap.find(Option);
+    if (MetaEnvironment == OptionMap.end()) {
+      // Doesn't exist, just insert
+      OptionMap.insert_or_assign(Option, Value);
+      return;
+    }
+
+    // If an environment variable exists in both current meta and in the incoming layer then the meta layer value is overwritten
+    std::unordered_map<std::string, std::string> LookupMap;
+    const auto AddToMap = [&LookupMap](FEXCore::Config::LayerValue const &Value) {
+      for (const auto &EnvVar : Value) {
+        const auto ItEq = EnvVar.find_first_of('=');
+        if (ItEq == std::string::npos) {
+          // Broken environment variable
+          // Skip
+          continue;
+        }
+        auto Key = std::string(EnvVar.begin(), EnvVar.begin() + ItEq);
+        auto Value = std::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
+
+        // Add the key to the map, overwriting whatever previous value was there
+        LookupMap.insert_or_assign(std::move(Key), std::move(Value));
+      }
+    };
+
+    AddToMap(MetaEnvironment->second);
+    AddToMap(Value);
+
+    // Now with the two layers merged in the map
+    // Add all the values to the option
+    Erase(Option);
+    for (auto &Val : LookupMap) {
+      // Set will emplace multiple options in to its list
+      Set(Option, Val.first + "=" + Val.second);
+    }
+  }
+
   void MetaLayer::MergeConfigMap(const LayerOptions &Options) {
     // Insert this layer's options, overlaying previous options that exist here
     for (auto &it : Options) {
-      OptionMap.insert_or_assign(it.first, it.second);
+      if (it.first == FEXCore::Config::ConfigOption::CONFIG_ENV ||
+          it.first == FEXCore::Config::ConfigOption::CONFIG_HOSTENV) {
+        MergeEnvironmentVariables(it.first, it.second);
+      }
+      else {
+        OptionMap.insert_or_assign(it.first, it.second);
+      }
     }
   }
 
@@ -189,8 +320,190 @@ namespace FEXCore::Config {
     }
   }
 
+  std::string ExpandPath(std::string const &ContainerPrefix, std::string PathName) {
+    if (PathName.empty()) {
+      return {};
+    }
+
+    std::filesystem::path Path{PathName};
+
+    // Expand home if it exists
+    if (Path.is_relative()) {
+      std::string Home = getenv("HOME") ?: "";
+      // Home expansion only works if it is the first character
+      // This matches bash behaviour
+      if (PathName.at(0) == '~') {
+        PathName.replace(0, 1, Home);
+        return PathName;
+      }
+
+      // Expand relative path to absolute
+      Path = std::filesystem::absolute(Path);
+
+      // Only return if it exists
+      std::error_code ec{};
+      if (std::filesystem::exists(Path, ec)) {
+        return Path;
+      }
+    }
+    else {
+      // If the containerprefix and pathname isn't empty
+      // Then we check if the pathname exists in our current namespace
+      // If the path DOESN'T exist but DOES exist with the prefix applied
+      // then redirect to the prefix
+      //
+      // This might not be expected behaviour for some edge cases but since
+      // all paths aren't mounted inside the container, then it'll be fine
+      //
+      // Main catch case for this is the default thunk install folders
+      // HostThunks: $CMAKE_INSTALL_PREFIX/lib/fex-emu/HostThunks/
+      // GuestThunks: $CMAKE_INSTALL_PREFIX/share/fex-emu/GuestThunks/
+      if (!ContainerPrefix.empty() && !PathName.empty()) {
+        if (!std::filesystem::exists(PathName)) {
+          auto ContainerPath = ContainerPrefix + PathName;
+          if (std::filesystem::exists(ContainerPath)) {
+            return ContainerPath;
+          }
+        }
+      }
+    }
+    return {};
+  }
+
+  std::string ltrim(std::string String) {
+    size_t pos = std::string::npos;
+    if ((pos = String.find_first_not_of(" \t\n\r")) != std::string::npos) {
+      String.erase(0, pos);
+    }
+
+    return String;
+  }
+
+  std::string rtrim(std::string String) {
+    size_t pos = std::string::npos;
+    if ((pos = String.find_last_not_of(" \t\n\r")) != std::string::npos) {
+      String.erase(String.begin() + pos + 1, String.end());
+    }
+
+    return String;
+  }
+
+  std::string trim(std::string String) {
+    return rtrim(ltrim(String));
+  }
+
+
+  std::string FindContainerPrefix() {
+    // We only support pressure-vessel at the moment
+    const static std::string ContainerManager = "/run/host/container-manager";
+    if (std::filesystem::exists(ContainerManager)) {
+      std::vector<char> Manager{};
+      if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
+        // Trim the whitespace, may contain a newline
+        std::string ManagerStr = Manager.data();
+        ManagerStr = trim(ManagerStr);
+        if (strncmp(ManagerStr.data(), "pressure-vessel", Manager.size()) == 0) {
+          // We are running inside of pressure vessel
+          // Our $CMAKE_INSTALL_PREFIX paths are now inside of /run/host/$CMAKE_INSTALL_PREFIX
+          return "/run/host/";
+        }
+      }
+    }
+    return {};
+  }
+
   void ReloadMetaLayer() {
     Meta->Load();
+
+    // Do configuration option fix ups after everything is reloaded
+    {
+      // Always fix up the number of threads and create the configuration
+      // Otherwise the application could receive zero as the number of threads
+      FEX_CONFIG_OPT(Cores, THREADS);
+      if (Cores == 0) {
+        // When the number of emulated CPU cores is zero then auto detect
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THREADS, std::to_string(get_nprocs_conf()));
+      }
+    }
+
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_CORE)) {
+      // Sanitize Core option
+      FEX_CONFIG_OPT(Core, CORE);
+#if (_M_X86_64)
+      constexpr uint32_t MaxCoreNumber = 2;
+#else
+      constexpr uint32_t MaxCoreNumber = 1;
+#endif
+#ifdef INTERPRETER_ENABLED
+      constexpr uint32_t MinCoreNumber = 0;
+#else
+      constexpr uint32_t MinCoreNumber = 1;
+#endif
+      if (Core > MaxCoreNumber || Core < MinCoreNumber) {
+        // Sanitize the core option by setting the core to the JIT if invalid
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, std::to_string(FEXCore::Config::CONFIG_IRJIT));
+      }
+    }
+
+    std::string ContainerPrefix { FindContainerPrefix() };
+    auto ExpandPathIfExists = [&ContainerPrefix](FEXCore::Config::ConfigOption Config, std::string PathName) {
+      auto NewPath = ExpandPath(ContainerPrefix, PathName);
+      if (!NewPath.empty()) {
+        FEXCore::Config::EraseSet(Config, NewPath);
+      }
+    };
+
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_ROOTFS)) {
+      FEX_CONFIG_OPT(PathName, ROOTFS);
+      auto ExpandedString = ExpandPath(ContainerPrefix, PathName());
+      if (!ExpandedString.empty()) {
+        // Adjust the path if it ended up being relative
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, ExpandedString);
+      }
+      else if (!PathName().empty()) {
+        // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
+        std::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
+        std::error_code ec{};
+        if (std::filesystem::exists(NamedRootFS, ec)) {
+          FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NamedRootFS);
+        }
+      }
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKHOSTLIBS)) {
+      FEX_CONFIG_OPT(PathName, THUNKHOSTLIBS);
+      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKHOSTLIBS, PathName());
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKGUESTLIBS)) {
+      FEX_CONFIG_OPT(PathName, THUNKGUESTLIBS);
+      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKGUESTLIBS, PathName());
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKCONFIG)) {
+      FEX_CONFIG_OPT(PathName, THUNKCONFIG);
+      auto ExpandedString = ExpandPath(ContainerPrefix, PathName());
+      if (!ExpandedString.empty()) {
+        // Adjust the path if it ended up being relative
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, ExpandedString);
+      }
+      else if (!PathName().empty()) {
+        // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
+        std::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
+        std::error_code ec{};
+        if (std::filesystem::exists(NamedConfig, ec)) {
+          FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, NamedConfig);
+        }
+      }
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_OUTPUTLOG)) {
+      FEX_CONFIG_OPT(PathName, OUTPUTLOG);
+      if (PathName() != "stdout" && PathName() != "stderr") {
+        ExpandPathIfExists(FEXCore::Config::CONFIG_OUTPUTLOG, PathName());
+      }
+    }
+
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_SINGLESTEP)) {
+      // Single stepping also enforces single instruction size blocks
+      Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, std::to_string(1u));
+    }
   }
 
   void AddLayer(std::unique_ptr<FEXCore::Config::Layer> _Layer) {
@@ -209,11 +522,15 @@ namespace FEXCore::Config {
     return Meta->Get(Option);
   }
 
-  void Set(ConfigOption Option, std::string Data) {
+  void Set(ConfigOption Option, std::string_view Data) {
     Meta->Set(Option, Data);
   }
 
-  void EraseSet(ConfigOption Option, std::string Data) {
+  void Erase(ConfigOption Option) {
+    Meta->Erase(Option);
+  }
+
+  void EraseSet(ConfigOption Option, std::string_view Data) {
     Meta->EraseSet(Option, Data);
   }
 
@@ -252,8 +569,25 @@ namespace FEXCore::Config {
     }
   }
 
-  template bool Value<bool>::GetIfExists(FEXCore::Config::ConfigOption Option, bool Default);
-  template uint8_t Value<uint8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint8_t Default);
+  template<>
+  std::string Value<std::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string_view Default) {
+    auto Value = FEXCore::Config::Get(Option);
+    if (Value) {
+      return **Value;
+    }
+    else {
+      return std::string(Default);
+    }
+  }
+
+  template bool     Value<bool>::GetIfExists(FEXCore::Config::ConfigOption Option, bool Default);
+  template int8_t   Value<int8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int8_t Default);
+  template uint8_t  Value<uint8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint8_t Default);
+  template int16_t   Value<int16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int16_t Default);
+  template uint16_t  Value<uint16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint16_t Default);
+  template int32_t  Value<int32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int32_t Default);
+  template uint32_t Value<uint32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint32_t Default);
+  template int64_t  Value<int64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int64_t Default);
   template uint64_t Value<uint64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint64_t Default);
 
   // Constructor
@@ -270,5 +604,148 @@ namespace FEXCore::Config {
       *List = **Value;
     }
   }
+  template void Value<std::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, std::list<std::string> *List);
+
+  // Application loaders
+  class MainLoader final : public FEXCore::Config::OptionMapper {
+  public:
+    explicit MainLoader();
+    explicit MainLoader(std::string ConfigFile);
+    void Load() override;
+
+  private:
+    std::string Config;
+  };
+
+  class AppLoader final : public FEXCore::Config::OptionMapper {
+  public:
+    explicit AppLoader(const std::string& Filename, bool Global);
+    void Load();
+
+  private:
+    std::string Config;
+  };
+
+  class EnvLoader final : public FEXCore::Config::Layer {
+  public:
+    explicit EnvLoader(char *const _envp[]);
+    void Load() override;
+
+  private:
+    char *const *envp;
+  };
+
+  static const std::map<std::string, FEXCore::Config::ConfigOption, std::less<>> ConfigLookup = {{
+#define OPT_BASE(type, group, enum, json, default) {#json, FEXCore::Config::ConfigOption::CONFIG_##enum},
+#include <FEXCore/Config/ConfigValues.inl>
+  }};
+  static const std::vector<std::pair<const char*, FEXCore::Config::ConfigOption>> EnvConfigLookup = {{
+#define OPT_BASE(type, group, enum, json, default) {"FEX_" #enum, FEXCore::Config::ConfigOption::CONFIG_##enum},
+#include <FEXCore/Config/ConfigValues.inl>
+  }};
+
+  OptionMapper::OptionMapper(FEXCore::Config::LayerType Layer)
+    : FEXCore::Config::Layer(Layer) {
+  }
+
+  void OptionMapper::MapNameToOption(const char *ConfigName, const char *ConfigString) {
+    auto it = ConfigLookup.find(ConfigName);
+    if (it != ConfigLookup.end()) {
+      Set(it->second, ConfigString);
+    }
+  }
+
+  MainLoader::MainLoader()
+    : FEXCore::Config::OptionMapper(FEXCore::Config::LayerType::LAYER_MAIN)
+    , Config{FEXCore::Config::GetConfigFileLocation()} {
+  }
+
+  MainLoader::MainLoader(std::string ConfigFile)
+    : FEXCore::Config::OptionMapper(FEXCore::Config::LayerType::LAYER_MAIN)
+    , Config{std::move(ConfigFile)} {
+  }
+
+  void MainLoader::Load() {
+    JSON::LoadJSonConfig(Config, [this](const char *Name, const char *ConfigString) {
+      MapNameToOption(Name, ConfigString);
+    });
+  }
+
+  AppLoader::AppLoader(const std::string& Filename, bool Global)
+    : FEXCore::Config::OptionMapper(Global ? FEXCore::Config::LayerType::LAYER_GLOBAL_APP : FEXCore::Config::LayerType::LAYER_LOCAL_APP) {
+    Config = FEXCore::Config::GetApplicationConfig(Filename, Global);
+
+    // Immediately load so we can reload the meta layer
+    Load();
+  }
+
+  void AppLoader::Load() {
+    JSON::LoadJSonConfig(Config, [this](const char *Name, const char *ConfigString) {
+      MapNameToOption(Name, ConfigString);
+    });
+  }
+
+  EnvLoader::EnvLoader(char *const _envp[])
+    : FEXCore::Config::Layer(FEXCore::Config::LayerType::LAYER_ENVIRONMENT)
+    , envp {_envp} {
+  }
+
+  void EnvLoader::Load() {
+    std::unordered_map<std::string_view, std::string_view> EnvMap;
+
+    for(const char *const *pvar=envp; pvar && *pvar; pvar++) {
+      std::string_view Var(*pvar);
+      size_t pos = Var.rfind('=');
+      if (std::string::npos == pos)
+        continue;
+
+      std::string_view Key = Var.substr(0,pos);
+      std::string_view Value {Var.substr(pos+1)};
+
+#define ENVLOADER
+#include <FEXCore/Config/ConfigOptions.inl>
+
+      EnvMap[Key]=Value;
+    }
+
+    std::function GetVar = [=](const std::string_view id)  -> std::optional<std::string_view> {
+      if (EnvMap.find(id) != EnvMap.end())
+        return EnvMap.at(id);
+
+      // If envp[] was empty, search using std::getenv()
+      const char* vs = std::getenv(id.data());
+      if (vs) {
+        return vs;
+      }
+      else {
+        return std::nullopt;
+      }
+    };
+
+    std::optional<std::string_view> Value;
+
+    for (auto &it : EnvConfigLookup) {
+      if ((Value = GetVar(it.first)).has_value()) {
+        Set(it.second, std::string(*Value));
+      }
+    }
+  }
+
+  std::unique_ptr<FEXCore::Config::Layer> CreateMainLayer(std::string const *File) {
+    if (File) {
+      return std::make_unique<FEXCore::Config::MainLoader>(*File);
+    }
+    else {
+      return std::make_unique<FEXCore::Config::MainLoader>();
+    }
+  }
+
+  std::unique_ptr<FEXCore::Config::Layer> CreateAppLayer(const std::string& Filename, bool Global) {
+    return std::make_unique<FEXCore::Config::AppLoader>(Filename, Global);
+  }
+
+  std::unique_ptr<FEXCore::Config::Layer> CreateEnvironmentLayer(char *const _envp[]) {
+    return std::make_unique<FEXCore::Config::EnvLoader>(_envp);
+  }
 }
 

External/FEXCore/Source/Interface/Config/Config.json.in

@@ -0,0 +1,326 @@
+{
+  "Options": {
+    "CPU": {
+      "Core": {
+        "Type": "uint32",
+        "Default": "FEXCore::Config::ConfigCore::CONFIG_IRJIT",
+        "TextDefault": "irjit",
+        "ShortArg": "c",
+        "Choices": [ "irint", "irjit", "host" ],
+        "ArgumentHandler": "CoreHandler",
+        "Desc": [
+          "Which CPU core to use",
+          "host only exists on x86_64",
+          "[irint, irjit, host]"
+        ]
+      },
+      "Multiblock": {
+        "Type": "bool",
+        "Default": "true",
+        "ShortArg": "m",
+        "Desc": [
+          "Controls multiblock code compilation"
+        ]
+      },
+      "MaxInst": {
+        "Type": "int32",
+        "Default": "5000",
+        "ShortArg": "n",
+        "Desc": [
+          "Maximum number of instruction to store in a block"
+        ]
+      },
+      "Threads": {
+        "Type": "uint32",
+        "Default": "0",
+        "ShortArg": "T",
+        "Desc": [
+          "Number of physical hardware threads to tell the process we have.",
+          "0 will auto detect."
+        ]
+      }
+    },
+    "Emulation": {
+      "RootFS": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "R",
+        "Desc": [
+          "Which Root filesystem prefix to use",
+          "This can be a filesystem path",
+          "\teg: ~/RootFS/Debian_x86_64",
+          "Or this can be a name of a rootfs",
+          "If the named rootfs exists in the FEX data folder then it will use that one",
+          "\teg: $HOME/.fex-emu/RootFS/<RootFS name>/",
+          "Or if you have XDG_DATA_HOME the config will search in that directory",
+          "\teg: $XDG_DATA_HOME/.fex-emu/RootFS/<RootFS name>/"
+        ]
+      },
+      "ThunkHostLibs": {
+        "Type": "str",
+        "Default": "@CMAKE_INSTALL_PREFIX@/lib/fex-emu/HostThunks/",
+        "ShortArg": "t",
+        "Desc": [
+          "Folder to find the host-side thunking libraries."
+        ]
+      },
+      "ThunkGuestLibs": {
+        "Type": "str",
+        "Default": "@CMAKE_INSTALL_PREFIX@/share/fex-emu/GuestThunks/",
+        "ShortArg": "j",
+        "Desc": [
+          "Folder to find the guest-side thunking libraries."
+        ]
+      },
+      "ThunkConfig": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "k",
+        "Desc": [
+          "A json file specifying where to overlay the thunks.",
+          "This can be a filesystem path",
+          "\teg: ~/MyThunkConfig.json",
+          "Or this can be a named of a Thunk config file",
+          "If the named config file exists in the FEX data folder folder the it will use that one",
+          "\teg: $HOME/.fex-emu/ThunkConfigs/<ThunkConfig name>",
+          "Or if you have XDG_DATA_HOME the config will search in that directory",
+          "\teg: $XDG_DATA_HOME/.fex-emu/ThunkConfigs/<ThunkConfig name>"
+        ]
+      },
+      "Env": {
+        "Type": "strarray",
+        "Default": "",
+        "ShortArg": "E",
+        "Desc": [
+          "Adds an environment variable to the emulated environment."
+        ]
+      },
+      "HostEnv": {
+        "Type": "strarray",
+        "Default": "",
+        "ShortArg": "H",
+        "Desc": [
+          "Adds an environment variable to the host environment.",
+          "This can be useful for setting environment variables that thunks can pick up.",
+          "Typically isn't necessary since the guest libc isn't thunked. But is possible."
+        ]
+      }
+    },
+    "Debug": {
+      "SingleStep": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "S",
+        "Desc": [
+          "Single stepping configuration."
+        ]
+      },
+      "GdbServer": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "G",
+        "Desc": [
+          "Enables the GDB server."
+        ]
+      },
+      "DumpIR": {
+        "Type": "str",
+        "Default": "no",
+        "Desc": [
+          "Folder to dump the IR in to.",
+          "[no, stdout, stderr, <Folder>]"
+        ]
+      },
+      "DumpGPRs": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "g",
+        "Desc": [
+          "When the test harness ends, print the GPR state."
+        ]
+      },
+      "O0": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "O0",
+        "Desc": [
+          "Disables optimizations passes for debugging."
+        ]
+      },
+      "SRA": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "Set to false to disable Static Register Allocation"
+        ]
+      },
+      "Force32BitAllocator": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Forces use of the 32-bit allocator on 32-bit applications",
+          "Used to work around ulimit problems of CI runner",
+          "Potentially useful for debugging memory problems",
+          "32-bit allocator is always used if your host kernel is older than 4.17"
+        ]
+      },
+      "GlobalJITNaming": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Uses JITSymbols to name all JIT state as one symbol",
+          "Useful for querying how much time is spent inside of the JIT",
+          "Profiling tools will show JIT time as FEXJIT"
+        ]
+      },
+      "LibraryJITNaming": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Uses JITSymbols to name JIT symbols grouped by library",
+          "Useful for querying how much time is spent in each guest library",
+          "Can be used to help guide thunk generation"
+        ]
+      },
+      "BlockJITNaming": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Uses JITSymbols to name JIT symbols",
+          "Useful for determining hot blocks of code",
+          "Has some file writing overhead per JIT block"
+        ]
+      }
+    },
+    "Logging": {
+      "SilentLog": {
+        "Type": "bool",
+        "Default": "true",
+        "ShortArg": "s",
+        "Desc": [
+          "Disables logging"
+        ]
+      },
+      "OutputSocket": {
+        "Type": "str",
+        "Default": "",
+        "Desc": [
+          "Socket to connect to",
+          "eg: localhost:8087",
+          "If set will override the OutputLog location"
+        ]
+      },
+      "OutputLog": {
+        "Type": "str",
+        "Default": "stderr",
+        "ShortArg": "o",
+        "Desc": [
+          "File to write FEX output to.",
+          "[stdout, stderr, <Filename>]"
+        ]
+      }
+    },
+    "Hacks": {
+      "SMCChecks": {
+        "Type": "uint8",
+        "Default": "FEXCore::Config::CONFIG_SMC_MMAN",
+        "TextDefault": "mman",
+        "ArgumentHandler": "SMCCheckHandler",
+        "Desc": [
+          "Checks code for modification before execution.",
+          "\tnone: No checks",
+          "\tmman: Invalidate on mmap, mprotect, munmap",
+          "\tfull: Validate code before every run (slow)"
+        ]
+      },
+      "TSOEnabled": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "Controls TSO IR ops.",
+          "Highly likely to break any multithreaded application if disabled."
+        ]
+      },
+      "ABILocalFlags": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "When enabled enables an optimization around flags.",
+          "Assumes flags are not used across cals.",
+          "Hand-written assembly can violate this assumption."
+        ]
+      },
+      "ABINoPF": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "When enabled enables an optimization around parity flag calculation.",
+          "Removes the calculation of the parity flag from GPR instructions.",
+          "Assuming no uses rely on it"
+        ]
+      },
+      "ParanoidTSO": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Makes TSO operations even more strict.",
+          "Forces vector loadstores to also become atomic."
+        ]
+      },
+      "StallProcess": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Forces a process to stall out on initialization",
+          "Useful for a process that keeps restarting and doesn't work"
+        ]
+      }
+    },
+    "Misc": {
+      "AOTIRCapture": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Captures IR and generates an AOT IR cache.",
+          "Captures both the loaded executable and libraries it loads."
+        ]
+      },
+      "AOTIRGenerate": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Scans file for executable code and generates an AOT IR cache.",
+          "Does not run the executable."
+        ]
+      },
+      "AOTIRLoad": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Loads an AOT IR cache for the loaded executable."
+        ]
+      }
+    }
+  },
+  "UnnamedOptions": {
+    "Misc": {
+      "IS_INTERPRETER": {
+        "Type": "bool",
+        "Default": "false"
+      },
+      "INTERPRETER_INSTALLED": {
+        "Type": "bool",
+        "Default": "false"
+      },
+      "APP_FILENAME": {
+        "Type": "str",
+        "Default": ""
+      },
+      "IS64BIT_MODE": {
+        "Type": "bool",
+        "Default": "false"
+      }
+    }
+  }
+}
+

External/FEXCore/Source/Interface/Context/Context.cpp

@@ -2,10 +2,20 @@
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Core.h"
 #include "Interface/Core/OpcodeDispatcher.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 
-#include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Debug/X86Tables.h>
+#include <FEXCore/Core/Context.h>
+#include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Core/SignalDelegator.h>
+#include "FEXCore/Debug/InternalThreadState.h"
+
+#include <string.h>
+#include <utility>
+
+namespace FEXCore::HLE {
+  class SyscallVisitor;
+}
 
 namespace FEXCore::Context {
   void InitializeStaticTables(OperatingMode Mode) {
@@ -14,6 +24,10 @@ namespace FEXCore::Context {
     IR::InstallOpcodeHandlers(Mode);
   }
 
+  void ShutdownStaticTables() {
+    FEXCore::Paths::ShutdownPaths();
+  }
+
   FEXCore::Context::Context *CreateNewContext() {
     return new FEXCore::Context::Context{};
   }
@@ -23,19 +37,21 @@ namespace FEXCore::Context {
   }
 
   void DestroyContext(FEXCore::Context::Context *CTX) {
+    if (CTX->ParentThread) {
+      CTX->DestroyThread(CTX->ParentThread);
+    }
     delete CTX;
   }
 
-  bool InitCore(FEXCore::Context::Context *CTX, FEXCore::CodeLoader *Loader) {
+  FEXCore::Core::InternalThreadState* InitCore(FEXCore::Context::Context *CTX, FEXCore::CodeLoader *Loader) {
     return CTX->InitCore(Loader);
   }
 
-  void SetExitHandler(FEXCore::Context::Context *CTX,
-      std::function<void(uint64_t ThreadId, FEXCore::Context::ExitReason)> handler) {
-    CTX->CustomExitHandler = handler;
+  void SetExitHandler(FEXCore::Context::Context *CTX, ExitHandler handler) {
+    CTX->CustomExitHandler = std::move(handler);
   }
 
-  std::function<void(uint64_t ThreadId, FEXCore::Context::ExitReason)> GetExitHandler(FEXCore::Context::Context *CTX) {
+  ExitHandler GetExitHandler(const FEXCore::Context::Context *CTX) {
     return CTX->CustomExitHandler;
   }
 
@@ -47,29 +63,32 @@ namespace FEXCore::Context {
     CTX->Step();
   }
 
+  void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
+    Thread->CTX->CompileBlock(Thread->CurrentFrame, GuestRIP);
+  }
 
   FEXCore::Context::ExitReason RunUntilExit(FEXCore::Context::Context *CTX) {
     return CTX->RunUntilExit();
   }
 
-  int GetProgramStatus(FEXCore::Context::Context *CTX) {
+  int GetProgramStatus(const FEXCore::Context::Context *CTX) {
     return CTX->GetProgramStatus();
   }
 
-  FEXCore::Context::ExitReason GetExitReason(FEXCore::Context::Context *CTX) {
+  FEXCore::Context::ExitReason GetExitReason(const FEXCore::Context::Context *CTX) {
     return CTX->ParentThread->ExitReason;
   }
 
-  bool IsDone(FEXCore::Context::Context *CTX) {
+  bool IsDone(const FEXCore::Context::Context *CTX) {
     return CTX->IsPaused();
   }
 
-  void GetCPUState(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
-    memcpy(State, &CTX->ParentThread->State.State, sizeof(FEXCore::Core::CPUState));
+  void GetCPUState(const FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
+    memcpy(State, CTX->ParentThread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
   }
 
-  void SetCPUState(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
-    memcpy(&CTX->ParentThread->State.State, State, sizeof(FEXCore::Core::CPUState));
+  void SetCPUState(FEXCore::Context::Context *CTX, const FEXCore::Core::CPUState *State) {
+    memcpy(CTX->ParentThread->CurrentFrame, State, sizeof(FEXCore::Core::CPUState));
   }
 
   void Pause(FEXCore::Context::Context *CTX) {
@@ -84,10 +103,6 @@ namespace FEXCore::Context {
     CTX->CustomCPUFactory = std::move(Factory);
   }
 
-  void SetFallbackCPUBackendFactory(FEXCore::Context::Context *CTX, CustomCPUFactoryType Factory) {
-    CTX->FallbackCPUFactory = std::move(Factory);
-  }
-
   bool AddVirtualMemoryMapping([[maybe_unused]] FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t VirtualAddress, [[maybe_unused]] uint64_t PhysicalAddress, [[maybe_unused]] uint64_t Size) {
     return false;
   }
@@ -95,22 +110,26 @@ namespace FEXCore::Context {
   void RegisterExternalSyscallVisitor(FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t Syscall, [[maybe_unused]] FEXCore::HLE::SyscallVisitor *Visitor) {
   }
 
-  void HandleCallback(FEXCore::Context::Context *CTX, uint64_t RIP) {
-    CTX->HandleCallback(RIP);
+  void HandleCallback(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
+    CTX->HandleCallback(Thread, RIP);
   }
 
-  void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func) {
-      CTX->RegisterHostSignalHandler(Signal, Func);
+  void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
+      CTX->RegisterHostSignalHandler(Signal, std::move(Func), Required);
   }
 
-  void RegisterFrontendHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func) {
-    CTX->RegisterFrontendHostSignalHandler(Signal, Func);
+  void RegisterFrontendHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
+    CTX->RegisterFrontendHostSignalHandler(Signal, std::move(Func), Required);
   }
 
   FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) {
     return CTX->CreateThread(NewThreadState, ParentTID);
   }
 
+  void ExecutionThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
+    return CTX->ExecutionThread(Thread);
+  }
+
   void InitializeThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
     return CTX->InitializeThread(Thread);
   }
@@ -123,20 +142,12 @@ namespace FEXCore::Context {
     CTX->StopThread(Thread);
   }
 
-  void DeleteForkedThreads(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    // This function is called after fork
-    // We need to cleanup some of the thread data that is dead
-    for (auto &DeadThread : CTX->Threads) {
-      if (DeadThread == Thread) {
-        continue;
-      }
+  void DestroyThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
+    CTX->DestroyThread(Thread);
+  }
 
-      // Setting running to false ensures that when they are shutdown we won't send signals to kill them
-      DeadThread->State.RunningEvents.Running = false;
-    }
-
-    // We now only have one thread
-    CTX->IdleWaitRefCount = 1;
+  void CleanupAfterFork(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
+    CTX->CleanupAfterFork(Thread);
   }
 
   void SetSignalDelegator(FEXCore::Context::Context *CTX, FEXCore::SignalDelegator *SignalDelegation) {
@@ -147,16 +158,32 @@ namespace FEXCore::Context {
     CTX->SyscallHandler = Handler;
   }
 
-  FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, [[maybe_unused]] uint32_t Leaf) {
-    return CTX->CPUID.RunFunction(Function);
+  FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf) {
+    return CTX->CPUID.RunFunction(Function, Leaf);
   }
 
-  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::istream>(const std::string&)> CacheReader) {
-    CTX->AOTIRLoader = CacheReader;
+  FEX_DEFAULT_VISIBILITY FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf, uint32_t CPU) {
+    return CTX->CPUID.RunFunctionName(Function, Leaf, CPU);
   }
 
-  bool WriteAOTIR(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ostream>(const std::string&)> CacheWriter) {
-    return CTX->WriteAOTIRCache(CacheWriter);
+  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<int(const std::string&)> CacheReader) {
+    CTX->SetAOTIRLoader(CacheReader);
+  }
+
+  void SetAOTIRWriter(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) {
+    CTX->SetAOTIRWriter(CacheWriter);
+  }
+
+  void SetAOTIRRenamer(FEXCore::Context::Context *CTX, std::function<void(const std::string&)> CacheRenamer) {
+    CTX->SetAOTIRRenamer(CacheRenamer);
+  }
+
+  void FinalizeAOTIRCache(FEXCore::Context::Context *CTX) {
+    CTX->FinalizeAOTIRCache();
+  }
+
+  void WriteFilesWithCode(FEXCore::Context::Context *CTX, std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
+    CTX->WriteFilesWithCode(Writer);
   }
 
   void AddNamedRegion(FEXCore::Context::Context *CTX, uintptr_t Base, uintptr_t Length, uintptr_t Offset, const std::string& Name) {
@@ -178,10 +205,6 @@ namespace Debug {
     return CTX->GetRuntimeStatsForThread(Thread);
   }
 
-  FEXCore::Core::CPUState GetCPUState(FEXCore::Context::Context *CTX) {
-    return CTX->GetCPUState();
-  }
-
   bool GetDebugDataForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::Core::DebugData *Data) {
     return CTX->GetDebugDataForRIP(RIP, Data);
   }
@@ -198,10 +221,6 @@ namespace Debug {
   // void SetIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir) {
   //   CTX->SetIRForRIP(RIP, ir);
   // }
-
-  FEXCore::Core::ThreadState *GetThreadState(FEXCore::Context::Context *CTX) {
-    return CTX->GetThreadState();
-  }
 }
 
 }

External/FEXCore/Source/Interface/Context/Context.h

@@ -1,42 +1,50 @@
 #pragma once
+
 #include "Common/JitSymbols.h"
 #include "Interface/Core/CPUID.h"
-#include "Interface/Core/Frontend.h"
 #include "Interface/Core/HostFeatures.h"
-#include "Interface/Core/InternalThreadState.h"
 #include "Interface/Core/X86HelperGen.h"
-#include "Interface/IR/PassManager.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
+#include "Interface/IR/AOTIR.h"
 #include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Core/Context.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/SignalDelegator.h>
+#include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/Event.h>
 #include <stdint.h>
 
-#include <memory>
-#include <map>
-#include <unordered_map>
-#include <set>
-#include <mutex>
-#include <istream>
-#include <ostream>
+
+#include <atomic>
+#include <condition_variable>
 #include <functional>
+#include <istream>
+#include <map>
+#include <memory>
+#include <mutex>
+#include <shared_mutex>
+#include <stddef.h>
+#include <string>
+#include <unordered_map>
+#include <queue>
+#include <vector>
 
 namespace FEXCore {
+class CodeLoader;
 class ThunkHandler;
-class BlockSamplingData;
 class GdbServer;
-class SiganlDelegator;
 
 namespace CPU {
-  class JITCore;
+  class Arm64JITCore;
+  class X86JITCore;
 }
 namespace HLE {
+struct SyscallArguments;
 class SyscallHandler;
 }
 }
 
 namespace FEXCore::IR {
-  class RegisterAllocationPass;
   class RegisterAllocationData;
   class IRListView;
 namespace Validation {
@@ -52,37 +60,47 @@ namespace FEXCore::Context {
 
   struct Context {
     friend class FEXCore::HLE::SyscallHandler;
-    friend class FEXCore::CPU::JITCore;
+  #ifdef JIT_ARM64
+    friend class FEXCore::CPU::Arm64JITCore;
+  #endif
+  #ifdef JIT_X86_64
+    friend class FEXCore::CPU::X86JITCore;
+  #endif
+
     friend class FEXCore::IR::Validation::IRValidation;
 
     struct {
-      bool Multiblock {false};
-      bool BreakOnFrontendFailure {true};
-      int64_t MaxInstPerBlock {-1LL};
-      uint64_t VirtualMemSize {1ULL << 36};
       CoreRunningMode RunningMode {CoreRunningMode::MODE_RUN};
-      FEXCore::Config::ConfigCore Core {FEXCore::Config::CONFIG_INTERPRETER};
-      bool GdbServer {false};
-      std::string RootFSPath;
-      std::string ThunkLibsPath;
-
-      bool Is64BitMode {true};
-      bool TSOEnabled {true};
-      FEXCore::Config::ConfigSMCChecks SMCChecks {FEXCore::Config::CONFIG_SMC_MMAN};
-      bool ABILocalFlags {false};
-      bool ABINoPF {false};
-
-      bool AOTIRCapture {false};
-      bool AOTIRLoad {false};
-
-      std::string DumpIR;
+      uint64_t VirtualMemSize{1ULL << 36};
 
       // this is for internal use
       bool ValidateIRarser { false };
 
+      FEX_CONFIG_OPT(Multiblock, MULTIBLOCK);
+      FEX_CONFIG_OPT(SingleStepConfig, SINGLESTEP);
+      FEX_CONFIG_OPT(GdbServer, GDBSERVER);
+      FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
+      FEX_CONFIG_OPT(TSOEnabled, TSOENABLED);
+      FEX_CONFIG_OPT(ABILocalFlags, ABILOCALFLAGS);
+      FEX_CONFIG_OPT(ABINoPF, ABINOPF);
+      FEX_CONFIG_OPT(AOTIRCapture, AOTIRCAPTURE);
+      FEX_CONFIG_OPT(AOTIRGenerate, AOTIRGENERATE);
+      FEX_CONFIG_OPT(AOTIRLoad, AOTIRLOAD);
+      FEX_CONFIG_OPT(SMCChecks, SMCCHECKS);
+      FEX_CONFIG_OPT(Core, CORE);
+      FEX_CONFIG_OPT(MaxInstPerBlock, MAXINST);
+      FEX_CONFIG_OPT(RootFSPath, ROOTFS);
+      FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
+      FEX_CONFIG_OPT(ThunkConfigFile, THUNKCONFIG);
+      FEX_CONFIG_OPT(DumpIR, DUMPIR);
+      FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
+      FEX_CONFIG_OPT(GlobalJITNaming, GLOBALJITNAMING);
+      FEX_CONFIG_OPT(LibraryJITNaming, LIBRARYJITNAMING);
+      FEX_CONFIG_OPT(BlockJITNaming, BLOCKJITNAMING);
+      FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
     } Config;
 
-    using IntCallbackReturn =  __attribute__((naked)) void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
+    using IntCallbackReturn =  FEX_NAKED void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
     IntCallbackReturn InterpreterCallbackReturn;
 
     FEXCore::HostFeatures HostFeatures;
@@ -105,30 +123,7 @@ namespace FEXCore::Context {
     std::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
 
     CustomCPUFactoryType CustomCPUFactory;
-    CustomCPUFactoryType FallbackCPUFactory;
-    std::function<void(uint64_t ThreadId, FEXCore::Context::ExitReason)> CustomExitHandler;
-
-    struct AOTIRCacheEntry {
-      uint64_t start;
-      uint64_t len;
-      uint64_t crc;
-      IR::IRListView *IR;
-      IR::RegisterAllocationData *RAData;
-    };
-
-    std::function<std::unique_ptr<std::istream>(const std::string&)> AOTIRLoader;
-    std::unordered_map<std::string, std::map<uint64_t, AOTIRCacheEntry>> AOTIRCache;
-
-    struct AddrToFileEntry {
-      uint64_t Start;
-      uint64_t Len;
-      uint64_t Offset;
-      std::string fileid;
-      void *CachedFileEntry;
-    };
-
-    std::map<uint64_t, AddrToFileEntry> AddrToFile;
-
+    FEXCore::Context::ExitHandler CustomExitHandler;
 
 #ifdef BLOCKSTATS
     std::unique_ptr<FEXCore::BlockSamplingData> BlockData;
@@ -140,9 +135,9 @@ namespace FEXCore::Context {
     Context();
     ~Context();
 
-    bool InitCore(FEXCore::CodeLoader *Loader);
+    FEXCore::Core::InternalThreadState* InitCore(FEXCore::CodeLoader *Loader);
     FEXCore::Context::ExitReason RunUntilExit();
-    int GetProgramStatus();
+    int GetProgramStatus() const;
     bool IsPaused() const { return !Running; }
     void Pause();
     void Run();
@@ -153,79 +148,185 @@ namespace FEXCore::Context {
     void StopThread(FEXCore::Core::InternalThreadState *Thread);
     void SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event);
 
-    bool GetGdbServerStatus() { return (bool)DebugServer; }
+    bool GetGdbServerStatus() const { return DebugServer != nullptr; }
     void StartGdbServer();
     void StopGdbServer();
-    void HandleCallback(uint64_t RIP);
-    void RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func);
-    void RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func);
+    void HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
+    void RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
+    void RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
 
     static void RemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
 
+    // Wrapper which takes CpuStateFrame instead of InternalThreadState
+    static void RemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
+      RemoveCodeEntry(Frame->Thread, GuestRIP);
+    }
+
     // Debugger interface
     void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
     uint64_t GetThreadCount() const;
     FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(uint64_t Thread);
-    FEXCore::Core::CPUState GetCPUState();
     bool GetDebugDataForRIP(uint64_t RIP, FEXCore::Core::DebugData *Data);
     bool FindHostCodeForRIP(uint64_t RIP, uint8_t **Code);
 
-    // XXX:
-    // bool FindIRForRIP(uint64_t RIP, FEXCore::IR::IntrusiveIRList **ir);
-    // void SetIRForRIP(uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir);
-    FEXCore::Core::ThreadState *GetThreadState();
-    void LoadEntryList();
+    struct GenerateIRResult {
+      FEXCore::IR::IRListView* IRList;
+      // User's responsibility to deallocate this.
+      FEXCore::IR::RegisterAllocationData* RAData;
+      uint64_t TotalInstructions;
+      uint64_t TotalInstructionsLength;
+      uint64_t StartAddr;
+      uint64_t Length;
+    };
+    [[nodiscard]] GenerateIRResult GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
 
-    std::tuple<FEXCore::IR::IRListView *, FEXCore::IR::RegisterAllocationData *, uint64_t, uint64_t, uint64_t, uint64_t> GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    struct CompileCodeResult {
+      void* CompiledCode;
+      FEXCore::IR::IRListView* IRData;
+      FEXCore::Core::DebugData* DebugData;
+      // User's responsibility to deallocate this.
+      FEXCore::IR::RegisterAllocationData* RAData;
+      bool GeneratedIR;
+      uint64_t StartAddr;
+      uint64_t Length;
+    };
+    [[nodiscard]] CompileCodeResult CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    uintptr_t CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
 
-    std::tuple<void *, FEXCore::IR::IRListView *, FEXCore::Core::DebugData *, FEXCore::IR::RegisterAllocationData *, bool, uint64_t, uint64_t> CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-    uintptr_t CompileBlock(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    // same as CompileBlock, but aborts on failure
+    void CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
 
-    bool LoadAOTIRCache(std::istream &stream);
-    bool WriteAOTIRCache(std::function<std::unique_ptr<std::ostream>(const std::string&)> CacheWriter);
-    // Used for thread creation from syscalls
+    /**
+     * @brief Initializes the JIT compilers for the thread
+     *
+     * @param State The internal FEX thread state object
+     * @param CompileThread Is this for the compile service or not?
+     *
+     * InitializeCompiler is called inside of CreateThread, so you likely don't need this
+     * This is exposed because the CompileService needs to initialize compilers while copying data from
+     * the paired InternalThreadState that it is compiling code for
+     */
     void InitializeCompiler(FEXCore::Core::InternalThreadState* State, bool CompileThread);
+
+    // Used for thread creation from syscalls
+    /**
+     * @brief Used to create FEX thread objects in preparation for creating a true OS thread
+     *
+     * @param NewThreadState The initial thread state to setup for our state
+     * @param ParentTID The PID that was the parent thread that created this
+     *
+     * @return The InternalThreadState object that tracks all of the emulated thread's state
+     *
+     * Usecases:
+     *  OS thread Creation:
+     *    - Thread = CreateThread(NewState, PPID);
+     *    - InitializeThread(Thread);
+     *  OS fork (New thread created with a clone of thread state):
+     *    - clone{2, 3}
+     *    - Thread = CreateThread(CopyOfThreadState, PPID);
+     *    - ExecutionThread(Thread); // Starts executing without creating another host thread
+     *  Thunk callback executing guest code from native host thread
+     *    - Thread = CreateThread(NewState, PPID);
+     *    - InitializeThreadTLSData(Thread);
+     *    - HandleCallback(Thread, RIP);
+     */
     FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID);
-    void InitializeThreadData(FEXCore::Core::InternalThreadState *Thread);
+
+    /**
+     * @brief Initializes the TLS data for a thread
+     *
+     * @param Thread The internal FEX thread state object
+     */
+    void InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread);
+
+    /**
+     * @brief Initializes the OS thread object and prepares to start executing on that new OS thread
+     *
+     * @param Thread The internal FEX thread state object
+     *
+     * The OS thread will wait until RunThread is executed
+     */
     void InitializeThread(FEXCore::Core::InternalThreadState *Thread);
-    void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread);
+
+    /**
+     * @brief Starts the OS thread object to start executing guest code
+     *
+     * @param Thread The internal FEX thread state object
+     */
     void RunThread(FEXCore::Core::InternalThreadState *Thread);
 
-    std::vector<FEXCore::Core::InternalThreadState*> *const GetThreads() { return &Threads; }
+    /**
+     * @brief Destroys this FEX thread object and stops tracking it internally
+     *
+     * @param Thread The internal FEX thread state object
+     */
+    void DestroyThread(FEXCore::Core::InternalThreadState *Thread);
+    void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread);
+
+    void CleanupAfterFork(FEXCore::Core::InternalThreadState *ExceptForThread);
+
+    std::vector<FEXCore::Core::InternalThreadState*>* GetThreads() { return &Threads; }
+
+    uint8_t GetGPRSize() const { return Config.Is64BitMode ? 8 : 4; }
 
     void AddNamedRegion(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const std::string &filename);
     void RemoveNamedRegion(uintptr_t Base, uintptr_t Size);
 
-#if ENABLE_JITSYMBOLS
     FEXCore::JITSymbols Symbols;
-#endif
+
+    // Public for threading
+    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);
+
+    void FinalizeAOTIRCache() {
+      IRCaptureCache.FinalizeAOTIRCache();
+    }
+
+    void WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
+      IRCaptureCache.WriteFilesWithCode(Writer);
+    }
+
+    void SetAOTIRLoader(std::function<int(const std::string&)> CacheReader) {
+      IRCaptureCache.SetAOTIRLoader(CacheReader);
+    }
+
+    void SetAOTIRWriter(std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) {
+      IRCaptureCache.SetAOTIRWriter(CacheWriter);
+    }
+
+    void SetAOTIRRenamer(std::function<void(const std::string&)> CacheRenamer) {
+      IRCaptureCache.SetAOTIRRenamer(CacheRenamer);
+    }
 
   protected:
     void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread, bool AlsoClearIRCache);
 
   private:
+    /**
+     * @brief Does some final thread initialization
+     *
+     * @param Thread The internal FEX thread state object
+     *
+     * InitCore and CreateThread both call this to finish up thread object initialization
+     */
+    void InitializeThreadData(FEXCore::Core::InternalThreadState *Thread);
+
     void WaitForIdleWithTimeout();
 
-    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);
     void NotifyPause();
 
     void AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr, uint64_t Start, uint64_t Length);
-
     FEXCore::CodeLoader *LocalLoader{};
 
     // Entry Cache
-    bool GetFilenameHash(std::string const &Filename, std::string &Hash);
-    void AddThreadRIPsToEntryList(FEXCore::Core::InternalThreadState *Thread);
-    void SaveEntryList();
-    std::set<uint64_t> EntryList;
-    std::vector<uint64_t> InitLocations;
     uint64_t StartingRIP;
     std::mutex ExitMutex;
     std::unique_ptr<GdbServer> DebugServer;
 
+    IR::AOTIRCaptureCache IRCaptureCache;
+
     bool StartPaused = false;
-    FEXCore::Config::Value<std::string> AppFilename{FEXCore::Config::CONFIG_APP_FILENAME, ""};
+    FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
   };
 
-  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::InternalThreadState *Thread, FEXCore::HLE::SyscallArguments *Args);
+  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args);
 }

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64.h

@@ -12,6 +12,45 @@ namespace FEXCore::ArchHelpers::Arm64 {
   constexpr uint32_t ATOMIC_MEM_MASK = 0x3B200C00;
   constexpr uint32_t ATOMIC_MEM_INST = 0x38200000;
 
+  constexpr uint32_t LDAXP_MASK = 0xBF'FF'80'00;
+  constexpr uint32_t LDAXP_INST = 0x88'7F'80'00;
+
+  constexpr uint32_t STLXP_MASK = 0xBF'E0'80'00;
+  constexpr uint32_t STLXP_INST = 0x88'20'80'00;
+
+  constexpr uint32_t LDAXR_MASK = 0x3F'FF'FC'00;
+  constexpr uint32_t LDAXR_INST = 0x08'5F'FC'00;
+
+  constexpr uint32_t STLXR_MASK = 0x3F'E0'FC'00;
+  constexpr uint32_t STLXR_INST = 0x08'00'FC'00;
+
+  constexpr uint32_t CBNZ_MASK = 0x7F'00'00'00;
+  constexpr uint32_t CBNZ_INST = 0x35'00'00'00;
+
+  constexpr uint32_t ALU_OP_MASK = 0x7F'00'00'00;
+  constexpr uint32_t ADD_INST    = 0x0B'00'00'00;
+  constexpr uint32_t SUB_INST    = 0x4B'00'00'00;
+  constexpr uint32_t CMP_INST    = 0x6B'00'00'00;
+  constexpr uint32_t AND_INST    = 0x0A'00'00'00;
+  constexpr uint32_t OR_INST     = 0x2A'00'00'00;
+  constexpr uint32_t EOR_INST    = 0x4A'00'00'00;
+
+  constexpr uint32_t CCMP_MASK   = 0x7F'E0'0C'10;
+  constexpr uint32_t CCMP_INST   = 0x7A'40'00'00;
+
+  constexpr uint32_t CLREX_MASK = 0xFF'FF'F0'FF;
+  constexpr uint32_t CLREX_INST = 0xD5'03'30'5F;
+
+  enum ExclusiveAtomicPairType {
+    TYPE_SWAP,
+    TYPE_ADD,
+    TYPE_SUB,
+    TYPE_AND,
+    TYPE_OR,
+    TYPE_EOR,
+    TYPE_NEG, // This is just a sub with zero. Need to know the differences
+  };
+
   // Load ops are 4 bits
   // Acquire and release bits are independent on the instruction
   constexpr uint32_t ATOMIC_ADD_OP  = 0b0000;
@@ -24,7 +63,34 @@ namespace FEXCore::ArchHelpers::Arm64 {
   constexpr uint32_t ATOMIC_UMIN_OP = 0b0111;
   constexpr uint32_t ATOMIC_SWAP_OP = 0b1000;
 
-  bool HandleCASPAL(void *_mcontext, void *_info, uint32_t Instr);
-  bool HandleCASAL(void *_mcontext, void *_info, uint32_t Instr);
-  bool HandleAtomicMemOp(void *_mcontext, void *_info, uint32_t Instr);
+  constexpr uint32_t REGISTER_MASK = 0b11111;
+  constexpr uint32_t RD_OFFSET = 0;
+  constexpr uint32_t RN_OFFSET = 5;
+  constexpr uint32_t RM_OFFSET = 16;
+
+  constexpr uint32_t DMB = 0b1101'0101'0000'0011'0011'0000'1011'1111 |
+    0b1011'0000'0000; // Inner shareable all
+
+  inline uint32_t GetRdReg(uint32_t Instr) {
+    return (Instr >> RD_OFFSET) & REGISTER_MASK;
+  }
+
+  inline uint32_t GetRnReg(uint32_t Instr) {
+    return (Instr >> RN_OFFSET) & REGISTER_MASK;
+  }
+
+  inline uint32_t GetRmReg(uint32_t Instr) {
+    return (Instr >> RM_OFFSET) & REGISTER_MASK;
+  }
+
+  bool HandleAtomicLoad(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicStore(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicLoad128(void *_ucontext, void *_info, uint32_t Instr);
+  uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info);
+  bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr);
+  uint64_t HandleCASPAL_ARMv8(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicVectorStore(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleCASAL(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr);
+  [[nodiscard]] bool HandleSIGBUS(bool ParanoidTSO, int Signal, void *info, void *ucontext);
 }

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -0,0 +1,247 @@
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Context/Context.h"
+
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/MathUtils.h>
+
+#include "aarch64/cpu-aarch64.h"
+#include "cpu-features.h"
+#include "aarch64/instructions-aarch64.h"
+#include "utils-vixl.h"
+
+#include <tuple>
+
+namespace FEXCore::CPU {
+#define STATE x28
+
+// We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
+Arm64Emitter::Arm64Emitter(FEXCore::Context::Context *ctx, size_t size) : vixl::aarch64::Assembler(size, vixl::aarch64::PositionDependentCode) {
+  CPU.SetUp();
+
+  auto Features = vixl::CPUFeatures::InferFromOS();
+  if (ctx->HostFeatures.SupportsAtomics) {
+    // Hypervisor can hide this on the c630?
+    Features.Combine(vixl::CPUFeatures::Feature::kLORegions);
+  }
+
+  SetCPUFeatures(Features);
+}
+
+void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant) {
+  bool Is64Bit = Reg.IsX();
+  int Segments = Is64Bit ? 4 : 2;
+
+  if (Is64Bit && ((~Constant)>> 16) == 0) {
+    movn(Reg, (~Constant) & 0xFFFF);
+    return;
+  }
+
+  movz(Reg, (Constant) & 0xFFFF, 0);
+  for (int i = 1; i < Segments; ++i) {
+    uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
+    if (Part) {
+      movk(Reg, Part, i * 16);
+    }
+  }
+}
+
+void Arm64Emitter::PushCalleeSavedRegisters() {
+  // We need to save pairs of registers
+  // We save r19-r30
+  MemOperand PairOffset(sp, -16, PreIndex);
+  const std::array<std::pair<vixl::aarch64::Register, vixl::aarch64::Register>, 6> CalleeSaved = {{
+    {x19, x20},
+    {x21, x22},
+    {x23, x24},
+    {x25, x26},
+    {x27, x28},
+    {x29, x30},
+  }};
+
+  for (auto &RegPair : CalleeSaved) {
+    stp(RegPair.first, RegPair.second, PairOffset);
+  }
+
+  // Additionally we need to store the lower 64bits of v8-v15
+  // Here's a fun thing, we can use two ST4 instructions to store everything
+  // We just need a single sub to sp before that
+  const std::array<
+    std::tuple<vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister>, 2> FPRs = {{
+    {v8, v9, v10, v11},
+    {v12, v13, v14, v15},
+  }};
+
+  uint32_t VectorSaveSize = sizeof(uint64_t) * 8;
+  sub(sp, sp, VectorSaveSize);
+  // SP supporting move
+  // We just saved x19 so it is safe
+  add(x19, sp, 0);
+
+  MemOperand QuadOffset(x19, 32, PostIndex);
+  for (auto &RegQuad : FPRs) {
+    st4(std::get<0>(RegQuad).D(),
+        std::get<1>(RegQuad).D(),
+        std::get<2>(RegQuad).D(),
+        std::get<3>(RegQuad).D(),
+        0,
+        QuadOffset);
+  }
+}
+
+void Arm64Emitter::PopCalleeSavedRegisters() {
+  const std::array<
+    std::tuple<vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister>, 2> FPRs = {{
+    {v12, v13, v14, v15},
+    {v8, v9, v10, v11},
+  }};
+
+  MemOperand QuadOffset(sp, 32, PostIndex);
+  for (auto &RegQuad : FPRs) {
+    ld4(std::get<0>(RegQuad).D(),
+        std::get<1>(RegQuad).D(),
+        std::get<2>(RegQuad).D(),
+        std::get<3>(RegQuad).D(),
+        0,
+        QuadOffset);
+  }
+
+  MemOperand PairOffset(sp, 16, PostIndex);
+  const std::array<std::pair<vixl::aarch64::Register, vixl::aarch64::Register>, 6> CalleeSaved = {{
+    {x29, x30},
+    {x27, x28},
+    {x25, x26},
+    {x23, x24},
+    {x21, x22},
+    {x19, x20},
+  }};
+
+  for (auto &RegPair : CalleeSaved) {
+    ldp(RegPair.first, RegPair.second, PairOffset);
+  }
+}
+
+
+void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t SpillMask) {
+  if (StaticRegisterAllocation()) {
+    for (size_t i = 0; i < SRA64.size(); i+=2) {
+      auto Reg1 = SRA64[i];
+      auto Reg2 = SRA64[i+1];
+      if (((1U << Reg1.GetCode()) & SpillMask) &&
+          ((1U << Reg2.GetCode()) & SpillMask)) {
+        stp(Reg1, Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      }
+      else if (((1U << Reg1.GetCode()) & SpillMask)) {
+        str(Reg1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      }
+      else if (((1U << Reg2.GetCode()) & SpillMask)) {
+        str(Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1])));
+      }
+    }
+
+    if (FPRs) {
+      for (size_t i = 0; i < SRAFPR.size(); i+=2) {
+        stp(SRAFPR[i].Q(), SRAFPR[i+1].Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+      }
+    }
+  }
+}
+
+void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t FillMask) {
+  if (StaticRegisterAllocation()) {
+    for (size_t i = 0; i < SRA64.size(); i+=2) {
+      auto Reg1 = SRA64[i];
+      auto Reg2 = SRA64[i+1];
+      if (((1U << Reg1.GetCode()) & FillMask) &&
+          ((1U << Reg2.GetCode()) & FillMask)) {
+        ldp(Reg1, Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      }
+      else if (((1U << Reg1.GetCode()) & FillMask)) {
+        ldr(Reg1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      }
+      else if (((1U << Reg2.GetCode()) & FillMask)) {
+        ldr(Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1])));
+      }
+    }
+
+    if (FPRs) {
+      for (size_t i = 0; i < SRAFPR.size(); i+=2) {
+        ldp(SRAFPR[i].Q(), SRAFPR[i+1].Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+      }
+    }
+  }
+}
+
+void Arm64Emitter::PushDynamicRegsAndLR() {
+  uint64_t SPOffset = AlignUp((RA64.size() + 1) * 8 + RAFPR.size() * 16, 16);
+
+  sub(sp, sp, SPOffset);
+  int i = 0;
+
+  for (auto RA : RAFPR)
+  {
+    str(RA.Q(), MemOperand(sp, i * 8));
+    i+=2;
+  }
+
+#if 0 // All GPRs should be caller saved
+  for (auto RA : RA64)
+  {
+    str(RA, MemOperand(sp, i * 8));
+    i++;
+  }
+#endif
+
+  str(lr, MemOperand(sp, i * 8));
+}
+
+void Arm64Emitter::PopDynamicRegsAndLR() {
+  uint64_t SPOffset = AlignUp((RA64.size() + 1) * 8 + RAFPR.size() * 16, 16);
+  int i = 0;
+
+  for (auto RA : RAFPR)
+  {
+    ldr(RA.Q(), MemOperand(sp, i * 8));
+    i+=2;
+  }
+
+#if 0 // All GPRs should be caller saved
+  for (auto RA : RA64)
+  {
+    ldr(RA, MemOperand(sp, i * 8));
+    i++;
+  }
+#endif
+
+  ldr(lr, MemOperand(sp, i * 8));
+
+  add(sp, sp, SPOffset);
+}
+
+void Arm64Emitter::ResetStack() {
+  if (SpillSlots == 0)
+    return;
+
+  if (IsImmAddSub(SpillSlots * 16)) {
+    add(sp, sp, SpillSlots * 16);
+  } else {
+   // Too big to fit in a 12bit immediate
+   LoadConstant(x0, SpillSlots * 16);
+   add(sp, sp, x0);
+  }
+}
+
+void Arm64Emitter::Align16B() {
+  uint64_t CurrentOffset = GetCursorAddress<uint64_t>();
+  for (uint64_t i = (16 - (CurrentOffset & 0xF)); i != 0; i -= 4) {
+      nop();
+  }
+}
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h

@@ -0,0 +1,82 @@
+#pragma once
+
+#include "aarch64/assembler-aarch64.h"
+#include "aarch64/constants-aarch64.h"
+#include "aarch64/cpu-aarch64.h"
+#include "aarch64/operands-aarch64.h"
+#include "platform-vixl.h"
+#include "FEXCore/Config/Config.h"
+
+#include <array>
+#include <stddef.h>
+#include <stdint.h>
+#include <utility>
+
+namespace FEXCore::CPU {
+using namespace vixl;
+using namespace vixl::aarch64;
+
+// All but x29 are caller saved
+const std::array<aarch64::Register, 16> SRA64 = {
+  x4, x5, x6, x7, x8, x9, x10, x11,
+  x12, x18, x17, x16, x15, x14, x13, x29
+};
+
+// All are callee saved
+const std::array<aarch64::Register, 9> RA64 = {
+  x20, x21, x22, x23, x24, x25, x26, x27,
+  x19
+};
+
+const std::array<std::pair<aarch64::Register, aarch64::Register>, 4>  RA64Pair = {{
+  {x20, x21},
+  {x22, x23},
+  {x24, x25},
+  {x26, x27},
+}};
+
+const std::array<std::pair<aarch64::Register, aarch64::Register>, 4> RA32Pair = {{
+  {w20, w21},
+  {w22, w23},
+  {w24, w25},
+  {w26, w27},
+}};
+
+// All are caller saved
+const std::array<aarch64::VRegister, 16> SRAFPR = {
+  v16, v17, v18, v19, v20, v21, v22, v23,
+  v24, v25, v26, v27, v28, v29, v30, v31
+};
+
+//  v8..v15 = (lower 64bits) Callee saved
+const std::array<aarch64::VRegister, 12> RAFPR = {
+/*v0,  v1,  v2,  v3,*/v4,  v5,  v6,  v7,  // v0 ~ v3 are used as temps
+  v8,  v9,  v10, v11, v12, v13, v14, v15
+};
+
+// This class contains common emitter utility functions that can
+// be used by both Arm64 JIT and ARM64 Dispatcher
+class Arm64Emitter : public vixl::aarch64::Assembler {
+protected:
+  Arm64Emitter(FEXCore::Context::Context *ctx, size_t size);
+
+  vixl::aarch64::CPU CPU;
+  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
+  void SpillStaticRegs(bool FPRs = true, uint32_t SpillMask = ~0U);
+  void FillStaticRegs(bool FPRs = true, uint32_t FillMask = ~0U);
+
+  void PushDynamicRegsAndLR();
+  void PopDynamicRegsAndLR();
+
+  void PushCalleeSavedRegisters();
+  void PopCalleeSavedRegisters();
+
+  void ResetStack();
+  void Align16B();
+
+  uint32_t SpillSlots{};
+
+  FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
+};
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64_stubs.cpp

@@ -0,0 +1,27 @@
+#include "Interface/Core/ArchHelpers/Arm64.h"
+
+#include <FEXCore/Utils/LogManager.h>
+#include <stdint.h>
+
+namespace FEXCore::ArchHelpers::Arm64 {
+
+#ifndef _M_ARM_64
+// These are stub implementations that exist only to allow instantiating the arm64 jit
+// on non arm platforms.
+
+// Obvously such a configuration can't do the actual arm64-specific stuff
+
+bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE_FMT("HandleCASPAL Not Implemented");
+}
+
+bool HandleCASAL(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE_FMT("HandleCASAL Not Implemented");
+}
+
+bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE_FMT("HandleAtomicMemOp Not Implemented");
+}
+#endif
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/MContext.h

@@ -0,0 +1,267 @@
+#pragma once
+
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/UContext.h>
+
+#include <signal.h>
+#include <string.h>
+#include <ucontext.h>
+#include <stdint.h>
+#include <type_traits>
+
+
+namespace FEXCore::ArchHelpers::Context {
+
+enum ContextFlags : uint32_t {
+  CONTEXT_FLAG_INJIT = (1U << 0),
+  CONTEXT_FLAG_32BIT = (1U << 1),
+};
+
+struct X86ContextBackup {
+  // Host State
+  // RIP and RSP is stored in GPRs here
+  uint64_t GPRs[23];
+  FEXCore::x86_64::_libc_fpstate FPRState;
+  uint64_t sa_mask;
+  bool FaultToTopAndGeneratedException;
+
+  // Guest state
+  int Signal;
+  uint32_t Flags;
+  uint64_t OriginalRIP;
+  uint64_t FPStateLocation;
+  uint64_t UContextLocation;
+  uint64_t SigInfoLocation;
+  FEXCore::Core::CPUState GuestState;
+  static constexpr int RedZoneSize = 128;
+};
+
+struct ArmContextBackup {
+  // Host State
+  uint64_t GPRs[31];
+  uint64_t PrevSP;
+  uint64_t PrevPC;
+  uint64_t PState;
+  uint32_t FPSR;
+  uint32_t FPCR;
+  __uint128_t FPRs[32];
+  uint64_t sa_mask;
+  bool FaultToTopAndGeneratedException;
+
+  // Guest state
+  int Signal;
+  uint32_t Flags;
+  uint64_t OriginalRIP;
+  uint64_t FPStateLocation;
+  uint64_t UContextLocation;
+  uint64_t SigInfoLocation;
+  FEXCore::Core::CPUState GuestState;
+
+  // Arm64 doesn't have a red zone
+  static constexpr int RedZoneSize = 0;
+};
+
+static inline ucontext_t* GetUContext(void* ucontext) {
+  ucontext_t* _context = (ucontext_t*)ucontext;
+  return _context;
+}
+
+static inline mcontext_t* GetMContext(void* ucontext) {
+  ucontext_t* _context = (ucontext_t*)ucontext;
+  return &_context->uc_mcontext;
+}
+
+
+#ifdef _M_ARM_64
+
+constexpr uint32_t FPR_MAGIC = 0x46508001U;
+
+struct HostCTXHeader {
+  uint32_t Magic;
+  uint32_t Size;
+};
+
+struct HostFPRState {
+  HostCTXHeader Head;
+  uint32_t FPSR;
+  uint32_t FPCR;
+  __uint128_t FPRs[32];
+};
+
+static inline uint64_t GetSp(void* ucontext) {
+  return GetMContext(ucontext)->sp;
+}
+
+static inline uint64_t GetPc(void* ucontext) {
+  return GetMContext(ucontext)->pc;
+}
+
+static inline void SetSp(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->sp = val;
+}
+
+static inline void SetPc(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->pc = val;
+}
+
+static inline uint64_t GetState(void* ucontext) {
+  return GetMContext(ucontext)->regs[28];
+}
+
+static inline void SetState(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->regs[28] = val;
+}
+
+static inline uint64_t GetArmReg(void* ucontext, uint32_t id) {
+  return GetMContext(ucontext)->regs[id];
+}
+
+static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
+  GetMContext(ucontext)->regs[id] = val;
+}
+
+static inline __uint128_t GetArmFPR(void* ucontext, uint32_t id) {
+  auto MContext = GetMContext(ucontext);
+  HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&MContext->__reserved[0]);
+  LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
+
+  return HostState->FPRs[id];
+}
+
+using ContextBackup = ArmContextBackup;
+template <typename T>
+static inline void BackupContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, ArmContextBackup>::value) {
+    auto _ucontext = GetUContext(ucontext);
+    auto _mcontext = GetMContext(ucontext);
+
+    memcpy(&Backup->GPRs[0], &_mcontext->regs[0], 31 * sizeof(uint64_t));
+    Backup->PrevSP = ArchHelpers::Context::GetSp(ucontext);
+    Backup->PrevPC = ArchHelpers::Context::GetPc(ucontext);
+    Backup->PState = _mcontext->pstate;
+
+    // Host FPR state starts at _mcontext->reserved[0];
+    HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
+    LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
+    Backup->FPSR = HostState->FPSR;
+    Backup->FPCR = HostState->FPCR;
+    memcpy(&Backup->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t));
+
+    // Save the signal mask so we can restore it
+    memcpy(&Backup->sa_mask, &_ucontext->uc_sigmask, sizeof(uint64_t));
+  } else {
+    // This must be a runtime error
+    ERROR_AND_DIE_FMT("Wrong context type");
+  }
+}
+
+template <typename T>
+static inline void RestoreContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, ArmContextBackup>::value) {
+    auto _ucontext = GetUContext(ucontext);
+   auto _mcontext = GetMContext(ucontext);
+
+    HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
+    LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
+    memcpy(&HostState->FPRs[0], &Backup->FPRs[0], 32 * sizeof(__uint128_t));
+    HostState->FPCR = Backup->FPCR;
+    HostState->FPSR = Backup->FPSR;
+
+    // Restore GPRs and other state
+    _mcontext->pstate = Backup->PState;
+    ArchHelpers::Context::SetPc(ucontext, Backup->PrevPC);
+    ArchHelpers::Context::SetSp(ucontext, Backup->PrevSP);
+    memcpy(&_mcontext->regs[0], &Backup->GPRs[0], 31 * sizeof(uint64_t));
+
+    // Restore the signal mask now
+    memcpy(&_ucontext->uc_sigmask, &Backup->sa_mask, sizeof(uint64_t));
+  } else {
+    // This must be a runtime error
+    ERROR_AND_DIE_FMT("Wrong context type");
+  }
+}
+
+#endif
+
+#ifdef _M_X86_64
+
+static inline uint64_t GetSp(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_RSP];
+}
+
+static inline uint64_t GetPc(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_RIP];
+  }
+
+static inline void SetSp(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_RSP] = val;
+}
+
+static inline void SetPc(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_RIP] = val;
+}
+
+static inline uint64_t GetState(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_R14];
+}
+
+static inline void SetState(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_R14] = val;
+}
+
+static inline uint64_t GetArmReg(void* ucontext, uint32_t id) {
+  ERROR_AND_DIE_FMT("Not impelented for x86 host");
+}
+
+static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
+  ERROR_AND_DIE_FMT("Not impelented for x86 host");
+}
+
+static inline __uint128_t GetArmFPR(void* ucontext, uint32_t id) {
+  ERROR_AND_DIE_FMT("Not implemented for x86 host");
+}
+
+using ContextBackup = X86ContextBackup;
+template <typename T>
+static inline void BackupContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, X86ContextBackup>::value) {
+    auto _ucontext = GetUContext(ucontext);
+    auto _mcontext = GetMContext(ucontext);
+
+    // Copy the GPRs
+    memcpy(&Backup->GPRs[0], &_mcontext->gregs[0], sizeof(X86ContextBackup::GPRs));
+    // Copy the FPRState
+    memcpy(&Backup->FPRState, _mcontext->fpregs, sizeof(X86ContextBackup::FPRState));
+    // XXX: Save 256bit and 512bit AVX register state
+
+    // Save the signal mask so we can restore it
+    memcpy(&Backup->sa_mask, &_ucontext->uc_sigmask, sizeof(uint64_t));
+  } else {
+    // This must be a runtime error
+    ERROR_AND_DIE_FMT("Wrong context type");
+  }
+}
+
+template <typename T>
+static inline void RestoreContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, X86ContextBackup>::value) {
+    auto _ucontext = GetUContext(ucontext);
+    auto _mcontext = GetMContext(ucontext);
+
+    // Copy the GPRs
+    memcpy(&_mcontext->gregs[0], &Backup->GPRs[0], sizeof(X86ContextBackup::GPRs));
+    // Copy the FPRState
+    memcpy(_mcontext->fpregs, &Backup->FPRState, sizeof(X86ContextBackup::FPRState));
+
+    // Restore the signal mask now
+    memcpy(&_ucontext->uc_sigmask, &Backup->sa_mask, sizeof(uint64_t));
+  } else {
+    // This must be a runtime error
+    ERROR_AND_DIE_FMT("Wrong context type");
+  }
+}
+
+#endif
+
+} // namespace FEXCore::ArchHelpers::Context

External/FEXCore/Source/Interface/Core/BlockSamplingData.cpp

@@ -2,6 +2,7 @@
 #include <FEXCore/Utils/LogManager.h>
 #include <cstring>
 #include <fstream>
+#include <utility>
 
 namespace FEXCore {
   void BlockSamplingData::DumpBlockData() {
@@ -26,7 +27,7 @@ namespace FEXCore {
              << std::endl;
     }
     Output.close();
-    LogMan::Msg::D("Dumped %d blocks of sampling data", SamplingMap.size());
+    LogMan::Msg::DFmt("Dumped {} blocks of sampling data", SamplingMap.size());
   }
 
   BlockSamplingData::BlockData *BlockSamplingData::GetBlockData(uint64_t RIP) {

External/FEXCore/Source/Interface/Core/BlockSamplingData.h

@@ -1,6 +1,7 @@
 #pragma once
+
+#include <cstdint>
 #include <unordered_map>
-#include <stdint.h>
 
 namespace FEXCore {
 class BlockSamplingData {

External/FEXCore/Source/Interface/Core/CPUID.h

@@ -1,9 +1,11 @@
 #pragma once
-#include <functional>
+
+#include <cstdint>
 #include <unordered_map>
+#include <utility>
 
 #include <FEXCore/Core/CPUID.h>
-#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Config/Config.h>
 
 namespace FEXCore {
 namespace Context {
@@ -21,43 +23,81 @@ private:
   constexpr static uint32_t CPUID_VENDOR_AMD3 = 0x444D4163; // "cAMD"
 
 public:
+  // X86 cacheline size effectively has to be hardcoded to 64
+  // if we report anything differently then applications are likely to break
+  constexpr static uint64_t CACHELINE_SIZE = 64;
+
   void Init(FEXCore::Context::Context *ctx);
 
-  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function) {
-    auto Handler = FunctionHandlers.find(Function);
+  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, uint32_t Leaf) {
+    const auto Handler = FunctionHandlers.find(Function);
 
     if (Handler == FunctionHandlers.end()) {
-      #ifndef NDEBUG
-        LogMan::Msg::E("Unhandled CPU ID function, 0x%x", Function);
-      #endif
-      return Function_Reserved();
+      return Function_Reserved(Leaf);
     }
 
-    return Handler->second();
+    return (this->*Handler->second)(Leaf);
   }
+
+  FEXCore::CPUID::FunctionResults RunFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
+    if (Function == 0x8000'0002U)
+      return Function_8000_0002h(Leaf, CPU % PerCPUData.size());
+    else if (Function == 0x8000'0003U)
+      return Function_8000_0003h(Leaf, CPU % PerCPUData.size());
+    else
+      return Function_8000_0004h(Leaf, CPU % PerCPUData.size());
+  }
+
 private:
   FEXCore::Context::Context *CTX;
+  bool Hybrid{};
+  FEX_CONFIG_OPT(Cores, THREADS);
 
-  using FunctionHandler = std::function<FEXCore::CPUID::FunctionResults()>;
+  using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf);
   void RegisterFunction(uint32_t Function, FunctionHandler Handler) {
-    FunctionHandlers[Function] = Handler;
+    FunctionHandlers.insert_or_assign(Function, Handler);
   }
 
   std::unordered_map<uint32_t, FunctionHandler> FunctionHandlers;
+  struct CPUData {
+    const char *ProductName{};
+#ifdef _M_ARM_64
+    uint32_t MIDR{};
+#endif
+    bool IsBig{};
+  };
+  std::vector<CPUData> PerCPUData{};
 
   // Functions
-  FEXCore::CPUID::FunctionResults Function_0h();
-  FEXCore::CPUID::FunctionResults Function_01h();
-  FEXCore::CPUID::FunctionResults Function_02h();
-  FEXCore::CPUID::FunctionResults Function_06h();
-  FEXCore::CPUID::FunctionResults Function_07h();
-  FEXCore::CPUID::FunctionResults Function_8000_0000h();
-  FEXCore::CPUID::FunctionResults Function_8000_0001h();
-  FEXCore::CPUID::FunctionResults Function_8000_0002h();
-  FEXCore::CPUID::FunctionResults Function_8000_0003h();
-  FEXCore::CPUID::FunctionResults Function_8000_0004h();
-  FEXCore::CPUID::FunctionResults Function_8000_0007h();
+  FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_01h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_02h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_04h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_06h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_07h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_0Dh(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_15h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_1Ah(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0000h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0001h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf);
+
+  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf, uint32_t CPU);
+  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf, uint32_t CPU);
+  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf, uint32_t CPU);
+
+  FEXCore::CPUID::FunctionResults Function_8000_0005h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0006h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0007h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0008h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0009h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0019h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_001Dh(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_Reserved(uint32_t Leaf);
+
+  void SetupHostHybridFlag();
 
-  FEXCore::CPUID::FunctionResults Function_Reserved();
 };
 }

External/FEXCore/Source/Interface/Core/CompileService.cpp

@@ -1,10 +1,29 @@
 #include "Interface/Context/Context.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/CompileService.h"
-#include "Interface/Core/InternalThreadState.h"
 #include "Interface/Core/OpcodeDispatcher.h"
+#include "FEXCore/Debug/InternalThreadState.h"
+#include "FEXCore/HLE/Linux/ThreadManagement.h"
+#include "Interface/IR/PassManager.h"
+
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/SignalDelegator.h>
+#include <FEXCore/Utils/Event.h>
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/Threads.h>
+
+#include <memory>
+#include <pthread.h>
+#include <stdio.h>
 
 namespace FEXCore {
+  static void* ThreadHandler(void *Arg) {
+    FEXCore::CompileService *This = reinterpret_cast<FEXCore::CompileService*>(Arg);
+    This->ExecutionThread();
+    return nullptr;
+  }
+
   CompileService::CompileService(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
     : CTX {ctx}
     , ParentThread {Thread} {
@@ -16,9 +35,9 @@ namespace FEXCore {
     CTX->InitializeCompiler(CompileThreadData.get(), true);
     CompileThreadData->CPUBackend->CopyNecessaryDataForCompileThread(ParentThread->CPUBackend.get());
 
-    WorkerThread = std::thread([this]() {
-      ExecutionThread();
-    });
+    uint64_t OldMask = FEXCore::Threads::SetSignalMask(~0ULL);
+    WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
+    FEXCore::Threads::SetSignalMask(OldMask);
   }
 
   void CompileService::Initialize() {
@@ -30,7 +49,7 @@ namespace FEXCore {
     ShuttingDown = true;
     // Kick the working thread
     StartWork.NotifyAll();
-    WorkerThread.join();
+    WorkerThread->join(nullptr);
   }
 
   void CompileService::ClearCache(FEXCore::Core::InternalThreadState *Thread) {
@@ -41,23 +60,15 @@ namespace FEXCore {
       // Grab the work queue and clear it
       // We don't need to grab the queue mutex since this thread will no longer receive any work events
       // Threads are bounded 1:1
-      while (WorkQueue.size()) {
-        WorkItem *Item = WorkQueue.front();
+      while (!WorkQueue.empty()) {
         WorkQueue.pop();
-        delete Item;
       }
 
       // Go through the garbage collection array and clear it
       // It's safe to clear things that aren't marked safe since we are clearing cache
-      if (GCArray.size()) {
-        // Clean up our GC array
-        for (auto it = GCArray.begin(); it != GCArray.end();) {
-          delete *it;
-          it = GCArray.erase(it);
-        }
-      }
+      GCArray.clear();
 
-      LogMan::Throw::A(CompileThreadData->LocalIRCache.size() == 0, "Compile service must never have LocalIRCache");
+      LOGMAN_THROW_A_FMT(CompileThreadData->LocalIRCache.empty(), "Compile service must never have LocalIRCache");
 
       CompileMutex.unlock();
     }
@@ -68,31 +79,29 @@ namespace FEXCore {
     SelectedThread->CPUBackend->ClearCache();
   }
 
-
   CompileService::WorkItem *CompileService::CompileCode(uint64_t RIP) {
-    // Tell the worker thread to compile code for us
-    WorkItem *Item = new WorkItem{};
-    Item->RIP = RIP;
+    WorkItem* ResultItem = nullptr;
 
     {
+      // Tell the worker thread to compile code for us
+      auto Item = std::make_unique<WorkItem>();
+      Item->RIP = RIP;
+
       // Fill the threads work queue
-      std::scoped_lock<std::mutex> lk(QueueMutex);
-      WorkQueue.emplace(Item);
+      std::scoped_lock lk(QueueMutex);
+      ResultItem = WorkQueue.emplace(std::move(Item)).get();
     }
 
     // Notify the thread that it has more work
     StartWork.NotifyAll();
 
-    return Item;
+    return ResultItem;
   }
 
   void CompileService::ExecutionThread() {
-    // Ignore signals coming from the guest
-    CTX->SignalDelegation->MaskThreadSignals();
-
     // Set our thread name so we can see its relation
     char ThreadName[16]{};
-    snprintf(ThreadName, 16, "%ld-CS", ParentThread->State.ThreadManager.TID.load());
+    snprintf(ThreadName, 16, "%ld-CS", ParentThread->ThreadManager.TID.load());
     pthread_setname_np(pthread_self(), ThreadName);
 
     while (true) {
@@ -101,18 +110,18 @@ namespace FEXCore {
       if (ShuttingDown.load()) {
         break;
       }
-      std::scoped_lock<std::mutex> lk(CompileMutex);
 
+      std::scoped_lock lk(CompileMutex);
       size_t WorkItems{};
 
       do {
         // Grab a work item
-        WorkItem *Item{};
+        std::unique_ptr<WorkItem> Item{};
         {
-          std::scoped_lock<std::mutex> lk(QueueMutex);
+          std::scoped_lock lk(QueueMutex);
           WorkItems = WorkQueue.size();
-          if (WorkItems) {
-            Item = WorkQueue.front();
+          if (WorkItems != 0) {
+            Item = std::move(WorkQueue.front());
             WorkQueue.pop();
           }
         }
@@ -120,19 +129,19 @@ namespace FEXCore {
         // If we had a work item then work on it
         if (Item) {
           // Make sure it's not in lookup cache by accident
-          LogMan::Throw::A(CompileThreadData->LookupCache->FindBlock(Item->RIP) == 0, "Compile Service must never have entries in the LookupCache");
-          
+          LOGMAN_THROW_A_FMT(CompileThreadData->LookupCache->FindBlock(Item->RIP) == 0, "Compile Service must never have entries in the LookupCache");
+
           // Code isn't in cache, compile now
           // Set our thread state's RIP
-          CompileThreadData->State.State.rip = Item->RIP;
+          CompileThreadData->CurrentFrame->State.rip = Item->RIP;
 
           auto [CodePtr, IRList, DebugData, RAData, Generated, StartAddr, Length] = CTX->CompileCode(CompileThreadData.get(), Item->RIP);
 
-          LogMan::Throw::A(Generated == true, "Compile Service doesn't have IR Cache");
+          LOGMAN_THROW_A_FMT(Generated == true, "Compile Service doesn't have IR Cache");
 
           if (!CodePtr) {
             // XXX: We currently have the expectation that compile service code will be significantly smaller than regular thread's code
-            ERROR_AND_DIE("Couldn't compile code for thread at RIP: 0x%lx", Item->RIP);
+            ERROR_AND_DIE_FMT("Couldn't compile code for thread at RIP: 0x{:x}", Item->RIP);
           }
 
           Item->CodePtr = CodePtr;
@@ -142,23 +151,15 @@ namespace FEXCore {
           Item->StartAddr = StartAddr;
           Item->Length = Length;
 
-          GCArray.emplace_back(Item);
-          Item->ServiceWorkDone.NotifyAll();
+          auto& GCItem = GCArray.emplace_back(std::move(Item));
+          GCItem->ServiceWorkDone.NotifyAll();
         }
       } while (WorkItems != 0);
 
-      if (GCArray.size()) {
-        // Clean up our GC array
-        for (auto it = GCArray.begin(); it != GCArray.end();) {
-          if ((*it)->SafeToClear) {
-            delete *it;
-            it = GCArray.erase(it);
-          }
-          else {
-            ++it;
-          }
-        }
-      }
+      // Clean up any safe entries in our GC array if we have any.
+      std::erase_if(GCArray, [](const auto& Entry) {
+        return Entry->SafeToClear.load(std::memory_order_relaxed);
+      });
     }
   }
 }

External/FEXCore/Source/Interface/Core/CompileService.h

@@ -1,22 +1,22 @@
 #pragma once
 
-#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/Event.h>
+#include <FEXCore/Utils/Threads.h>
 
+#include <atomic>
 #include <memory>
-#include <thread>
-#include <unordered_map>
+#include <mutex>
 #include <queue>
+#include <stdint.h>
+#include <vector>
 
 namespace FEXCore {
 namespace Context {
   struct Context;
 }
-namespace Core {
-  struct InternalThreadState;
-}
-
 namespace IR {
+  class IRListView;
   class RegisterAllocationData;
 };
 class CompileService final {
@@ -45,18 +45,23 @@ class CompileService final {
     WorkItem *CompileCode(uint64_t RIP);
     void ClearCache(FEXCore::Core::InternalThreadState *Thread);
 
+    // Public for threading
+    void ExecutionThread();
+
+    bool IsAddressInJITCode(uint64_t Address) const {
+      return CompileThreadData->CPUBackend->IsAddressInJITCode(Address, false, false);
+    }
   private:
     FEXCore::Context::Context *CTX;
     FEXCore::Core::InternalThreadState *ParentThread;
 
-    void ExecutionThread();
-    std::thread WorkerThread;
+    std::unique_ptr<FEXCore::Threads::Thread> WorkerThread;
     std::unique_ptr<FEXCore::Core::InternalThreadState> CompileThreadData;
 
     std::mutex QueueMutex{};
     std::mutex CompileMutex{};
-    std::queue<WorkItem*> WorkQueue{};
-    std::vector<WorkItem*> GCArray{};
+    std::queue<std::unique_ptr<WorkItem>> WorkQueue{};
+    std::vector<std::unique_ptr<WorkItem>> GCArray{};
     Event StartWork{};
     std::atomic_bool ShuttingDown{false};
 };

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp

@@ -0,0 +1,497 @@
+#include "Interface/Core/LookupCache.h"
+
+#include "Interface/Core/ArchHelpers/MContext.h"
+#include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+
+#include "Interface/Context/Context.h"
+#include "Interface/Core/X86HelperGen.h"
+
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/X86Enums.h>
+#include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXHeaderUtils/Syscalls.h>
+
+#include <array>
+#include <bit>
+#include <cmath>
+#include <cstdint>
+#include <memory>
+#include <stddef.h>
+
+#include "aarch64/assembler-aarch64.h"
+#include "aarch64/constants-aarch64.h"
+#include "aarch64/operands-aarch64.h"
+#include "aarch64/cpu-aarch64.h"
+#include "code-buffer-vixl.h"
+#include "platform-vixl.h"
+
+#include <sys/syscall.h>
+#include <unistd.h>
+
+namespace FEXCore::CPU {
+
+using namespace vixl;
+using namespace vixl::aarch64;
+
+static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
+#define STATE x28
+
+Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config)
+  : Dispatcher(ctx, Thread), Arm64Emitter(ctx, MAX_DISPATCHER_CODE_SIZE) {
+  SRAEnabled = config.StaticRegisterAssignment;
+  SetAllowAssembler(true);
+
+  DispatchPtr = GetCursorAddress<CPUBackend::AsmDispatch>();
+
+  // while (true) {
+  //    Ptr = FindBlock(RIP)
+  //    if (!Ptr)
+  //      Ptr = CTX->CompileBlock(RIP);
+  //
+  //    Ptr();
+  // }
+
+  uint64_t VirtualMemorySize = Thread->LookupCache->GetVirtualMemorySize();
+  Literal l_VirtualMemory {VirtualMemorySize};
+  Literal l_PagePtr {Thread->LookupCache->GetPagePointer()};
+  Literal l_L1Ptr {Thread->LookupCache->GetL1Pointer()};
+  Literal l_CTX {reinterpret_cast<uintptr_t>(CTX)};
+  Literal l_Sleep {reinterpret_cast<uint64_t>(SleepThread)};
+  Literal l_CompileBlock {GetCompileBlockPtr()};
+  Literal l_ExitFunctionLink {config.ExitFunctionLink};
+  Literal l_ExitFunctionLinkThis {config.ExitFunctionLinkThis};
+
+  // Push all the register we need to save
+  PushCalleeSavedRegisters();
+
+  // Push our memory base to the correct register
+  // Move our thread pointer to the correct register
+  // This is passed in to parameter 0 (x0)
+  mov(STATE, x0);
+
+  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
+  // regardless of where we were in the stack
+  add(x0, sp, 0);
+  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)));
+
+  AbsoluteLoopTopAddressFillSRA = GetCursorAddress<uint64_t>();
+
+  if (SRAEnabled) {
+    FillStaticRegs();
+  }
+
+  // We want to ensure that we are 16 byte aligned at the top of this loop
+  Align16B();
+  aarch64::Label FullLookup{};
+  aarch64::Label CallBlock{};
+  aarch64::Label LoopTop{};
+  aarch64::Label ExitSpillSRA{};
+  aarch64::Label ThreadPauseHandler{};
+
+  bind(&LoopTop);
+  AbsoluteLoopTopAddress = GetLabelAddress<uint64_t>(&LoopTop);
+
+  // Load in our RIP
+  // Don't modify x2 since it contains our RIP once the block doesn't exist
+  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
+  auto RipReg = x2;
+
+  // L1 Cache
+  ldr(x0, &l_L1Ptr);
+
+  and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
+  add(x0, x0, Operand(x3, Shift::LSL, 4));
+  ldp(x3, x0, MemOperand(x0));
+  cmp(x0, RipReg);
+  b(&FullLookup, Condition::ne);
+
+  if (!config.ExecuteBlocksWithCall) {
+    br(x3);
+  } else {
+    b(&CallBlock);
+  }
+
+  // L1C check failed, do a full lookup
+  bind(&FullLookup);
+
+  // This is the block cache lookup routine
+  // It matches what is going on it LookupCache.h::FindBlock
+  ldr(x0, &l_PagePtr);
+
+  // Mask the address by the virtual address size so we can check for aliases
+  if (std::popcount(VirtualMemorySize) == 1) {
+    and_(x3, RipReg, Thread->LookupCache->GetVirtualMemorySize() - 1);
+  }
+  else {
+    ldr(x3, &l_VirtualMemory);
+    and_(x3, RipReg, x3);
+  }
+
+  aarch64::Label NoBlock;
+  {
+    // Offset the address and add to our page pointer
+    lsr(x1, x3, 12);
+
+    // Load the pointer from the offset
+    ldr(x0, MemOperand(x0, x1, Shift::LSL, 3));
+
+    // If page pointer is zero then we have no block
+    cbz(x0, &NoBlock);
+
+    // Steal the page offset
+    and_(x1, x3, 0x0FFF);
+
+    // Shift the offset by the size of the block cache entry
+    add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
+
+    // Load the guest address first to ensure it maps to the address we are currently at
+    // This fixes aliasing problems
+    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
+    cmp(x1, RipReg);
+    b(&NoBlock, Condition::ne);
+
+    // Now load the actual host block to execute if we can
+    ldr(x3, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
+    cbz(x3, &NoBlock);
+
+    // If we've made it here then we have a real compiled block
+    {
+      // update L1 cache
+      ldr(x0, &l_L1Ptr);
+
+      and_(x1, RipReg, LookupCache::L1_ENTRIES_MASK);
+      add(x0, x0, Operand(x1, Shift::LSL, 4));
+      stp(x3, x2, MemOperand(x0));
+
+      // Jump to the block
+      if (!config.ExecuteBlocksWithCall) {
+        br(x3);
+      } else {
+        bind(&CallBlock);
+        mov(x0, STATE);
+        blr(x3);
+
+        if (CTX->GetGdbServerStatus()) {
+          // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
+          // This happens when single stepping
+
+          static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
+          ldr(x0, &l_CTX);
+          ldr(w0, MemOperand(x0, offsetof(FEXCore::Context::Context, Config.RunningMode)));
+          // If the value == 0 then branch to the top
+          cbz(x0, &LoopTop);
+          // Else we need to pause now
+          b(&ThreadPauseHandler);
+        } else {
+          // Unconditionally loop to the top
+          // We will only stop on error when compiling a block or signal
+          b(&LoopTop);
+        }
+      }
+    }
+  }
+
+  {
+    bind(&ExitSpillSRA);
+    ThreadStopHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    ThreadStopHandlerAddress = GetCursorAddress<uint64_t>();
+
+    PopCalleeSavedRegisters();
+
+    // Return from the function
+    // LR is set to the correct return location now
+    ret();
+  }
+
+  constexpr bool SignalSafeCompile = true;
+  {
+    ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    if (SignalSafeCompile) {
+      // When compiling code, mask all signals to reduce the chance of reentrant allocations
+      // Args:
+      // X0: SETMASK
+      // X1: Pointer to mask value (uint64_t)
+      // X2: Pointer to old mask value (uint64_t)
+      // X3: Size of mask, sizeof(uint64_t)
+      // X8: Syscall
+
+      LoadConstant(x0, ~0ULL);
+      stp(x0, x0, MemOperand(sp, -16, PreIndex));
+      LoadConstant(x0, SIG_SETMASK);
+      add(x1, sp, 0);
+      add(x2, sp, 0);
+      LoadConstant(x3, 8);
+      LoadConstant(x8, SYS_rt_sigprocmask);
+      svc(0);
+    }
+
+    ldr(x0, &l_ExitFunctionLinkThis);
+    mov(x1, STATE);
+    mov(x2, lr);
+
+    ldr(x3, &l_ExitFunctionLink);
+    blr(x3);
+
+    if (SignalSafeCompile) {
+      // Now restore the signal mask
+      // Living in the same location
+
+      mov(x4, x0);
+      LoadConstant(x0, SIG_SETMASK);
+      add(x1, sp, 0);
+      LoadConstant(x2, 0);
+      LoadConstant(x3, 8);
+      LoadConstant(x8, SYS_rt_sigprocmask);
+      svc(0);
+
+      // Bring stack back
+      add(sp, sp, 16);
+
+      mov(x0, x4);
+    }
+
+    if (SRAEnabled)
+      FillStaticRegs();
+    br(x0);
+  }
+
+  // Need to create the block
+  {
+    bind(&NoBlock);
+
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    if (SignalSafeCompile) {
+      // When compiling code, mask all signals to reduce the chance of reentrant allocations
+      // Args:
+      // X0: SETMASK
+      // X1: Pointer to mask value (uint64_t)
+      // X2: Pointer to old mask value (uint64_t)
+      // X3: Size of mask, sizeof(uint64_t)
+      // X8: Syscall
+
+      LoadConstant(x0, ~0ULL);
+      stp(x0, x2, MemOperand(sp, -16, PreIndex));
+      LoadConstant(x0, SIG_SETMASK);
+      add(x1, sp, 0);
+      add(x2, sp, 0);
+      LoadConstant(x3, 8);
+      LoadConstant(x8, SYS_rt_sigprocmask);
+      svc(0);
+
+      // Reload x2 to bring back RIP
+      ldr(x2, MemOperand(sp, 8, Offset));
+    }
+
+    ldr(x0, &l_CTX);
+    mov(x1, STATE);
+    ldr(x3, &l_CompileBlock);
+
+    // X2 contains our guest RIP
+    blr(x3); // { CTX, Frame, RIP}
+
+
+    if (SignalSafeCompile) {
+      // Now restore the signal mask
+      // Living in the same location
+      LoadConstant(x0, SIG_SETMASK);
+      add(x1, sp, 0);
+      LoadConstant(x2, 0);
+      LoadConstant(x3, 8);
+      LoadConstant(x8, SYS_rt_sigprocmask);
+      svc(0);
+
+      // Bring stack back
+      add(sp, sp, 16);
+    }
+
+    if (SRAEnabled)
+      FillStaticRegs();
+
+    b(&LoopTop);
+  }
+
+  {
+    SignalHandlerReturnAddress = GetCursorAddress<uint64_t>();
+
+    // Now to get back to our old location we need to do a fault dance
+    // We can't use SIGTRAP here since gdb catches it and never gives it to the application!
+    hlt(0);
+  }
+
+  {
+    // Guest SIGILL handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    UnimplementedInstructionAddress = GetCursorAddress<uint64_t>();
+
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    hlt(0);
+  }
+
+  {
+    // Guest Overflow handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    OverflowExceptionInstructionAddress = GetCursorAddress<uint64_t>();
+
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    LoadConstant(x0, reinterpret_cast<uint64_t>(&SynchronousFaultData));
+    LoadConstant(w1, 1);
+    strb(w1, MemOperand(x0, offsetof(Dispatcher::SynchronousFaultDataStruct, FaultToTopAndGeneratedException)));
+    LoadConstant(w1, X86State::X86_TRAPNO_OF);
+    str(w1, MemOperand(x0, offsetof(Dispatcher::SynchronousFaultDataStruct, TrapNo)));
+    LoadConstant(w1, 0x80);
+    str(w1, MemOperand(x0, offsetof(Dispatcher::SynchronousFaultDataStruct, si_code)));
+    LoadConstant(x1, 0);
+    str(w1, MemOperand(x0, offsetof(Dispatcher::SynchronousFaultDataStruct, err_code)));
+
+    // hlt/udf = SIGILL
+    // brk = SIGTRAP
+    // ??? = SIGSEGV
+    // Force a SIGSEGV by loading zero
+    ldr(x1, MemOperand(x1));
+  }
+
+  {
+    ThreadPauseHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    bind(&ThreadPauseHandler);
+    ThreadPauseHandlerAddress = GetCursorAddress<uint64_t>();
+    // We are pausing, this means the frontend should be waiting for this thread to idle
+    // We will have faulted and jumped to this location at this point
+
+    // Call our sleep handler
+    ldr(x0, &l_CTX);
+    mov(x1, STATE);
+    ldr(x2, &l_Sleep);
+    blr(x2);
+
+    PauseReturnInstruction = GetCursorAddress<uint64_t>();
+    // Fault to start running again
+    hlt(0);
+  }
+
+  {
+    // The expectation here is that a thunked function needs to call back in to the JIT in a reentrant safe way
+    // To do this safely we need to do some state tracking and register saving
+    //
+    // eg:
+    // JIT Call->
+    //  Thunk->
+    //    Thunk callback->
+    //
+    // The thunk callback needs to execute JIT code and when it returns, it needs to safely return to the thunk rather than JIT space
+    // This is handled by pushing a return address trampoline to the stack so when the guest address returns it hits our custom thunk return
+    //  - This will safely return us to the thunk
+    //
+    // On return to the thunk, the thunk can get whatever its return value is from the thread context depending on ABI handling on its end
+    // When the thunk itself returns, it'll do its regular return logic there
+    // void ReentrantCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
+    CallbackPtr = GetCursorAddress<CPUBackend::JITCallback>();
+
+    // We expect the thunk to have previously pushed the registers it was using
+    PushCalleeSavedRegisters();
+
+    // First thing we need to move the thread state pointer back in to our register
+    mov(STATE, x0);
+
+    // Make sure to adjust the refcounter so we don't clear the cache now
+    LoadConstant(x0, reinterpret_cast<uint64_t>(&SignalHandlerRefCounter));
+    ldr(w2, MemOperand(x0));
+    add(w2, w2, 1);
+    str(w2, MemOperand(x0));
+
+    // Now push the callback return trampoline to the guest stack
+    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
+    LoadConstant(x0, CTX->X86CodeGen.CallbackReturn);
+
+    ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
+    sub(x2, x2, 16);
+    str(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
+
+    // Store the trampoline to the guest stack
+    // Guest stack is now correctly misaligned after a regular call instruction
+    str(x0, MemOperand(x2));
+
+    // Store RIP to the context state
+    str(x1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
+
+    // load static regs
+    if (SRAEnabled)
+      FillStaticRegs();
+
+    // Now go back to the regular dispatcher loop
+    b(&LoopTop);
+  }
+
+  place(&l_VirtualMemory);
+  place(&l_PagePtr);
+  place(&l_L1Ptr);
+  place(&l_CTX);
+  place(&l_Sleep);
+  place(&l_CompileBlock);
+  place(&l_ExitFunctionLink);
+  place(&l_ExitFunctionLinkThis);
+
+
+  FinalizeCode();
+  Start = reinterpret_cast<uint64_t>(DispatchPtr);
+  End = GetCursorAddress<uint64_t>();
+  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
+  GetBuffer()->SetExecutable();
+
+  if (CTX->Config.BlockJITNaming()) {
+    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
+    CTX->Symbols.Register(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr), Name);
+  }
+  if (CTX->Config.GlobalJITNaming()) {
+    CTX->Symbols.RegisterJITSpace(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
+  }
+}
+
+void Arm64Dispatcher::SpillSRA(void *ucontext, uint32_t IgnoreMask) {
+  for(int i = 0; i < SRA64.size(); i++) {
+    if (IgnoreMask & (1U << SRA64[i].GetCode())) {
+      // Skip this one, it's already spilled
+      continue;
+    }
+    ThreadState->CurrentFrame->State.gregs[i] = ArchHelpers::Context::GetArmReg(ucontext, SRA64[i].GetCode());
+  }
+
+  for(int i = 0; i < SRAFPR.size(); i++) {
+    auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].GetCode());
+    memcpy(&ThreadState->CurrentFrame->State.xmm[i][0], &FPR, sizeof(__uint128_t));
+  }
+}
+
+#ifdef _M_ARM_64
+
+void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  DispatcherConfig config;
+  config.ExecuteBlocksWithCall = true;
+
+  Dispatcher = std::make_unique<Arm64Dispatcher>(ctx, Thread, config);
+  DispatchPtr = Dispatcher->DispatchPtr;
+  CallbackPtr = Dispatcher->CallbackPtr;
+
+  // TODO: It feels wrong to initialize this way
+  ctx->InterpreterCallbackReturn = Dispatcher->ReturnPtr;
+}
+
+#endif
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.h

@@ -0,0 +1,24 @@
+#pragma once
+
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+
+namespace FEXCore::Context {
+struct Context;
+}
+
+namespace FEXCore::Core {
+struct InternalThreadState;
+}
+
+namespace FEXCore::CPU {
+
+class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
+  public:
+    Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config);
+
+  protected:
+    void SpillSRA(void *ucontext, uint32_t IgnoreMask) override;
+};
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -0,0 +1,779 @@
+
+#include "Interface/Core/ArchHelpers/MContext.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/X86HelperGen.h"
+#include "Interface/Core/CompileService.h"
+
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/SignalDelegator.h>
+#include <FEXCore/Core/UContext.h>
+#include <FEXCore/Core/X86Enums.h>
+#include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXCore/Utils/Event.h>
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/MathUtils.h>
+
+#include <atomic>
+#include <condition_variable>
+#include <bits/types/siginfo_t.h>
+#include <csignal>
+#include <cstring>
+
+namespace FEXCore::CPU {
+
+void Dispatcher::SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame) {
+  auto Thread = Frame->Thread;
+
+  --ctx->IdleWaitRefCount;
+  ctx->IdleWaitCV.notify_all();
+
+  Thread->RunningEvents.ThreadSleeping = true;
+
+  // Go to sleep
+  Thread->StartRunning.Wait();
+
+  Thread->RunningEvents.Running = true;
+  ++ctx->IdleWaitRefCount;
+  Thread->RunningEvents.ThreadSleeping = false;
+
+  ctx->IdleWaitCV.notify_all();
+}
+
+ArchHelpers::Context::ContextBackup* Dispatcher::StoreThreadState(int Signal, void *ucontext) {
+  // We can end up getting a signal at any point in our host state
+  // Jump to a handler that saves all state so we can safely return
+  uint64_t OldSP = ArchHelpers::Context::GetSp(ucontext);
+  uintptr_t NewSP = OldSP;
+
+  size_t StackOffset = sizeof(ArchHelpers::Context::ContextBackup);
+
+  // We need to back up behind the host's red zone
+  // We do this on the guest side as well
+  // (does nothing on arm hosts)
+  NewSP -= ArchHelpers::Context::ContextBackup::RedZoneSize;
+
+  NewSP -= StackOffset;
+  NewSP = AlignDown(NewSP, 16);
+
+  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
+  ArchHelpers::Context::BackupContext(ucontext, Context);
+
+  // Retain the action pointer so we can see it when we return
+  Context->Signal = Signal;
+
+  // Save guest state
+  // We can't guarantee if registers are in context or host GPRs
+  // So we need to save everything
+  memcpy(&Context->GuestState, ThreadState->CurrentFrame, sizeof(FEXCore::Core::CPUState));
+
+  // Set the new SP
+  ArchHelpers::Context::SetSp(ucontext, NewSP);
+
+  // Signal frames are only used on the interpreter
+  // The JITS require the stack to be setup correctly on rt_sigreturn
+  if (CTX->Config.Core() == FEXCore::Config::CONFIG_INTERPRETER) {
+    SignalFrames.push(NewSP);
+  }
+
+  Context->Flags = 0;
+  Context->FPStateLocation = 0;
+  Context->UContextLocation = 0;
+  Context->SigInfoLocation = 0;
+
+  // Store fault to top status and then reset it
+  Context->FaultToTopAndGeneratedException = SynchronousFaultData.FaultToTopAndGeneratedException;
+  SynchronousFaultData.FaultToTopAndGeneratedException = false;
+
+  return Context;
+}
+
+void Dispatcher::RestoreThreadState(void *ucontext) {
+  uint64_t OldSP{};
+  if (CTX->Config.Core() == FEXCore::Config::CONFIG_IRJIT) {
+    OldSP = ArchHelpers::Context::GetSp(ucontext);
+  }
+  else {
+    LOGMAN_THROW_A_FMT(!SignalFrames.empty(), "Trying to restore a signal frame when we don't have any");
+    OldSP = SignalFrames.top();
+    SignalFrames.pop();
+  }
+
+  uintptr_t NewSP = OldSP;
+  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
+
+  // First thing, reset the guest state
+  memcpy(ThreadState->CurrentFrame, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
+
+  // Now restore host state
+  ArchHelpers::Context::RestoreContext(ucontext, Context);
+
+  if (Context->UContextLocation) {
+    auto Frame = ThreadState->CurrentFrame;
+
+    if (Context->Flags &ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_INJIT) {
+      // XXX: Unsupported since it needs state reconstruction
+      // If we are in the JIT then SRA might need to be restored to values from the context
+      // We can't currently support this since it might result in tearing without real state reconstruction
+    }
+
+    if (!(Context->Flags & ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT)) {
+      auto *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(Context->UContextLocation);
+      [[maybe_unused]] auto *guest_siginfo = reinterpret_cast<siginfo_t*>(Context->SigInfoLocation);
+
+      // If the guest modified the RIP then we need to take special precautions here
+      if (Context->OriginalRIP != guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] ||
+          Context->FaultToTopAndGeneratedException) {
+        // Hack! Go back to the top of the dispatcher top
+        // This is only safe inside the JIT rather than anything outside of it
+        ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
+        // Set our state register to point to our guest thread data
+        ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+        Frame->State.rip = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP];
+        // XXX: Full context setting
+        uint32_t eflags = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL];
+        for (size_t i = 0; i < 32; ++i) {
+          Frame->State.flags[i] = (eflags & (1U << i)) ? 1 : 0;
+        }
+
+        Frame->State.flags[1] = 1;
+        Frame->State.flags[9] = 1;
+
+#define COPY_REG(x) \
+            Frame->State.gregs[X86State::REG_##x] = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x];
+            COPY_REG(R8);
+            COPY_REG(R9);
+            COPY_REG(R10);
+            COPY_REG(R11);
+            COPY_REG(R12);
+            COPY_REG(R13);
+            COPY_REG(R14);
+            COPY_REG(R15);
+            COPY_REG(RDI);
+            COPY_REG(RSI);
+            COPY_REG(RBP);
+            COPY_REG(RBX);
+            COPY_REG(RDX);
+            COPY_REG(RAX);
+            COPY_REG(RCX);
+            COPY_REG(RSP);
+#undef COPY_REG
+        FEXCore::x86_64::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86_64::_libc_fpstate*>(guest_uctx->uc_mcontext.fpregs);
+        // Copy float registers
+        memcpy(Frame->State.mm, fpstate->_st, sizeof(Frame->State.mm));
+        memcpy(Frame->State.xmm, fpstate->_xmm, sizeof(Frame->State.xmm));
+
+        // FCW store default
+        Frame->State.FCW = fpstate->fcw;
+        Frame->State.FTW = fpstate->ftw;
+
+        // Deconstruct FSW
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] = (fpstate->fsw >> 8) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] = (fpstate->fsw >> 9) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] = (fpstate->fsw >> 10) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] = (fpstate->fsw >> 14) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] = (fpstate->fsw >> 11) & 0b111;
+      }
+    }
+    else {
+      auto *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(Context->UContextLocation);
+      [[maybe_unused]] auto *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(Context->SigInfoLocation);
+      // If the guest modified the RIP then we need to take special precautions here
+      if (Context->OriginalRIP != guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] ||
+          Context->FaultToTopAndGeneratedException) {
+        // Hack! Go back to the top of the dispatcher top
+        // This is only safe inside the JIT rather than anything outside of it
+        ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
+        // Set our state register to point to our guest thread data
+        ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+        // XXX: Full context setting
+        // First 32-bytes of flags is EFLAGS broken out
+        uint32_t eflags = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL];
+        for (size_t i = 0; i < 32; ++i) {
+          Frame->State.flags[i] = (eflags & (1U << i)) ? 1 : 0;
+        }
+
+        Frame->State.flags[1] = 1;
+        Frame->State.flags[9] = 1;
+
+        Frame->State.rip = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP];
+        Frame->State.cs = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS];
+        Frame->State.ds = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS];
+        Frame->State.es = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES];
+        Frame->State.fs = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS];
+        Frame->State.gs = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS];
+        Frame->State.ss = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS];
+#define COPY_REG(x) \
+      Frame->State.gregs[X86State::REG_##x] = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x];
+        COPY_REG(RDI);
+        COPY_REG(RSI);
+        COPY_REG(RBP);
+        COPY_REG(RBX);
+        COPY_REG(RDX);
+        COPY_REG(RAX);
+        COPY_REG(RCX);
+        COPY_REG(RSP);
+#undef COPY_REG
+        FEXCore::x86::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86::_libc_fpstate*>(guest_uctx->uc_mcontext.fpregs);
+
+        // Copy float registers
+        for (size_t i = 0; i < 8; ++i) {
+          // 32-bit st register size is only 10 bytes. Not padded to 16byte like x86-64
+          memcpy(&Frame->State.mm[i], &fpstate->_st[i], 10);
+        }
+
+        // Extended XMM state
+        memcpy(fpstate->_xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+
+        // FCW store default
+        Frame->State.FCW = fpstate->fcw;
+        Frame->State.FTW = fpstate->ftw;
+
+        // Deconstruct FSW
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] = (fpstate->fsw >> 8) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] = (fpstate->fsw >> 9) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] = (fpstate->fsw >> 10) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] = (fpstate->fsw >> 14) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] = (fpstate->fsw >> 11) & 0b111;
+      }
+    }
+  }
+}
+
+static uint32_t ConvertSignalToTrapNo(int Signal, siginfo_t *HostSigInfo) {
+  switch (Signal) {
+    case SIGSEGV:
+      if (HostSigInfo->si_code == SEGV_MAPERR ||
+          HostSigInfo->si_code == SEGV_ACCERR) {
+        // Protection fault
+        return X86State::X86_TRAPNO_PF;
+      }
+      break;
+  }
+
+  // Unknown mapping, fall back to old behaviour and just pass signal
+  return Signal;
+}
+
+static uint32_t ConvertSignalToError(int Signal, siginfo_t *HostSigInfo) {
+  switch (Signal) {
+    case SIGSEGV:
+      if (HostSigInfo->si_code == SEGV_MAPERR ||
+          HostSigInfo->si_code == SEGV_ACCERR) {
+        // Protection fault
+        // Always a user fault for us
+        // XXX: PF_PROT and PF_WRITE
+        return X86State::X86_PF_USER;
+      }
+      break;
+  }
+
+  // Not a page fault issue
+  return 0;
+}
+
+bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
+  auto ContextBackup = StoreThreadState(Signal, ucontext);
+
+  auto Frame = ThreadState->CurrentFrame;
+
+  // Ref count our faults
+  // We use this to track if it is safe to clear cache
+  ++SignalHandlerRefCounter;
+
+  uint64_t OldPC = ArchHelpers::Context::GetPc(ucontext);
+  // Set the new PC
+  ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
+  // Set our state register to point to our guest thread data
+  ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+  uint64_t OldGuestSP = Frame->State.gregs[X86State::REG_RSP];
+  uint64_t NewGuestSP = OldGuestSP;
+
+  // Pulling from context here
+  bool Is64BitMode = CTX->Config.Is64BitMode;
+  uint64_t SignalReturn = CTX->X86CodeGen.SignalReturn;
+
+  // Spill the SRA regardless of signal handler type
+  // We are going to be returning to the top of the dispatcher which will fill again
+  // Otherwise we might load garbage
+  if (SRAEnabled) {
+    if (IsAddressInJITCode(OldPC, false)) {
+      uint32_t IgnoreMask{};
+#ifdef _M_ARM_64
+      if (Frame->InSyscallInfo != 0) {
+        // We are in a syscall, this means we are in a weird register state
+        // We need to spill SRA but only some of it, since some values have already been spilled
+        // Lower 16 bits tells us which registers are already spilled to the context
+        // So we ignore spilling those ones
+        uint16_t NumRegisters = std::popcount(Frame->InSyscallInfo & 0xFFFF);
+        if (NumRegisters >= 4) {
+          // Unhandled case
+          IgnoreMask = 0;
+        }
+        else {
+          IgnoreMask = Frame->InSyscallInfo & 0xFFFF;
+        }
+      }
+      else {
+        // We must spill everything
+        IgnoreMask = 0;
+      }
+#endif
+
+      // We are in jit, SRA must be spilled
+      SpillSRA(ucontext, IgnoreMask);
+
+      ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_INJIT;
+    } else {
+      if (!IsAddressInJITCode(OldPC, true)) {
+        // This is likely to cause issues but in some cases it isn't fatal
+        // This can also happen if we have put a signal on hold, then we just reenabled the signal
+        // So we are in the syscall handler
+        // Only throw a log message in this case
+        if constexpr (false) {
+          // XXX: Messages in the signal handler can cause us to crash
+          LogMan::Msg::EFmt("Signals in dispatcher have unsynchronized context");
+        }
+      }
+    }
+  }
+
+  // altstack is only used if the signal handler was setup with SA_ONSTACK
+  if (GuestAction->sa_flags & SA_ONSTACK) {
+    // Additionally the altstack is only used if the enabled (SS_DISABLE flag is not set)
+    if (!(GuestStack->ss_flags & SS_DISABLE)) {
+      // If our guest is already inside of the alternative stack
+      // Then that means we are hitting recursive signals and we need to walk back the stack correctly
+      uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
+      uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
+      if (OldGuestSP >= AltStackBase &&
+          OldGuestSP <= AltStackEnd) {
+        // We are already in the alt stack, the rest of the code will handle adjusting this
+      }
+      else {
+        NewGuestSP = AltStackEnd;
+      }
+    }
+  }
+
+  if (Is64BitMode) {
+    // Back up past the redzone, which is 128bytes
+    // 32-bit doesn't have a redzone
+    NewGuestSP -= 128;
+  }
+
+  // siginfo_t
+  siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);
+
+  // Backup where we think the RIP currently is
+  ContextBackup->OriginalRIP = Frame->State.rip;
+
+  if (GuestAction->sa_flags & SA_SIGINFO) {
+    // Setup ucontext a bit
+    if (Is64BitMode) {
+      NewGuestSP -= sizeof(FEXCore::x86_64::_libc_fpstate);
+      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86_64::_libc_fpstate));
+      uint64_t FPStateLocation = NewGuestSP;
+
+      NewGuestSP -= sizeof(FEXCore::x86_64::ucontext_t);
+      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86_64::ucontext_t));
+      uint64_t UContextLocation = NewGuestSP;
+
+      NewGuestSP -= sizeof(siginfo_t);
+      NewGuestSP = AlignDown(NewGuestSP, alignof(siginfo_t));
+      uint64_t SigInfoLocation = NewGuestSP;
+
+      ContextBackup->FPStateLocation = FPStateLocation;
+      ContextBackup->UContextLocation = UContextLocation;
+      ContextBackup->SigInfoLocation = SigInfoLocation;
+
+      FEXCore::x86_64::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(UContextLocation);
+      siginfo_t *guest_siginfo = reinterpret_cast<siginfo_t*>(SigInfoLocation);
+
+      // We have extended float information
+      guest_uctx->uc_flags = FEXCore::x86_64::UC_FP_XSTATE;
+
+      // Pointer to where the fpreg memory is
+      guest_uctx->uc_mcontext.fpregs = reinterpret_cast<FEXCore::x86_64::_libc_fpstate*>(FPStateLocation);
+      FEXCore::x86_64::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86_64::_libc_fpstate*>(FPStateLocation);
+
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] = Frame->State.rip;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CSGSFS] = 0;
+
+      // aarch64 and x86_64 siginfo_t matches. We can just copy this over
+      // SI_USER could also potentially have random data in it, needs to be bit perfect
+      // For guest faults we don't have a real way to reconstruct state to a real guest RIP
+      *guest_siginfo = *HostSigInfo;
+
+      if (ContextBackup->FaultToTopAndGeneratedException) {
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = SynchronousFaultData.TrapNo;
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = SynchronousFaultData.err_code;
+
+        // Overwrite si_code
+        guest_siginfo->si_code = SynchronousFaultData.si_code;
+      }
+      else {
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
+      }
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_OLDMASK] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CR2] = 0;
+
+#define COPY_REG(x) \
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
+      COPY_REG(R8);
+      COPY_REG(R9);
+      COPY_REG(R10);
+      COPY_REG(R11);
+      COPY_REG(R12);
+      COPY_REG(R13);
+      COPY_REG(R14);
+      COPY_REG(R15);
+      COPY_REG(RDI);
+      COPY_REG(RSI);
+      COPY_REG(RBP);
+      COPY_REG(RBX);
+      COPY_REG(RDX);
+      COPY_REG(RAX);
+      COPY_REG(RCX);
+      COPY_REG(RSP);
+#undef COPY_REG
+
+      // Copy float registers
+      memcpy(fpstate->_st, Frame->State.mm, sizeof(Frame->State.mm));
+      memcpy(fpstate->_xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+
+      // FCW store default
+      fpstate->fcw = Frame->State.FCW;
+      fpstate->ftw = Frame->State.FTW;
+
+      // Reconstruct FSW
+      fpstate->fsw =
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
+
+      // Copy over signal stack information
+      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
+      guest_uctx->uc_stack.ss_sp = GuestStack->ss_sp;
+      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
+
+      Frame->State.gregs[X86State::REG_RSI] = SigInfoLocation;
+      Frame->State.gregs[X86State::REG_RDX] = UContextLocation;
+    }
+    else {
+      ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT;
+
+      NewGuestSP -= sizeof(FEXCore::x86::_libc_fpstate);
+      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::_libc_fpstate));
+      uint64_t FPStateLocation = NewGuestSP;
+
+      NewGuestSP -= sizeof(FEXCore::x86::ucontext_t);
+      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::ucontext_t));
+      uint64_t UContextLocation = NewGuestSP;
+
+      NewGuestSP -= sizeof(FEXCore::x86::siginfo_t);
+      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::siginfo_t));
+      uint64_t SigInfoLocation = NewGuestSP;
+
+      ContextBackup->FPStateLocation = FPStateLocation;
+      ContextBackup->UContextLocation = UContextLocation;
+      ContextBackup->SigInfoLocation = SigInfoLocation;
+
+      FEXCore::x86::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(UContextLocation);
+      FEXCore::x86::siginfo_t *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(SigInfoLocation);
+
+      // We have extended float information
+      guest_uctx->uc_flags = FEXCore::x86::UC_FP_XSTATE;
+
+      // Pointer to where the fpreg memory is
+      guest_uctx->uc_mcontext.fpregs = static_cast<uint32_t>(FPStateLocation);
+      FEXCore::x86::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86::_libc_fpstate*>(FPStateLocation);
+
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS] = Frame->State.gs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS] = Frame->State.fs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES] = Frame->State.es;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS] = Frame->State.ds;
+      if (ContextBackup->FaultToTopAndGeneratedException) {
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = SynchronousFaultData.TrapNo;
+        guest_siginfo->si_code = SynchronousFaultData.si_code;
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = SynchronousFaultData.err_code;
+      }
+      else {
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
+        guest_siginfo->si_code = HostSigInfo->si_code;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
+      }
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] = Frame->State.rip;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS] = Frame->State.cs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_UESP] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS] = Frame->State.ss;
+
+#define COPY_REG(x) \
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
+      COPY_REG(RDI);
+      COPY_REG(RSI);
+      COPY_REG(RBP);
+      COPY_REG(RBX);
+      COPY_REG(RDX);
+      COPY_REG(RAX);
+      COPY_REG(RCX);
+      COPY_REG(RSP);
+#undef COPY_REG
+
+      // Copy float registers
+      for (size_t i = 0; i < 8; ++i) {
+        // 32-bit st register size is only 10 bytes. Not padded to 16byte like x86-64
+        memcpy(&fpstate->_st[i], &Frame->State.mm[i], 10);
+      }
+
+      // Extended XMM state
+      fpstate->status = FEXCore::x86::fpstate_magic::MAGIC_XFPSTATE;
+      memcpy(fpstate->_xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+
+      // FCW store default
+      fpstate->fcw = Frame->State.FCW;
+      fpstate->ftw = Frame->State.FTW;
+      // Reconstruct FSW
+      fpstate->fsw =
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
+
+      // Copy over signal stack information
+      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
+      guest_uctx->uc_stack.ss_sp = static_cast<uint32_t>(reinterpret_cast<uint64_t>(GuestStack->ss_sp));
+      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
+
+      // These three elements are in every siginfo
+      guest_siginfo->si_signo = HostSigInfo->si_signo;
+      guest_siginfo->si_errno = HostSigInfo->si_errno;
+
+      switch (Signal) {
+        case SIGSEGV:
+        case SIGBUS:
+          // Macro expansion to get the si_addr
+          // This is the address trying to be accessed, not the RIP
+          guest_siginfo->_sifields._sigfault.addr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(HostSigInfo->si_addr));
+          break;
+        case SIGFPE:
+        case SIGILL:
+          // Macro expansion to get the si_addr
+          // Can't really give a real result here. Pull from the context for now
+          guest_siginfo->_sifields._sigfault.addr = Frame->State.rip;
+          break;
+        case SIGCHLD:
+          guest_siginfo->_sifields._sigchld.pid = HostSigInfo->si_pid;
+          guest_siginfo->_sifields._sigchld.uid = HostSigInfo->si_uid;
+          guest_siginfo->_sifields._sigchld.status = HostSigInfo->si_status;
+          guest_siginfo->_sifields._sigchld.utime = HostSigInfo->si_utime;
+          guest_siginfo->_sifields._sigchld.stime = HostSigInfo->si_stime;
+          break;
+        case SIGALRM:
+        case SIGVTALRM:
+          guest_siginfo->_sifields._timer.tid = HostSigInfo->si_timerid;
+          guest_siginfo->_sifields._timer.overrun = HostSigInfo->si_overrun;
+          guest_siginfo->_sifields._timer.sigval.sival_int = HostSigInfo->si_int;
+          break;
+        default:
+          LogMan::Msg::EFmt("Unhandled siginfo_t for signal: {}\n", Signal);
+          break;
+      }
+
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = UContextLocation;
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = SigInfoLocation;
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = Signal;
+    }
+
+    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
+  }
+  else {
+    if (!Is64BitMode) {
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = Signal;
+    }
+
+    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
+  }
+
+  if (Is64BitMode) {
+    Frame->State.gregs[FEXCore::X86State::REG_RDI] = Signal;
+
+    // Set up the new SP for stack handling
+    NewGuestSP -= 8;
+    *(uint64_t*)NewGuestSP = SignalReturn;
+    Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP;
+  }
+  else {
+    NewGuestSP -= 4;
+    *(uint32_t*)NewGuestSP = SignalReturn;
+    LOGMAN_THROW_A_FMT(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
+    Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP;
+  }
+
+  // The guest starts its signal frame with a zero initialized FPU
+  // Set that up now. Little bit costly but it's a requirement
+  // This state will be restored on rt_sigreturn
+  memset(Frame->State.xmm, 0, sizeof(Frame->State.xmm));
+  memset(Frame->State.mm, 0, sizeof(Frame->State.mm));
+  Frame->State.FCW = 0x37F;
+  Frame->State.FTW = 0xFFFF;
+
+  return true;
+}
+
+bool Dispatcher::HandleSIGILL(int Signal, void *info, void *ucontext) {
+
+  if (ArchHelpers::Context::GetPc(ucontext) == SignalHandlerReturnAddress) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+    return true;
+  }
+
+  if (ArchHelpers::Context::GetPc(ucontext) == PauseReturnInstruction) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+    return true;
+  }
+
+  return false;
+}
+
+bool Dispatcher::HandleSignalPause(int Signal, void *info, void *ucontext) {
+  FEXCore::Core::SignalEvent SignalReason = ThreadState->SignalReason.load();
+  auto Frame = ThreadState->CurrentFrame;
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Pause) {
+    // Store our thread state so we can come back to this
+    StoreThreadState(Signal, ucontext);
+
+    if (SRAEnabled && IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
+      // We are in jit, SRA must be spilled
+      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddressSpillSRA);
+    } else {
+      if (SRAEnabled) {
+        // We are in non-jit, SRA is already spilled
+        LOGMAN_THROW_A_FMT(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true),
+                           "Signals in dispatcher have unsynchronized context");
+      }
+      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddress);
+    }
+
+    // Set our state register to point to our guest thread data
+    ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    ++SignalHandlerRefCounter;
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Stop) {
+    // Our thread is stopping
+    // We don't care about anything at this point
+    // Set the stack to our starting location when we entered the core and get out safely
+    ArchHelpers::Context::SetSp(ucontext, Frame->ReturningStackLocation);
+
+    // Our ref counting doesn't matter anymore
+    SignalHandlerRefCounter = 0;
+
+    // Set the new PC
+    if (SRAEnabled && IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
+      // We are in jit, SRA must be spilled
+      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddressSpillSRA);
+    } else {
+      if (SRAEnabled) {
+        // We are in non-jit, SRA is already spilled
+        LOGMAN_THROW_A_FMT(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true),
+                           "Signals in dispatcher have unsynchronized context");
+      }
+      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddress);
+    }
+
+    // We need to be a little bit careful here
+    // If we were already paused (due to GDB) and we are immediately stopping (due to gdb kill)
+    // Then we need to ensure we don't double decrement our idle thread counter
+    if (ThreadState->RunningEvents.ThreadSleeping) {
+      // If the thread was sleeping then its idle counter was decremented
+      // Reincrement it here to not break logic
+      ++ThreadState->CTX->IdleWaitRefCount;
+    }
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Return) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  return false;
+}
+
+uint64_t Dispatcher::GetCompileBlockPtr() {
+  using ClassPtrType = void (FEXCore::Context::Context::*)(FEXCore::Core::CpuStateFrame *, uint64_t);
+  union PtrCast {
+    ClassPtrType ClassPtr;
+    uintptr_t Data;
+  };
+
+  PtrCast CompileBlockPtr;
+  CompileBlockPtr.ClassPtr = &FEXCore::Context::Context::CompileBlockJit;
+  return CompileBlockPtr.Data;
+}
+
+void Dispatcher::RemoveCodeBuffer(uint8_t* start_to_remove) {
+  for (auto iter = CodeBuffers.begin(); iter != CodeBuffers.end(); ++iter) {
+    auto [start, end] = *iter;
+    if (start == reinterpret_cast<uint64_t>(start_to_remove)) {
+      CodeBuffers.erase(iter);
+      return;
+    }
+  }
+}
+
+bool Dispatcher::IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher, bool IncludeCompileService) const {
+  for (auto [start, end] : CodeBuffers) {
+    if (Address >= start && Address < end) {
+      return true;
+    }
+  }
+
+  if (IncludeDispatcher && IsAddressInDispatcher(Address)) {
+    return true;
+  }
+
+  if (IncludeCompileService &&  ThreadState->CompileService && ThreadState->CompileService->IsAddressInJITCode(Address)) {
+    return true;
+  }
+  return false;
+}
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -0,0 +1,108 @@
+#pragma once
+
+#include <FEXCore/Core/CPUBackend.h>
+
+#include "Interface/Context/Context.h"
+#include "Interface/Core/ArchHelpers/MContext.h"
+
+#include <bits/types/stack_t.h>
+#include <cstdint>
+#include <stddef.h>
+#include <stack>
+#include <tuple>
+#include <vector>
+
+namespace FEXCore {
+struct GuestSigAction;
+}
+
+namespace FEXCore::Core {
+struct CpuStateFrame;
+struct InternalThreadState;
+}
+
+namespace FEXCore::CPU {
+
+struct DispatcherConfig {
+  bool ExecuteBlocksWithCall = false;
+  uintptr_t ExitFunctionLink = 0;
+  uintptr_t ExitFunctionLinkThis = 0;
+  bool StaticRegisterAssignment = false;
+};
+
+class Dispatcher {
+public:
+  virtual ~Dispatcher() = default;
+  CPUBackend::AsmDispatch DispatchPtr;
+  CPUBackend::JITCallback CallbackPtr;
+  FEXCore::Context::Context::IntCallbackReturn ReturnPtr;
+
+  /**
+   * @name Dispatch Helper functions
+   * @{ */
+  uint64_t ThreadStopHandlerAddress{};
+  uint64_t ThreadStopHandlerAddressSpillSRA{};
+  uint64_t AbsoluteLoopTopAddress{};
+  uint64_t AbsoluteLoopTopAddressFillSRA{};
+  uint64_t ThreadPauseHandlerAddress{};
+  uint64_t ThreadPauseHandlerAddressSpillSRA{};
+  uint64_t ExitFunctionLinkerAddress{};
+  uint64_t SignalHandlerReturnAddress{};
+  uint64_t UnimplementedInstructionAddress{};
+  uint64_t OverflowExceptionInstructionAddress{};
+
+  uint64_t PauseReturnInstruction{};
+
+  /**  @} */
+
+  uint32_t SignalHandlerRefCounter{};
+  struct SynchronousFaultDataStruct {
+    bool FaultToTopAndGeneratedException{};
+    uint32_t TrapNo;
+    uint32_t err_code;
+    uint32_t si_code;
+  } SynchronousFaultData;
+
+  uint64_t Start{};
+  uint64_t End{};
+
+  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
+  bool HandleSIGILL(int Signal, void *info, void *ucontext);
+  bool HandleSignalPause(int Signal, void *info, void *ucontext);
+
+  void RegisterCodeBuffer(uint8_t* start, size_t size) {
+    CodeBuffers.emplace_back(reinterpret_cast<uint64_t>(start),
+        reinterpret_cast<uint64_t>(start + size));
+  }
+
+  void RemoveCodeBuffer(uint8_t* start);
+
+  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true, bool IncludeCompileService = true) const;
+  bool IsAddressInDispatcher(uint64_t Address) const {
+    return Address >= Start && Address < End;
+  }
+
+protected:
+  Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
+    : CTX {ctx}
+    , ThreadState {Thread} {}
+
+  ArchHelpers::Context::ContextBackup* StoreThreadState(int Signal, void *ucontext);
+  void RestoreThreadState(void *ucontext);
+  std::stack<uint64_t, std::vector<uint64_t>> SignalFrames;
+
+  bool SRAEnabled = false;
+  virtual void SpillSRA(void *ucontext, uint32_t IgnoreMask) {}
+
+  FEXCore::Context::Context *CTX;
+  FEXCore::Core::InternalThreadState *ThreadState;
+
+  static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame);
+
+  static uint64_t GetCompileBlockPtr();
+
+private:
+  std::vector<std::tuple<uint64_t, uint64_t>> CodeBuffers; // Start, End
+};
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp

@@ -0,0 +1,362 @@
+#include "Interface/Core/LookupCache.h"
+
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/X86HelperGen.h"
+#include "Interface/Context/Context.h"
+
+#include <FEXCore/Core/X86Enums.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXCore/Utils/Allocator.h>
+#include <FEXHeaderUtils/Syscalls.h>
+
+#include <cmath>
+#include <memory>
+#include <stddef.h>
+#include <stdint.h>
+#include <sys/mman.h>
+#include "xbyak/xbyak.h"
+
+namespace FEXCore::CPU {
+static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
+#define STATE r14
+
+X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config)
+  : Dispatcher(ctx, Thread)
+  , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE,
+      FEXCore::Allocator::mmap(nullptr, MAX_DISPATCHER_CODE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0),
+      nullptr) {
+
+  using namespace Xbyak;
+  using namespace Xbyak::util;
+  DispatchPtr = getCurr<CPUBackend::AsmDispatch>();
+
+  // Temp registers
+  // rax, rcx, rdx, rsi, r8, r9,
+  // r10, r11
+  //
+  // Callee Saved
+  // rbx, rbp, r12, r13, r14, r15
+  //
+  // 1St Argument: rdi <ThreadState>
+  // XMM:
+  // All temp
+
+  // while (true) {
+  //    Ptr = FindBlock(RIP)
+  //    if (!Ptr)
+  //      Ptr = CTX->CompileBlock(RIP);
+  //
+  //    if (Ptr)
+  //      Ptr();
+  //    else
+  //    {
+  //      Ptr = FallbackCore->CompileBlock()
+  //      if (Ptr)
+  //        Ptr()
+  //      else {
+  //        ShouldStop = true;
+  //      }
+  //    }
+  // }
+  // Bunch of exit state stuff
+
+  // x86-64 ABI has the stack aligned when /call/ happens
+  // Which means the destination has a misaligned stack at that point
+  push(rbx);
+  push(rbp);
+  push(r12);
+  push(r13);
+  push(r14);
+  push(r15);
+  sub(rsp, 8);
+
+  mov(STATE, rdi);
+
+  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
+  // regardless of where we were in the stack
+  mov(qword [rdi + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)], rsp);
+
+  Label LoopTop;
+  Label FullLookup;
+  Label CallBlock;
+  Label NoBlock;
+  Label ExitBlock;
+  Label ThreadPauseHandler;
+
+  L(LoopTop);
+  AbsoluteLoopTopAddressFillSRA = AbsoluteLoopTopAddress = getCurr<uint64_t>();
+
+  {
+    // Load our RIP
+    mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);
+
+    // L1 Cache
+    mov(r13, Thread->LookupCache->GetL1Pointer());
+    mov(rax, rdx);
+
+    and_(rax, LookupCache::L1_ENTRIES_MASK);
+    shl(rax, 4);
+    cmp(qword[r13 + rax + 8], rdx);
+    jne(FullLookup);
+
+    if (!config.ExecuteBlocksWithCall) {
+      jmp(qword[r13 + rax + 0]);
+    } else {
+      mov(rax, qword[r13 + rax + 0]);
+      jmp(CallBlock);
+    }
+
+    L(FullLookup);
+    mov(r13, Thread->LookupCache->GetPagePointer());
+
+    // Full lookup
+    mov(rax, rdx);
+    mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
+    and_(rax, rbx);
+    shr(rax, 12);
+
+    // Load page pointer
+    mov(rdi, qword [r13 + rax * 8]);
+
+    cmp(rdi, 0);
+    je(NoBlock);
+
+    mov (rax, rdx);
+    and_(rax, 0x0FFF);
+
+    shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
+
+    // check for aliasing
+    mov(rcx, qword [rdi + rax + 8]);
+    cmp(rcx, rdx);
+    jne(NoBlock);
+
+    // Load the block pointer
+    mov(rax, qword [rdi + rax]);
+
+    cmp(rax, 0);
+    je(NoBlock);
+
+    // Update L1
+
+    mov(r13, Thread->LookupCache->GetL1Pointer());
+    mov(rcx, rdx);
+    and_(rcx, LookupCache::L1_ENTRIES_MASK);
+    shl(rcx, 1);
+    mov(qword[r13 + rcx*8 + 8], rdx);
+    mov(qword[r13 + rcx*8 + 0], rax);
+
+    // Real block if we made it here
+    if (!config.ExecuteBlocksWithCall) {
+      jmp(rax);
+    } else {
+      L(CallBlock);
+      mov(rdi, STATE);
+      call(rax);
+
+      if (CTX->GetGdbServerStatus()) {
+        // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
+        // This happens when single stepping
+        static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
+        mov(rax, qword [STATE + (offsetof(FEXCore::Core::InternalThreadState, CTX))]);
+
+        // If the value == 0 then branch to the top
+        cmp(dword [rax + (offsetof(FEXCore::Context::Context, Config.RunningMode))], 0);
+        je(LoopTop);
+        // Else we need to pause now
+        jmp(ThreadPauseHandler);
+        ud2();
+      }
+      else {
+        jmp(LoopTop);
+      }
+    }
+  }
+
+  {
+    L(ExitBlock);
+    ThreadStopHandlerAddress = getCurr<uint64_t>();
+
+    add(rsp, 8);
+
+    pop(r15);
+    pop(r14);
+    pop(r13);
+    pop(r12);
+    pop(rbp);
+    pop(rbx);
+
+    ret();
+  }
+
+  // Block creation
+  {
+    L(NoBlock);
+
+    // {rdi, rsi, rdx}
+    mov(rdi, reinterpret_cast<uint64_t>(CTX));
+    mov(rsi, STATE);
+    mov(rax, GetCompileBlockPtr());
+
+    call(rax);
+
+    // rdx already contains RIP here
+    jmp(LoopTop);
+  }
+
+  {
+    ExitFunctionLinkerAddress = getCurr<uint64_t>();
+    // {rdi, rsi, rdx}
+    mov(rdi, config.ExitFunctionLinkThis);
+    mov(rsi, STATE);
+    mov(rdx, rax); // rax is set at the block end
+
+    mov(rax, config.ExitFunctionLink);
+    call(rax);
+    jmp(rax);
+  }
+
+  {
+    // Pause handler
+    ThreadPauseHandlerAddress = getCurr<uint64_t>();
+    L(ThreadPauseHandler);
+
+    mov(rdi, reinterpret_cast<uintptr_t>(CTX));
+    mov(rsi, STATE);
+    mov(rax, reinterpret_cast<uint64_t>(SleepThread));
+
+    call(rax);
+
+    // XXX: Unsupported atm
+    PauseReturnInstruction = getCurr<uint64_t>();
+    ud2();
+  }
+
+  {
+    CallbackPtr = getCurr<CPUBackend::JITCallback>();
+
+    push(rbx);
+    push(rbp);
+    push(r12);
+    push(r13);
+    push(r14);
+    push(r15);
+    sub(rsp, 8);
+
+    // First thing we need to move the thread state pointer back in to our register
+    mov(STATE, rdi);
+    // XXX: XMM?
+
+    // Make sure to adjust the refcounter so we don't clear the cache now
+    mov(rax, reinterpret_cast<uint64_t>(&SignalHandlerRefCounter));
+    add(dword [rax], 1);
+
+    // Now push the callback return trampoline to the guest stack
+    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
+    mov(rax, CTX->X86CodeGen.CallbackReturn);
+
+    // Store the trampoline to the guest stack
+    // Guest stack is now correctly misaligned after a regular call instruction
+    sub(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])], 16);
+    mov(rbx, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])]);
+    mov(qword [rbx], rax);
+
+    // Store RIP to the context state
+    mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.rip)], rsi);
+
+    // Back to the loop top now
+    jmp(LoopTop);
+  }
+
+  {
+    // Signal return handler
+    SignalHandlerReturnAddress = getCurr<uint64_t>();
+    ud2();
+  }
+
+  {
+    // Guest SIGILL handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    UnimplementedInstructionAddress = getCurr<uint64_t>();
+    ud2();
+  }
+
+  {
+    // Guest Overflow handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    OverflowExceptionInstructionAddress = getCurr<uint64_t>();
+
+    // ud2 = SIGILL
+    // int3 = SIGTRAP
+    // hlt = SIGSEGV
+
+    mov(rax, reinterpret_cast<uint64_t>(&SynchronousFaultData));
+    add(byte [rax + offsetof(Dispatcher::SynchronousFaultDataStruct, FaultToTopAndGeneratedException)], 1);
+    mov(dword [rax + offsetof(Dispatcher::SynchronousFaultDataStruct, TrapNo)], X86State::X86_TRAPNO_OF);
+    mov(dword [rax + offsetof(Dispatcher::SynchronousFaultDataStruct, err_code)], 0);
+    mov(dword [rax + offsetof(Dispatcher::SynchronousFaultDataStruct, si_code)], 0x80);
+
+    hlt();
+  }
+
+  {
+    ReturnPtr = getCurr<FEXCore::Context::Context::IntCallbackReturn>();
+//  using CallbackReturn =  FEX_NAKED void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
+
+    // rdi = thread
+    // rsi = rsp
+
+    mov(rsp, rsi);
+
+    // Now jump back to the thunk
+    // XXX: XMM?
+    add(rsp, 8);
+
+    pop(r15);
+    pop(r14);
+    pop(r13);
+    pop(r12);
+    pop(rbp);
+    pop(rbx);
+
+    ret();
+  }
+  ready();
+
+  Start = reinterpret_cast<uint64_t>(getCode());
+  End = Start + getSize();
+
+  if (CTX->Config.BlockJITNaming()) {
+    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
+    CTX->Symbols.Register(reinterpret_cast<void*>(Start), End-Start, Name);
+  }
+  if (CTX->Config.GlobalJITNaming()) {
+    CTX->Symbols.RegisterJITSpace(reinterpret_cast<void*>(Start), End-Start);
+  }
+}
+
+X86Dispatcher::~X86Dispatcher() {
+  FEXCore::Allocator::munmap(top_, MAX_DISPATCHER_CODE_SIZE);
+}
+
+#ifdef _M_X86_64
+
+void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  DispatcherConfig config;
+  config.ExecuteBlocksWithCall = true;
+
+  Dispatcher = std::make_unique<X86Dispatcher>(ctx, Thread, config);
+  DispatchPtr = Dispatcher->DispatchPtr;
+  CallbackPtr = Dispatcher->CallbackPtr;
+
+  // TODO: It feels wrong to initialize this way
+  ctx->InterpreterCallbackReturn = Dispatcher->ReturnPtr;
+}
+
+#endif
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.h

@@ -0,0 +1,25 @@
+#pragma once
+
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+
+#define XBYAK64
+#include <xbyak/xbyak.h>
+
+namespace FEXCore::Context {
+  struct Context;
+}
+
+namespace FEXCore::Core {
+  struct InternalThreadState;
+}
+
+namespace FEXCore::CPU {
+
+class X86Dispatcher final : public Dispatcher, public Xbyak::CodeGenerator {
+  public:
+    X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config);
+
+    virtual ~X86Dispatcher() override;
+};
+
+}

External/FEXCore/Source/Interface/Core/Frontend.cpp

@@ -1,19 +1,36 @@
+/*
+$info$
+tags: frontend|x86-meta-blocks
+desc: Extracts instruction & block meta info, frontend multiblock logic
+$end_info$
+*/
+
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Frontend.h"
-#include "Interface/Core/InternalThreadState.h"
 
 #include <array>
+#include <assert.h>
 #include <algorithm>
 #include <cstring>
+#include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/X86Tables.h>
+#include <FEXCore/HLE/SyscallHandler.h>
+#include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/Telemetry.h>
+#include <set>
+#include <sys/mman.h>
 
 namespace FEXCore::Frontend {
+#include "Interface/Core/VSyscall/VSyscall.inc"
+
 using namespace FEXCore::X86Tables;
 
 static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool HasREX, bool HasXMM, bool HasMM, uint8_t InvalidOffset = 16) {
-  constexpr std::array<uint64_t, 16> GPRIndexes = {
+  using GPRArray = std::array<uint32_t, 16>;
+
+  static constexpr GPRArray GPRIndexes = {
     // Classical ordering?
     FEXCore::X86State::REG_RAX,
     FEXCore::X86State::REG_RCX,
@@ -33,7 +50,7 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_R15,
   };
 
-  constexpr std::array<uint64_t, 16> GPR8BitHighIndexes = {
+  static constexpr GPRArray GPR8BitHighIndexes = {
     // Classical ordering?
     FEXCore::X86State::REG_RAX,
     FEXCore::X86State::REG_RCX,
@@ -53,7 +70,7 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_R15,
   };
 
-  constexpr std::array<uint64_t, 16> XMMIndexes = {
+  static constexpr GPRArray XMMIndexes = {
     FEXCore::X86State::REG_XMM_0,
     FEXCore::X86State::REG_XMM_1,
     FEXCore::X86State::REG_XMM_2,
@@ -72,7 +89,7 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_XMM_15,
   };
 
-  constexpr std::array<uint64_t, 16> MMIndexes = {
+  static constexpr GPRArray MMIndexes = {
     FEXCore::X86State::REG_MM_0,
     FEXCore::X86State::REG_MM_1,
     FEXCore::X86State::REG_MM_2,
@@ -91,7 +108,7 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_INVALID
   };
 
-  const std::array<uint64_t, 16> *GPRs = &GPRIndexes;
+  const GPRArray *GPRs = &GPRIndexes;
   if (HasXMM) {
     GPRs = &XMMIndexes;
   }
@@ -110,45 +127,94 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
   return (*GPRs)[(REX << 3) | bits];
 }
 
+static uint32_t MapVEXToReg(uint8_t vvvv, bool HasXMM) {
+  using GPRArray = std::array<uint32_t, 16>;
+
+  static constexpr GPRArray GPRIndexes = {
+    FEXCore::X86State::REG_RAX,
+    FEXCore::X86State::REG_RCX,
+    FEXCore::X86State::REG_RDX,
+    FEXCore::X86State::REG_RBX,
+    FEXCore::X86State::REG_RSP,
+    FEXCore::X86State::REG_RBP,
+    FEXCore::X86State::REG_RSI,
+    FEXCore::X86State::REG_RDI,
+    FEXCore::X86State::REG_R8,
+    FEXCore::X86State::REG_R9,
+    FEXCore::X86State::REG_R10,
+    FEXCore::X86State::REG_R11,
+    FEXCore::X86State::REG_R12,
+    FEXCore::X86State::REG_R13,
+    FEXCore::X86State::REG_R14,
+    FEXCore::X86State::REG_R15,
+  };
+
+  static constexpr GPRArray XMMIndexes = {
+    FEXCore::X86State::REG_XMM_0,
+    FEXCore::X86State::REG_XMM_1,
+    FEXCore::X86State::REG_XMM_2,
+    FEXCore::X86State::REG_XMM_3,
+    FEXCore::X86State::REG_XMM_4,
+    FEXCore::X86State::REG_XMM_5,
+    FEXCore::X86State::REG_XMM_6,
+    FEXCore::X86State::REG_XMM_7,
+    FEXCore::X86State::REG_XMM_8,
+    FEXCore::X86State::REG_XMM_9,
+    FEXCore::X86State::REG_XMM_10,
+    FEXCore::X86State::REG_XMM_11,
+    FEXCore::X86State::REG_XMM_12,
+    FEXCore::X86State::REG_XMM_13,
+    FEXCore::X86State::REG_XMM_14,
+    FEXCore::X86State::REG_XMM_15,
+  };
+
+  if (HasXMM) {
+    return XMMIndexes[vvvv];
+  } else {
+    return GPRIndexes[vvvv];
+  }
+}
+
 Decoder::Decoder(FEXCore::Context::Context *ctx)
-  : CTX {ctx} {
-  DecodedBuffer.resize(DefaultDecodedBufferSize);
+  : CTX {ctx}
+  , OSABI { ctx->SyscallHandler ? ctx->SyscallHandler->GetOSABI() : FEXCore::HLE::SyscallOSABI::OS_UNKNOWN } {
+  // Using mmap is a start-up time optimization
+  // Take advantage of page faulting to reduce startup time for minimal runtime cost
+  DecodedBuffer =
+    reinterpret_cast<FEXCore::X86Tables::DecodedInst *>(
+      FEXCore::Allocator::mmap(0, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize,
+      PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+}
+
+Decoder::~Decoder() {
+  FEXCore::Allocator::munmap(DecodedBuffer, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize);
 }
 
 uint8_t Decoder::ReadByte() {
   uint8_t Byte = InstStream[InstructionSize];
-  LogMan::Throw::A(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
+  LOGMAN_THROW_A_FMT(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
   Instruction[InstructionSize] = Byte;
   InstructionSize++;
   return Byte;
 }
 
-uint8_t Decoder::PeekByte(uint8_t Offset) {
+uint8_t Decoder::PeekByte(uint8_t Offset) const {
   uint8_t Byte = InstStream[InstructionSize + Offset];
   return Byte;
 }
 
 uint64_t Decoder::ReadData(uint8_t Size) {
-  uint64_t Res{};
-#define READ_DATA(x, y) \
-  case x: { \
-    y const *Data = reinterpret_cast<y const*>(&InstStream[InstructionSize]); \
-    Res = *Data; \
-  } \
-  break
-
-  switch (Size) {
-  case 0: return 0;
-  READ_DATA(1, uint8_t);
-  READ_DATA(2, uint16_t);
-  case 3: memcpy(&Res, &InstStream[InstructionSize], Size);
-  READ_DATA(4, uint32_t);
-  READ_DATA(8, uint64_t);
-  default:
-  LogMan::Msg::A("Unknown data size to read");
-  return 0;
+  if (Size == 0) {
+    return 0;
   }
-#undef READ_DATA
+
+  if (Size > sizeof(uint64_t)) {
+    LOGMAN_MSG_A_FMT("Unknown data size to read");
+    return 0;
+  }
+
+  uint64_t Res = 0;
+  std::memcpy(&Res, &InstStream[InstructionSize], Size);
 
 #ifndef NDEBUG
   for(size_t i = 0; i < Size; ++i) {
@@ -157,6 +223,7 @@ uint64_t Decoder::ReadData(uint8_t Size) {
 #else
   SkipBytes(Size);
 #endif
+
   return Res;
 }
 
@@ -197,9 +264,9 @@ void Decoder::DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     }
   }
 
-  Operand->TypeSIB.Type = DecodedOperand::TYPE_SIB;
-  Operand->TypeSIB.Scale = 1;
-  Operand->TypeSIB.Offset = Literal;
+  Operand->Type = DecodedOperand::OpType::SIB;
+  Operand->Data.SIB.Scale = 1;
+  Operand->Data.SIB.Offset = Literal;
 
   // Only called when ModRM.mod != 0b11
   struct Encodings {
@@ -212,34 +279,34 @@ void Decoder::DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {255, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_INVALID, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
     // Mod = 0b01
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {FEXCore::X86State::REG_RBP, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
     // Mod = 0b10
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {FEXCore::X86State::REG_RBP, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
   }};
 
   uint8_t LookupIndex = ModRM.mod << 3 | ModRM.rm;
   auto it = Lookup[LookupIndex];
-  Operand->TypeSIB.Base = it.Base;
-  Operand->TypeSIB.Index = it.Index;
+  Operand->Data.SIB.Base = it.Base;
+  Operand->Data.SIB.Index = it.Index;
 }
 
 void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM) {
@@ -277,79 +344,77 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     }
 
     // SIB
-    Operand->TypeSIB.Type = DecodedOperand::TYPE_SIB;
-    Operand->TypeSIB.Scale = 1 << SIB.scale;
+    Operand->Type = DecodedOperand::OpType::SIB;
+    Operand->Data.SIB.Scale = 1 << SIB.scale;
 
     // The invalid encoding types are described at Table 1-12. "promoted nsigned is always non-zero"
-    Operand->TypeSIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
-    Operand->TypeSIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
+    Operand->Data.SIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
+    Operand->Data.SIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
 
-    uint64_t Literal {0};
-    LogMan::Throw::A(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
+    LOGMAN_THROW_A_FMT(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
 
-    Literal = ReadData(Displacement);
+    uint64_t Literal = ReadData(Displacement);
     if (Displacement == 1) {
       Literal = static_cast<int8_t>(Literal);
     }
-    Operand->TypeSIB.Offset = Literal;
+    Operand->Data.SIB.Offset = Literal;
   }
   else if (ModRM.mod == 0) {
     // Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes"
     if (ModRM.rm == 0b101) {
       // 32bit Displacement
-      uint32_t Literal;
-      Literal = ReadData(4);
+      const uint32_t Literal = ReadData(4);
 
-      Operand->TypeRIPLiteral.Type = DecodedOperand::TYPE_RIP_RELATIVE;
-      Operand->TypeRIPLiteral.Literal.u = Literal;
+      Operand->Type = DecodedOperand::OpType::RIPRelative;
+      Operand->Data.RIPLiteral.Value.u = Literal;
     }
     else {
       // Register-direct addressing
-      Operand->TypeGPR.Type = DecodedOperand::TYPE_GPR_DIRECT;
-      Operand->TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
+      Operand->Type = DecodedOperand::OpType::GPRDirect;
+      Operand->Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
     }
   }
   else {
     uint8_t DisplacementSize = ModRM.mod == 1 ? 1 : 4;
-    uint32_t Literal{};
-    Literal = ReadData(DisplacementSize);
+    uint32_t Literal = ReadData(DisplacementSize);
     if (DisplacementSize == 1) {
       Literal = static_cast<int8_t>(Literal);
     }
     Displacement = DisplacementSize;
 
-    Operand->TypeGPRIndirect.Type = DecodedOperand::TYPE_GPR_INDIRECT;
-    Operand->TypeGPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
-    Operand->TypeGPRIndirect.Displacement = Literal;
+    Operand->Type = DecodedOperand::OpType::GPRIndirect;
+    Operand->Data.GPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
+    Operand->Data.GPRIndirect.Displacement = Literal;
   }
 }
 
-bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op) {
+bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, DecodedHeader Options) {
   DecodeInst->OP = Op;
   DecodeInst->TableInfo = Info;
 
   // XXX: Once we support 32bit x86 then this will be necessary to support
   if (Info->Type == FEXCore::X86Tables::TYPE_LEGACY_PREFIX) {
-    LogMan::Msg::D("Legacy Prefix");
+    LogMan::Msg::DFmt("Legacy Prefix");
     return false;
   }
 
   if (Info->Type == FEXCore::X86Tables::TYPE_UNKNOWN) {
-    LogMan::Msg::D("Unknown instruction: %s 0x%04x 0x%lx", Info->Name, Op, DecodeInst->PC);
+    LogMan::Msg::DFmt("Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
     return false;
   }
 
   if (Info->Type == FEXCore::X86Tables::TYPE_INVALID) {
-    LogMan::Msg::D("Invalid or Unknown instruction: %s 0x%04x 0x%lx", Info->Name, Op, DecodeInst->PC);
+    LogMan::Msg::DFmt("Invalid or Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
     return false;
   }
 
-  LogMan::Throw::A(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
-    "Group Ops should have been decoded before this!");
+  LOGMAN_THROW_A_FMT(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
+                     "Group Ops should have been decoded before this!");
 
   uint8_t DestSize{};
-  bool HasWideningDisplacement = FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_WIDENING_SIZE_LAST;
-  bool HasNarrowingDisplacement = FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST;
+  const bool HasWideningDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_WIDENING_SIZE_LAST) != 0 ||
+                                       (Options.w && CTX->Config.Is64BitMode);
+  const bool HasNarrowingDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST) != 0;
 
   bool HasXMMSrc = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
     !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_GPR) &&
@@ -382,8 +447,8 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
   // New instruction size decoding
   {
     // Decode destinations first
-    uint32_t DstSizeFlag = FEXCore::X86Tables::InstFlags::GetSizeDstFlags(Info->Flags);
-    uint32_t SrcSizeFlag = FEXCore::X86Tables::InstFlags::GetSizeSrcFlags(Info->Flags);
+    const auto DstSizeFlag = FEXCore::X86Tables::InstFlags::GetSizeDstFlags(Info->Flags);
+    const auto SrcSizeFlag = FEXCore::X86Tables::InstFlags::GetSizeSrcFlags(Info->Flags);
 
     if (DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_8BIT) {
       DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_8BIT);
@@ -460,22 +525,25 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ||
       HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RDX)) {
     // Some instructions hardcode their destination as RAX
-    CurrentDest->TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    CurrentDest->TypeGPR.HighBits = false;
-    CurrentDest->TypeGPR.GPR = HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ? FEXCore::X86State::REG_RAX : FEXCore::X86State::REG_RDX;
+    CurrentDest->Type = DecodedOperand::OpType::GPR;
+    CurrentDest->Data.GPR.HighBits = false;
+    CurrentDest->Data.GPR.GPR = HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ? FEXCore::X86State::REG_RAX : FEXCore::X86State::REG_RDX;
     CurrentDest = &DecodeInst->Src[0];
   }
 
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) {
-    LogMan::Throw::A(!HasMODRM, "This instruction shouldn't have ModRM!");
+    LOGMAN_THROW_A_FMT(!HasMODRM, "This instruction shouldn't have ModRM!");
 
     // If the REX is in the byte that means the lower nibble of the OP contains the destination GPR
     // This also means that the destination is always a GPR on these ones
     // ADDITIONALLY:
     // If there is a REX prefix then that allows extended GPR usage
-    CurrentDest->TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Dest.TypeGPR.HighBits = (Is8BitDest && !HasREX && (Op & 0b111) >= 0b100) || HasHighXMM;
-    CurrentDest->TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, Op & 0b111, Is8BitDest, HasREX, false, false);
+    CurrentDest->Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Dest.Data.GPR.HighBits = (Is8BitDest && !HasREX && (Op & 0b111) >= 0b100) || HasHighXMM;
+    CurrentDest->Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, Op & 0b111, Is8BitDest, HasREX, false, false);
+
+    if (CurrentDest->Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+      return false;
   }
 
   uint8_t Bytes = Info->MoreBytes;
@@ -498,55 +566,83 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
     ModRM.Hex = DecodeInst->ModRM;
 
     // Decode the GPR source first
-    GPR.TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    GPR.TypeGPR.HighBits = (GPR8Bit && ModRM.reg >= 0b100 && !HasREX) || HasHighXMM;
-    GPR.TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_R ? 1 : 0, ModRM.reg, GPR8Bit, HasREX, HasXMMGPR, HasMMGPR);
+    GPR.Type = DecodedOperand::OpType::GPR;
+    GPR.Data.GPR.HighBits = (GPR8Bit && ModRM.reg >= 0b100 && !HasREX) || HasHighXMM;
+    GPR.Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_R ? 1 : 0, ModRM.reg, GPR8Bit, HasREX, HasXMMGPR, HasMMGPR);
+
+    if (GPR.Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+      return false;
 
     // ModRM.mod == 0b11 == Register
     // ModRM.Mod != 0b11 == Register-direct addressing
     if (ModRM.mod == 0b11) {
-      NonGPR.TypeGPR.Type = DecodedOperand::TYPE_GPR;
-      NonGPR.TypeGPR.HighBits = (NonGPR8Bit && ModRM.rm >= 0b100 && !HasREX) || HasHighXMM;
-      NonGPR.TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, NonGPR8Bit, HasREX, HasXMMNonGPR, HasMMNonGPR);
+      NonGPR.Type = DecodedOperand::OpType::GPR;
+      NonGPR.Data.GPR.HighBits = (NonGPR8Bit && ModRM.rm >= 0b100 && !HasREX) || HasHighXMM;
+      NonGPR.Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, NonGPR8Bit, HasREX, HasXMMNonGPR, HasMMNonGPR);
+      if (NonGPR.Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+        return false;
     }
     else {
       auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
       (this->*Disp)(&NonGPR, ModRM);
     }
+
+    return true;
   };
 
   size_t CurrentSrc = 0;
 
+  if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_VEX_1ST_SRC) != 0) {
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMSrc);
+    ++CurrentSrc;
+  }
+
   if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM) {
     if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SF_MOD_DST) {
-      ModRMOperand(DecodeInst->Src[CurrentSrc], DecodeInst->Dest, HasXMMSrc, HasXMMDst, HasMMSrc, HasMMDst, Is8BitSrc, Is8BitDest);
+      if (!ModRMOperand(DecodeInst->Src[CurrentSrc], DecodeInst->Dest, HasXMMSrc, HasXMMDst, HasMMSrc, HasMMDst, Is8BitSrc, Is8BitDest))
+        return false;
     }
     else {
-      ModRMOperand(DecodeInst->Dest, DecodeInst->Src[CurrentSrc], HasXMMDst, HasXMMSrc, HasMMDst, HasMMSrc, Is8BitDest, Is8BitSrc);
+      if (!ModRMOperand(DecodeInst->Dest, DecodeInst->Src[CurrentSrc], HasXMMDst, HasXMMSrc, HasMMDst, HasMMSrc, Is8BitDest, Is8BitSrc))
+        return false;
     }
     ++CurrentSrc;
   }
 
+  if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_VEX_2ND_SRC) != 0) {
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMSrc);
+    ++CurrentSrc;
+  }
+
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RAX)) {
-    DecodeInst->Src[CurrentSrc].TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Src[CurrentSrc].TypeGPR.HighBits = false;
-    DecodeInst->Src[CurrentSrc].TypeGPR.GPR = FEXCore::X86State::REG_RAX;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = FEXCore::X86State::REG_RAX;
     ++CurrentSrc;
   }
   else if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RCX)) {
-    DecodeInst->Src[CurrentSrc].TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Src[CurrentSrc].TypeGPR.HighBits = false;
-    DecodeInst->Src[CurrentSrc].TypeGPR.GPR = FEXCore::X86State::REG_RCX;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = FEXCore::X86State::REG_RCX;
     ++CurrentSrc;
   }
 
+  if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_VEX_DST) != 0) {
+    CurrentDest->Type = DecodedOperand::OpType::GPR;
+    CurrentDest->Data.GPR.HighBits = false;
+    CurrentDest->Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMDst);
+  }
+
   if (Bytes != 0) {
-    LogMan::Throw::A(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
+    LOGMAN_THROW_A_FMT(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
 
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Size = Bytes;
+    DecodeInst->Src[CurrentSrc].Data.Literal.Size = Bytes;
 
-    uint64_t Literal {0};
-    Literal = ReadData(Bytes);
+    uint64_t Literal = ReadData(Bytes);
 
     if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT) ||
         (DecodeFlags::GetSizeDstFlags(DecodeInst->Flags) == DecodeFlags::SIZE_64BIT && Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT64BIT)) {
@@ -559,15 +655,16 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
       else {
         Literal = static_cast<int32_t>(Literal);
       }
-      DecodeInst->Src[CurrentSrc].TypeLiteral.Size = DestSize;
+      DecodeInst->Src[CurrentSrc].Data.Literal.Size = DestSize;
     }
 
     Bytes = 0;
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Type = DecodedOperand::TYPE_LITERAL;
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Literal = Literal;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::Literal;
+    DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
   }
 
-  LogMan::Throw::A(Bytes == 0, "Inst at 0x%lx: 0x%04x '%s' Had an instruction of size %d with %d remaining", DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name, InstructionSize, Bytes);
+  LOGMAN_THROW_A_FMT(Bytes == 0, "Inst at 0x{:x}: 0x{:04x} '{}' Had an instruction of size {} with {} remaining",
+                     DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name ?: "UND", InstructionSize, Bytes);
   DecodeInst->InstSize = InstructionSize;
   return true;
 }
@@ -578,21 +675,22 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
 
   // XXX: Once we support 32bit x86 then this will be necessary to support
   if (Info->Type == FEXCore::X86Tables::TYPE_LEGACY_PREFIX) {
-    LogMan::Msg::D("Legacy Prefix");
+    LogMan::Msg::DFmt("Legacy Prefix");
     return false;
   }
 
   if (Info->Type == FEXCore::X86Tables::TYPE_UNKNOWN) {
-    LogMan::Msg::D("Unknown instruction: %s 0x%04x 0x%lx", Info->Name, Op, DecodeInst->PC);
+    LogMan::Msg::DFmt("Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
     return false;
   }
 
   if (Info->Type == FEXCore::X86Tables::TYPE_INVALID) {
-    LogMan::Msg::D("Invalid or Unknown instruction: %s 0x%04x 0x%lx", Info->Name, Op, DecodeInst->PC);
+    LogMan::Msg::DFmt("Invalid or Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
     return false;
   }
 
-  LogMan::Throw::A(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX, "REX PREFIX should have been decoded before this!");
+  LOGMAN_THROW_A_FMT(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX,
+                     "REX PREFIX should have been decoded before this!");
 
   if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 &&
       Info->Type <= FEXCore::X86Tables::TYPE_GROUP_11) {
@@ -648,7 +746,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
         3,
       };
       uint8_t Field = RegToField[ModRM.reg];
-      LogMan::Throw::A(Field != 255, "Invalid field selected!");
+      LOGMAN_THROW_A_FMT(Field != 255, "Invalid field selected!");
 
       LocalOp = (Field << 3) | ModRM.rm;
       return NormalOp(&SecondModRMTableOps[LocalOp], LocalOp);
@@ -670,19 +768,38 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
     return NormalOp(&X87Ops[X87Op], X87Op);
   }
   else if (Info->Type == FEXCore::X86Tables::TYPE_VEX_TABLE_PREFIX) {
+    FEXCORE_TELEMETRY_SET(VEXOpTelem, 1);
     uint16_t map_select = 1;
     uint16_t pp = 0;
+    const uint8_t Byte1 = ReadByte();
+    DecodedHeader options{};
 
-    uint8_t Byte1 = ReadByte();
+    if ((Byte1 & 0b10000000) == 0) {
+      LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "VEX.R shouldn't be 0 in 32-bit mode!");
+      DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_R;
+    }
 
     if (Op == 0xC5) { // Two byte VEX
       pp = Byte1 & 0b11;
+      options.vvvv = 15 - ((Byte1 & 0b01111000) >> 3);
     }
     else { // 0xC4 = Three byte VEX
-      uint8_t Byte2 = ReadByte();
+      const uint8_t Byte2 = ReadByte();
       pp = Byte2 & 0b11;
       map_select = Byte1 & 0b11111;
-      LogMan::Throw::A(map_select >= 1 && map_select <= 3, "We don't understand a map_select of: %d", map_select);
+      options.vvvv = 15 - ((Byte2 & 0b01111000) >> 3);
+      options.w = (Byte2 & 0b10000000) != 0;
+      if ((Byte1 & 0b01000000) == 0) {
+        LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "VEX.X shouldn't be 0 in 32-bit mode!");
+        DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_X;
+      }
+      if (CTX->Config.Is64BitMode && (Byte1 & 0b00100000) == 0) {
+        DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_B;
+      }
+      if (!(map_select >= 1 && map_select <= 3)) {
+        LogMan::Msg::EFmt("We don't understand a map_select of: {}", map_select);
+        return false;
+      }
     }
 
     uint16_t VEXOp = ReadByte();
@@ -694,6 +811,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
 
     if (LocalInfo->Type >= FEXCore::X86Tables::TYPE_VEX_GROUP_12 &&
         LocalInfo->Type <= FEXCore::X86Tables::TYPE_VEX_GROUP_17) {
+    FEXCORE_TELEMETRY_SET(VEXOpTelem, 1);
     // We have ModRM
     uint8_t ModRMByte = ReadByte();
     DecodeInst->ModRM = ModRMByte;
@@ -705,12 +823,14 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
 #define OPD(group, pp, opcode) (((group - TYPE_VEX_GROUP_12) << 4) | (pp << 3) | (opcode))
       Op = OPD(LocalInfo->Type, pp, ModRM.reg);
 #undef OPD
-      return NormalOp(&VEXTableGroupOps[Op], Op);
+      return NormalOp(&VEXTableGroupOps[Op], Op, options);
+    } else {
+      return NormalOp(LocalInfo, Op, options);
     }
-    else
-      return NormalOp(LocalInfo, Op);
   }
   else if (Info->Type == FEXCore::X86Tables::TYPE_GROUP_EVEX) {
+    FEXCORE_TELEMETRY_SET(EVEXOpTelem, 1);
+
     /* uint8_t P1 = */ ReadByte();
     /* uint8_t P2 = */ ReadByte();
     /* uint8_t P3 = */ ReadByte();
@@ -730,6 +850,8 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
   DecodeInst->PC = PC;
 
   for(;;) {
+    if (InstructionSize >= MAX_INST_SIZE)
+      return false;
     uint8_t Op = ReadByte();
     switch (Op) {
     case 0x0F: {// Escape Op
@@ -758,14 +880,20 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
       }
       case 0x38: { // F38 Table!
         constexpr uint16_t PF_38_NONE = 0;
-        constexpr uint16_t PF_38_66 = 1;
-        constexpr uint16_t PF_38_F2 = 2;
+        constexpr uint16_t PF_38_66   = (1U << 0);
+        constexpr uint16_t PF_38_F2   = (1U << 1);
+        constexpr uint16_t PF_38_F3   = (1U << 2);
 
         uint16_t Prefix = PF_38_NONE;
-        if (DecodeInst->LastEscapePrefix == 0xF2) // REPNE
-          Prefix = PF_38_F2;
-        else if (DecodeInst->LastEscapePrefix == 0x66) // Operand Size
-          Prefix = PF_38_66;
+        if (DecodeInst->Flags & DecodeFlags::FLAG_OPERAND_SIZE) {
+          Prefix |= PF_38_66;
+        }
+        if (DecodeInst->Flags & DecodeFlags::FLAG_REPNE_PREFIX) {
+          Prefix |= PF_38_F2;
+        }
+        if (DecodeInst->Flags & DecodeFlags::FLAG_REP_PREFIX) {
+          Prefix |= PF_38_F3;
+        }
 
         uint16_t LocalOp = (Prefix << 8) | ReadByte();
         return NormalOpHeader(&FEXCore::X86Tables::H0F38TableOps[LocalOp], LocalOp);
@@ -880,7 +1008,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
       auto Info = &FEXCore::X86Tables::BaseOps[Op];
 
       if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) {
-        LogMan::Throw::A(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode");
+        LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode");
         DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX;
 
         // Widening displacement
@@ -910,6 +1038,10 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
 
   }
 
+  if (DecodeInst->Dest.IsGPR()) {
+    assert(DecodeInst->Dest.Data.GPR.GPR != FEXCore::X86State::REG_INVALID);
+  }
+
   return true;
 }
 
@@ -919,6 +1051,7 @@ void Decoder::BranchTargetInMultiblockRange() {
 
   // If the RIP setting is conditional AND within our symbol range then it can be considered for multiblock
   uint64_t TargetRIP = 0;
+  const uint8_t GPRSize = CTX->GetGPRSize();
   bool Conditional = true;
 
   switch (DecodeInst->OP) {
@@ -928,24 +1061,33 @@ void Decoder::BranchTargetInMultiblockRange() {
       // auto RIPOffset = LoadSource(Op, Op->Src[0], Op->Flags);
       // auto RIPTargetConst = _Constant(Op->PC + Op->InstSize);
       // Target offset is PC + InstSize + Literal
-      LogMan::Throw::A(DecodeInst->Src[0].TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
-      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].TypeLiteral.Literal;
+      LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
     break;
     }
     case 0xE9:
     case 0xEB: // Both are unconditional JMP instructions
-      LogMan::Throw::A(DecodeInst->Src[0].TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
-      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].TypeLiteral.Literal;
+      LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
       Conditional = false;
     break;
+    case 0xE8: // Call - Immediate target, We don't want to inline calls
+      if (ExternalBranches) {
+        ExternalBranches->insert(DecodeInst->PC + DecodeInst->InstSize);
+      }
+      [[fallthrough]];
     case 0xC2: // RET imm
     case 0xC3: // RET
-    case 0xE8: // Call - Immediate target, We don't want to inline calls
     default:
       return;
     break;
   }
 
+  if (GPRSize == 4) {
+    // If we are running a 32bit guest then wrap around addresses that go above 32bit
+    TargetRIP &= 0xFFFFFFFFU;
+  }
+
   // If the target RIP is within the symbol ranges then we are golden
   if (TargetRIP >= SymbolMinAddress && TargetRIP < SymbolMaxAddress) {
     // Update our conditional branch ranges before we return
@@ -965,10 +1107,33 @@ void Decoder::BranchTargetInMultiblockRange() {
         BlocksToDecode.find(TargetRIP) == BlocksToDecode.end()) {
       BlocksToDecode.emplace(TargetRIP);
     }
+  } else {
+    if (ExternalBranches) {
+      ExternalBranches->insert(TargetRIP);
+    }
   }
 }
 
-bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC) {
+const uint8_t *Decoder::AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP) {
+  constexpr uint64_t VSyscall_Base = 0xFFFF'FFFF'FF60'0000ULL;
+  constexpr uint64_t VSyscall_End = VSyscall_Base + 0x1000;
+
+  if (OSABI == FEXCore::HLE::SyscallOSABI::OS_LINUX64 &&
+      RIP >= VSyscall_Base &&
+      RIP < VSyscall_End) {
+    // VSyscall
+    // This doesn't exist on AArch64 and on x86_64 hosts this is emulated with faults to a region mapped with --xp permissions
+    // Offset     0: vgettimeofday
+    // Offset 0x400: vtime
+    // Offset 0x800: vgetcpu
+    uint64_t Offset = RIP - VSyscall_Base;
+    return VSyscallData + Offset;
+  }
+
+  return _InstStream - EntryPoint + RIP;
+}
+
+void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC) {
   Blocks.clear();
   BlocksToDecode.clear();
   HasBlocks.clear();
@@ -982,13 +1147,12 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
   EntryPoint = PC;
   InstStream = _InstStream;
 
-  bool ErrorDuringDecoding = false;
   uint64_t TotalInstructions{};
 
   // If we don't have symbols available then we become a bit optimistic about multiblock ranges
   if (!SymbolAvailable) {
     // If we don't have a symbol available then assume all branches are valid for multiblock
-    SymbolMaxAddress = ~0ULL;
+    SymbolMaxAddress = SectionMaxAddress;
     SymbolMinAddress = EntryPoint;
   }
 
@@ -1011,20 +1175,18 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
     uint64_t BlockStartOffset = DecodedSize;
 
     // Do a bit of pointer math to figure out where we are in code
-    InstStream = _InstStream - EntryPoint + RIPToDecode;
+    InstStream = AdjustAddrForSpecialRegion(_InstStream, EntryPoint, RIPToDecode);
 
     while (1) {
-      ErrorDuringDecoding = !DecodeInstruction(RIPToDecode + PCOffset);
+      bool ErrorDuringDecoding = !DecodeInstruction(RIPToDecode + PCOffset);
 
       if (ErrorDuringDecoding) {
-        LogMan::Msg::D("Couldn't Decode something at 0x%lx, Started at 0x%lx", PC + PCOffset, PC);
-        LogMan::Throw::A(Blocks.size() != 1, "Decode Error in entry block");
-
+        LogMan::Msg::DFmt("Couldn't Decode something at 0x{:x}, Started at 0x{:x}", PC + PCOffset, PC);
+        // Put an invalid instruction in the stream so the core can raise SIGILL if hit
         CurrentBlockDecoding.HasInvalidInstruction = true;
-        if (ErrorDuringDecoding && Blocks.size() != 1) {
-          ErrorDuringDecoding = false;
-        }
-        break;
+        // Error while decoding instruction. We don't know the table or instruction size
+        DecodeInst->TableInfo = nullptr;
+        DecodeInst->InstSize = 0;
       }
 
       DecodedMinAddress = std::min(DecodedMinAddress, RIPToDecode + PCOffset);
@@ -1033,6 +1195,11 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
       ++BlockNumberOfInstructions;
       ++DecodedSize;
 
+      // Can not continue this block at all on invalid instruction
+      if (CurrentBlockDecoding.HasInvalidInstruction) {
+        break;
+      }
+
       bool CanContinue = false;
       if (!(DecodeInst->TableInfo->Flags &
           (FEXCore::X86Tables::InstFlags::FLAGS_BLOCK_END | FEXCore::X86Tables::InstFlags::FLAGS_SETS_RIP))) {
@@ -1052,7 +1219,7 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
       }
 
       if (DecodedSize >= CTX->Config.MaxInstPerBlock ||
-          DecodedSize >= DecodedBuffer.size()) {
+          DecodedSize >= DefaultDecodedBufferSize) {
         break;
       }
 
@@ -1069,7 +1236,7 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
 
     // Copy over only the number of instructions we decoded
     CurrentBlockDecoding.NumInstructions = BlockNumberOfInstructions;
-    CurrentBlockDecoding.DecodedInstructions = &DecodedBuffer.at(BlockStartOffset);
+    CurrentBlockDecoding.DecodedInstructions = &DecodedBuffer[BlockStartOffset];
   }
 
 
@@ -1077,7 +1244,6 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
   std::sort(Blocks.begin(), Blocks.end(), [](const FEXCore::Frontend::Decoder::DecodedBlocks& a, const FEXCore::Frontend::Decoder::DecodedBlocks& b) {
     return a.Entry < b.Entry;
   });
-  return !ErrorDuringDecoding;
 }
 
 }

External/FEXCore/Source/Interface/Core/Frontend.h

@@ -1,11 +1,13 @@
 #pragma once
 
 #include <FEXCore/Debug/X86Tables.h>
+#include <FEXCore/HLE/SyscallHandler.h>
+#include <FEXCore/Utils/Telemetry.h>
+
 #include <array>
 #include <cstdint>
-#include <utility>
 #include <set>
-#include <stack>
+#include <stddef.h>
 #include <vector>
 
 namespace FEXCore::Context {
@@ -24,31 +26,43 @@ public:
   };
 
   Decoder(FEXCore::Context::Context *ctx);
-  bool DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC);
+  ~Decoder();
+  void DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC);
 
-  std::vector<DecodedBlocks> const *GetDecodedBlocks() {
+  std::vector<DecodedBlocks> const *GetDecodedBlocks() const {
     return &Blocks;
   }
 
   uint64_t DecodedMinAddress {};
   uint64_t DecodedMaxAddress {~0ULL};
-  
+
+  void SetSectionMaxAddress(uint64_t v) { SectionMaxAddress = v; }
+  void SetExternalBranches(std::set<uint64_t> *v) { ExternalBranches = v; }
 private:
+  // To pass any information from instruction prefixes
+  // down into the actual instruction handling machinery.
+  struct DecodedHeader {
+    uint8_t vvvv; // Encoded operand in a VEX prefix.
+    bool w;       // VEX.W bit.
+  };
+
   FEXCore::Context::Context *CTX;
+  const FEXCore::HLE::SyscallOSABI OSABI{};
 
   bool DecodeInstruction(uint64_t PC);
 
   void BranchTargetInMultiblockRange();
 
   uint8_t ReadByte();
-  uint8_t PeekByte(uint8_t Offset);
+  uint8_t PeekByte(uint8_t Offset) const;
   uint64_t ReadData(uint8_t Size);
   void SkipBytes(uint8_t Size) { InstructionSize += Size; }
-  bool NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op);
+
+  bool NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, DecodedHeader Options = {});
   bool NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op);
 
   static constexpr size_t DefaultDecodedBufferSize = 0x10000;
-  std::vector<FEXCore::X86Tables::DecodedInst> DecodedBuffer;
+  FEXCore::X86Tables::DecodedInst *DecodedBuffer{};
   size_t DecodedSize {};
 
   uint8_t const *InstStream;
@@ -65,19 +79,26 @@ private:
   uint64_t MaxCondBranchBackwards {~0ULL};
   uint64_t SymbolMaxAddress {};
   uint64_t SymbolMinAddress {~0ULL};
+  uint64_t SectionMaxAddress {~0ULL};
 
   std::vector<DecodedBlocks> Blocks;
   std::set<uint64_t> BlocksToDecode;
   std::set<uint64_t> HasBlocks;
+  std::set<uint64_t> *ExternalBranches {nullptr};
 
   // ModRM rm decoding
   using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
   void DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
   void DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
 
-  const std::array<DecodeModRMPtr, 2> DecodeModRMs_Disp {
+  static constexpr std::array<DecodeModRMPtr, 2> DecodeModRMs_Disp{
     &FEXCore::Frontend::Decoder::DecodeModRM_64,
     &FEXCore::Frontend::Decoder::DecodeModRM_16,
   };
+
+  const uint8_t *AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP);
+
+  FEXCORE_TELEMETRY_INIT(VEXOpTelem, TYPE_USES_VEX_OPS);
+  FEXCORE_TELEMETRY_INIT(EVEXOpTelem, TYPE_USES_EVEX_OPS);
 };
 }

External/FEXCore/Source/Interface/Core/GdbServer.cpp

@@ -1,46 +1,69 @@
+/*
+$info$
+tags: glue|gdbserver
+desc: Provides a gdb interface to the guest state
+$end_info$
+*/
+
 #include <cstdlib>
 #include <cstdio>
 #include <iomanip>
-#include <iostream>
 #include <sstream>
 #include <string>
 #include <memory>
 #include <optional>
-#include "Common/NetStream.h"
+#include <vector>
 #include "Common/SoftFloat.h"
-#include <FEXCore/Utils/LogManager.h>
+#include "Interface/Context/Context.h"
 
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <netdb.h>
-#include <string.h>
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/Core/Context.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/SignalDelegator.h>
+#include <FEXCore/Core/X86Enums.h>
+#include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXCore/HLE/Linux/ThreadManagement.h>
+#include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/NetStream.h>
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/Threads.h>
+
+#include <atomic>
+#include <cstring>
+#include <errno.h>
 #include <fcntl.h>
-#include <unistd.h>
 #include <fstream>
+#include <fmt/format.h>
+#include <netdb.h>
+#include <signal.h>
+#include <stddef.h>
+#include <string_view>
+#include <sys/socket.h>
+#include <unistd.h>
+#include <utility>
+#include <vector>
 
 #include "GdbServer.h"
-#include <FEXCore/Core/CodeLoader.h>
-#include <FEXCore/Core/X86Enums.h>
 
 namespace FEXCore
 {
 
 void GdbServer::Break(int signal) {
     std::lock_guard lk(sendMutex);
+    if (!CommsStream) {
+      return;
+    }
 
-    std::ostringstream ss;
-    ss << "S" << std::setfill('0') << std::setw(2) << std::hex << signal;
-
-    if (CommsStream)
-        SendPacket(*CommsStream, ss.str());
+    const auto str = fmt::format("S{:02x}", signal);
+    SendPacket(*CommsStream, str);
 }
 
 GdbServer::GdbServer(FEXCore::Context::Context *ctx) : CTX(ctx) {
-    ctx->CustomExitHandler = [this](uint64_t ThreadId, FEXCore::Context::ExitReason ExitReason) {
+    Context::SetExitHandler(ctx, [this](uint64_t ThreadId, FEXCore::Context::ExitReason ExitReason) {
         if (ExitReason == FEXCore::Context::ExitReason::EXIT_DEBUG) {
             this->Break(SIGTRAP);
         }
-    };
+    });
 
     // This is a total hack as there is currently no way to resume once hitting a segfault
     // But it's semi-useful for debugging.
@@ -53,12 +76,12 @@ GdbServer::GdbServer(FEXCore::Context::Context *ctx) : CTX(ctx) {
           usleep(100000);
 
         return true;
-    });
+    }, true);
 
     StartThread();
 }
 
-static int calculateChecksum(std::string &packet) {
+static int calculateChecksum(const std::string &packet) {
     unsigned char checksum = 0;
     for (const char &c : packet) {
         checksum += c;
@@ -92,11 +115,9 @@ static std::string encodeHex(unsigned char *data, size_t length) {
 }
 
 static std::string getThreadName(uint32_t ThreadID) {
-  std::fstream fs;
-  std::ostringstream ThreadFile;
-  ThreadFile << "/proc/" << getpid() << "/task/" << ThreadID << "/comm";
+  const auto ThreadFile = fmt::format("/proc/{}/task/{}/comm", getpid(), ThreadID);
+  std::fstream fs(ThreadFile, std::fstream::in | std::fstream::binary);
 
-  fs.open(ThreadFile.str(), std::fstream::in | std::fstream::binary);
   if (fs.is_open()) {
     std::string ThreadName;
     fs >> ThreadName;
@@ -128,7 +149,7 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
         switch(c) {
         case '$': // start of packet
             if (packet.size() != 0)
-                LogMan::Msg::E("Dropping unexpected data: \"%s\"", packet.c_str());
+                LogMan::Msg::EFmt("Dropping unexpected data: \"{}\"", packet);
 
             // clear any existing data, must have been a mistake.
             packet = std::string();
@@ -149,7 +170,7 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
             if (calculateChecksum(packet) == expected_checksum) {
                 return packet;
             } else {
-                LogMan::Msg::E("Received Invalid Packet: $%s#%02x %c%c", packet.c_str(), expected_checksum);
+                LogMan::Msg::EFmt("Received Invalid Packet: ${}#{:02x}", packet, expected_checksum);
             }
             break;
         }
@@ -162,10 +183,10 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
     return "";
 }
 
-static std::string escapePacket(std::string packet) {
+static std::string escapePacket(const std::string& packet) {
     std::ostringstream ss;
 
-    for(auto &c : packet) {
+    for(const auto &c : packet) {
         switch (c) {
         case '$':
         case '#':
@@ -184,13 +205,11 @@ static std::string escapePacket(std::string packet) {
     return ss.str();
 }
 
-void GdbServer::SendPacket(std::ostream &stream, std::string packet) {
-  auto escaped = escapePacket(packet);
-  std::ostringstream ss;
+void GdbServer::SendPacket(std::ostream &stream, const std::string& packet) {
+  const auto escaped = escapePacket(packet);
+  const auto str = fmt::format("${}#{:02x}", escaped, calculateChecksum(escaped));
 
-  ss << '$' << escaped << '#';
-  ss << std::setfill('0') << std::setw(2) << std::hex << (int)calculateChecksum(escaped);
-  stream << ss.str() << std::flush;
+  stream << str << std::flush;
 }
 
 void GdbServer::SendACK(std::ostream &stream, bool NACK) {
@@ -211,7 +230,7 @@ void GdbServer::SendACK(std::ostream &stream, bool NACK) {
   }
 }
 
-struct __attribute__((packed)) GDBContextDefinition {
+struct FEX_PACKED GDBContextDefinition {
   uint64_t gregs[16];
   uint64_t rip;
   uint32_t eflags;
@@ -232,17 +251,17 @@ std::string GdbServer::readRegs() {
   bool Found = false;
 
   for (auto &Thread : *Threads) {
-    if (Thread->State.ThreadManager.GetTID() != CurrentDebuggingThread) {
+    if (Thread->ThreadManager.GetTID() != CurrentDebuggingThread) {
       continue;
     }
-    state = Thread->State.State;
+    memcpy(&state, Thread->CurrentFrame, sizeof(state));
     Found = true;
     break;
   }
 
   if (!Found) {
     // If set to an invalid thread then just get the parent thread ID
-    state = CTX->GetCPUState();
+    memcpy(&state, CTX->ParentThread->CurrentFrame, sizeof(state));
   }
 
   // Encode the GDB context definition
@@ -272,7 +291,7 @@ std::string GdbServer::readRegs() {
   return encodeHex((unsigned char *)&GDB, sizeof(GDBContextDefinition));
 }
 
-GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
+GdbServer::HandledPacketType GdbServer::readReg(const std::string& packet) {
 	size_t addr;
 	auto ss = std::istringstream(packet);
 	ss.get(); // Drop first letter
@@ -284,17 +303,17 @@ GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
   bool Found = false;
 
   for (auto &Thread : *Threads) {
-    if (Thread->State.ThreadManager.GetTID() != CurrentDebuggingThread) {
+    if (Thread->ThreadManager.GetTID() != CurrentDebuggingThread) {
       continue;
     }
-    state = Thread->State.State;
+    memcpy(&state, Thread->CurrentFrame, sizeof(state));
     Found = true;
     break;
   }
 
   if (!Found) {
     // If set to an invalid thread then just get the parent thread ID
-    state = CTX->GetCPUState();
+    memcpy(&state, CTX->ParentThread->CurrentFrame, sizeof(state));
   }
 
 
@@ -350,7 +369,7 @@ GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
     return {encodeHex((unsigned char *)(&Empty), sizeof(uint32_t)), HandledPacketType::TYPE_ACK};
   }
 
-  LogMan::Msg::E("Unknown GDB register 0x%lx", addr);
+  LogMan::Msg::EFmt("Unknown GDB register 0x{:x}", addr);
   return {"E00", HandledPacketType::TYPE_ACK};
 }
 
@@ -455,7 +474,49 @@ std::string buildTargetXML() {
     return xml.str();
 }
 
-GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
+std::string buildMemoryMap() {
+  std::ostringstream xml;
+
+  xml << "<?xml version='1.0'?>\n";
+
+  xml << "<!DOCTYPE memory-map>\n";
+  xml << "<memory-map>\n";
+
+  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
+  std::string Line;
+
+  while (std::getline(fs, Line)) {
+    if (fs.eof()) break;
+    uint64_t Begin, End;
+    char r,w,x,p;
+    if (sscanf(Line.c_str(), "%lx-%lx %c%c%c%c", &Begin, &End, &r, &w, &x, &p) == 6) {
+      xml << "<memory type=\"ram\" start=\"0x" << std::hex << Begin << "\" length=\"0x" << (End - Begin) << "\"/>\n";
+    }
+  }
+
+  xml << "</memory-map>\n";
+
+  xml << std::flush;
+
+  return xml.str();
+}
+
+std::string buildOSData() {
+  std::ostringstream xml;
+
+  xml << "<?xml version='1.0'?>\n";
+
+  xml << "<!DOCTYPE target SYSTEM \"osdata.dtd\">\n";
+  xml << "<osdata type=\"processes\">";
+  // XXX
+  xml << "</osdata>";
+
+  xml << std::flush;
+
+  return xml.str();
+}
+
+GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
     std::string object;
     std::string rw;
     std::string annex;
@@ -521,11 +582,11 @@ GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
 
         ThreadString.clear();
         std::ostringstream ss;
-        ss << "<?xml version=\"1.0\?>\n";
+        ss << "<?xml version=\"1.0\"?>\n";
         ss << "<threads>\n";
-        for (size_t i = 0; i < Threads->size(); ++i) {
-          auto Thread = Threads->at(i);
-          ss << "\t<thread id=\"" << std::hex << Thread->State.ThreadManager.GetTID() << "\" core=\"" << i << "\" name=\"" <<  getThreadName(Thread->State.ThreadManager.GetTID()) << "\">\n";
+        for (auto &Thread : *Threads) {
+          // Thread id is in hex without 0x prefix
+          ss << "\t<thread id=\"" << std::hex << Thread->ThreadManager.GetTID() << "\" name=\"" <<  getThreadName(Thread->ThreadManager.GetTID()) << "\">\n";
           ss << "\t</thread>\n";
         }
 
@@ -534,17 +595,30 @@ GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
         ThreadString = ss.str();
       }
 
-      return {encode(ThreadString.substr(offset, length)), HandledPacketType::TYPE_ACK};
+      return {encode(ThreadString), HandledPacketType::TYPE_ACK};
     }
+
+    if (object == "memory-map") {
+      if (offset == 0) {
+        MemoryMapString = buildMemoryMap();
+      }
+      return {encode(MemoryMapString), HandledPacketType::TYPE_ACK};
+    }
+    if (object == "osdata") {
+      if (offset == 0) {
+        OSDataString = buildOSData();
+      }
+      return {encode(OSDataString), HandledPacketType::TYPE_ACK};
+    }
+
     return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
 static size_t CheckMemMapping(uint64_t Address, size_t Size) {
   uint64_t AddressEnd = Address + Size;
-
-  std::fstream fs;
-  fs.open("/proc/self/maps", std::fstream::in | std::fstream::binary);
+  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
   std::string Line;
+
   while (std::getline(fs, Line)) {
     if (fs.eof()) break;
     uint64_t Begin, End;
@@ -561,32 +635,29 @@ static size_t CheckMemMapping(uint64_t Address, size_t Size) {
     }
   }
 
-  fs.close();
   return 0;
 }
 
 GdbServer::HandledPacketType GdbServer::handleProgramOffsets() {
-  std::fstream fs;
-  fs.open("/proc/self/maps", std::fstream::in | std::fstream::binary);
+  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
   std::string Line;
   std::string const &RuntimeExecutable = Filename();
+
   while (std::getline(fs, Line)) {
     uint64_t Begin, End;
     char Filename[255];
     if (sscanf(Line.c_str(), "%lx-%lx %*c%*c%*c%*c %*x %*x:%*x %*d%s", &Begin, &End, Filename) == 3) {
       if (RuntimeExecutable == Filename) {
-        std::ostringstream ss;
-        ss << "Text=" << std::hex << Begin << ";Data=" << std::hex << Begin << ";Bss=" << std::hex << Begin;
-        ss << std::flush;
-        return {ss.str(), HandledPacketType::TYPE_ACK};
+        auto str = fmt::format("Text={:x};Data={:x};Bss={:x}", Begin, Begin, Begin);
+        return {std::move(str), HandledPacketType::TYPE_ACK};
       }
     }
   }
-  fs.close();
+
   return {"Text=0;Data=0;Bss=0", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleMemory(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleMemory(const std::string &packet) {
     bool write;
     size_t addr;
     size_t length;
@@ -627,14 +698,84 @@ GdbServer::HandledPacketType GdbServer::handleMemory(std::string &packet) {
 }
 
 
-GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
-  auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
+GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
+  const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
+  const auto MatchStr = [](const std::string &Str, const char *str) -> bool { return Str.rfind(str, 0) == 0; };
 
-  if (match("qSupported")) {
-    return {"PacketSize=5000;xmlRegisters=i386;qXfer:exec-file:read+;qXfer:features:read+;", HandledPacketType::TYPE_ACK};
+  const auto split = [](const std::string &Str, char deliminator) -> std::vector<std::string> {
+    std::vector<std::string> Elements;
+    std::istringstream Input(Str);
+    for (std::string line;
+         std::getline(Input, line);
+         Elements.emplace_back(line));
+    return Elements;
+  };
+
+  if (match("QNonStop:")) {
+    auto ss = std::istringstream(packet);
+    ss.seekg(std::string("QNonStop:").size());
+    ss.get(); // discard colon
+    ss >> NonStopMode;
+    return {"OK", HandledPacketType::TYPE_ACK};
+  }
+  if (match("qSupported:")) {
+    // eg: qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+;memory-tagging+;xmlRegisters=i386
+    auto Features = split(packet.substr(strlen("qSupported:")), ';');
+
+    // For feature documentation
+    // https://sourceware.org/gdb/current/onlinedocs/gdb/General-Query-Packets.html#qSupported
+    std::string SupportedFeatures{};
+
+    // Required features
+    SupportedFeatures += "PacketSize=5000;";
+    SupportedFeatures += "xmlRegisters=i386;";
+
+    // XXX: Not yet supported, would be easy
+    // SupportedFeatures += "qXfer:auxv-file:read+";
+    SupportedFeatures += "qXfer:exec-file:read+;";
+    SupportedFeatures += "qXfer:features:read+;";
+    // XXX: Requires parsing the ELF and watching the library list
+    // SupportedFeatures += "qXfer:libraries:read+;";
+    SupportedFeatures += "qXfer:memory-map:read+;";
+    SupportedFeatures += "qXfer:siginfo:read+;";
+    SupportedFeatures += "qXfer:siginfo:write+;";
+    // XXX: Allowing this causes GDB to crash
+    SupportedFeatures += "qXfer:threads:read+;";
+    // QCatchSignals
+    // QPassSignals
+    SupportedFeatures += "QNonStop+;";
+
+    SupportedFeatures += "qXfer:osdata:read+;";
+
+    // Causes GDB to crash?
+    // SupportedFeatures += "QStartNoAckMode+;";
+
+    for (auto &Feature : Features) {
+
+      if (MatchStr(Feature, "swbreak+")) {
+        SupportedFeatures += "swbreak+;";
+      }
+      if (MatchStr(Feature, "hwbreak+")) {
+        SupportedFeatures += "hwbreak+;";
+      }
+      if (MatchStr(Feature, "vContSupported+")) {
+        SupportedFeatures += "vContSupported+;";
+      }
+
+      // Unsupported:
+      //  multiprocess
+      //  qRelocInsn
+      //  fork-events
+      //  vfork-events
+      //  exec-events
+      //  QThreadEvents
+      //  no-resumed
+      //  memory-tagging
+    }
+    return {SupportedFeatures, HandledPacketType::TYPE_ACK};
   }
   if (match("qAttached")) {
-    return {"1", HandledPacketType::TYPE_ACK}; // We don't currently support launching executables from gdb.
+    return {"tnotrun:0", HandledPacketType::TYPE_ACK}; // We don't currently support launching executables from gdb.
   }
   if (match("qXfer")) {
     return handleXfer(packet);
@@ -653,7 +794,10 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
     ss << "m";
     for (size_t i = 0; i < Threads->size(); ++i) {
       auto Thread = Threads->at(i);
-      ss << std::hex << Thread->State.ThreadManager.TID << ",";
+      ss << std::hex << Thread->ThreadManager.TID;
+      if (i != (Threads->size() - 1)) {
+        ss << ",";
+      }
     }
     return {ss.str(), HandledPacketType::TYPE_ACK};
   }
@@ -672,7 +816,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
   if (match("qC")) {
     // Returns the current Thread ID
     std::ostringstream ss;
-    ss << "m" <<  std::hex << CTX->ParentThread->State.ThreadManager.TID;
+    ss << "m" <<  std::hex << CTX->ParentThread->ThreadManager.TID;
     return {ss.str(), HandledPacketType::TYPE_ACK};
   }
   if (match("QStartNoAckMode")) {
@@ -686,8 +830,32 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
   return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
-GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
-    auto match = [&](std::string str) -> std::optional<std::istringstream> {
+
+GdbServer::HandledPacketType GdbServer::ThreadAction(char action, uint32_t tid) {
+  switch (action) {
+    case 'c': {
+      CTX->Run();
+      CTX->WaitForThreadsToRun();
+      return {"", HandledPacketType::TYPE_ONLYACK};
+    }
+    case 's': {
+      CTX->Step();
+      SendPacketPair({"OK", HandledPacketType::TYPE_ACK});
+      auto str = fmt::format("T05thread:{:02x};core:2c;", getpid());
+      SendPacketPair({std::move(str), HandledPacketType::TYPE_ACK});
+      return {"OK", HandledPacketType::TYPE_ACK};
+    }
+    case 't':
+      // This thread isn't part of the thread pool
+      CTX->Stop(false /* Ignore current thread */);
+      return {"OK", HandledPacketType::TYPE_ACK};
+    default:
+      return {"E00", HandledPacketType::TYPE_ACK};
+  }
+}
+
+GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
+    const auto match = [&](const std::string& str) -> std::optional<std::istringstream> {
         if (packet.rfind(str, 0) == 0) {
             auto ss = std::istringstream(packet);
             ss.seekg(str.size());
@@ -696,18 +864,11 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         return std::nullopt;
     };
 
-    auto F = [](int result) {
-        std::ostringstream ss;
-        ss << "F" << std::hex << result;
-        return ss.str(); };
-    auto F_error = [&]() {
-        std::ostringstream ss;
-        ss << "F-1," << std::hex << errno;
-        return ss.str(); };
-    auto F_data = [&](int result, std::string data) {
-        std::ostringstream ss;
-        ss << "F" << std::hex << result << ";" << data;
-        return ss.str(); };
+    const auto F       = [](int result) { return fmt::format("F{:x}", result); };
+    const auto F_error = [] { return fmt::format("F-1,{:x}", errno); };
+    const auto F_data  = [](int result, const std::string& data) {
+        return fmt::format("F{:x};{}", result, data);
+    };
 
     std::optional<std::istringstream> ss;
     if((ss = match("vFile:open:"))) {
@@ -729,11 +890,11 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         return {F(pid == 0 ? 0 : -1), HandledPacketType::TYPE_ACK}; // Only support the common filesystem
     }
     if((ss = match("vFile:close:"))) {
-			int fd;
-			*ss >> std::hex >> fd;
-			close(fd);
-			return {F(0), HandledPacketType::TYPE_ACK};
-		}
+      int fd;
+      *ss >> std::hex >> fd;
+      close(fd);
+      return {F(0), HandledPacketType::TYPE_ACK};
+    }
     if((ss = match("vFile:pread:"))) {
         int fd, count, offset;
 
@@ -755,52 +916,31 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         return {F_data(ret, data), HandledPacketType::TYPE_ACK};
     }
     if ((ss = match("vCont?"))) {
-        return {"vCont;c;C;t;s;S;r", HandledPacketType::TYPE_ACK}; // We support continue, step and terminate
-                                // FIXME: We also claim to support continue with signal... because it's compulsory
+      return {"vCont;c;t;s;r", HandledPacketType::TYPE_ACK}; // We support continue, step and terminate
+      // FIXME: We also claim to support continue with signal... because it's compulsory
     }
     if ((ss = match("vCont;"))) {
-        char action;
-        int thread;
+      char action{};
+      int thread{};
 
-        action = ss->get();
+      action = ss->get();
 
-        if (ss->peek() == ':') {
-            ss->get();
-            *ss >> std::hex >> thread;
-        }
+      if (ss->peek() == ':') {
+        ss->get();
+        *ss >> std::hex >> thread;
+      }
 
-        if (ss->fail()) {
- 						return {"E00", HandledPacketType::TYPE_ACK};
-        }
-
-        switch (action) {
-        case 'c': {
-            CTX->Run();
-            return {"", HandledPacketType::TYPE_ONLYACK};
-          }
-        case 's': {
-            CTX->Step();
-						SendPacketPair({"OK", HandledPacketType::TYPE_ACK});
-            std::ostringstream ss;
-            ss << "T05thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-
-            SendPacketPair({ss.str(), HandledPacketType::TYPE_ACK});
-            return {"OK", HandledPacketType::TYPE_ACK};
-          }
-        case 't':
-            // This thread isn't part of the thread pool
-            CTX->Stop(false /* Ignore current thread */);
- 						return {"OK", HandledPacketType::TYPE_ACK};
-        default:
- 						return {"E00", HandledPacketType::TYPE_ACK};
-        }
+      if (ss->fail()) {
+        return {"E00", HandledPacketType::TYPE_ACK};
+      }
 
+      return ThreadAction(action, thread);
     }
-		return {"", HandledPacketType::TYPE_ACK};
+    return {"", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
-  auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
+GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet) {
+  const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
 
   if (match("Hc")) {
     // Sets thread to this ID for stepping
@@ -816,7 +956,7 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
   if (match("Hg")) {
     // Sets thread for "other" operations
     auto ss = std::istringstream(packet);
-    ss.seekg(std::string("Hg").size());
+    ss.seekg(std::string_view("Hg").size());
     ss >> std::hex >> CurrentDebuggingThread;
 
     // This must return quick otherwise IDA complains
@@ -827,10 +967,11 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
   return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
-GdbServer::HandledPacketType GdbServer::handleBreakpoint(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleBreakpoint(const std::string &packet) {
   auto ss = std::istringstream(packet);
 
-  bool Set{};
+  // Don't do anything with set breakpoints yet
+  [[maybe_unused]] bool Set{};
   uint64_t Addr;
   uint64_t Type;
   Set = ss.get() == 'Z';
@@ -843,19 +984,30 @@ GdbServer::HandledPacketType GdbServer::handleBreakpoint(std::string &packet) {
   return {"OK", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::ProcessPacket(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::ProcessPacket(const std::string &packet) {
   switch (packet[0]) {
     case '?': {
       // Indicates the reason that the thread has stopped
       // Behaviour changes if the target is in non-stop mode
       // Binja doesn't support S response here
-      //return {"S00", HandledPacketType::TYPE_ACK};
-      std::ostringstream ss;
-      ss << "T00thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-
-      return {ss.str(), HandledPacketType::TYPE_ACK};
+      auto str = fmt::format("T00thread:{:x};", getpid());
+      return {std::move(str), HandledPacketType::TYPE_ACK};
     }
+    case 'c':
+      // Continue
+      CTX->Run();
+      CTX->WaitForThreadsToRun();
+      return {"OK", HandledPacketType::TYPE_ACK};
+    case 'D':
+      // Detach
+      // Ensure the threads are back in running state on detach
+      CTX->Run();
+      CTX->WaitForThreadsToRun();
+      return {"OK", HandledPacketType::TYPE_ACK};
     case 'g':
+      // We might be running while we try reading
+      // Pause up front
+      CTX->Pause();
       return {readRegs(), HandledPacketType::TYPE_ACK};
     case 'p':
       return readReg(packet);
@@ -872,6 +1024,8 @@ GdbServer::HandledPacketType GdbServer::ProcessPacket(std::string &packet) {
     case '!': // Enable extended mode
     case 'T': // Is a thread alive?
       return {"OK", HandledPacketType::TYPE_ACK};
+    case 's': // Step
+      return ThreadAction('s', 0);
     case 'Z': // Inserts breakpoint or watchpoint
       return handleBreakpoint(packet);
     case 'k': // Kill the process
@@ -883,14 +1037,14 @@ GdbServer::HandledPacketType GdbServer::ProcessPacket(std::string &packet) {
   }
 }
 
-void GdbServer::SendPacketPair(HandledPacketType response) {
+void GdbServer::SendPacketPair(const HandledPacketType& response) {
   std::lock_guard lk(sendMutex);
   if (response.TypeResponse == HandledPacketType::TYPE_ACK ||
       response.TypeResponse == HandledPacketType::TYPE_ONLYACK) {
     SendACK(*CommsStream, false);
   }
   else if (response.TypeResponse == HandledPacketType::TYPE_NACK ||
-      response.TypeResponse == HandledPacketType::TYPE_ONLYNACK) {
+           response.TypeResponse == HandledPacketType::TYPE_ONLYNACK) {
     SendACK(*CommsStream, true);
   }
 
@@ -898,13 +1052,15 @@ void GdbServer::SendPacketPair(HandledPacketType response) {
     SendPacket(*CommsStream, "");
   }
   else if (response.TypeResponse != HandledPacketType::TYPE_ONLYNACK &&
-      response.TypeResponse != HandledPacketType::TYPE_ONLYACK &&
-      response.TypeResponse != HandledPacketType::TYPE_NONE) {
+           response.TypeResponse != HandledPacketType::TYPE_ONLYACK &&
+           response.TypeResponse != HandledPacketType::TYPE_NONE) {
     SendPacket(*CommsStream, response.Response);
   }
 }
 
 void GdbServer::GdbServerLoop() {
+  OpenListenSocket();
+
   while (!CTX->CoreShuttingDown.load()) {
     CommsStream = OpenSocket();
 
@@ -920,7 +1076,7 @@ void GdbServer::GdbServerLoop() {
             response = ProcessPacket(packet);
             SendPacketPair(response);
             if (response.TypeResponse == HandledPacketType::TYPE_UNKNOWN) {
-              LogMan::Msg::D("Unknown packet %s", packet.c_str());
+              LogMan::Msg::DFmt("Unknown packet {}", packet);
             }
             break;
         }
@@ -936,67 +1092,76 @@ void GdbServer::GdbServerLoop() {
             break;
         case '\x03': { // ASCII EOT
             CTX->Pause();
-            std::ostringstream ss;
-            ss << "T02thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-            SendPacketPair({ss.str(), HandledPacketType::TYPE_ACK});
+            auto str = fmt::format("T02thread:{:02x};core:2c;", getpid());
+            SendPacketPair({std::move(str), HandledPacketType::TYPE_ACK});
             break;
           }
         default:
-            LogMan::Msg::D("GdbServer: Unexpected byte %c (%02x)", c, c);
+            LogMan::Msg::DFmt("GdbServer: Unexpected byte {} ({:02x})", static_cast<char>(c), c);
         }
     }
 
     {
         std::lock_guard lk(sendMutex);
-        CommsStream.release();
+        CommsStream.reset();
     }
   }
+
+  close(ListenSocket);
+}
+static void* ThreadHandler(void *Arg) {
+  FEXCore::GdbServer *This = reinterpret_cast<FEXCore::GdbServer*>(Arg);
+  This->GdbServerLoop();
+  return nullptr;
 }
 
 void GdbServer::StartThread() {
-    gdbServerThread = std::thread(&GdbServer::GdbServerLoop, this);
+  uint64_t OldMask = FEXCore::Threads::SetSignalMask(~0ULL);
+  gdbServerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
+  FEXCore::Threads::SetSignalMask(OldMask);
+}
+
+void GdbServer::OpenListenSocket() {
+  // open socket
+  struct addrinfo hints, *res;
+
+  memset(&hints, 0, sizeof(hints));
+  hints.ai_family = AF_UNSPEC;
+  hints.ai_socktype = SOCK_STREAM;
+  hints.ai_flags = AI_PASSIVE;
+
+  if(getaddrinfo(NULL, "8086", &hints, &res) < 0) {
+    perror("getaddrinfo");
+  }
+
+  int on = 1;
+
+  ListenSocket = socket(res->ai_family, res->ai_socktype, res->ai_protocol);
+  if (ListenSocket < 0) {
+    perror("socket");
+  }
+  if(setsockopt(ListenSocket, SOL_SOCKET, SO_REUSEADDR, (char*)&on, sizeof(on)) < 0) {
+    perror("setsockopt");
+    close(ListenSocket);
+  }
+
+  if (bind(ListenSocket, res->ai_addr, res->ai_addrlen) < 0) {
+    perror("bind");
+    close(ListenSocket);
+  }
+
+  listen(ListenSocket, 1);
 }
 
 std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
-    // open socket
-    int sockfd, new_fd;
+  // Block until a connection arrives
+  struct sockaddr_storage their_addr;
+  socklen_t addr_size;
 
-    struct addrinfo hints, *res;
-    struct sockaddr_storage their_addr;
-    socklen_t addr_size;
+  LogMan::Msg::IFmt("GdbServer, waiting for connection on localhost:8086");
+  int new_fd = accept(ListenSocket, (struct sockaddr *)&their_addr, &addr_size);
 
-
-    memset(&hints, 0, sizeof(hints));
-    hints.ai_family = AF_UNSPEC;
-    hints.ai_socktype = SOCK_STREAM;
-    hints.ai_flags = AI_PASSIVE;
-
-    if(getaddrinfo(NULL, "8086", &hints, &res) < 0) {
-        perror("getaddrinfo");
-    }
-
-    int on = 1;
-
-    sockfd = socket(res->ai_family, res->ai_socktype, res->ai_protocol);
-    if (sockfd < 0) {
-        perror("socket");
-    }
-    if(setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, (char*)&on, sizeof(on)) < 0) {
-        perror("setsockopt");
-    }
-
-    if (bind(sockfd, res->ai_addr, res->ai_addrlen) < 0) {
-        perror("bind");
-    }
-
-    // Block until a connection arrives
-
-    LogMan::Msg::I("GdbServer, waiting for connection on localhost:8086");
-    listen(sockfd, 1);
-
-    new_fd = accept(sockfd, (struct sockaddr *)&their_addr, &addr_size);
-
-    return std::make_unique<NetStream>(new_fd);
+  return std::make_unique<FEXCore::Utils::NetStream>(new_fd);
 }
 
 

External/FEXCore/Source/Interface/Core/GdbServer.h

@@ -1,25 +1,40 @@
+/*
+$info$
+tags: glue|gdbserver
+$end_info$
+*/
+#pragma once
 
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/Utils/Threads.h>
+
+#include <istream>
+#include <memory>
 #include <mutex>
-#include <thread>
-
-#include "Interface/Context/Context.h"
-
-#include "Common/NetStream.h"
+#include <stdint.h>
+#include <string>
 
 namespace FEXCore {
 
+namespace Context {
+  struct Context;
+}
+
 class GdbServer {
 public:
     GdbServer(FEXCore::Context::Context *ctx);
 
+    // Public for threading
+    void GdbServerLoop();
+
 private:
     void Break(int signal);
 
+    void OpenListenSocket();
     std::unique_ptr<std::iostream> OpenSocket();
     void StartThread();
-    void GdbServerLoop();
     std::string ReadPacket(std::iostream &stream);
-    void SendPacket(std::ostream &stream, std::string packet);
+    void SendPacket(std::ostream &stream, const std::string& packet);
 
     void SendACK(std::ostream &stream, bool NACK);
 
@@ -36,28 +51,35 @@ private:
       ResponseType TypeResponse{};
     };
 
-    void SendPacketPair(HandledPacketType packetPair);
-    HandledPacketType ProcessPacket(std::string &packet);
-    HandledPacketType handleQuery(std::string &packet);
-    HandledPacketType handleXfer(std::string &packet);
-    HandledPacketType handleMemory(std::string &packet);
-    HandledPacketType handleV(std::string& packet);
-    HandledPacketType handleThreadOp(std::string &packet);
-    HandledPacketType handleBreakpoint(std::string &packet);
+    void SendPacketPair(const HandledPacketType& packetPair);
+    HandledPacketType ProcessPacket(const std::string &packet);
+    HandledPacketType handleQuery(const std::string &packet);
+    HandledPacketType handleXfer(const std::string &packet);
+    HandledPacketType handleMemory(const std::string &packet);
+    HandledPacketType handleV(const std::string& packet);
+    HandledPacketType handleThreadOp(const std::string &packet);
+    HandledPacketType handleBreakpoint(const std::string &packet);
     HandledPacketType handleProgramOffsets();
 
+    HandledPacketType ThreadAction(char action, uint32_t tid);
+
     std::string readRegs();
-    HandledPacketType readReg(std::string& packet);
+    HandledPacketType readReg(const std::string& packet);
 
     FEXCore::Context::Context *CTX;
-    std::thread gdbServerThread;
+    std::unique_ptr<FEXCore::Threads::Thread> gdbServerThread;
     std::unique_ptr<std::iostream> CommsStream;
     std::mutex sendMutex;
     bool SettingNoAckMode{false};
     bool NoAckMode{false};
+    bool NonStopMode{false};
     std::string ThreadString{};
+    std::string MemoryMapString{};
+    std::string OSDataString{};
+
     uint32_t CurrentDebuggingThread{};
-    FEXCore::Config::Value<std::string> Filename{FEXCore::Config::CONFIG_APP_FILENAME, ""};
+    int ListenSocket{};
+    FEX_CONFIG_OPT(Filename, APP_FILENAME);
 };
 
 }

External/FEXCore/Source/Interface/Core/HostFeatures.cpp

@@ -1,3 +1,4 @@
+#include "Interface/Core/CPUID.h"
 #include "Interface/Core/HostFeatures.h"
 
 #ifdef _M_ARM_64
@@ -13,14 +14,103 @@
 
 namespace FEXCore {
 
+// Data Zero Prohibited flag
+// 0b0 = ZVA/GVA/GZVA permitted
+// 0b1 = ZVA/GVA/GZVA prohibited
+constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
+// Log2 of the blocksize in 32-bit words
+constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
+
+#ifdef _M_ARM_64
+static uint32_t GetDCZID() {
+  uint64_t Result{};
+  __asm("mrs %[Res], DCZID_EL0"
+      : [Res] "=r" (Result));
+  return Result;
+}
+
+static uint32_t GetFPCR() {
+  uint64_t Result{};
+  __asm ("mrs %[Res], FPCR"
+    : [Res] "=r" (Result));
+  return Result;
+}
+
+static void SetFPCR(uint64_t Value) {
+  __asm ("msr FPCR, %[Value]"
+    :: [Value] "r" (Value));
+}
+
+#else
+static uint32_t GetDCZID() {
+  // Return unsupported
+  return DCZID_DZP_MASK;
+}
+#endif
+
+
 HostFeatures::HostFeatures() {
 #ifdef _M_ARM_64
   auto Features = vixl::CPUFeatures::InferFromOS();
   SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
+  SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
+  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
+  // Only supported when FEAT_AFP is supported
+  SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
+
+  // RCPC is bugged on Snapdragon 865
+  // Causes glibc cond16 test to immediately throw assert
+  // __pthread_mutex_cond_lock: Assertion `mutex->__data.__owner == 0'
+  SupportsRCPC = false; //Features.Has(vixl::CPUFeatures::Feature::kRCpc);
+
+  // We need to get the CPU's cache line size
+  // We expect sane targets that have correct cacheline sizes across clusters
+  uint64_t CTR;
+  __asm volatile ("mrs %[ctr], ctr_el0"
+    : [ctr] "=r"(CTR));
+
+  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
+  ICacheLineSize = 4 << (CTR & 0xF);
+
+  if (!SupportsAtomics) {
+    WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
+  }
 #endif
 #ifdef _M_X86_64
   Xbyak::util::Cpu Features{};
   SupportsAES = Features.has(Xbyak::util::Cpu::tAESNI);
+  SupportsCRC = Features.has(Xbyak::util::Cpu::tSSE42);
+  SupportsFlushInputsToZero = true;
+  SupportsFloatExceptions = true;
+#else
+  // Test if this CPU supports float exception trapping by attempting to enable
+  // On unsupported these bits are architecturally defined as RAZ/WI
+  constexpr uint32_t ExceptionEnableTraps =
+    (1U << 8) |  // Invalid Operation float exception trap enable
+    (1U << 9) |  // Divide by zero float exception trap enable
+    (1U << 10) | // Overflow float exception trap enable
+    (1U << 11) | // Underflow float exception trap enable
+    (1U << 12) | // Inexact float exception trap enable
+    (1U << 15);  // Input Denormal float exception trap enable
+
+  uint32_t OriginalFPCR = GetFPCR();
+  uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
+  SetFPCR(FPCR);
+  FPCR = GetFPCR();
+  SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
+
+  // Set FPCR back to original just in case anything changed
+  SetFPCR(OriginalFPCR);
 #endif
+
+  // Check if we can support cacheline clears
+  uint32_t DCZID = GetDCZID();
+  if ((DCZID & DCZID_DZP_MASK) == 0) {
+    uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
+    uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
+    // If the DC ZVA size matches the emulated cache line size
+    // This means we can use the instruction
+    SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
+  }
 }
 }

External/FEXCore/Source/Interface/Core/HostFeatures.h

@@ -1,9 +1,27 @@
 #pragma once
+#include <cstdint>
 
 namespace FEXCore {
 class HostFeatures final {
   public:
     HostFeatures();
+
+    /**
+     * @brief Backend features that change how codegen is generated from IR
+     *
+     * Specifically things that affect the IR->Codegen process
+     * Not the x86->IR process
+     */
+    uint32_t DCacheLineSize{};
+    uint32_t ICacheLineSize{};
     bool SupportsAES{};
+    bool SupportsCRC{};
+    bool SupportsCLZERO{};
+    bool SupportsAtomics{};
+    bool SupportsRCPC{};
+
+    // Float exception behaviour
+    bool SupportsFlushInputsToZero{};
+    bool SupportsFloatExceptions{};
 };
 }

External/FEXCore/Source/Interface/Core/Interpreter/Arm64Dispatcher.cpp

@@ -1,563 +0,0 @@
-#include "Common/MathUtils.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include <FEXCore/Core/X86Enums.h>
-
-#include <cmath>
-
-#include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
-#include "aarch64/disasm-aarch64.h"
-#include "aarch64/assembler-aarch64.h"
-
-namespace FEXCore::CPU {
-static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->State.RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-}
-
-using namespace vixl;
-using namespace vixl::aarch64;
-
-#define STATE x28
-static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
-
-class DispatchGenerator : public vixl::aarch64::Assembler {
-  public:
-    DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-    bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-    bool HandleSignalPause(int Signal, void *info, void *ucontext);
-
-  CPUBackend::AsmDispatch DispatchPtr;
-  CPUBackend::JITCallback CallbackPtr;
-
-  uint64_t ThreadStopHandlerAddress;
-  uint64_t AbsoluteLoopTopAddress;
-  uint64_t ThreadPauseHandlerAddress;
-  FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
-  private:
-    void StoreThreadState(int Signal, void *ucontext);
-    void RestoreThreadState(void *ucontext);
-    void PushCalleeSavedRegisters();
-    void PopCalleeSavedRegisters();
-    void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
-    std::stack<uint64_t> SignalFrames;
-};
-
-void DispatchGenerator::PushCalleeSavedRegisters() {
-  // We need to save pairs of registers
-  // We save r19-r30
-  MemOperand PairOffset(sp, -16, PreIndex);
-  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
-    {x19, x20},
-    {x21, x22},
-    {x23, x24},
-    {x25, x26},
-    {x27, x28},
-    {x29, x30},
-  }};
-
-  for (auto &RegPair : CalleeSaved) {
-    stp(RegPair.first, RegPair.second, PairOffset);
-  }
-
-  // Additionally we need to store the lower 64bits of v8-v15
-  // Here's a fun thing, we can use two ST4 instructions to store everything
-  // We just need a single sub to sp before that
-  const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v8, v9, v10, v11},
-    {v12, v13, v14, v15},
-  }};
-
-  uint32_t VectorSaveSize = sizeof(uint64_t) * 8;
-  sub(sp, sp, VectorSaveSize);
-  // SP supporting move
-  // We just saved x19 so it is safe
-  add(x19, sp, 0);
-
-  MemOperand QuadOffset(x19, 32, PostIndex);
-  for (auto &RegQuad : FPRs) {
-    st4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
-        0,
-        QuadOffset);
-  }
-}
-
-void DispatchGenerator::PopCalleeSavedRegisters() {
-  const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v12, v13, v14, v15},
-    {v8, v9, v10, v11},
-  }};
-
-  MemOperand QuadOffset(sp, 32, PostIndex);
-  for (auto &RegQuad : FPRs) {
-    ld4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
-        0,
-        QuadOffset);
-  }
-
-  MemOperand PairOffset(sp, 16, PostIndex);
-  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
-    {x29, x30},
-    {x27, x28},
-    {x25, x26},
-    {x23, x24},
-    {x21, x22},
-    {x19, x20},
-  }};
-
-  for (auto &RegPair : CalleeSaved) {
-    ldp(RegPair.first, RegPair.second, PairOffset);
-  }
-}
-
-void DispatchGenerator::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant) {
-  bool Is64Bit = Reg.IsX();
-  int Segments = Is64Bit ? 4 : 2;
-
-  movz(Reg, (Constant) & 0xFFFF, 0);
-  for (int i = 1; i < Segments; ++i) {
-    uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
-    if (Part) {
-      movk(Reg, Part, i * 16);
-    }
-  }
-}
-
-DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
-  : vixl::aarch64::Assembler(MAX_DISPATCHER_CODE_SIZE, vixl::aarch64::PositionDependentCode)
-  , CTX {ctx}
-  , State {Thread} {
-
-  SetAllowAssembler(true);
-  auto Buffer = GetBuffer();
-
-  DispatchPtr = Buffer->GetOffsetAddress<CPUBackend::AsmDispatch>(GetCursorOffset());
-
-  // while (!Thread->State.RunningEvents.ShouldStop.load()) {
-  //    Ptr = FindBlock(RIP)
-  //    if (!Ptr)
-  //      Ptr = CTX->CompileBlock(RIP);
-  //
-  //    if (Ptr)
-  //      Ptr();
-  //    else
-  //    {
-  //      Ptr = FallbackCore->CompileBlock()
-  //      if (Ptr)
-  //        Ptr()
-  //      else {
-  //        ShouldStop = true;
-  //      }
-  //    }
-  // }
-
-  // Push all the register we need to save
-  PushCalleeSavedRegisters();
-
-  // Push our memory base to the correct register
-  // Move our thread pointer to the correct register
-  // This is passed in to parameter 0 (x0)
-  mov(STATE, x0);
-
-  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
-  // regardless of where we were in the stack
-  add(x0, sp, 0);
-  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)));
-
-  Label Exit;
-  Label LoopTop;
-  Label NoBlock;
-  Label ThreadPauseHandler;
-  bind(&LoopTop);
-  AbsoluteLoopTopAddress = GetLabelAddress<uint64_t>(&LoopTop);
-
-  // Load in our RIP
-  // Don't modify x2 since it contains our RIP once the block doesn't exist
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, State.rip)));
-  auto RipReg = x2;
-
-  // Mask the address by the virtual address size so we can check for aliases
-  LoadConstant(x3, Thread->LookupCache->GetVirtualMemorySize() - 1);
-  and_(x3, RipReg, x3);
-
-  {
-    // This is the block cache lookup routine
-    // It matches what is going on it LookupCache.h::FindBlock
-    LoadConstant(x0, Thread->LookupCache->GetPagePointer());
-
-    // Offset the address and add to our page pointer
-    lsr(x1, x3, 12);
-
-    // Load the pointer from the offset
-    ldr(x0, MemOperand(x0, x1, Shift::LSL, 3));
-
-    // If page pointer is zero then we have no block
-    cbz(x0, &NoBlock);
-
-    // Steal the page offset
-    and_(x1, x3, 0x0FFF);
-
-    // Shift the offset by the size of the block cache entry
-    add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
-
-    // Load the guest address first to ensure it maps to the address we are currently at
-    // This fixes aliasing problems
-    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
-    cmp(x1, RipReg);
-    b(&NoBlock, Condition::ne);
-
-    // Now load the actual host block to execute if we can
-    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
-    cbz(x1, &NoBlock);
-
-    // If we've made it here then we have a real compiled block
-    {
-      mov(x0, STATE);
-      blr(x1);
-    }
-
-    if (CTX->GetGdbServerStatus()) {
-      // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
-      // This happens when single stepping
-
-      static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
-      ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, CTX)));
-      ldr(w0, MemOperand(x0, offsetof(FEXCore::Context::Context, Config.RunningMode)));
-      // If the value == 0 then branch to the top
-      cbz(x0, &LoopTop);
-      // Else we need to pause now
-      b(&ThreadPauseHandler);
-    }
-    else {
-      // Unconditionally loop to the top
-      // We will only stop on error when compiling a block or signal
-      b(&LoopTop);
-    }
-  }
-
-  {
-    bind(&Exit);
-    ThreadStopHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    PopCalleeSavedRegisters();
-
-    // Return from the function
-    // LR is set to the correct return location now
-    ret();
-  }
-
-  // Need to create the block
-  {
-    bind(&NoBlock);
-
-    ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, CTX)));
-    mov(x1, STATE);
-
-    using ClassPtrType = uintptr_t (FEXCore::Context::Context::*)(FEXCore::Core::InternalThreadState *, uint64_t);
-    union PtrCast {
-      ClassPtrType ClassPtr;
-      uintptr_t Data;
-    };
-
-    PtrCast Ptr;
-    Ptr.ClassPtr = &FEXCore::Context::Context::CompileBlock;
-    LoadConstant(x3, Ptr.Data);
-
-    // X2 contains our guest RIP
-    blr(x3); // { CTX, ThreadState, RIP}
-
-    b(&LoopTop);
-  }
-
-  {
-    bind(&ThreadPauseHandler);
-    ThreadPauseHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    // We are pausing, this means the frontend should be waiting for this thread to idle
-    // We will have faulted and jumped to this location at this point
-
-    // Call our sleep handler
-    LoadConstant(x0, reinterpret_cast<uintptr_t>(CTX));
-    mov(x1, STATE);
-    LoadConstant(x2, reinterpret_cast<uint64_t>(SleepThread));
-    blr(x2);
-
-    // XXX: Unsupported atm
-    //PauseReturnInstruction = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    //// Fault to start running again
-    //hlt(0);
-  }
-
-  {
-    CallbackPtr = Buffer->GetOffsetAddress<CPUBackend::JITCallback>(GetCursorOffset());
-
-    // We expect the thunk to have previously pushed the registers it was using
-    PushCalleeSavedRegisters();
-
-    // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, x0);
-
-    // Now push the callback return trampoline to the guest stack
-    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    LoadConstant(x0, CTX->X86CodeGen.CallbackReturn);
-
-    ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
-    sub(x2, x2, 16);
-    str(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
-
-    // Store the trampoline to the guest stack
-    // Guest stack is now correctly misaligned after a regular call instruction
-    str(x0, MemOperand(x2));
-
-    // Store RIP to the context state
-    str(x1, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.rip)));
-
-    // Now go back to the regular dispatcher loop
-    b(&LoopTop);
-  }
-
-  FinalizeCode();
-  uint64_t CodeEnd = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(reinterpret_cast<void*>(DispatchPtr), CodeEnd - reinterpret_cast<uint64_t>(DispatchPtr));
-  GetBuffer()->SetExecutable();
-}
-
-
-struct HostCTXHeader {
-  uint32_t Magic;
-  uint32_t Size;
-};
-
-constexpr uint32_t FPR_MAGIC = 0x46508001U;
-
-struct HostFPRState {
-  HostCTXHeader Head;
-  uint32_t FPSR;
-  uint32_t FPCR;
-  __uint128_t FPRs[32];
-};
-
-struct ContextBackup {
-  // Host State
-  uint64_t GPRs[31];
-  uint64_t PrevSP;
-  uint64_t PrevPC;
-  uint64_t PState;
-  uint32_t FPSR;
-  uint32_t FPCR;
-  __uint128_t FPRs[32];
-
-  // Guest state
-  int Signal;
-  FEXCore::Core::CPUState GuestState;
-};
-
-void DispatchGenerator::StoreThreadState(int Signal, void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  // We can end up getting a signal at any point in our host state
-  // Jump to a handler that saves all state so we can safely return
-  uint64_t OldSP = _mcontext->sp;
-  uintptr_t NewSP = OldSP;
-
-  size_t StackOffset = sizeof(ContextBackup);
-  NewSP -= StackOffset;
-  NewSP = AlignDown(NewSP, 16);
-
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-  memcpy(&Context->GPRs[0], &_mcontext->regs[0], 31 * sizeof(uint64_t));
-  Context->PrevSP = _mcontext->sp;
-  Context->PrevPC = _mcontext->pc;
-  Context->PState = _mcontext->pstate;
-
-  // Host FPR state starts at _mcontext->reserved[0];
-  HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-  LogMan::Throw::A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
-  Context->FPSR = HostState->FPSR;
-  Context->FPCR = HostState->FPCR;
-  memcpy(&Context->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t));
-
-  // Retain the action pointer so we can see it when we return
-  Context->Signal = Signal;
-
-  // Save guest state
-  // We can't guarantee if registers are in context or host GPRs
-  // So we need to save everything
-  memcpy(&Context->GuestState, &State->State, sizeof(FEXCore::Core::CPUState));
-
-  // Set the new SP
-  _mcontext->sp = NewSP;
-}
-
-void DispatchGenerator::RestoreThreadState(void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  uint64_t OldSP = _mcontext->sp;
-  uintptr_t NewSP = OldSP;
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  // First thing, reset the guest state
-  memcpy(&State->State, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
-
-  // Now restore host state
-  HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-  LogMan::Throw::A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
-  memcpy(&HostState->FPRs[0], &Context->FPRs[0], 32 * sizeof(__uint128_t));
-  Context->FPCR = HostState->FPCR;
-  Context->FPSR = HostState->FPSR;
-
-  // Restore GPRs and other state
-  _mcontext->pstate = Context->PState;
-  _mcontext->pc = Context->PrevPC;
-  _mcontext->sp = Context->PrevSP;
-  memcpy(&_mcontext->regs[0], &Context->GPRs[0], 31 * sizeof(uint64_t));
-
-  // Restore the previous signal state
-  // This allows recursive signals to properly handle signal masking as we are walking back up the list of signals
-  CTX->SignalDelegation->SetCurrentSignal(Context->Signal);
-}
-
-bool DispatchGenerator::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  StoreThreadState(Signal, ucontext);
-
-  // Set the new PC
-  _mcontext->pc = AbsoluteLoopTopAddress;
-  // Set x28 (which is our state register) to point to our guest thread data
-  _mcontext->regs[28 /* STATE */] = reinterpret_cast<uint64_t>(State);
-
-  State->State.State.gregs[X86State::REG_RDI] = Signal;
-  uint64_t OldGuestSP = State->State.State.gregs[X86State::REG_RSP];
-  uint64_t NewGuestSP = OldGuestSP;
-
-  if (!(GuestStack->ss_flags & SS_DISABLE)) {
-    // If our guest is already inside of the alternative stack
-    // Then that means we are hitting recursive signals and we need to walk back the stack correctly
-    uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
-    uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
-    if (OldGuestSP >= AltStackBase &&
-        OldGuestSP <= AltStackEnd) {
-      // We are already in the alt stack, the rest of the code will handle adjusting this
-    }
-    else {
-      NewGuestSP = AltStackEnd;
-    }
-  }
-
-  // Back up past the redzone, which is 128bytes
-  // Don't need this offset if we aren't going to be putting siginfo in to it
-  NewGuestSP -= 128;
-
-  if (GuestAction->sa_flags & SA_SIGINFO) {
-    // XXX: siginfo_t(RSI), ucontext (RDX)
-    State->State.State.gregs[X86State::REG_RSI] = 0;
-    State->State.State.gregs[X86State::REG_RDX] = 0;
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
-  }
-  else {
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
-  }
-
-  // Set up the new SP for stack handling
-  NewGuestSP -= 8;
-  *(uint64_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
-  State->State.State.gregs[X86State::REG_RSP] = NewGuestSP;
-
-  return true;
-}
-
-bool DispatchGenerator::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  FEXCore::Core::SignalEvent SignalReason = State->SignalReason.load();
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_PAUSE) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Store our thread state so we can come back to this
-    StoreThreadState(Signal, ucontext);
-
-    // Set the new PC
-    _mcontext->pc = ThreadPauseHandlerAddress;
-
-    // Set our state register to point to our guest thread data
-    _mcontext->regs[28 /* STATE */] = reinterpret_cast<uint64_t>(State);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_RETURN) {
-    RestoreThreadState(ucontext);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_STOP) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Our thread is stopping
-    // We don't care about anything at this point
-    // Set the stack to our starting location when we entered the JIT and get out safely
-    _mcontext->sp = State->State.ReturningStackLocation;
-
-    // Set the new PC
-    _mcontext->pc = ThreadStopHandlerAddress;
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  return false;
-}
-
-void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  Generator = new DispatchGenerator(ctx, Thread);
-  DispatchPtr = Generator->DispatchPtr;
-  CallbackPtr = Generator->CallbackPtr;
-
-  // TODO: Implement this. It is missing from the dispatcher
-  // TODO: It feels wrong to initialize this way
-  ctx->InterpreterCallbackReturn = nullptr;
-}
-
-bool InterpreterCore::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-}
-
-bool InterpreterCore::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleSignalPause(Signal, info, ucontext);
-}
-
-void InterpreterCore::DeleteAsmDispatch() {
-  delete Generator;
-}
-
-}

External/FEXCore/Source/Interface/Core/Interpreter/AtomicOps.cpp

@@ -0,0 +1,778 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+
+#include <FEXCore/Utils/BitUtils.h>
+
+#include <cstdint>
+
+namespace FEXCore::CPU {
+
+#ifdef _M_X86_64
+uint8_t AtomicFetchNeg(uint8_t *Addr) {
+  using Type = uint8_t;
+  std::atomic<Type> *MemData = reinterpret_cast<std::atomic<Type>*>(Addr);
+  Type Expected = MemData->load();
+  Type Desired = -Expected;
+  do {
+    Desired = -Expected;
+  } while (!MemData->compare_exchange_strong(Expected, Desired, std::memory_order_seq_cst));
+
+  return Expected;
+}
+
+uint16_t AtomicFetchNeg(uint16_t *Addr) {
+  using Type = uint16_t;
+  std::atomic<Type> *MemData = reinterpret_cast<std::atomic<Type>*>(Addr);
+  Type Expected = MemData->load();
+  Type Desired = -Expected;
+  do {
+    Desired = -Expected;
+  } while (!MemData->compare_exchange_strong(Expected, Desired, std::memory_order_seq_cst));
+
+  return Expected;
+}
+
+uint32_t AtomicFetchNeg(uint32_t *Addr) {
+  using Type = uint32_t;
+  std::atomic<Type> *MemData = reinterpret_cast<std::atomic<Type>*>(Addr);
+  Type Expected = MemData->load();
+  Type Desired = -Expected;
+  do {
+    Desired = -Expected;
+  } while (!MemData->compare_exchange_strong(Expected, Desired, std::memory_order_seq_cst));
+
+  return Expected;
+}
+
+uint64_t AtomicFetchNeg(uint64_t *Addr) {
+  using Type = uint64_t;
+  std::atomic<Type> *MemData = reinterpret_cast<std::atomic<Type>*>(Addr);
+  Type Expected = MemData->load();
+  Type Desired = -Expected;
+  do {
+    Desired = -Expected;
+  } while (!MemData->compare_exchange_strong(Expected, Desired, std::memory_order_seq_cst));
+
+  return Expected;
+}
+
+template<typename T>
+T AtomicCompareAndSwap(T expected, T desired, T *addr)
+{
+  std::atomic<T> *MemData = reinterpret_cast<std::atomic<T>*>(addr);
+
+  T Src1 = expected;
+  T Src2 = desired;
+
+  T Expected = Src1;
+  bool Result = MemData->compare_exchange_strong(Expected, Src2);
+
+  return Result ? Src1 : Expected;
+}
+
+template uint8_t AtomicCompareAndSwap<uint8_t>(uint8_t expected, uint8_t desired, uint8_t *addr);
+template uint16_t AtomicCompareAndSwap<uint16_t>(uint16_t expected, uint16_t desired, uint16_t *addr);
+template uint32_t AtomicCompareAndSwap<uint32_t>(uint32_t expected, uint32_t desired, uint32_t *addr);
+template uint64_t AtomicCompareAndSwap<uint64_t>(uint64_t expected, uint64_t desired, uint64_t *addr);
+
+#else
+// Needs to match what the AArch64 JIT and unaligned signal handler expects
+uint8_t AtomicFetchNeg(uint8_t *Addr) {
+  using Type = uint8_t;
+  Type Result{};
+  Type Tmp{};
+  Type TmpStatus{};
+
+  __asm__ volatile(
+  R"(
+  1:
+    ldaxrb %w[Result], [%[Memory]];
+    neg %w[Tmp], %w[Result];
+    stlxrb %w[TmpStatus], %w[Tmp], [%[Memory]];
+    cbnz %w[TmpStatus], 1b;
+  )"
+  : [Result] "=r" (Result)
+  , [Tmp] "=r" (Tmp)
+  , [TmpStatus] "=r" (TmpStatus)
+  , [Memory] "+r" (Addr)
+  :: "memory"
+  );
+  return Result;
+}
+
+uint16_t AtomicFetchNeg(uint16_t *Addr) {
+  using Type = uint16_t;
+  Type Result{};
+  Type Tmp{};
+  Type TmpStatus{};
+
+  __asm__ volatile(
+  R"(
+  1:
+    ldaxrh %w[Result], [%[Memory]];
+    neg %w[Tmp], %w[Result];
+    stlxrh %w[TmpStatus], %w[Tmp], [%[Memory]];
+    cbnz %w[TmpStatus], 1b;
+  )"
+  : [Result] "=r" (Result)
+  , [Tmp] "=r" (Tmp)
+  , [TmpStatus] "=r" (TmpStatus)
+  , [Memory] "+r" (Addr)
+  :: "memory"
+  );
+  return Result;
+}
+
+uint32_t AtomicFetchNeg(uint32_t *Addr) {
+  using Type = uint32_t;
+  Type Result{};
+  Type Tmp{};
+  Type TmpStatus{};
+
+  __asm__ volatile(
+  R"(
+  1:
+    ldaxr %w[Result], [%[Memory]];
+    neg %w[Tmp], %w[Result];
+    stlxr %w[TmpStatus], %w[Tmp], [%[Memory]];
+    cbnz %w[TmpStatus], 1b;
+  )"
+  : [Result] "=r" (Result)
+  , [Tmp] "=r" (Tmp)
+  , [TmpStatus] "=r" (TmpStatus)
+  , [Memory] "+r" (Addr)
+  :: "memory"
+  );
+  return Result;
+}
+
+uint64_t AtomicFetchNeg(uint64_t *Addr) {
+  using Type = uint64_t;
+  Type Result{};
+  Type Tmp{};
+  Type TmpStatus{};
+
+  __asm__ volatile(
+  R"(
+  1:
+    ldaxr %[Result], [%[Memory]];
+    neg %[Tmp], %[Result];
+    stlxr %w[TmpStatus], %[Tmp], [%[Memory]];
+    cbnz %w[TmpStatus], 1b;
+  )"
+  : [Result] "=r" (Result)
+  , [Tmp] "=r" (Tmp)
+  , [TmpStatus] "=r" (TmpStatus)
+  , [Memory] "+r" (Addr)
+  :: "memory"
+  );
+  return Result;
+}
+
+template<>
+uint8_t AtomicCompareAndSwap(uint8_t expected, uint8_t desired, uint8_t *addr) {
+  using Type = uint8_t;
+  //force Result to r9 (scratch register) or clang spills to stack
+  register Type Result asm("r9"){};
+  Type Tmp{};
+  Type Tmp2{};
+  __asm__ volatile(
+  R"(
+  1:
+    ldaxrb %w[Tmp], [%[Memory]];
+    cmp %w[Tmp], %w[Expected], uxtb;
+    b.ne 2f;
+    stlxrb %w[Tmp2], %w[Desired], [%[Memory]];
+    cbnz %w[Tmp2], 1b;
+    mov %w[Result], %w[Expected];
+    b 3f;
+  2:
+    mov %w[Result], %w[Tmp];
+    clrex;
+  3:
+  )"
+  : [Tmp] "=r" (Tmp)
+  , [Tmp2] "=r" (Tmp2)
+  , [Desired] "+r" (desired)
+  , [Expected] "+r" (expected)
+  , [Result] "=r" (Result)
+  , [Memory] "+r" (addr)
+  :: "memory"
+  );
+  return Result;
+}
+
+template<>
+uint16_t AtomicCompareAndSwap(uint16_t expected, uint16_t desired, uint16_t *addr) {
+  using Type = uint16_t;
+  //force Result to r9 (scratch register) or clang spills to stack
+  register Type Result asm("r9"){};
+  Type Tmp{};
+  Type Tmp2{};
+  __asm__ volatile(
+  R"(
+  1:
+    ldaxrh %w[Tmp], [%[Memory]];
+    cmp %w[Tmp], %w[Expected], uxth;
+    b.ne 2f;
+    stlxrh %w[Tmp2], %w[Desired], [%[Memory]];
+    cbnz %w[Tmp2], 1b;
+    mov %w[Result], %w[Expected];
+    b 3f;
+  2:
+    mov %w[Result], %w[Tmp];
+    clrex;
+  3:
+  )"
+  : [Tmp] "=r" (Tmp)
+  , [Tmp2] "=r" (Tmp2)
+  , [Desired] "+r" (desired)
+  , [Expected] "+r" (expected)
+  , [Result] "=r" (Result)
+  , [Memory] "+r" (addr)
+  :: "memory"
+  );
+  return Result;
+}
+
+template<>
+uint32_t AtomicCompareAndSwap(uint32_t expected, uint32_t desired, uint32_t *addr) {
+  using Type = uint32_t;
+  //force Result to r9 (scratch register) or clang spills to stack
+  register Type Result asm("r9"){};
+  Type Tmp{};
+  Type Tmp2{};
+  __asm__ volatile(
+  R"(
+  1:
+    ldaxr %w[Tmp], [%[Memory]];
+    cmp %w[Tmp], %w[Expected];
+    b.ne 2f;
+    stlxr %w[Tmp2], %w[Desired], [%[Memory]];
+    cbnz %w[Tmp2], 1b;
+    mov %w[Result], %w[Expected];
+    b 3f;
+  2:
+    mov %w[Result], %w[Tmp];
+    clrex;
+  3:
+  )"
+  : [Tmp] "=r" (Tmp)
+  , [Tmp2] "=r" (Tmp2)
+  , [Desired] "+r" (desired)
+  , [Expected] "+r" (expected)
+  , [Result] "=r" (Result)
+  , [Memory] "+r" (addr)
+  :: "memory"
+  );
+  return Result;
+}
+
+template<>
+uint64_t AtomicCompareAndSwap(uint64_t expected, uint64_t desired, uint64_t *addr) {
+  using Type = uint64_t;
+  //force Result to r9 (scratch register) or clang spills to stack
+  register Type Result asm("r9"){};
+  Type Tmp{};
+  Type Tmp2{};
+  __asm__ volatile(
+  R"(
+  1:
+    ldaxr %[Tmp], [%[Memory]];
+    cmp %[Tmp], %[Expected];
+    b.ne 2f;
+    stlxr %w[Tmp2], %[Desired], [%[Memory]];
+    cbnz %w[Tmp2], 1b;
+    mov %[Result], %[Expected];
+    b 3f;
+  2:
+    mov %[Result], %[Tmp];
+    clrex;
+  3:
+  )"
+  : [Tmp] "=r" (Tmp)
+  , [Tmp2] "=r" (Tmp2)
+  , [Desired] "+r" (desired)
+  , [Expected] "+r" (expected)
+  , [Result] "=r" (Result)
+  , [Memory] "+r" (addr)
+  :: "memory"
+  );
+  return Result;
+}
+
+#endif
+
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+DEF_OP(CASPair) {
+  auto Op = IROp->C<IR::IROp_CASPair>();
+  uint8_t OpSize = IROp->Size;
+
+  // Size is the size of each pair element
+  switch (OpSize) {
+    case 4: {
+      GD = AtomicCompareAndSwap(
+        *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]),
+        *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]),
+        *GetSrc<uint64_t**>(Data->SSAData, Op->Header.Args[2])
+      );
+      break;
+    }
+    case 8: {
+      std::atomic<__uint128_t> *MemData = *GetSrc<std::atomic<__uint128_t> **>(Data->SSAData, Op->Header.Args[2]);
+
+      __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+      __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+
+      __uint128_t Expected = Src1;
+      bool Result = MemData->compare_exchange_strong(Expected, Src2);
+      memcpy(GDP, Result ? &Src1 : &Expected, 16);
+      break;
+    }
+    default: LOGMAN_MSG_A_FMT("Unknown CAS size: {}", OpSize); break;
+  }
+}
+
+DEF_OP(CAS) {
+  auto Op = IROp->C<IR::IROp_CAS>();
+  uint8_t OpSize = IROp->Size;
+
+  switch (OpSize) {
+    case 1: {
+      GD = AtomicCompareAndSwap(
+        *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]),
+        *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]),
+        *GetSrc<uint8_t**>(Data->SSAData, Op->Header.Args[2])
+      );
+      break;
+    }
+    case 2: {
+      GD = AtomicCompareAndSwap(
+        *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]),
+        *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]),
+        *GetSrc<uint16_t**>(Data->SSAData, Op->Header.Args[2])
+      );
+      break;
+    }
+    case 4: {
+      GD = AtomicCompareAndSwap(
+        *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]),
+        *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]),
+        *GetSrc<uint32_t**>(Data->SSAData, Op->Header.Args[2])
+      );
+      break;
+    }
+    case 8: {
+      GD = AtomicCompareAndSwap(
+        *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]),
+        *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]),
+        *GetSrc<uint64_t**>(Data->SSAData, Op->Header.Args[2])
+      );
+      break;
+    }
+    default: LOGMAN_MSG_A_FMT("Unknown CAS size: {}", OpSize); break;
+  }
+}
+
+DEF_OP(AtomicAdd) {
+  auto Op = IROp->C<IR::IROp_AtomicAdd>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData += Src;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData += Src;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData += Src;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData += Src;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicSub) {
+  auto Op = IROp->C<IR::IROp_AtomicSub>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData -= Src;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData -= Src;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData -= Src;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData -= Src;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicAnd) {
+  auto Op = IROp->C<IR::IROp_AtomicAnd>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData &= Src;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData &= Src;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData &= Src;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData &= Src;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicOr) {
+  auto Op = IROp->C<IR::IROp_AtomicOr>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData |= Src;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData |= Src;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData |= Src;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData |= Src;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicXor) {
+  auto Op = IROp->C<IR::IROp_AtomicXor>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData ^= Src;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData ^= Src;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData ^= Src;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      *MemData ^= Src;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicSwap) {
+  auto Op = IROp->C<IR::IROp_AtomicSwap>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint8_t Previous = MemData->exchange(Src);
+      GD = Previous;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint16_t Previous = MemData->exchange(Src);
+      GD = Previous;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint32_t Previous = MemData->exchange(Src);
+      GD = Previous;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint64_t Previous = MemData->exchange(Src);
+      GD = Previous;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicFetchAdd) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint8_t Previous = MemData->fetch_add(Src);
+      GD = Previous;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint16_t Previous = MemData->fetch_add(Src);
+      GD = Previous;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint32_t Previous = MemData->fetch_add(Src);
+      GD = Previous;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint64_t Previous = MemData->fetch_add(Src);
+      GD = Previous;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicFetchSub) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint8_t Previous = MemData->fetch_sub(Src);
+      GD = Previous;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint16_t Previous = MemData->fetch_sub(Src);
+      GD = Previous;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint32_t Previous = MemData->fetch_sub(Src);
+      GD = Previous;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint64_t Previous = MemData->fetch_sub(Src);
+      GD = Previous;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicFetchAnd) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint8_t Previous = MemData->fetch_and(Src);
+      GD = Previous;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint16_t Previous = MemData->fetch_and(Src);
+      GD = Previous;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint32_t Previous = MemData->fetch_and(Src);
+      GD = Previous;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint64_t Previous = MemData->fetch_and(Src);
+      GD = Previous;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicFetchOr) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint8_t Previous = MemData->fetch_or(Src);
+      GD = Previous;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint16_t Previous = MemData->fetch_or(Src);
+      GD = Previous;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint32_t Previous = MemData->fetch_or(Src);
+      GD = Previous;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint64_t Previous = MemData->fetch_or(Src);
+      GD = Previous;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicFetchXor) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
+  switch (IROp->Size) {
+    case 1: {
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint8_t Previous = MemData->fetch_xor(Src);
+      GD = Previous;
+      break;
+    }
+    case 2: {
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint16_t Previous = MemData->fetch_xor(Src);
+      GD = Previous;
+      break;
+    }
+    case 4: {
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint32_t Previous = MemData->fetch_xor(Src);
+      GD = Previous;
+      break;
+    }
+    case 8: {
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      uint64_t Previous = MemData->fetch_xor(Src);
+      GD = Previous;
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicFetchNeg) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
+  switch (IROp->Size) {
+    case 1: {
+      using Type = uint8_t;
+      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Header.Args[0]));
+      break;
+    }
+    case 2: {
+      using Type = uint16_t;
+      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Header.Args[0]));
+      break;
+    }
+    case 4: {
+      using Type = uint32_t;
+      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Header.Args[0]));
+      break;
+    }
+    case 8: {
+      using Type = uint64_t;
+      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Header.Args[0]));
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
+#undef DEF_OP
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/BranchOps.cpp

@@ -0,0 +1,170 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+#include "Interface/HLE/Thunks/Thunks.h"
+
+#include <FEXCore/Utils/BitUtils.h>
+#include <FEXCore/HLE/SyscallHandler.h>
+
+#include <cstdint>
+#include <unistd.h>
+
+namespace FEXCore::CPU {
+[[noreturn]]
+static void SignalReturn(FEXCore::Core::InternalThreadState *Thread) {
+  Thread->CTX->SignalThread(Thread, FEXCore::Core::SignalEvent::Return);
+
+  LOGMAN_MSG_A_FMT("unreachable");
+  FEX_UNREACHABLE;
+}
+
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+DEF_OP(GuestCallDirect) {
+  LogMan::Msg::DFmt("Unimplemented");
+}
+
+DEF_OP(GuestCallIndirect) {
+  LogMan::Msg::DFmt("Unimplemented");
+}
+
+DEF_OP(GuestReturn) {
+  LogMan::Msg::DFmt("Unimplemented");
+}
+
+DEF_OP(SignalReturn) {
+  SignalReturn(Data->State);
+}
+
+DEF_OP(CallbackReturn) {
+  Data->State->CTX->InterpreterCallbackReturn(Data->State, Data->StackEntry);
+}
+
+DEF_OP(ExitFunction) {
+  auto Op = IROp->C<IR::IROp_ExitFunction>();
+  uint8_t OpSize = IROp->Size;
+
+  uintptr_t* ContextPtr = reinterpret_cast<uintptr_t*>(Data->State->CurrentFrame);
+
+  void *ContextData = reinterpret_cast<void*>(ContextPtr);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+
+  memcpy(ContextData, Src, OpSize);
+
+  Data->BlockResults.Quit = true;
+}
+
+DEF_OP(Jump) {
+  auto Op = IROp->C<IR::IROp_Jump>();
+  uintptr_t ListBegin = Data->CurrentIR->GetListData();
+  uintptr_t DataBegin = Data->CurrentIR->GetData();
+
+  Data->BlockIterator = IR::NodeIterator(ListBegin, DataBegin, Op->Header.Args[0]);
+  Data->BlockResults.Redo = true;
+}
+
+DEF_OP(CondJump) {
+  auto Op = IROp->C<IR::IROp_CondJump>();
+  uintptr_t ListBegin = Data->CurrentIR->GetListData();
+  uintptr_t DataBegin = Data->CurrentIR->GetData();
+
+  bool CompResult;
+
+  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp1);
+  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp2);
+
+  if (Op->CompareSize == 4)
+    CompResult = IsConditionTrue<uint32_t, int32_t, float>(Op->Cond.Val, Src1, Src2);
+  else
+    CompResult = IsConditionTrue<uint64_t, int64_t, double>(Op->Cond.Val, Src1, Src2);
+
+  if (CompResult) {
+    Data->BlockIterator = IR::NodeIterator(ListBegin, DataBegin, Op->TrueBlock);
+  }
+  else  {
+    Data->BlockIterator = IR::NodeIterator(ListBegin, DataBegin, Op->FalseBlock);
+  }
+  Data->BlockResults.Redo = true;
+}
+
+DEF_OP(Syscall) {
+  auto Op = IROp->C<IR::IROp_Syscall>();
+
+  FEXCore::HLE::SyscallArguments Args;
+  for (size_t j = 0; j < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++j) {
+    if (Op->Header.Args[j].IsInvalid()) break;
+    Args.Argument[j] = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[j]);
+  }
+
+  uint64_t Res = FEXCore::Context::HandleSyscall(Data->State->CTX->SyscallHandler, Data->State->CurrentFrame, &Args);
+  GD = Res;
+}
+
+DEF_OP(InlineSyscall) {
+  auto Op = IROp->C<IR::IROp_InlineSyscall>();
+
+  FEXCore::HLE::SyscallArguments Args;
+  for (size_t j = 0; j < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++j) {
+    if (Op->Header.Args[j].IsInvalid()) break;
+    Args.Argument[j] = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[j]);
+  }
+
+  // We don't want the errno handling but I also don't want to write inline ASM atm
+  uint64_t Res = syscall(
+    Op->HostSyscallNumber,
+    Args.Argument[0],
+    Args.Argument[1],
+    Args.Argument[2],
+    Args.Argument[3],
+    Args.Argument[4],
+    Args.Argument[5],
+    Args.Argument[6]
+  );
+
+  if (Res == -1) {
+    Res = -errno;
+  }
+
+  GD = Res;
+}
+
+DEF_OP(Thunk) {
+  auto Op = IROp->C<IR::IROp_Thunk>();
+
+  auto thunkFn = Data->State->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
+  thunkFn(*GetSrc<void**>(Data->SSAData, Op->Header.Args[0]));
+}
+
+DEF_OP(ValidateCode) {
+  auto Op = IROp->C<IR::IROp_ValidateCode>();
+
+  auto CodePtr = Data->CurrentEntry + Op->Offset;
+  if (memcmp((void*)CodePtr, &Op->CodeOriginalLow, Op->CodeLength) != 0) {
+    GD = 1;
+  } else {
+    GD = 0;
+  }
+}
+
+DEF_OP(RemoveCodeEntry) {
+  Data->State->CTX->RemoveCodeEntry(Data->State, Data->CurrentEntry);
+}
+
+DEF_OP(CPUID) {
+  auto Op = IROp->C<IR::IROp_CPUID>();
+  uint64_t *DstPtr = GetDest<uint64_t*>(Data->SSAData, Node);
+  uint64_t Arg = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+  uint64_t Leaf = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+
+  auto Results = Data->State->CTX->CPUID.RunFunction(Arg, Leaf);
+  memcpy(DstPtr, &Results, sizeof(uint32_t) * 4);
+}
+
+#undef DEF_OP
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/ConversionOps.cpp

@@ -0,0 +1,224 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+
+#include <cstdint>
+
+namespace FEXCore::CPU {
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+DEF_OP(VInsGPR) {
+  auto Op = IROp->C<IR::IROp_VInsGPR>();
+  uint8_t OpSize = IROp->Size;
+
+  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+
+  uint64_t Offset = Op->Index * Op->Header.ElementSize * 8;
+  __uint128_t Mask = (1ULL << (Op->Header.ElementSize * 8)) - 1;
+  if (Op->Header.ElementSize == 8) {
+    Mask = ~0ULL;
+  }
+  Src2 = Src2 & Mask;
+  Mask <<= Offset;
+  Mask = ~Mask;
+  __uint128_t Dst = Src1 & Mask;
+  Dst |= Src2 << Offset;
+
+  memcpy(GDP, &Dst, OpSize);
+}
+
+DEF_OP(VCastFromGPR) {
+  auto Op = IROp->C<IR::IROp_VCastFromGPR>();
+  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Header.Args[0]), Op->Header.ElementSize);
+}
+
+DEF_OP(Float_FromGPR_S) {
+  auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
+
+  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+  switch (Conv) {
+    case 0x0404: { // Float <- int32_t
+      float Dst = (float)*GetSrc<int32_t*>(Data->SSAData, Op->Header.Args[0]);
+      memcpy(GDP, &Dst, Op->Header.ElementSize);
+      break;
+    }
+    case 0x0408: { // Float <- int64_t
+      float Dst = (float)*GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[0]);
+      memcpy(GDP, &Dst, Op->Header.ElementSize);
+      break;
+    }
+    case 0x0804: { // Double <- int32_t
+      double Dst = (double)*GetSrc<int32_t*>(Data->SSAData, Op->Header.Args[0]);
+      memcpy(GDP, &Dst, Op->Header.ElementSize);
+      break;
+    }
+    case 0x0808: { // Double <- int64_t
+      double Dst = (double)*GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[0]);
+      memcpy(GDP, &Dst, Op->Header.ElementSize);
+      break;
+    }
+  }
+}
+
+DEF_OP(Float_FToF) {
+  auto Op = IROp->C<IR::IROp_Float_FToF>();
+  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+  switch (Conv) {
+    case 0x0804: { // Double <- Float
+      double Dst = (double)*GetSrc<float*>(Data->SSAData, Op->Header.Args[0]);
+      memcpy(GDP, &Dst, 8);
+      break;
+    }
+    case 0x0408: { // Float <- Double
+      float Dst = (float)*GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+      memcpy(GDP, &Dst, 4);
+      break;
+    }
+    default: LOGMAN_MSG_A_FMT("Unknown FCVT sizes: 0x{:x}", Conv);
+  }
+}
+
+DEF_OP(Vector_SToF) {
+  auto Op = IROp->C<IR::IROp_Vector_SToF>();
+  uint8_t OpSize = IROp->Size;
+
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  uint8_t Tmp[16]{};
+
+  uint8_t Elements = OpSize / Op->Header.ElementSize;
+
+  auto Func = [](auto a, auto min, auto max) { return a; };
+  switch (Op->Header.ElementSize) {
+    DO_VECTOR_1SRC_2TYPE_OP(4, float, int32_t, Func, 0, 0)
+    DO_VECTOR_1SRC_2TYPE_OP(8, double, int64_t, Func, 0, 0)
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+  }
+  memcpy(GDP, Tmp, OpSize);
+}
+
+DEF_OP(Vector_FToZS) {
+  auto Op = IROp->C<IR::IROp_Vector_FToZS>();
+  uint8_t OpSize = IROp->Size;
+
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  uint8_t Tmp[16]{};
+
+  uint8_t Elements = OpSize / Op->Header.ElementSize;
+
+  auto Func = [](auto a, auto min, auto max) { return std::trunc(a); };
+  switch (Op->Header.ElementSize) {
+    DO_VECTOR_1SRC_2TYPE_OP(4, int32_t, float, Func, 0, 0)
+    DO_VECTOR_1SRC_2TYPE_OP(8, int64_t, double, Func, 0, 0)
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+  }
+  memcpy(GDP, Tmp, OpSize);
+}
+
+DEF_OP(Vector_FToS) {
+  auto Op = IROp->C<IR::IROp_Vector_FToS>();
+  uint8_t OpSize = IROp->Size;
+
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  uint8_t Tmp[16]{};
+
+  uint8_t Elements = OpSize / Op->Header.ElementSize;
+
+  auto Func = [](auto a, auto min, auto max) { return std::nearbyint(a); };
+  switch (Op->Header.ElementSize) {
+    DO_VECTOR_1SRC_2TYPE_OP(4, int32_t, float, Func, 0, 0)
+    DO_VECTOR_1SRC_2TYPE_OP(8, int64_t, double, Func, 0, 0)
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+  }
+  memcpy(GDP, Tmp, OpSize);
+}
+
+DEF_OP(Vector_FToF) {
+  auto Op = IROp->C<IR::IROp_Vector_FToF>();
+  uint8_t OpSize = IROp->Size;
+
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  uint8_t Tmp[16]{};
+
+  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+
+  auto Func = [](auto a, auto min, auto max) { return a; };
+  switch (Conv) {
+    case 0x0804: { // Double <- float
+      // Only the lower elements from the source
+      // This uses half the source elements
+      uint8_t Elements = OpSize / 8;
+      DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(double, float, Func, 0, 0)
+      break;
+    }
+    case 0x0408: { // Float <- Double
+      // Little bit tricky here
+      // Sometimes is used to convert from a 128bit vector register
+      // in to a 64bit vector register with different sized elements
+      // eg: %ssa5 i32v2 = Vector_FToF %ssa4 i128, #0x8
+      uint8_t Elements = (OpSize << 1) / Op->SrcElementSize;
+      DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(float, double, Func, 0, 0)
+      break;
+    }
+    default: LOGMAN_MSG_A_FMT("Unknown Conversion Type : 0x{:04x}", Conv); break;
+  }
+  memcpy(GDP, Tmp, OpSize);
+}
+
+DEF_OP(Vector_FToI) {
+  auto Op = IROp->C<IR::IROp_Vector_FToI>();
+  uint8_t OpSize = IROp->Size;
+
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  uint8_t Tmp[16]{};
+
+  uint8_t Elements = OpSize / Op->Header.ElementSize;
+  auto Func_Nearest = [](auto a) { return std::rint(a); };
+  auto Func_Neg = [](auto a) { return std::floor(a); };
+  auto Func_Pos = [](auto a) { return std::ceil(a); };
+  auto Func_Trunc = [](auto a) { return std::trunc(a); };
+  auto Func_Host = [](auto a) { return std::rint(a); };
+
+  switch (Op->Round) {
+    case FEXCore::IR::Round_Nearest.Val:
+      switch (Op->Header.ElementSize) {
+        DO_VECTOR_1SRC_OP(4, float, Func_Nearest)
+        DO_VECTOR_1SRC_OP(8, double, Func_Nearest)
+      }
+    break;
+    case FEXCore::IR::Round_Negative_Infinity.Val:
+      switch (Op->Header.ElementSize) {
+        DO_VECTOR_1SRC_OP(4, float, Func_Neg)
+        DO_VECTOR_1SRC_OP(8, double, Func_Neg)
+      }
+    break;
+    case FEXCore::IR::Round_Positive_Infinity.Val:
+      switch (Op->Header.ElementSize) {
+        DO_VECTOR_1SRC_OP(4, float, Func_Pos)
+        DO_VECTOR_1SRC_OP(8, double, Func_Pos)
+      }
+    break;
+    case FEXCore::IR::Round_Towards_Zero.Val:
+      switch (Op->Header.ElementSize) {
+        DO_VECTOR_1SRC_OP(4, float, Func_Trunc)
+        DO_VECTOR_1SRC_OP(8, double, Func_Trunc)
+      }
+    break;
+    case FEXCore::IR::Round_Host.Val:
+      switch (Op->Header.ElementSize) {
+        DO_VECTOR_1SRC_OP(4, float, Func_Host)
+        DO_VECTOR_1SRC_OP(8, double, Func_Host)
+      }
+    break;
+  }
+  memcpy(GDP, Tmp, OpSize);
+}
+
+#undef DEF_OP
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/EncryptionOps.cpp

@@ -0,0 +1,518 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+
+#include <cstdint>
+
+namespace AES {
+  static __uint128_t InvShiftRows(uint8_t *State) {
+    uint8_t Shifted[16] = {
+      State[0], State[13], State[10], State[7],
+      State[4], State[1], State[14], State[11],
+      State[8], State[5], State[2], State[15],
+      State[12], State[9], State[6], State[3],
+    };
+    __uint128_t Res{};
+    memcpy(&Res, Shifted, 16);
+    return Res;
+  }
+
+  static __uint128_t InvSubBytes(uint8_t *State) {
+    // 16x16 matrix table
+    static const uint8_t InvSubstitutionTable[256] = {
+      0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
+      0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
+      0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
+      0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
+      0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
+      0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
+      0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
+      0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
+      0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
+      0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
+      0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
+      0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
+      0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
+      0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
+      0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
+      0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d,
+    };
+
+    // Uses a byte substitution table with a constant set of values
+    // Needs to do a table look up
+    uint8_t Substituted[16];
+    for (size_t i = 0; i < 16; ++i) {
+      Substituted[i] = InvSubstitutionTable[State[i]];
+    }
+
+    __uint128_t Res{};
+    memcpy(&Res, Substituted, 16);
+    return Res;
+  }
+
+  static __uint128_t ShiftRows(uint8_t *State) {
+    uint8_t Shifted[16] = {
+      State[0], State[5], State[10], State[15],
+      State[4], State[9], State[14], State[3],
+      State[8], State[13], State[2], State[7],
+      State[12], State[1], State[6], State[11],
+    };
+    __uint128_t Res{};
+    memcpy(&Res, Shifted, 16);
+    return Res;
+  }
+
+  static __uint128_t SubBytes(uint8_t *State, size_t Bytes) {
+    // 16x16 matrix table
+    static const uint8_t SubstitutionTable[256] = {
+      0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
+      0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
+      0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+      0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
+      0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
+      0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+      0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
+      0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
+      0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+      0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
+      0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
+      0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+      0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
+      0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
+      0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+      0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16,
+    };
+    // Uses a byte substitution table with a constant set of values
+    // Needs to do a table look up
+    uint8_t Substituted[16];
+    Bytes = std::min(Bytes, (size_t)16);
+    for (size_t i = 0; i < Bytes; ++i) {
+      Substituted[i] = SubstitutionTable[State[i]];
+    }
+
+    __uint128_t Res{};
+    memcpy(&Res, Substituted, Bytes);
+    return Res;
+  }
+
+  static uint8_t FFMul02(uint8_t in) {
+    static const uint8_t FFMul02[256] = {
+      0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
+      0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
+      0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e,
+      0x60, 0x62, 0x64, 0x66, 0x68, 0x6a, 0x6c, 0x6e, 0x70, 0x72, 0x74, 0x76, 0x78, 0x7a, 0x7c, 0x7e,
+      0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9c, 0x9e,
+      0xa0, 0xa2, 0xa4, 0xa6, 0xa8, 0xaa, 0xac, 0xae, 0xb0, 0xb2, 0xb4, 0xb6, 0xb8, 0xba, 0xbc, 0xbe,
+      0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce, 0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde,
+      0xe0, 0xe2, 0xe4, 0xe6, 0xe8, 0xea, 0xec, 0xee, 0xf0, 0xf2, 0xf4, 0xf6, 0xf8, 0xfa, 0xfc, 0xfe,
+      0x1b, 0x19, 0x1f, 0x1d, 0x13, 0x11, 0x17, 0x15, 0x0b, 0x09, 0x0f, 0x0d, 0x03, 0x01, 0x07, 0x05,
+      0x3b, 0x39, 0x3f, 0x3d, 0x33, 0x31, 0x37, 0x35, 0x2b, 0x29, 0x2f, 0x2d, 0x23, 0x21, 0x27, 0x25,
+      0x5b, 0x59, 0x5f, 0x5d, 0x53, 0x51, 0x57, 0x55, 0x4b, 0x49, 0x4f, 0x4d, 0x43, 0x41, 0x47, 0x45,
+      0x7b, 0x79, 0x7f, 0x7d, 0x73, 0x71, 0x77, 0x75, 0x6b, 0x69, 0x6f, 0x6d, 0x63, 0x61, 0x67, 0x65,
+      0x9b, 0x99, 0x9f, 0x9d, 0x93, 0x91, 0x97, 0x95, 0x8b, 0x89, 0x8f, 0x8d, 0x83, 0x81, 0x87, 0x85,
+      0xbb, 0xb9, 0xbf, 0xbd, 0xb3, 0xb1, 0xb7, 0xb5, 0xab, 0xa9, 0xaf, 0xad, 0xa3, 0xa1, 0xa7, 0xa5,
+      0xdb, 0xd9, 0xdf, 0xdd, 0xd3, 0xd1, 0xd7, 0xd5, 0xcb, 0xc9, 0xcf, 0xcd, 0xc3, 0xc1, 0xc7, 0xc5,
+      0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5,
+    };
+    return FFMul02[in];
+  }
+
+  static uint8_t FFMul03(uint8_t in) {
+    static const uint8_t FFMul03[256] = {
+      0x00, 0x03, 0x06, 0x05, 0x0c, 0x0f, 0x0a, 0x09, 0x18, 0x1b, 0x1e, 0x1d, 0x14, 0x17, 0x12, 0x11,
+      0x30, 0x33, 0x36, 0x35, 0x3c, 0x3f, 0x3a, 0x39, 0x28, 0x2b, 0x2e, 0x2d, 0x24, 0x27, 0x22, 0x21,
+      0x60, 0x63, 0x66, 0x65, 0x6c, 0x6f, 0x6a, 0x69, 0x78, 0x7b, 0x7e, 0x7d, 0x74, 0x77, 0x72, 0x71,
+      0x50, 0x53, 0x56, 0x55, 0x5c, 0x5f, 0x5a, 0x59, 0x48, 0x4b, 0x4e, 0x4d, 0x44, 0x47, 0x42, 0x41,
+      0xc0, 0xc3, 0xc6, 0xc5, 0xcc, 0xcf, 0xca, 0xc9, 0xd8, 0xdb, 0xde, 0xdd, 0xd4, 0xd7, 0xd2, 0xd1,
+      0xf0, 0xf3, 0xf6, 0xf5, 0xfc, 0xff, 0xfa, 0xf9, 0xe8, 0xeb, 0xee, 0xed, 0xe4, 0xe7, 0xe2, 0xe1,
+      0xa0, 0xa3, 0xa6, 0xa5, 0xac, 0xaf, 0xaa, 0xa9, 0xb8, 0xbb, 0xbe, 0xbd, 0xb4, 0xb7, 0xb2, 0xb1,
+      0x90, 0x93, 0x96, 0x95, 0x9c, 0x9f, 0x9a, 0x99, 0x88, 0x8b, 0x8e, 0x8d, 0x84, 0x87, 0x82, 0x81,
+      0x9b, 0x98, 0x9d, 0x9e, 0x97, 0x94, 0x91, 0x92, 0x83, 0x80, 0x85, 0x86, 0x8f, 0x8c, 0x89, 0x8a,
+      0xab, 0xa8, 0xad, 0xae, 0xa7, 0xa4, 0xa1, 0xa2, 0xb3, 0xb0, 0xb5, 0xb6, 0xbf, 0xbc, 0xb9, 0xba,
+      0xfb, 0xf8, 0xfd, 0xfe, 0xf7, 0xf4, 0xf1, 0xf2, 0xe3, 0xe0, 0xe5, 0xe6, 0xef, 0xec, 0xe9, 0xea,
+      0xcb, 0xc8, 0xcd, 0xce, 0xc7, 0xc4, 0xc1, 0xc2, 0xd3, 0xd0, 0xd5, 0xd6, 0xdf, 0xdc, 0xd9, 0xda,
+      0x5b, 0x58, 0x5d, 0x5e, 0x57, 0x54, 0x51, 0x52, 0x43, 0x40, 0x45, 0x46, 0x4f, 0x4c, 0x49, 0x4a,
+      0x6b, 0x68, 0x6d, 0x6e, 0x67, 0x64, 0x61, 0x62, 0x73, 0x70, 0x75, 0x76, 0x7f, 0x7c, 0x79, 0x7a,
+      0x3b, 0x38, 0x3d, 0x3e, 0x37, 0x34, 0x31, 0x32, 0x23, 0x20, 0x25, 0x26, 0x2f, 0x2c, 0x29, 0x2a,
+      0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a,
+    };
+    return FFMul03[in];
+  }
+
+  static __uint128_t MixColumns(uint8_t *State) {
+    uint8_t In0[16] = {
+      State[0], State[4], State[8], State[12],
+      State[1], State[5], State[9], State[13],
+      State[2], State[6], State[10], State[14],
+      State[3], State[7], State[11], State[15],
+    };
+
+    uint8_t Out0[4]{};
+    uint8_t Out1[4]{};
+    uint8_t Out2[4]{};
+    uint8_t Out3[4]{};
+
+    for (size_t i = 0; i < 4; ++i) {
+      Out0[i] = FFMul02(In0[0 + i]) ^ FFMul03(In0[4 + i]) ^ In0[8 + i] ^ In0[12 + i];
+      Out1[i] = In0[0 + i] ^ FFMul02(In0[4 + i]) ^ FFMul03(In0[8 + i]) ^ In0[12 + i];
+      Out2[i] = In0[0 + i] ^ In0[4 + i] ^ FFMul02(In0[8 + i]) ^ FFMul03(In0[12 + i]);
+      Out3[i] = FFMul03(In0[0 + i]) ^ In0[4 + i] ^ In0[8 + i] ^ FFMul02(In0[12 + i]);
+    }
+
+    uint8_t OutArray[16] = {
+      Out0[0], Out1[0], Out2[0], Out3[0],
+      Out0[1], Out1[1], Out2[1], Out3[1],
+      Out0[2], Out1[2], Out2[2], Out3[2],
+      Out0[3], Out1[3], Out2[3], Out3[3],
+    };
+    __uint128_t Res{};
+    memcpy(&Res, OutArray, 16);
+    return Res;
+  }
+
+  static uint8_t FFMul09(uint8_t in) {
+    static const uint8_t FFMul09[256] = {
+      0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
+      0x90, 0x99, 0x82, 0x8b, 0xb4, 0xbd, 0xa6, 0xaf, 0xd8, 0xd1, 0xca, 0xc3, 0xfc, 0xf5, 0xee, 0xe7,
+      0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
+      0xab, 0xa2, 0xb9, 0xb0, 0x8f, 0x86, 0x9d, 0x94, 0xe3, 0xea, 0xf1, 0xf8, 0xc7, 0xce, 0xd5, 0xdc,
+      0x76, 0x7f, 0x64, 0x6d, 0x52, 0x5b, 0x40, 0x49, 0x3e, 0x37, 0x2c, 0x25, 0x1a, 0x13, 0x08, 0x01,
+      0xe6, 0xef, 0xf4, 0xfd, 0xc2, 0xcb, 0xd0, 0xd9, 0xae, 0xa7, 0xbc, 0xb5, 0x8a, 0x83, 0x98, 0x91,
+      0x4d, 0x44, 0x5f, 0x56, 0x69, 0x60, 0x7b, 0x72, 0x05, 0x0c, 0x17, 0x1e, 0x21, 0x28, 0x33, 0x3a,
+      0xdd, 0xd4, 0xcf, 0xc6, 0xf9, 0xf0, 0xeb, 0xe2, 0x95, 0x9c, 0x87, 0x8e, 0xb1, 0xb8, 0xa3, 0xaa,
+      0xec, 0xe5, 0xfe, 0xf7, 0xc8, 0xc1, 0xda, 0xd3, 0xa4, 0xad, 0xb6, 0xbf, 0x80, 0x89, 0x92, 0x9b,
+      0x7c, 0x75, 0x6e, 0x67, 0x58, 0x51, 0x4a, 0x43, 0x34, 0x3d, 0x26, 0x2f, 0x10, 0x19, 0x02, 0x0b,
+      0xd7, 0xde, 0xc5, 0xcc, 0xf3, 0xfa, 0xe1, 0xe8, 0x9f, 0x96, 0x8d, 0x84, 0xbb, 0xb2, 0xa9, 0xa0,
+      0x47, 0x4e, 0x55, 0x5c, 0x63, 0x6a, 0x71, 0x78, 0x0f, 0x06, 0x1d, 0x14, 0x2b, 0x22, 0x39, 0x30,
+      0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5, 0xd2, 0xdb, 0xc0, 0xc9, 0xf6, 0xff, 0xe4, 0xed,
+      0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35, 0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d,
+      0xa1, 0xa8, 0xb3, 0xba, 0x85, 0x8c, 0x97, 0x9e, 0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6,
+      0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46,
+    };
+    return FFMul09[in];
+  }
+
+  static uint8_t FFMul0B(uint8_t in) {
+    static const uint8_t FFMul0B[256] = {
+      0x00, 0x0b, 0x16, 0x1d, 0x2c, 0x27, 0x3a, 0x31, 0x58, 0x53, 0x4e, 0x45, 0x74, 0x7f, 0x62, 0x69,
+      0xb0, 0xbb, 0xa6, 0xad, 0x9c, 0x97, 0x8a, 0x81, 0xe8, 0xe3, 0xfe, 0xf5, 0xc4, 0xcf, 0xd2, 0xd9,
+      0x7b, 0x70, 0x6d, 0x66, 0x57, 0x5c, 0x41, 0x4a, 0x23, 0x28, 0x35, 0x3e, 0x0f, 0x04, 0x19, 0x12,
+      0xcb, 0xc0, 0xdd, 0xd6, 0xe7, 0xec, 0xf1, 0xfa, 0x93, 0x98, 0x85, 0x8e, 0xbf, 0xb4, 0xa9, 0xa2,
+      0xf6, 0xfd, 0xe0, 0xeb, 0xda, 0xd1, 0xcc, 0xc7, 0xae, 0xa5, 0xb8, 0xb3, 0x82, 0x89, 0x94, 0x9f,
+      0x46, 0x4d, 0x50, 0x5b, 0x6a, 0x61, 0x7c, 0x77, 0x1e, 0x15, 0x08, 0x03, 0x32, 0x39, 0x24, 0x2f,
+      0x8d, 0x86, 0x9b, 0x90, 0xa1, 0xaa, 0xb7, 0xbc, 0xd5, 0xde, 0xc3, 0xc8, 0xf9, 0xf2, 0xef, 0xe4,
+      0x3d, 0x36, 0x2b, 0x20, 0x11, 0x1a, 0x07, 0x0c, 0x65, 0x6e, 0x73, 0x78, 0x49, 0x42, 0x5f, 0x54,
+      0xf7, 0xfc, 0xe1, 0xea, 0xdb, 0xd0, 0xcd, 0xc6, 0xaf, 0xa4, 0xb9, 0xb2, 0x83, 0x88, 0x95, 0x9e,
+      0x47, 0x4c, 0x51, 0x5a, 0x6b, 0x60, 0x7d, 0x76, 0x1f, 0x14, 0x09, 0x02, 0x33, 0x38, 0x25, 0x2e,
+      0x8c, 0x87, 0x9a, 0x91, 0xa0, 0xab, 0xb6, 0xbd, 0xd4, 0xdf, 0xc2, 0xc9, 0xf8, 0xf3, 0xee, 0xe5,
+      0x3c, 0x37, 0x2a, 0x21, 0x10, 0x1b, 0x06, 0x0d, 0x64, 0x6f, 0x72, 0x79, 0x48, 0x43, 0x5e, 0x55,
+      0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30, 0x59, 0x52, 0x4f, 0x44, 0x75, 0x7e, 0x63, 0x68,
+      0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80, 0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8,
+      0x7a, 0x71, 0x6c, 0x67, 0x56, 0x5d, 0x40, 0x4b, 0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13,
+      0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3,
+    };
+    return FFMul0B[in];
+  }
+
+  static uint8_t FFMul0D(uint8_t in) {
+    static const uint8_t FFMul0D[256] = {
+      0x00, 0x0d, 0x1a, 0x17, 0x34, 0x39, 0x2e, 0x23, 0x68, 0x65, 0x72, 0x7f, 0x5c, 0x51, 0x46, 0x4b,
+      0xd0, 0xdd, 0xca, 0xc7, 0xe4, 0xe9, 0xfe, 0xf3, 0xb8, 0xb5, 0xa2, 0xaf, 0x8c, 0x81, 0x96, 0x9b,
+      0xbb, 0xb6, 0xa1, 0xac, 0x8f, 0x82, 0x95, 0x98, 0xd3, 0xde, 0xc9, 0xc4, 0xe7, 0xea, 0xfd, 0xf0,
+      0x6b, 0x66, 0x71, 0x7c, 0x5f, 0x52, 0x45, 0x48, 0x03, 0x0e, 0x19, 0x14, 0x37, 0x3a, 0x2d, 0x20,
+      0x6d, 0x60, 0x77, 0x7a, 0x59, 0x54, 0x43, 0x4e, 0x05, 0x08, 0x1f, 0x12, 0x31, 0x3c, 0x2b, 0x26,
+      0xbd, 0xb0, 0xa7, 0xaa, 0x89, 0x84, 0x93, 0x9e, 0xd5, 0xd8, 0xcf, 0xc2, 0xe1, 0xec, 0xfb, 0xf6,
+      0xd6, 0xdb, 0xcc, 0xc1, 0xe2, 0xef, 0xf8, 0xf5, 0xbe, 0xb3, 0xa4, 0xa9, 0x8a, 0x87, 0x90, 0x9d,
+      0x06, 0x0b, 0x1c, 0x11, 0x32, 0x3f, 0x28, 0x25, 0x6e, 0x63, 0x74, 0x79, 0x5a, 0x57, 0x40, 0x4d,
+      0xda, 0xd7, 0xc0, 0xcd, 0xee, 0xe3, 0xf4, 0xf9, 0xb2, 0xbf, 0xa8, 0xa5, 0x86, 0x8b, 0x9c, 0x91,
+      0x0a, 0x07, 0x10, 0x1d, 0x3e, 0x33, 0x24, 0x29, 0x62, 0x6f, 0x78, 0x75, 0x56, 0x5b, 0x4c, 0x41,
+      0x61, 0x6c, 0x7b, 0x76, 0x55, 0x58, 0x4f, 0x42, 0x09, 0x04, 0x13, 0x1e, 0x3d, 0x30, 0x27, 0x2a,
+      0xb1, 0xbc, 0xab, 0xa6, 0x85, 0x88, 0x9f, 0x92, 0xd9, 0xd4, 0xc3, 0xce, 0xed, 0xe0, 0xf7, 0xfa,
+      0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94, 0xdf, 0xd2, 0xc5, 0xc8, 0xeb, 0xe6, 0xf1, 0xfc,
+      0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44, 0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c,
+      0x0c, 0x01, 0x16, 0x1b, 0x38, 0x35, 0x22, 0x2f, 0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47,
+      0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97,
+    };
+
+    return FFMul0D[in];
+  }
+
+  static uint8_t FFMul0E(uint8_t in) {
+    static const uint8_t FFMul0E[256] = {
+      0x00, 0x0e, 0x1c, 0x12, 0x38, 0x36, 0x24, 0x2a, 0x70, 0x7e, 0x6c, 0x62, 0x48, 0x46, 0x54, 0x5a,
+      0xe0, 0xee, 0xfc, 0xf2, 0xd8, 0xd6, 0xc4, 0xca, 0x90, 0x9e, 0x8c, 0x82, 0xa8, 0xa6, 0xb4, 0xba,
+      0xdb, 0xd5, 0xc7, 0xc9, 0xe3, 0xed, 0xff, 0xf1, 0xab, 0xa5, 0xb7, 0xb9, 0x93, 0x9d, 0x8f, 0x81,
+      0x3b, 0x35, 0x27, 0x29, 0x03, 0x0d, 0x1f, 0x11, 0x4b, 0x45, 0x57, 0x59, 0x73, 0x7d, 0x6f, 0x61,
+      0xad, 0xa3, 0xb1, 0xbf, 0x95, 0x9b, 0x89, 0x87, 0xdd, 0xd3, 0xc1, 0xcf, 0xe5, 0xeb, 0xf9, 0xf7,
+      0x4d, 0x43, 0x51, 0x5f, 0x75, 0x7b, 0x69, 0x67, 0x3d, 0x33, 0x21, 0x2f, 0x05, 0x0b, 0x19, 0x17,
+      0x76, 0x78, 0x6a, 0x64, 0x4e, 0x40, 0x52, 0x5c, 0x06, 0x08, 0x1a, 0x14, 0x3e, 0x30, 0x22, 0x2c,
+      0x96, 0x98, 0x8a, 0x84, 0xae, 0xa0, 0xb2, 0xbc, 0xe6, 0xe8, 0xfa, 0xf4, 0xde, 0xd0, 0xc2, 0xcc,
+      0x41, 0x4f, 0x5d, 0x53, 0x79, 0x77, 0x65, 0x6b, 0x31, 0x3f, 0x2d, 0x23, 0x09, 0x07, 0x15, 0x1b,
+      0xa1, 0xaf, 0xbd, 0xb3, 0x99, 0x97, 0x85, 0x8b, 0xd1, 0xdf, 0xcd, 0xc3, 0xe9, 0xe7, 0xf5, 0xfb,
+      0x9a, 0x94, 0x86, 0x88, 0xa2, 0xac, 0xbe, 0xb0, 0xea, 0xe4, 0xf6, 0xf8, 0xd2, 0xdc, 0xce, 0xc0,
+      0x7a, 0x74, 0x66, 0x68, 0x42, 0x4c, 0x5e, 0x50, 0x0a, 0x04, 0x16, 0x18, 0x32, 0x3c, 0x2e, 0x20,
+      0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6, 0x9c, 0x92, 0x80, 0x8e, 0xa4, 0xaa, 0xb8, 0xb6,
+      0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26, 0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56,
+      0x37, 0x39, 0x2b, 0x25, 0x0f, 0x01, 0x13, 0x1d, 0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d,
+      0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d,
+    };
+
+    return FFMul0E[in];
+  }
+
+  static __uint128_t InvMixColumns(uint8_t *State) {
+    uint8_t In0[16] = {
+      State[0], State[4], State[8], State[12],
+      State[1], State[5], State[9], State[13],
+      State[2], State[6], State[10], State[14],
+      State[3], State[7], State[11], State[15],
+    };
+
+    uint8_t Out0[4]{};
+    uint8_t Out1[4]{};
+    uint8_t Out2[4]{};
+    uint8_t Out3[4]{};
+
+    for (size_t i = 0; i < 4; ++i) {
+      Out0[i] = FFMul0E(In0[0 + i]) ^ FFMul0B(In0[4 + i]) ^ FFMul0D(In0[8 + i]) ^ FFMul09(In0[12 + i]);
+      Out1[i] = FFMul09(In0[0 + i]) ^ FFMul0E(In0[4 + i]) ^ FFMul0B(In0[8 + i]) ^ FFMul0D(In0[12 + i]);
+      Out2[i] = FFMul0D(In0[0 + i]) ^ FFMul09(In0[4 + i]) ^ FFMul0E(In0[8 + i]) ^ FFMul0B(In0[12 + i]);
+      Out3[i] = FFMul0B(In0[0 + i]) ^ FFMul0D(In0[4 + i]) ^ FFMul09(In0[8 + i]) ^ FFMul0E(In0[12 + i]);
+    }
+
+    uint8_t OutArray[16] = {
+      Out0[0], Out1[0], Out2[0], Out3[0],
+      Out0[1], Out1[1], Out2[1], Out3[1],
+      Out0[2], Out1[2], Out2[2], Out3[2],
+      Out0[3], Out1[3], Out2[3], Out3[3],
+    };
+    __uint128_t Res{};
+    memcpy(&Res, OutArray, 16);
+    return Res;
+  }
+}
+
+namespace CRC32 {
+  // CRC32 per byte lookup table.
+  constexpr std::array<uint32_t, 256> CRC32CTable = []() consteval {
+    std::array<uint32_t, 256> Table{};
+
+    // Clang 11.x doesn't support bitreverse as a consteval
+    // constexpr uint32_t Polynomial = 0x1EDC6F41;
+    constexpr uint32_t PolynomialRev = 0x82F63B78; //__builtin_bitreverse32(Polynomial);
+
+    for (size_t Char = 0; Char < std::size(Table); ++Char) {
+      uint32_t CurrentChar = Char;
+      for (size_t i = 0; i < 8; ++i) {
+        if (CurrentChar & 1) {
+          CurrentChar = (CurrentChar >> 1) ^ PolynomialRev;
+        }
+        else {
+          CurrentChar >>= 1;
+        }
+      }
+      Table[Char] = CurrentChar;
+    }
+
+    return Table;
+  }();
+
+  uint32_t crc32cb(uint32_t Accumulator, uint8_t data) {
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ data] ^ Accumulator >> 8;
+    return Accumulator;
+  }
+
+  uint32_t crc32ch(uint32_t Accumulator, uint16_t data) {
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 0) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 8) & 0xFF)] ^ Accumulator >> 8;
+    return Accumulator;
+  }
+
+  uint32_t crc32cw(uint32_t Accumulator, uint32_t data) {
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  0) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  8) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 16) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 24) & 0xFF)] ^ Accumulator >> 8;
+    return Accumulator;
+  }
+
+  uint32_t crc32cx(uint32_t Accumulator, uint64_t data) {
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  0) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  8) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 16) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 24) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 32) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 40) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 48) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 56) & 0xFF)] ^ Accumulator >> 8;
+    return Accumulator;
+  }
+}
+
+namespace FEXCore::CPU {
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+
+DEF_OP(AESImc) {
+  auto Op = IROp->C<IR::IROp_VAESImc>();
+  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+
+  // Pseudo-code
+  // Dst = InvMixColumns(STATE)
+  __uint128_t Tmp{};
+  Tmp = AES::InvMixColumns(reinterpret_cast<uint8_t*>(&Src1));
+  memcpy(GDP, &Tmp, sizeof(Tmp));
+}
+
+DEF_OP(AESEnc) {
+  auto Op = IROp->C<IR::IROp_VAESEnc>();
+  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+
+  // Pseudo-code
+  // STATE = Src1
+  // RoundKey = Src2
+  // STATE = ShiftRows(STATE)
+  // STATE = SubBytes(STATE)
+  // STATE = MixColumns(STATE)
+  // Dst = STATE XOR RoundKey
+  __uint128_t Tmp{};
+  Tmp = AES::ShiftRows(reinterpret_cast<uint8_t*>(&Src1));
+  Tmp = AES::SubBytes(reinterpret_cast<uint8_t*>(&Tmp), 16);
+  Tmp = AES::MixColumns(reinterpret_cast<uint8_t*>(&Tmp));
+  Tmp = Tmp ^ Src2;
+  memcpy(GDP, &Tmp, sizeof(Tmp));
+}
+
+DEF_OP(AESEncLast) {
+  auto Op = IROp->C<IR::IROp_VAESEncLast>();
+  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+
+  // Pseudo-code
+  // STATE = Src1
+  // RoundKey = Src2
+  // STATE = ShiftRows(STATE)
+  // STATE = SubBytes(STATE)
+  // Dst = STATE XOR RoundKey
+  __uint128_t Tmp{};
+  Tmp = AES::ShiftRows(reinterpret_cast<uint8_t*>(&Src1));
+  Tmp = AES::SubBytes(reinterpret_cast<uint8_t*>(&Tmp), 16);
+  Tmp = Tmp ^ Src2;
+  memcpy(GDP, &Tmp, sizeof(Tmp));
+}
+
+DEF_OP(AESDec) {
+  auto Op = IROp->C<IR::IROp_VAESDec>();
+  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+
+  // Pseudo-code
+  // STATE = Src1
+  // RoundKey = Src2
+  // STATE = InvShiftRows(STATE)
+  // STATE = InvSubBytes(STATE)
+  // STATE = InvMixColumns(STATE)
+  // Dst = STATE XOR RoundKey
+  __uint128_t Tmp{};
+  Tmp = AES::InvShiftRows(reinterpret_cast<uint8_t*>(&Src1));
+  Tmp = AES::InvSubBytes(reinterpret_cast<uint8_t*>(&Tmp));
+  Tmp = AES::InvMixColumns(reinterpret_cast<uint8_t*>(&Tmp));
+  Tmp = Tmp ^ Src2;
+  memcpy(GDP, &Tmp, sizeof(Tmp));
+}
+
+DEF_OP(AESDecLast) {
+  auto Op = IROp->C<IR::IROp_VAESDecLast>();
+  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+
+  // Pseudo-code
+  // STATE = Src1
+  // RoundKey = Src2
+  // STATE = InvShiftRows(STATE)
+  // STATE = InvSubBytes(STATE)
+  // Dst = STATE XOR RoundKey
+  __uint128_t Tmp{};
+  Tmp = AES::InvShiftRows(reinterpret_cast<uint8_t*>(&Src1));
+  Tmp = AES::InvSubBytes(reinterpret_cast<uint8_t*>(&Tmp));
+  Tmp = Tmp ^ Src2;
+  memcpy(GDP, &Tmp, sizeof(Tmp));
+}
+
+DEF_OP(AESKeyGenAssist) {
+  auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
+  uint8_t *Src1 = GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+
+  // Pseudo-code
+  // X3 = Src1[127:96]
+  // X2 = Src1[95:64]
+  // X1 = Src1[63:32]
+  // X0 = Src1[31:30]
+  // RCON = (Zext)rcon
+  // Dest[31:0] = SubWord(X1)
+  // Dest[63:32] = RotWord(SubWord(X1)) XOR RCON
+  // Dest[95:64] = SubWord(X3)
+  // Dest[127:96] = RotWord(SubWord(X3)) XOR RCON
+  __uint128_t Tmp{};
+  uint32_t X1{};
+  uint32_t X3{};
+  memcpy(&X1, &Src1[4], 4);
+  memcpy(&X3, &Src1[12], 4);
+  uint32_t SubWord_X1 = AES::SubBytes(reinterpret_cast<uint8_t*>(&X1), 4);
+  uint32_t SubWord_X3 = AES::SubBytes(reinterpret_cast<uint8_t*>(&X3), 4);
+
+  auto Ror = [] (auto In, auto R) {
+    auto RotateMask = sizeof(In) * 8 - 1;
+    R &= RotateMask;
+    return (In >> R) | (In << (sizeof(In) * 8 - R));
+  };
+
+  uint32_t Rot_X1 = Ror(SubWord_X1, 8);
+  uint32_t Rot_X3 = Ror(SubWord_X3, 8);
+
+  Tmp = Rot_X3 ^ Op->RCON;
+  Tmp <<= 32;
+  Tmp |= SubWord_X3;
+  Tmp <<= 32;
+  Tmp |= Rot_X1 ^ Op->RCON;
+  Tmp <<= 32;
+  Tmp |= SubWord_X1;
+  memcpy(GDP, &Tmp, sizeof(Tmp));
+}
+
+DEF_OP(CRC32) {
+  auto Op = IROp->C<IR::IROp_CRC32>();
+  uint32_t Src1 = *GetSrc<uint32_t*>(Data->SSAData, Op->Src1);
+  uint8_t *Src2 = GetSrc<uint8_t*>(Data->SSAData, Op->Src2);
+  uint32_t Tmp{};
+
+  switch (Op->SrcSize) {
+    case 1:
+      Tmp = CRC32::crc32cb(Src1, *(uint8_t*)Src2);
+      break;
+    case 2:
+      Tmp = CRC32::crc32ch(Src1, *(uint16_t*)Src2);
+      break;
+    case 4:
+      Tmp = CRC32::crc32cw(Src1, *(uint32_t*)Src2);
+      break;
+    case 8:
+      Tmp = CRC32::crc32cx(Src1, *(uint64_t*)Src2);
+      break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown CRC32C size: {}", Op->SrcSize);
+      break;
+
+  }
+  memcpy(GDP, &Tmp, sizeof(Tmp));
+}
+
+#undef DEF_OP
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp

@@ -0,0 +1,361 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+
+#include "F80Ops.h"
+
+#include <cstdint>
+
+namespace FEXCore::CPU {
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+DEF_OP(F80LOADFCW) {
+  FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle(*GetSrc<uint16_t*>(Data->SSAData, IROp->Args[0]));
+}
+
+DEF_OP(F80ADD) {
+  auto Op = IROp->C<IR::IROp_F80Add>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FADD(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80SUB) {
+  auto Op = IROp->C<IR::IROp_F80Sub>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FSUB(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80MUL) {
+  auto Op = IROp->C<IR::IROp_F80Mul>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FMUL(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80DIV) {
+  auto Op = IROp->C<IR::IROp_F80Div>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FDIV(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80FYL2X) {
+  auto Op = IROp->C<IR::IROp_F80FYL2X>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FYL2X(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80ATAN) {
+  auto Op = IROp->C<IR::IROp_F80ATAN>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FATAN(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80FPREM1) {
+  auto Op = IROp->C<IR::IROp_F80FPREM1>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FREM1(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80FPREM) {
+  auto Op = IROp->C<IR::IROp_F80FPREM>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FREM(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80SCALE) {
+  auto Op = IROp->C<IR::IROp_F80SCALE>();
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FSCALE(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80CVT) {
+  auto Op = IROp->C<IR::IROp_F80CVT>();
+  uint8_t OpSize = IROp->Size;
+
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+
+  switch (OpSize) {
+    case 4: {
+      float Tmp = Src;
+      memcpy(GDP, &Tmp, OpSize);
+      break;
+    }
+    case 8: {
+      double Tmp = Src;
+      memcpy(GDP, &Tmp, OpSize);
+      break;
+    }
+    default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+  }
+}
+
+DEF_OP(F80CVTINT) {
+  auto Op = IROp->C<IR::IROp_F80CVTInt>();
+  uint8_t OpSize = IROp->Size;
+
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+
+  switch (OpSize) {
+    case 2: {
+      int16_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t : FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2)(Src);
+      memcpy(GDP, &Tmp, sizeof(Tmp));
+      break;
+    }
+    case 4: {
+      int32_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t : FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4)(Src);
+      memcpy(GDP, &Tmp, sizeof(Tmp));
+      break;
+    }
+    case 8: {
+      int64_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t : FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8)(Src);
+      memcpy(GDP, &Tmp, sizeof(Tmp));
+      break;
+    }
+    default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+  }
+}
+
+DEF_OP(F80CVTTO) {
+  auto Op = IROp->C<IR::IROp_F80CVTTo>();
+
+  switch (Op->Size) {
+    case 4: {
+      float Src = *GetSrc<float *>(Data->SSAData, Op->Header.Args[0]);
+      X80SoftFloat Tmp = Src;
+      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+      break;
+    }
+    case 8: {
+      double Src = *GetSrc<double *>(Data->SSAData, Op->Header.Args[0]);
+      X80SoftFloat Tmp = Src;
+      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+      break;
+    }
+    default: LogMan::Msg::DFmt("Unhandled size: {}", Op->Size);
+  }
+}
+
+DEF_OP(F80CVTTOINT) {
+  auto Op = IROp->C<IR::IROp_F80CVTToInt>();
+
+  switch (Op->Size) {
+    case 2: {
+      int16_t Src = *GetSrc<int16_t*>(Data->SSAData, Op->Header.Args[0]);
+      X80SoftFloat Tmp = Src;
+      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+      break;
+    }
+    case 4: {
+      int32_t Src = *GetSrc<int32_t*>(Data->SSAData, Op->Header.Args[0]);
+      X80SoftFloat Tmp = Src;
+      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+      break;
+    }
+    default: LogMan::Msg::DFmt("Unhandled size: {}", Op->Size);
+  }
+}
+
+DEF_OP(F80ROUND) {
+  auto Op = IROp->C<IR::IROp_F80Round>();
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FRNDINT(Src);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80F2XM1) {
+  auto Op = IROp->C<IR::IROp_F80F2XM1>();
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::F2XM1(Src);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80TAN) {
+  auto Op = IROp->C<IR::IROp_F80TAN>();
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FTAN(Src);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80SQRT) {
+  auto Op = IROp->C<IR::IROp_F80SQRT>();
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FSQRT(Src);
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80SIN) {
+  auto Op = IROp->C<IR::IROp_F80SIN>();
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FSIN(Src);
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80COS) {
+  auto Op = IROp->C<IR::IROp_F80COS>();
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FCOS(Src);
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80XTRACT_EXP) {
+  auto Op = IROp->C<IR::IROp_F80XTRACT_EXP>();
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FXTRACT_EXP(Src);
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80XTRACT_SIG) {
+  auto Op = IROp->C<IR::IROp_F80XTRACT_SIG>();
+  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Tmp;
+  Tmp = X80SoftFloat::FXTRACT_SIG(Src);
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80CMP) {
+  auto Op = IROp->C<IR::IROp_F80Cmp>();
+  uint32_t ResultFlags{};
+  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  bool eq, lt, nan;
+  X80SoftFloat::FCMP(Src1, Src2, &eq, &lt, &nan);
+  if (Op->Flags & (1 << IR::FCMP_FLAG_LT) &&
+      lt) {
+    ResultFlags |= (1 << IR::FCMP_FLAG_LT);
+  }
+  if (Op->Flags & (1 << IR::FCMP_FLAG_UNORDERED) &&
+      nan) {
+    ResultFlags |= (1 << IR::FCMP_FLAG_UNORDERED);
+  }
+  if (Op->Flags & (1 << IR::FCMP_FLAG_EQ) &&
+      eq) {
+    ResultFlags |= (1 << IR::FCMP_FLAG_EQ);
+  }
+
+  GD = ResultFlags;
+}
+
+DEF_OP(F80BCDLOAD) {
+  auto Op = IROp->C<IR::IROp_F80BCDLoad>();
+  uint8_t *Src1 = GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+  uint64_t BCD{};
+  // We walk through each uint8_t and pull out the BCD encoding
+  // Each 4bit split is a digit
+  // Only 0-9 is supported, A-F results in undefined data
+  // | 4 bit     | 4 bit    |
+  // | 10s place | 1s place |
+  // EG 0x48 = 48
+  // EG 0x4847 = 4847
+  // This gives us an 18digit value encoded in BCD
+  // The last byte lets us know if it negative or not
+  for (size_t i = 0; i < 9; ++i) {
+    uint8_t Digit = Src1[8 - i];
+    // First shift our last value over
+    BCD *= 100;
+
+    // Add the tens place digit
+    BCD += (Digit >> 4) * 10;
+
+    // Add the ones place digit
+    BCD += Digit & 0xF;
+  }
+
+  // Set negative flag once converted to x87
+  bool Negative = Src1[9] & 0x80;
+  X80SoftFloat Tmp;
+
+  Tmp = BCD;
+  Tmp.Sign = Negative;
+
+  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
+}
+
+DEF_OP(F80BCDSTORE) {
+  auto Op = IROp->C<IR::IROp_F80BCDStore>();
+  X80SoftFloat Src1 = X80SoftFloat::FRNDINT(*GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]));
+  bool Negative = Src1.Sign;
+
+  // Clear the Sign bit
+  Src1.Sign = 0;
+
+  uint64_t Tmp = Src1;
+  uint8_t BCD[10]{};
+
+  for (size_t i = 0; i < 9; ++i) {
+    if (Tmp == 0) {
+      // Nothing left? Just leave
+      break;
+    }
+    // Extract the lower 100 values
+    uint8_t Digit = Tmp % 100;
+
+    // Now divide it for the next iteration
+    Tmp /= 100;
+
+    uint8_t UpperNibble = Digit / 10;
+    uint8_t LowerNibble = Digit % 10;
+
+    // Now store the BCD
+    BCD[i] = (UpperNibble << 4) | LowerNibble;
+  }
+
+  // Set negative flag once converted to x87
+  BCD[9] = Negative ? 0x80 : 0;
+
+  memcpy(GDP, BCD, 10);
+}
+
+#undef DEF_OP
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.h

@@ -0,0 +1,332 @@
+#pragma once
+#include "Common/SoftFloat.h"
+#include "Common/SoftFloat-3e/softfloat.h"
+
+#include <FEXCore/IR/IR.h>
+
+namespace FEXCore::CPU {
+template<IR::IROps Op>
+struct OpHandlers {
+
+};
+
+template<>
+struct OpHandlers<IR::OP_F80CVTTO> {
+  static X80SoftFloat handle4(float src) {
+    return src;
+  }
+
+  static X80SoftFloat handle8(double src) {
+    return src;
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80CMP> {
+  template<uint32_t Flags>
+  static uint64_t handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    bool eq, lt, nan;
+    uint64_t ResultFlags = 0;
+
+    X80SoftFloat::FCMP(Src1, Src2, &eq, &lt, &nan);
+    if (Flags & (1 << IR::FCMP_FLAG_LT) &&
+        lt) {
+      ResultFlags |= (1 << IR::FCMP_FLAG_LT);
+    }
+    if (Flags & (1 << IR::FCMP_FLAG_UNORDERED) &&
+        nan) {
+      ResultFlags |= (1 << IR::FCMP_FLAG_UNORDERED);
+    }
+    if (Flags & (1 << IR::FCMP_FLAG_EQ) &&
+        eq) {
+      ResultFlags |= (1 << IR::FCMP_FLAG_EQ);
+    }
+    return ResultFlags;
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80CVT> {
+  static float handle4(X80SoftFloat src) {
+    return src;
+  }
+
+  static double handle8(X80SoftFloat src) {
+    return src;
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80CVTINT> {
+  static  int16_t handle2(X80SoftFloat src) {
+    return src;
+  }
+
+  static int32_t handle4(X80SoftFloat src) {
+    return src;
+  }
+
+  static int64_t handle8(X80SoftFloat src) {
+    return src;
+  }
+
+  static  int16_t handle2t(X80SoftFloat src) {
+    auto rv = extF80_to_i32(src, softfloat_round_minMag, false);
+
+    if (rv > INT16_MAX) {
+      return INT16_MAX;
+    } else if (rv < INT16_MIN) {
+      return INT16_MIN;
+    } else {
+      return rv;
+    }
+  }
+
+  static int32_t handle4t(X80SoftFloat src) {
+    return extF80_to_i32(src, softfloat_round_minMag, false);
+  }
+
+  static int64_t handle8t(X80SoftFloat src) {
+    return extF80_to_i64(src, softfloat_round_minMag, false);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80CVTTOINT> {
+  static X80SoftFloat handle2(int16_t src) {
+    return src;
+  }
+
+  static X80SoftFloat handle4(int32_t src) {
+    return src;
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80ROUND> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    return X80SoftFloat::FRNDINT(Src1);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80F2XM1> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    return X80SoftFloat::F2XM1(Src1);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80TAN> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    return X80SoftFloat::FTAN(Src1);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80SQRT> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    return X80SoftFloat::FSQRT(Src1);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80SIN> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    return X80SoftFloat::FSIN(Src1);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80COS> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    return X80SoftFloat::FCOS(Src1);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80XTRACT_EXP> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    return X80SoftFloat::FXTRACT_EXP(Src1);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80XTRACT_SIG> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    return X80SoftFloat::FXTRACT_SIG(Src1);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80ADD> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FADD(Src1, Src2);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80SUB> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FSUB(Src1, Src2);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80MUL> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FMUL(Src1, Src2);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80DIV> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FDIV(Src1, Src2);
+  }
+};
+
+
+template<>
+struct OpHandlers<IR::OP_F80FYL2X> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FYL2X(Src1, Src2);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80ATAN> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FATAN(Src1, Src2);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80FPREM1> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FREM1(Src1, Src2);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80FPREM> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FREM(Src1, Src2);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80SCALE> {
+  static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) {
+    return X80SoftFloat::FSCALE(Src1, Src2);
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80BCDSTORE> {
+  static X80SoftFloat handle(X80SoftFloat Src1) {
+    bool Negative = Src1.Sign;
+
+    Src1 = X80SoftFloat::FRNDINT(Src1);
+
+    // Clear the Sign bit
+    Src1.Sign = 0;
+
+    uint64_t Tmp = Src1;
+    X80SoftFloat Rv;
+    uint8_t *BCD = reinterpret_cast<uint8_t*>(&Rv);
+    memset(BCD, 0, 10);
+
+    for (size_t i = 0; i < 9; ++i) {
+      if (Tmp == 0) {
+        // Nothing left? Just leave
+        break;
+      }
+      // Extract the lower 100 values
+      uint8_t Digit = Tmp % 100;
+
+      // Now divide it for the next iteration
+      Tmp /= 100;
+
+      uint8_t UpperNibble = Digit / 10;
+      uint8_t LowerNibble = Digit % 10;
+
+      // Now store the BCD
+      BCD[i] = (UpperNibble << 4) | LowerNibble;
+    }
+
+    // Set negative flag once converted to x87
+    BCD[9] = Negative ? 0x80 : 0;
+
+    return Rv;
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80BCDLOAD> {
+  static X80SoftFloat handle(X80SoftFloat Src) {
+    uint8_t *Src1 = reinterpret_cast<uint8_t *>(&Src);
+    uint64_t BCD{};
+    // We walk through each uint8_t and pull out the BCD encoding
+    // Each 4bit split is a digit
+    // Only 0-9 is supported, A-F results in undefined data
+    // | 4 bit     | 4 bit    |
+    // | 10s place | 1s place |
+    // EG 0x48 = 48
+    // EG 0x4847 = 4847
+    // This gives us an 18digit value encoded in BCD
+    // The last byte lets us know if it negative or not
+    for (size_t i = 0; i < 9; ++i) {
+      uint8_t Digit = Src1[8 - i];
+      // First shift our last value over
+      BCD *= 100;
+
+      // Add the tens place digit
+      BCD += (Digit >> 4) * 10;
+
+      // Add the ones place digit
+      BCD += Digit & 0xF;
+    }
+
+    // Set negative flag once converted to x87
+    bool Negative = Src1[9] & 0x80;
+    X80SoftFloat Tmp;
+
+    Tmp = BCD;
+    Tmp.Sign = Negative;
+    return Tmp;
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_F80LOADFCW> {
+  static void handle(uint16_t NewFCW) {
+
+    auto PC = (NewFCW >> 8) & 3;
+    switch(PC) {
+      case 0: extF80_roundingPrecision = 32; break;
+      case 2: extF80_roundingPrecision = 64; break;
+      case 3: extF80_roundingPrecision = 80; break;
+      case 1: LOGMAN_MSG_A_FMT("Invalid x87 precision mode, {}", PC);
+    }
+
+    auto RC = (NewFCW >> 10) & 3;
+    switch(RC) {
+      case 0:
+        softfloat_roundingMode = softfloat_round_near_even;
+        break;
+      case 1:
+        softfloat_roundingMode = softfloat_round_min;
+        break;
+      case 2:
+        softfloat_roundingMode = softfloat_round_max;
+        break;
+      case 3:
+        softfloat_roundingMode = softfloat_round_minMag;
+      break;
+    }
+  }
+};
+
+
+}

External/FEXCore/Source/Interface/Core/Interpreter/FlagOps.cpp

@@ -0,0 +1,21 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+
+#include <cstdint>
+
+namespace FEXCore::CPU {
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+DEF_OP(GetHostFlag) {
+  auto Op = IROp->C<IR::IROp_GetHostFlag>();
+  GD = (*GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]) >> Op->Flag) & 1;
+}
+#undef DEF_OP
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h

@@ -1,14 +1,15 @@
 #pragma once
 
-#include "Interface/Core/LookupCache.h"
 #include "Interface/Core/InternalThreadState.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 
 namespace FEXCore::CPU {
-class DispatchGenerator;
+class X86DispatchGenerator;
+class Arm64DispatchGenerator;
 
 #define DESTMAP_AS_MAP 0
 #if DESTMAP_AS_MAP
@@ -19,35 +20,36 @@ using DestMapType = std::vector<uint32_t>;
 
 class InterpreterCore final : public CPUBackend {
 public:
-  explicit InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
-  ~InterpreterCore() override;
-  std::string GetName() override { return "Interpreter"; }
-  void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
+  explicit InterpreterCore(FEXCore::Context::Context *ctx,
+                           FEXCore::Core::InternalThreadState *Thread,
+                           bool CompileThread);
 
-  void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
+  [[nodiscard]] std::string GetName() override { return "Interpreter"; }
 
-  bool NeedsOpDispatch() override { return true; }
+  [[nodiscard]] void *CompileCode(uint64_t Entry,
+                                  FEXCore::IR::IRListView const *IR,
+                                  FEXCore::Core::DebugData *DebugData,
+                                  FEXCore::IR::RegisterAllocationData *RAData) override;
+
+  [[nodiscard]] void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
+
+  [[nodiscard]] bool NeedsOpDispatch() override { return true; }
 
   void CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-  void DeleteAsmDispatch();
-
-  bool HandleSIGBUS(int Signal, void *info, void *ucontext);
 
 private:
   FEXCore::Context::Context *CTX;
   FEXCore::Core::InternalThreadState *State;
 
-  uint32_t AllocateTmpSpace(size_t Size);
-  bool HandleSignalPause(int Signal, void *info, void *ucontext);
-  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-
-  template<typename Res>
-  Res GetDest(void* SSAData, IR::OrderedNodeWrapper Op);
-
-  template<typename Res>
-  Res GetSrc(void* SSAData, IR::OrderedNodeWrapper Src);
-
-  DispatchGenerator *Generator{};
+  std::unique_ptr<Dispatcher> Dispatcher{};
 };
 
-}
+template<typename T>
+T AtomicCompareAndSwap(T expected, T desired, T *addr);
+
+uint8_t AtomicFetchNeg(uint8_t *Addr);
+uint16_t AtomicFetchNeg(uint16_t *Addr);
+uint32_t AtomicFetchNeg(uint32_t *Addr);
+uint64_t AtomicFetchNeg(uint64_t *Addr);
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -1,127 +1,75 @@
-#include "Common/MathUtils.h"
-#include "Common/SoftFloat.h"
 #include "Interface/Context/Context.h"
 
-#ifdef _M_ARM_64
 #include "Interface/Core/ArchHelpers/Arm64.h"
-#endif
-#include "Interface/Core/LookupCache.h"
-#include "Interface/Core/DebugData.h"
-#include "Interface/Core/InternalThreadState.h"
+#include "Interface/Core/ArchHelpers/MContext.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/Interpreter/InterpreterClass.h"
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/SignalDelegator.h>
+#include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/LogManager.h>
 
-#include <FEXCore/Core/CPUBackend.h>
-#include <FEXCore/HLE/SyscallHandler.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-
-#include "Interface/HLE/Thunks/Thunks.h"
-
-#include <atomic>
-#include <cmath>
-#include <limits>
-#include <vector>
-#ifdef _M_X86_64
-#include <xmmintrin.h>
-#endif
+#include <memory>
+#include <bits/types/stack_t.h>
+#include <signal.h>
+#include <stdint.h>
+#include <unordered_map>
+#include <utility>
 
 #include "InterpreterOps.h"
 
-namespace FEXCore::CPU {
-
-static void InterpreterExecution(FEXCore::Core::InternalThreadState *Thread) {
-  auto LocalEntry = Thread->LocalIRCache.find(Thread->State.State.rip);
-  
-  InterpreterOps::InterpretIR(Thread, LocalEntry->second.IR.get(), LocalEntry->second.DebugData.get());
+namespace FEXCore::IR {
+  class IRListView;
+  class RegisterAllocationData;
 }
 
+namespace FEXCore::CPU {
+class CPUBackend;
 
-bool InterpreterCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
-#ifdef _M_ARM_64
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-  uint32_t *PC = (uint32_t*)_mcontext->pc;
-  uint32_t Instr = PC[0];
-  if ((Instr & FEXCore::ArchHelpers::Arm64::CASPAL_MASK) == FEXCore::ArchHelpers::Arm64::CASPAL_INST) { // CASPAL
-    if (FEXCore::ArchHelpers::Arm64::HandleCASPAL(_mcontext, info, Instr)) {
-      // Skip this instruction now
-      _mcontext->pc += 4;
-      return true;
-    }
-    else {
-      LogMan::Msg::E("Unhandled JIT SIGBUS CASPAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
-      return false;
-    }
-  }
-  else if ((Instr & FEXCore::ArchHelpers::Arm64::CASAL_MASK) == FEXCore::ArchHelpers::Arm64::CASAL_INST) { // CASAL
-    if (FEXCore::ArchHelpers::Arm64::HandleCASAL(_mcontext, info, Instr)) {
-      // Skip this instruction now
-      _mcontext->pc += 4;
-      return true;
-    }
-    else {
-      LogMan::Msg::E("Unhandled JIT SIGBUS CASAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
-      return false;
-    }
-  }
-  else if ((Instr & FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_MASK) == FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_INST) { // Atomic memory op
-    if (FEXCore::ArchHelpers::Arm64::HandleAtomicMemOp(_mcontext, info, Instr)) {
-      // Skip this instruction now
-      _mcontext->pc += 4;
-      return true;
-    }
-    else {
-      uint8_t Op = (PC[0] >> 12) & 0xF;
-      LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x: PC: %p Instruction: 0x%08x\n", Op, PC, PC[0]);
-      return false;
-    }
-  }
-#endif
-  return false;
+static void InterpreterExecution(FEXCore::Core::CpuStateFrame *Frame) {
+  auto Thread = Frame->Thread;
+
+  auto LocalEntry = Thread->LocalIRCache.find(Thread->CurrentFrame->State.rip);
+
+  InterpreterOps::InterpretIR(Thread, Thread->CurrentFrame->State.rip, LocalEntry->second.IR.get(), LocalEntry->second.DebugData.get());
 }
 
 InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread)
   : CTX {ctx}
   , State {Thread} {
-  // Grab our space for temporary data
 
   if (!CompileThread &&
       CTX->Config.Core == FEXCore::Config::CONFIG_INTERPRETER) {
     CreateAsmDispatch(ctx, Thread);
     CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
       InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->HandleSignalPause(Signal, info, ucontext);
-    });
+      return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
+    }, true);
 
+#ifdef _M_ARM_64
     CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->HandleSIGBUS(Signal, info, ucontext);
-    });
+      return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(true, Signal, info, ucontext);
+    }, true);
+#endif
 
     auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
       InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
+      return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
     };
 
-    for (uint32_t Signal = 0; Signal < SignalDelegator::MAX_SIGNALS; ++Signal) {
+    for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
       CTX->SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
     }
   }
 }
 
-
-InterpreterCore::~InterpreterCore() {
-  DeleteAsmDispatch();
-}
-
-
-void *InterpreterCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
+void *InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
   return reinterpret_cast<void*>(InterpreterExecution);
 }
 
-FEXCore::CPU::CPUBackend *CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread) {
-  return new InterpreterCore(ctx, Thread, CompileThread);
+std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread) {
+  return std::make_unique<InterpreterCore>(ctx, Thread, CompileThread);
 }
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.h

@@ -1,5 +1,7 @@
 #pragma once
 
+#include <memory>
+
 namespace FEXCore::Context {
 struct Context;
 }
@@ -11,6 +13,8 @@ namespace FEXCore::Core {
 namespace FEXCore::CPU {
 class CPUBackend;
 
-FEXCore::CPU::CPUBackend *CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
+[[nodiscard]] std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx,
+                                                                FEXCore::Core::InternalThreadState *Thread,
+                                                                bool CompileThread);
 
-}
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterDefines.h

@@ -0,0 +1,179 @@
+#pragma once
+
+#include <FEXCore/IR/IR.h>
+
+#define GD *GetDest<uint64_t*>(Data->SSAData, Node)
+#define GDP GetDest<void*>(Data->SSAData, Node)
+
+#define DO_OP(size, type, func)              \
+  case size: {                                      \
+               auto *Dst_d  = reinterpret_cast<type*>(GDP);  \
+               auto *Src1_d = reinterpret_cast<type*>(Src1); \
+               auto *Src2_d = reinterpret_cast<type*>(Src2); \
+               *Dst_d = func(*Src1_d, *Src2_d);          \
+               break;                                            \
+             }
+#define DO_SCALAR_COMPARE_OP(size, type, type2, func)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type2*>(Tmp);  \
+  auto *Src1_d = reinterpret_cast<type*>(Src1); \
+  auto *Src2_d = reinterpret_cast<type*>(Src2); \
+  Dst_d[0] = func(Src1_d[0], Src2_d[0]);          \
+  break;                                            \
+  }
+
+#define DO_VECTOR_COMPARE_OP(size, type, type2, func)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type2*>(Tmp);  \
+  auto *Src1_d = reinterpret_cast<type*>(Src1); \
+  auto *Src2_d = reinterpret_cast<type*>(Src2); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = func(Src1_d[i], Src2_d[i]);          \
+  }                                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_OP(size, type, func)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src1_d = reinterpret_cast<type*>(Src1); \
+  auto *Src2_d = reinterpret_cast<type*>(Src2); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = func(Src1_d[i], Src2_d[i]);          \
+  }                                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_PAIR_OP(size, type, func)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src1_d = reinterpret_cast<type*>(Src1); \
+  auto *Src2_d = reinterpret_cast<type*>(Src2); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = func(Src1_d[i*2], Src1_d[i*2 + 1]);          \
+    Dst_d[i+Elements] = func(Src2_d[i*2], Src2_d[i*2 + 1]);          \
+  }                                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_SCALAR_OP(size, type, func)\
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src1_d = reinterpret_cast<type*>(Src1); \
+  auto *Src2_d = reinterpret_cast<type*>(Src2); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = func(Src1_d[i], *Src2_d);          \
+  }                                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_0SRC_OP(size, type, func)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = func();          \
+  }                                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_1SRC_OP(size, type, func)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src_d = reinterpret_cast<type*>(Src); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = func(Src_d[i]);          \
+  }                                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_REDUCE_1SRC_OP(size, type, func, start_val)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src_d = reinterpret_cast<type*>(Src); \
+  type begin = start_val;                           \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    begin = func(begin, Src_d[i]);          \
+  }                                                 \
+  Dst_d[0] = begin;                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_SAT_OP(size, type, func, min, max)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src1_d = reinterpret_cast<type*>(Src1); \
+  auto *Src2_d = reinterpret_cast<type*>(Src2); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = func(Src1_d[i], Src2_d[i], min, max);          \
+  }                                                 \
+  break;                                            \
+  }
+
+#define DO_VECTOR_1SRC_2TYPE_OP(size, type, type2, func, min, max)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src_d = reinterpret_cast<type2*>(Src); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = (type)func(Src_d[i], min, max);          \
+  }                                                 \
+  break;                                            \
+  }
+
+#define DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(type, type2, func, min, max)              \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src_d = reinterpret_cast<type2*>(Src); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = (type)func(Src_d[i], min, max);          \
+  }
+#define DO_VECTOR_1SRC_2TYPE_OP_TOP(size, type, type2, func, min, max)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src_d = reinterpret_cast<type2*>(Src2); \
+  memcpy(Dst_d, Src1, Elements * sizeof(type2));\
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i+Elements] = (type)func(Src_d[i], min, max);          \
+  }                                                 \
+  break;                                            \
+  }
+
+#define DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(size, type, type2, func, min, max)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src_d = reinterpret_cast<type2*>(Src); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = (type)func(Src_d[i+Elements], min, max);          \
+  }                                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_2SRC_2TYPE_OP(size, type, type2, func)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src1_d = reinterpret_cast<type2*>(Src1); \
+  auto *Src2_d = reinterpret_cast<type2*>(Src2); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = (type)func((type)Src1_d[i], (type)Src2_d[i]);          \
+  }                                                 \
+  break;                                            \
+  }
+#define DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(size, type, type2, func)              \
+  case size: {                                      \
+  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
+  auto *Src1_d = reinterpret_cast<type2*>(Src1); \
+  auto *Src2_d = reinterpret_cast<type2*>(Src2); \
+  for (uint8_t i = 0; i < Elements; ++i) {          \
+    Dst_d[i] = (type)func((type)Src1_d[i+Elements], (type)Src2_d[i+Elements]);          \
+  }                                                 \
+  break;                                            \
+  }
+
+template<typename Res>
+Res GetDest(void* SSAData, FEXCore::IR::OrderedNodeWrapper Op) {
+  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.ID().Value];
+  return reinterpret_cast<Res>(DstPtr);
+}
+
+template<typename Res>
+Res GetDest(void* SSAData, FEXCore::IR::NodeID Op) {
+  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.Value];
+  return reinterpret_cast<Res>(DstPtr);
+}
+
+
+template<typename Res>
+Res GetSrc(void* SSAData, FEXCore::IR::OrderedNodeWrapper Src) {
+  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Src.ID().Value];
+  return reinterpret_cast<Res>(DstPtr);
+}

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterFallbacks.cpp

@@ -0,0 +1,209 @@
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/F80Ops.h"
+
+#include <cstddef>
+#include <cstdint>
+
+namespace FEXCore::CPU {
+
+template<typename R, typename... Args>
+static FallbackInfo GetFallbackInfo(R(*fn)(Args...)) {
+  return {FABI_UNKNOWN, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(float)) {
+  return {FABI_F80_F32, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(double)) {
+  return {FABI_F80_F64, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int16_t)) {
+  return {FABI_F80_I16, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(void(*fn)(uint16_t)) {
+  return {FABI_VOID_U16, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int32_t)) {
+  return {FABI_F80_I32, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(float(*fn)(X80SoftFloat)) {
+  return {FABI_F32_F80, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(double(*fn)(X80SoftFloat)) {
+  return {FABI_F64_F80, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(int16_t(*fn)(X80SoftFloat)) {
+  return {FABI_I16_F80, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(int32_t(*fn)(X80SoftFloat)) {
+  return {FABI_I32_F80, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(int64_t(*fn)(X80SoftFloat)) {
+  return {FABI_I64_F80, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(uint64_t(*fn)(X80SoftFloat, X80SoftFloat)) {
+  return {FABI_I64_F80_F80, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat)) {
+  return {FABI_F80_F80, (void*)fn};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat, X80SoftFloat)) {
+  return {FABI_F80_F80_F80, (void*)fn};
+}
+
+bool InterpreterOps::GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info) {
+  uint8_t OpSize = IROp->Size;
+  switch(IROp->Op) {
+    case IR::OP_F80LOADFCW: {
+      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle);
+      return true;
+    }
+
+    case IR::OP_F80CVTTO: {
+      auto Op = IROp->C<IR::IROp_F80CVTTo>();
+
+      switch (Op->Size) {
+        case 4: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4);
+          return true;
+        }
+        case 8: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8);
+          return true;
+        }
+      default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+      }
+      break;
+    }
+    case IR::OP_F80CVT: {
+      switch (OpSize) {
+        case 4: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4);
+          return true;
+        }
+        case 8: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8);
+          return true;
+        }
+        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+      }
+      break;
+    }
+    case IR::OP_F80CVTINT: {
+      auto Op = IROp->C<IR::IROp_F80CVTInt>();
+
+      switch (OpSize) {
+        case 2: {
+          *Info = GetFallbackInfo(Op->Truncate ? &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t : &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2);
+          return true;
+        }
+        case 4: {
+          *Info = GetFallbackInfo(Op->Truncate ? &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t : &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4);
+          return true;
+        }
+        case 8: {
+          *Info = GetFallbackInfo(Op->Truncate ? &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t : &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8);
+          return true;
+        }
+        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+      }
+      break;
+    }
+    case IR::OP_F80CMP: {
+      auto Op = IROp->C<IR::IROp_F80Cmp>();
+
+      static constexpr std::array handlers{
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>,
+      };
+
+      *Info = GetFallbackInfo(handlers[Op->Flags]);
+      return true;
+    }
+
+    case IR::OP_F80CVTTOINT: {
+      auto Op = IROp->C<IR::IROp_F80CVTToInt>();
+
+      switch (Op->Size) {
+        case 2: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2);
+          return true;
+        }
+        case 4: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4);
+          return true;
+        }
+        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+      }
+      break;
+    }
+
+#define COMMON_X87_OP(OP) \
+    case IR::OP_F80##OP: { \
+      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle); \
+      return true; \
+    }
+
+    // Unary
+    COMMON_X87_OP(ROUND)
+    COMMON_X87_OP(F2XM1)
+    COMMON_X87_OP(TAN)
+    COMMON_X87_OP(SQRT)
+    COMMON_X87_OP(SIN)
+    COMMON_X87_OP(COS)
+    COMMON_X87_OP(XTRACT_EXP)
+    COMMON_X87_OP(XTRACT_SIG)
+    COMMON_X87_OP(BCDSTORE)
+    COMMON_X87_OP(BCDLOAD)
+
+    // Binary
+    COMMON_X87_OP(ADD)
+    COMMON_X87_OP(SUB)
+    COMMON_X87_OP(MUL)
+    COMMON_X87_OP(DIV)
+    COMMON_X87_OP(FYL2X)
+    COMMON_X87_OP(ATAN)
+    COMMON_X87_OP(FPREM1)
+    COMMON_X87_OP(FPREM)
+    COMMON_X87_OP(SCALE)
+
+    default:
+      break;
+  }
+
+  return false;
+}
+
+
+}

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -1,9 +1,16 @@
+#pragma once
+#include <stdint.h>
+
+#include <FEXCore/IR/IR.h>
+#include <FEXCore/IR/IntrusiveIRList.h>
+
 namespace FEXCore::Core {
   struct InternalThreadState;
 }
 
 namespace FEXCore::IR {
     class IRListView;
+    struct IROp_Header;
 }
 
 namespace FEXCore::Core{
@@ -32,11 +39,363 @@ namespace FEXCore::CPU {
     FallbackABI ABI;
     void *fn;
   };
-  
+
   class InterpreterOps {
 
     public:
-      static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData);
+      static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, uint64_t Entry, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData);
       static bool GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info);
+
+      struct IROpData {
+        FEXCore::Core::InternalThreadState *State{};
+        uint64_t CurrentEntry{};
+        FEXCore::IR::IRListView *CurrentIR{};
+        volatile void *StackEntry{};
+        void *SSAData{};
+        struct {
+          bool Quit;
+          bool Redo;
+        } BlockResults{};
+
+        IR::NodeIterator BlockIterator{0, 0};
+      };
+
+#define DEF_OP(x) static void Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+
+  ///< Unhandled handler
+  DEF_OP(Unhandled);
+
+  ///< No-op Handler
+  DEF_OP(NoOp);
+
+  ///< ALU Ops
+  DEF_OP(TruncElementPair);
+  DEF_OP(Constant);
+  DEF_OP(EntrypointOffset);
+  DEF_OP(InlineConstant);
+  DEF_OP(InlineEntrypointOffset);
+  DEF_OP(CycleCounter);
+  DEF_OP(Add);
+  DEF_OP(Sub);
+  DEF_OP(Neg);
+  DEF_OP(Mul);
+  DEF_OP(UMul);
+  DEF_OP(Div);
+  DEF_OP(UDiv);
+  DEF_OP(Rem);
+  DEF_OP(URem);
+  DEF_OP(MulH);
+  DEF_OP(UMulH);
+  DEF_OP(Or);
+  DEF_OP(And);
+  DEF_OP(Andn);
+  DEF_OP(Xor);
+  DEF_OP(Lshl);
+  DEF_OP(Lshr);
+  DEF_OP(Ashr);
+  DEF_OP(Rol);
+  DEF_OP(Ror);
+  DEF_OP(Extr);
+  DEF_OP(PDep);
+  DEF_OP(PExt);
+  DEF_OP(LDiv);
+  DEF_OP(LUDiv);
+  DEF_OP(LRem);
+  DEF_OP(LURem);
+  DEF_OP(Zext);
+  DEF_OP(Not);
+  DEF_OP(Popcount);
+  DEF_OP(FindLSB);
+  DEF_OP(FindMSB);
+  DEF_OP(FindTrailingZeros);
+  DEF_OP(CountLeadingZeroes);
+  DEF_OP(Rev);
+  DEF_OP(Bfi);
+  DEF_OP(Bfe);
+  DEF_OP(Sbfe);
+  DEF_OP(Select);
+  DEF_OP(VExtractToGPR);
+  DEF_OP(Float_ToGPR_ZU);
+  DEF_OP(Float_ToGPR_ZS);
+  DEF_OP(Float_ToGPR_S);
+  DEF_OP(FCmp);
+
+  ///< Atomic ops
+  DEF_OP(CASPair);
+  DEF_OP(CAS);
+  DEF_OP(AtomicAdd);
+  DEF_OP(AtomicSub);
+  DEF_OP(AtomicAnd);
+  DEF_OP(AtomicOr);
+  DEF_OP(AtomicXor);
+  DEF_OP(AtomicSwap);
+  DEF_OP(AtomicFetchAdd);
+  DEF_OP(AtomicFetchSub);
+  DEF_OP(AtomicFetchAnd);
+  DEF_OP(AtomicFetchOr);
+  DEF_OP(AtomicFetchXor);
+  DEF_OP(AtomicFetchNeg);
+
+  ///< Branch ops
+  DEF_OP(GuestCallDirect);
+  DEF_OP(GuestCallIndirect);
+  DEF_OP(GuestReturn);
+  DEF_OP(SignalReturn);
+  DEF_OP(CallbackReturn);
+  DEF_OP(ExitFunction);
+  DEF_OP(Jump);
+  DEF_OP(CondJump);
+  DEF_OP(Syscall);
+  DEF_OP(InlineSyscall);
+  DEF_OP(Thunk);
+  DEF_OP(ValidateCode);
+  DEF_OP(RemoveCodeEntry);
+  DEF_OP(CPUID);
+
+  ///< Conversion ops
+  DEF_OP(VInsGPR);
+  DEF_OP(VCastFromGPR);
+  DEF_OP(Float_FromGPR_S);
+  DEF_OP(Float_FToF);
+  DEF_OP(Vector_SToF);
+  DEF_OP(Vector_FToZS);
+  DEF_OP(Vector_FToS);
+  DEF_OP(Vector_FToF);
+  DEF_OP(Vector_FToI);
+
+  ///< Flag ops
+  DEF_OP(GetHostFlag);
+
+  ///< Memory ops
+  DEF_OP(LoadContext);
+  DEF_OP(StoreContext);
+  DEF_OP(LoadRegister);
+  DEF_OP(StoreRegister);
+  DEF_OP(LoadContextIndexed);
+  DEF_OP(StoreContextIndexed);
+  DEF_OP(SpillRegister);
+  DEF_OP(FillRegister);
+  DEF_OP(LoadFlag);
+  DEF_OP(StoreFlag);
+  DEF_OP(LoadMem);
+  DEF_OP(StoreMem);
+  DEF_OP(VLoadMemElement);
+  DEF_OP(VStoreMemElement);
+  DEF_OP(CacheLineClear);
+  DEF_OP(CacheLineZero);
+
+  ///< Misc ops
+  DEF_OP(EndBlock);
+  DEF_OP(Fence);
+  DEF_OP(Break);
+  DEF_OP(Phi);
+  DEF_OP(PhiValue);
+  DEF_OP(Print);
+  DEF_OP(GetRoundingMode);
+  DEF_OP(SetRoundingMode);
+  DEF_OP(ProcessorID);
+
+  ///< Move ops
+  DEF_OP(ExtractElementPair);
+  DEF_OP(CreateElementPair);
+  DEF_OP(Mov);
+
+  ///< Vector ops
+  DEF_OP(VectorZero);
+  DEF_OP(VectorImm);
+  DEF_OP(CreateVector2);
+  DEF_OP(CreateVector4);
+  DEF_OP(SplatVector);
+  DEF_OP(VMov);
+  DEF_OP(VAnd);
+  DEF_OP(VBic);
+  DEF_OP(VOr);
+  DEF_OP(VXor);
+  DEF_OP(VAdd);
+  DEF_OP(VSub);
+  DEF_OP(VUQAdd);
+  DEF_OP(VUQSub);
+  DEF_OP(VSQAdd);
+  DEF_OP(VSQSub);
+  DEF_OP(VAddP);
+  DEF_OP(VAddV);
+  DEF_OP(VUMinV);
+  DEF_OP(VURAvg);
+  DEF_OP(VAbs);
+  DEF_OP(VPopcount);
+  DEF_OP(VFAdd);
+  DEF_OP(VFAddP);
+  DEF_OP(VFSub);
+  DEF_OP(VFMul);
+  DEF_OP(VFDiv);
+  DEF_OP(VFMin);
+  DEF_OP(VFMax);
+  DEF_OP(VFRecp);
+  DEF_OP(VFSqrt);
+  DEF_OP(VFRSqrt);
+  DEF_OP(VNeg);
+  DEF_OP(VFNeg);
+  DEF_OP(VNot);
+  DEF_OP(VUMin);
+  DEF_OP(VSMin);
+  DEF_OP(VUMax);
+  DEF_OP(VSMax);
+  DEF_OP(VZip);
+  DEF_OP(VUnZip);
+  DEF_OP(VBSL);
+  DEF_OP(VCMPEQ);
+  DEF_OP(VCMPEQZ);
+  DEF_OP(VCMPGT);
+  DEF_OP(VCMPGTZ);
+  DEF_OP(VCMPLTZ);
+  DEF_OP(VFCMPEQ);
+  DEF_OP(VFCMPNEQ);
+  DEF_OP(VFCMPLT);
+  DEF_OP(VFCMPGT);
+  DEF_OP(VFCMPLE);
+  DEF_OP(VFCMPORD);
+  DEF_OP(VFCMPUNO);
+  DEF_OP(VUShl);
+  DEF_OP(VUShr);
+  DEF_OP(VSShr);
+  DEF_OP(VUShlS);
+  DEF_OP(VUShrS);
+  DEF_OP(VSShrS);
+  DEF_OP(VInsElement);
+  DEF_OP(VInsScalarElement);
+  DEF_OP(VExtractElement);
+  DEF_OP(VDupElement);
+  DEF_OP(VExtr);
+  DEF_OP(VSLI);
+  DEF_OP(VSRI);
+  DEF_OP(VUShrI);
+  DEF_OP(VSShrI);
+  DEF_OP(VShlI);
+  DEF_OP(VUShrNI);
+  DEF_OP(VUShrNI2);
+  DEF_OP(VBitcast);
+  DEF_OP(VSXTL);
+  DEF_OP(VSXTL2);
+  DEF_OP(VUXTL);
+  DEF_OP(VUXTL2);
+  DEF_OP(VSQXTN);
+  DEF_OP(VSQXTN2);
+  DEF_OP(VSQXTUN);
+  DEF_OP(VSQXTUN2);
+  DEF_OP(VUMul);
+  DEF_OP(VUMull);
+  DEF_OP(VSMul);
+  DEF_OP(VSMull);
+  DEF_OP(VUMull2);
+  DEF_OP(VSMull2);
+  DEF_OP(VUABDL);
+  DEF_OP(VTBL1);
+
+  ///< Encryption ops
+  DEF_OP(AESImc);
+  DEF_OP(AESEnc);
+  DEF_OP(AESEncLast);
+  DEF_OP(AESDec);
+  DEF_OP(AESDecLast);
+  DEF_OP(AESKeyGenAssist);
+  DEF_OP(CRC32);
+
+  ///< F80 ops
+  DEF_OP(F80LOADFCW);
+  DEF_OP(F80ADD);
+  DEF_OP(F80SUB);
+  DEF_OP(F80MUL);
+  DEF_OP(F80DIV);
+  DEF_OP(F80FYL2X);
+  DEF_OP(F80ATAN);
+  DEF_OP(F80FPREM1);
+  DEF_OP(F80FPREM);
+  DEF_OP(F80SCALE);
+  DEF_OP(F80CVT);
+  DEF_OP(F80CVTINT);
+  DEF_OP(F80CVTTO);
+  DEF_OP(F80CVTTOINT);
+  DEF_OP(F80ROUND);
+  DEF_OP(F80F2XM1);
+  DEF_OP(F80TAN);
+  DEF_OP(F80SQRT);
+  DEF_OP(F80SIN);
+  DEF_OP(F80COS);
+  DEF_OP(F80XTRACT_EXP);
+  DEF_OP(F80XTRACT_SIG);
+  DEF_OP(F80CMP);
+  DEF_OP(F80BCDLOAD);
+  DEF_OP(F80BCDSTORE);
+#undef DEF_OP
+  template<typename unsigned_type, typename signed_type, typename float_type>
+  [[nodiscard]] static bool IsConditionTrue(uint8_t Cond, uint64_t Src1, uint64_t Src2) {
+    bool CompResult = false;
+    switch (Cond) {
+      case FEXCore::IR::COND_EQ:
+        CompResult = static_cast<unsigned_type>(Src1) == static_cast<unsigned_type>(Src2);
+        break;
+      case FEXCore::IR::COND_NEQ:
+        CompResult = static_cast<unsigned_type>(Src1) != static_cast<unsigned_type>(Src2);
+        break;
+      case FEXCore::IR::COND_SGE:
+        CompResult = static_cast<signed_type>(Src1) >= static_cast<signed_type>(Src2);
+        break;
+      case FEXCore::IR::COND_SLT:
+        CompResult = static_cast<signed_type>(Src1) < static_cast<signed_type>(Src2);
+        break;
+      case FEXCore::IR::COND_SGT:
+        CompResult = static_cast<signed_type>(Src1) > static_cast<signed_type>(Src2);
+        break;
+      case FEXCore::IR::COND_SLE:
+        CompResult = static_cast<signed_type>(Src1) <= static_cast<signed_type>(Src2);
+        break;
+      case FEXCore::IR::COND_UGE:
+        CompResult = static_cast<unsigned_type>(Src1) >= static_cast<unsigned_type>(Src2);
+        break;
+      case FEXCore::IR::COND_ULT:
+        CompResult = static_cast<unsigned_type>(Src1) < static_cast<unsigned_type>(Src2);
+        break;
+      case FEXCore::IR::COND_UGT:
+        CompResult = static_cast<unsigned_type>(Src1) > static_cast<unsigned_type>(Src2);
+        break;
+      case FEXCore::IR::COND_ULE:
+        CompResult = static_cast<unsigned_type>(Src1) <= static_cast<unsigned_type>(Src2);
+        break;
+
+      case FEXCore::IR::COND_FLU:
+        CompResult = reinterpret_cast<float_type&>(Src1) < reinterpret_cast<float_type&>(Src2) || (std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
+        break;
+      case FEXCore::IR::COND_FGE:
+        CompResult = reinterpret_cast<float_type&>(Src1) >= reinterpret_cast<float_type&>(Src2) && !(std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
+        break;
+      case FEXCore::IR::COND_FLEU:
+        CompResult = reinterpret_cast<float_type&>(Src1) <= reinterpret_cast<float_type&>(Src2) || (std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
+        break;
+      case FEXCore::IR::COND_FGT:
+        CompResult = reinterpret_cast<float_type&>(Src1) > reinterpret_cast<float_type&>(Src2) && !(std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
+        break;
+      case FEXCore::IR::COND_FU:
+        CompResult = (std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
+        break;
+      case FEXCore::IR::COND_FNU:
+        CompResult = !(std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
+        break;
+      case FEXCore::IR::COND_MI:
+      case FEXCore::IR::COND_PL:
+      case FEXCore::IR::COND_VS:
+      case FEXCore::IR::COND_VC:
+      default:
+        LOGMAN_MSG_A_FMT("Unsupported compare type");
+        break;
+    }
+
+    return CompResult;
+  }
+
+  static uint8_t GetOpSize(FEXCore::IR::IRListView *CurrentIR, IR::OrderedNodeWrapper Node) {
+    auto IROp = CurrentIR->GetOp<FEXCore::IR::IROp_Header>(Node);
+    return IROp->Size;
+  }
+
   };
-};
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/MemoryOps.cpp

@@ -0,0 +1,285 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+
+#include <cstdint>
+
+namespace FEXCore::CPU {
+static inline void CacheLineFlush(char *Addr) {
+#ifdef _M_X86_64
+  __asm volatile (
+    "clflush (%[Addr]);"
+    :: [Addr] "r" (Addr)
+    : "memory");
+#else
+  __builtin___clear_cache(Addr, Addr+64);
+#endif
+}
+
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+DEF_OP(LoadContext) {
+  auto Op = IROp->C<IR::IROp_LoadContext>();
+  uint8_t OpSize = IROp->Size;
+
+  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
+  ContextPtr += Op->Offset;
+  #define LOAD_CTX(x, y) \
+    case x: { \
+      y const *MemData = reinterpret_cast<y const*>(ContextPtr); \
+      GD = *MemData; \
+      break; \
+    }
+  switch (OpSize) {
+    LOAD_CTX(1, uint8_t)
+    LOAD_CTX(2, uint16_t)
+    LOAD_CTX(4, uint32_t)
+    LOAD_CTX(8, uint64_t)
+    case 16: {
+      void const *MemData = reinterpret_cast<void const*>(ContextPtr);
+      memcpy(GDP, MemData, OpSize);
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
+  }
+  #undef LOAD_CTX
+}
+
+DEF_OP(StoreContext) {
+  auto Op = IROp->C<IR::IROp_StoreContext>();
+  uint8_t OpSize = IROp->Size;
+
+  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
+  ContextPtr += Op->Offset;
+
+  void *MemData = reinterpret_cast<void*>(ContextPtr);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  memcpy(MemData, Src, OpSize);
+}
+
+DEF_OP(LoadRegister) {
+  LOGMAN_MSG_A_FMT("Unimplemented");
+}
+
+DEF_OP(StoreRegister) {
+  LOGMAN_MSG_A_FMT("Unimplemented");
+}
+
+DEF_OP(LoadContextIndexed) {
+  auto Op = IROp->C<IR::IROp_LoadContextIndexed>();
+  uint64_t Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+
+  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
+
+  ContextPtr += Op->BaseOffset;
+  ContextPtr += Index * Op->Stride;
+
+  #define LOAD_CTX(x, y) \
+    case x: { \
+      y const *MemData = reinterpret_cast<y const*>(ContextPtr); \
+      GD = *MemData; \
+      break; \
+    }
+  switch (IROp->Size) {
+    LOAD_CTX(1, uint8_t)
+    LOAD_CTX(2, uint16_t)
+    LOAD_CTX(4, uint32_t)
+    LOAD_CTX(8, uint64_t)
+    case 16: {
+      void const *MemData = reinterpret_cast<void const*>(ContextPtr);
+      memcpy(GDP, MemData, IROp->Size);
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", IROp->Size);
+  }
+  #undef LOAD_CTX
+}
+
+DEF_OP(StoreContextIndexed) {
+  auto Op = IROp->C<IR::IROp_StoreContextIndexed>();
+  uint64_t Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+
+  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
+  ContextPtr += Op->BaseOffset;
+  ContextPtr += Index * Op->Stride;
+
+  void *MemData = reinterpret_cast<void*>(ContextPtr);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  memcpy(MemData, Src, IROp->Size);
+}
+
+DEF_OP(SpillRegister) {
+  LOGMAN_MSG_A_FMT("Unimplemented");
+}
+
+DEF_OP(FillRegister) {
+  LOGMAN_MSG_A_FMT("Unimplemented");
+}
+
+DEF_OP(LoadFlag) {
+  auto Op = IROp->C<IR::IROp_LoadFlag>();
+
+  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
+  ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
+  ContextPtr += Op->Flag;
+  uint8_t const *MemData = reinterpret_cast<uint8_t const*>(ContextPtr);
+  GD = *MemData;
+}
+
+DEF_OP(StoreFlag) {
+  auto Op = IROp->C<IR::IROp_StoreFlag>();
+  uint8_t Arg = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+
+  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
+  ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
+  ContextPtr += Op->Flag;
+  uint8_t *MemData = reinterpret_cast<uint8_t*>(ContextPtr);
+  *MemData = Arg;
+}
+
+DEF_OP(LoadMem) {
+  auto Op = IROp->C<IR::IROp_LoadMem>();
+  uint8_t OpSize = IROp->Size;
+
+  uint8_t const *MemData = *GetSrc<uint8_t const**>(Data->SSAData, Op->Addr);
+
+  if (!Op->Offset.IsInvalid()) {
+    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
+
+    switch(Op->OffsetType.Val) {
+      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
+      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
+      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
+    }
+  }
+  memset(GDP, 0, 16);
+  switch (OpSize) {
+    case 1: {
+      auto D = reinterpret_cast<const std::atomic<uint8_t>*>(MemData);
+      GD = D->load();
+      break;
+    }
+    case 2: {
+      auto D = reinterpret_cast<const std::atomic<uint16_t>*>(MemData);
+      GD = D->load();
+      break;
+    }
+    case 4: {
+      auto D = reinterpret_cast<const std::atomic<uint32_t>*>(MemData);
+      GD = D->load();
+      break;
+    }
+    case 8: {
+      auto D = reinterpret_cast<const std::atomic<uint64_t>*>(MemData);
+      GD = D->load();
+      break;
+    }
+
+    default:
+      memcpy(GDP, MemData, IROp->Size);
+      break;
+  }
+}
+
+DEF_OP(StoreMem) {
+  auto Op = IROp->C<IR::IROp_StoreMem>();
+  uint8_t OpSize = IROp->Size;
+
+  uint8_t *MemData = *GetSrc<uint8_t **>(Data->SSAData, Op->Addr);
+
+  if (!Op->Offset.IsInvalid()) {
+    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
+
+    switch(Op->OffsetType.Val) {
+      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
+      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
+      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
+    }
+  }
+  switch (OpSize) {
+    case 1: {
+      reinterpret_cast<std::atomic<uint8_t>*>(MemData)->store(*GetSrc<uint8_t*>(Data->SSAData, Op->Value));
+      break;
+    }
+    case 2: {
+      reinterpret_cast<std::atomic<uint16_t>*>(MemData)->store(*GetSrc<uint16_t*>(Data->SSAData, Op->Value));
+      break;
+    }
+    case 4: {
+      reinterpret_cast<std::atomic<uint32_t>*>(MemData)->store(*GetSrc<uint32_t*>(Data->SSAData, Op->Value));
+      break;
+    }
+    case 8: {
+      reinterpret_cast<std::atomic<uint64_t>*>(MemData)->store(*GetSrc<uint64_t*>(Data->SSAData, Op->Value));
+      break;
+    }
+
+    default:
+      memcpy(MemData, GetSrc<void*>(Data->SSAData, Op->Value), IROp->Size);
+      break;
+  }
+}
+
+DEF_OP(VLoadMemElement) {
+  auto Op = IROp->C<IR::IROp_VLoadMemElement>();
+  void const *MemData = *GetSrc<void const**>(Data->SSAData, Op->Header.Args[0]);
+
+  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Header.Args[1]), 16);
+  memcpy(reinterpret_cast<void*>(reinterpret_cast<uintptr_t>(GDP) + (Op->Header.ElementSize * Op->Index)),
+    MemData, Op->Header.ElementSize);
+}
+
+DEF_OP(VStoreMemElement) {
+  #define STORE_DATA(x, y) \
+    case x: { \
+      y *MemData = *GetSrc<y**>(Data->SSAData, Op->Header.Args[0]); \
+      memcpy(MemData, &GetSrc<y*>(Data->SSAData, Op->Header.Args[1])[Op->Index], sizeof(y)); \
+      break; \
+    }
+
+  auto Op = IROp->C<IR::IROp_VStoreMemElement>();
+  uint8_t OpSize = IROp->Size;
+
+  switch (OpSize) {
+    STORE_DATA(1, uint8_t)
+    STORE_DATA(2, uint16_t)
+    STORE_DATA(4, uint32_t)
+    STORE_DATA(8, uint64_t)
+    default: LOGMAN_MSG_A_FMT("Unhandled StoreMem size"); break;
+  }
+  #undef STORE_DATA
+}
+
+DEF_OP(CacheLineClear) {
+  auto Op = IROp->C<IR::IROp_CacheLineClear>();
+
+  char *MemData = *GetSrc<char **>(Data->SSAData, Op->Addr);
+
+  // 64-byte cache line clear
+  CacheLineFlush(MemData);
+}
+
+DEF_OP(CacheLineZero) {
+  auto Op = IROp->C<IR::IROp_CacheLineZero>();
+
+  uintptr_t MemData = *GetSrc<uintptr_t*>(Data->SSAData, Op->Addr);
+
+  // Force cacheline alignment
+  MemData = MemData & ~(CPUIDEmu::CACHELINE_SIZE - 1);
+
+  using DataType = uint64_t;
+  DataType *MemData64 = reinterpret_cast<DataType*>(MemData);
+
+  // 64-byte cache line zero
+  for (size_t i = 0; i < (CPUIDEmu::CACHELINE_SIZE / sizeof(DataType)); ++i) {
+    MemData64[i] = 0;
+  }
+}
+
+#undef DEF_OP
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/MiscOps.cpp

@@ -0,0 +1,153 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+
+#include <FEXHeaderUtils/Syscalls.h>
+
+#include <cstdint>
+#ifdef _M_X86_64
+#include <xmmintrin.h>
+#endif
+
+namespace FEXCore::CPU {
+[[noreturn]]
+static void StopThread(FEXCore::Core::InternalThreadState *Thread) {
+  Thread->CTX->StopThread(Thread);
+
+  LOGMAN_MSG_A_FMT("unreachable");
+  FEX_UNREACHABLE;
+}
+
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+DEF_OP(Fence) {
+  auto Op = IROp->C<IR::IROp_Fence>();
+  switch (Op->Fence) {
+    case IR::Fence_Load.Val:
+      std::atomic_thread_fence(std::memory_order_acquire);
+      break;
+    case IR::Fence_LoadStore.Val:
+      std::atomic_thread_fence(std::memory_order_seq_cst);
+      break;
+    case IR::Fence_Store.Val:
+      std::atomic_thread_fence(std::memory_order_release);
+      break;
+    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
+  }
+}
+
+DEF_OP(Break) {
+  auto Op = IROp->C<IR::IROp_Break>();
+  switch (Op->Reason) {
+    case FEXCore::IR::Break_Halt: // HLT
+      StopThread(Data->State);
+    break;
+    case FEXCore::IR::Break_InvalidInstruction:
+      FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGILL);
+    break;
+  default: LOGMAN_MSG_A_FMT("Unknown Break Reason: {}", Op->Reason); break;
+  }
+}
+
+DEF_OP(GetRoundingMode) {
+  uint32_t GuestRounding{};
+#ifdef _M_ARM_64
+  uint64_t Tmp{};
+  __asm(R"(
+    mrs %[Tmp], FPCR;
+  )"
+  : [Tmp] "=r" (Tmp));
+  // Extract the rounding
+  // On ARM the ordering is different than on x86
+  GuestRounding |= ((Tmp >> 24) & 1) ? IR::ROUND_MODE_FLUSH_TO_ZERO : 0;
+  uint8_t RoundingMode = (Tmp >> 22) & 0b11;
+  if (RoundingMode == 0)
+    GuestRounding |= IR::ROUND_MODE_NEAREST;
+  else if (RoundingMode == 1)
+    GuestRounding |= IR::ROUND_MODE_POSITIVE_INFINITY;
+  else if (RoundingMode == 2)
+    GuestRounding |= IR::ROUND_MODE_NEGATIVE_INFINITY;
+  else if (RoundingMode == 3)
+    GuestRounding |= IR::ROUND_MODE_TOWARDS_ZERO;
+#else
+  GuestRounding = _mm_getcsr();
+
+  // Extract the rounding
+  GuestRounding = (GuestRounding >> 13) & 0b111;
+#endif
+  memcpy(GDP, &GuestRounding, sizeof(GuestRounding));
+}
+
+DEF_OP(SetRoundingMode) {
+  auto Op = IROp->C<IR::IROp_SetRoundingMode>();
+  uint8_t GuestRounding = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+#ifdef _M_ARM_64
+  uint64_t HostRounding{};
+  __asm volatile(R"(
+    mrs %[Tmp], FPCR;
+  )"
+  : [Tmp] "=r" (HostRounding));
+  // Mask out the rounding
+  HostRounding &= ~(0b111 << 22);
+
+  HostRounding |= (GuestRounding & IR::ROUND_MODE_FLUSH_TO_ZERO) ? (1U << 24) : 0;
+
+  uint8_t RoundingMode = GuestRounding & 0b11;
+  if (RoundingMode == IR::ROUND_MODE_NEAREST)
+    HostRounding |= (0b00U << 22);
+  else if (RoundingMode == IR::ROUND_MODE_POSITIVE_INFINITY)
+    HostRounding |= (0b01U << 22);
+  else if (RoundingMode == IR::ROUND_MODE_NEGATIVE_INFINITY)
+    HostRounding |= (0b10U << 22);
+  else if (RoundingMode == IR::ROUND_MODE_TOWARDS_ZERO)
+    HostRounding |= (0b11U << 22);
+
+  __asm volatile(R"(
+    msr FPCR, %[Tmp];
+  )"
+  :: [Tmp] "r" (HostRounding));
+#else
+  uint32_t HostRounding = _mm_getcsr();
+
+  // Cut out the host rounding mode
+  HostRounding &= ~(0b111 << 13);
+
+  // Insert our new rounding mode
+  HostRounding |= GuestRounding << 13;
+  _mm_setcsr(HostRounding);
+#endif
+}
+
+DEF_OP(Print) {
+  auto Op = IROp->C<IR::IROp_Print>();
+  uint8_t OpSize = IROp->Size;
+
+  if (OpSize <= 8) {
+    uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+    LogMan::Msg::IFmt(">>>> Value in Arg: 0x{:x}, {}", Src, Src);
+  }
+  else if (OpSize == 16) {
+    __uint128_t Src = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+    uint64_t Src0 = Src;
+    uint64_t Src1 = Src >> 64;
+    LogMan::Msg::IFmt(">>>> Value[0] in Arg: 0x{:x}, {}", Src0, Src0);
+    LogMan::Msg::IFmt("     Value[1] in Arg: 0x{:x}, {}", Src1, Src1);
+  }
+  else
+    LOGMAN_MSG_A_FMT("Unknown value size: {}", OpSize);
+}
+
+DEF_OP(ProcessorID) {
+  uint32_t CPU, CPUNode;
+  FHU::Syscalls::getcpu(&CPU, &CPUNode);
+  GD = (CPUNode << 12) | CPU;
+}
+
+#undef DEF_OP
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/MoveOps.cpp

@@ -0,0 +1,42 @@
+/*
+$info$
+tags: backend|interpreter
+$end_info$
+*/
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/InterpreterDefines.h"
+
+#include <cstdint>
+
+namespace FEXCore::CPU {
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
+DEF_OP(ExtractElementPair) {
+  auto Op = IROp->C<IR::IROp_ExtractElementPair>();
+  uintptr_t Src = GetSrc<uintptr_t>(Data->SSAData, Op->Header.Args[0]);
+  memcpy(GDP,
+    reinterpret_cast<void*>(Src + Op->Header.Size * Op->Element), Op->Header.Size);
+}
+
+DEF_OP(CreateElementPair) {
+  auto Op = IROp->C<IR::IROp_CreateElementPair>();
+  void *Src_Lower = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src_Upper = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
+
+  uint8_t *Dst = GetDest<uint8_t*>(Data->SSAData, Node);
+
+  memcpy(Dst, Src_Lower, Op->Header.Size);
+  memcpy(Dst + Op->Header.Size, Src_Upper, Op->Header.Size);
+}
+
+DEF_OP(Mov) {
+  auto Op = IROp->C<IR::IROp_Mov>();
+  uint8_t OpSize = IROp->Size;
+
+  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Header.Args[0]), OpSize);
+}
+
+#undef DEF_OP
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/x86_64Dispatcher.cpp

@@ -1,470 +0,0 @@
-#include "Common/MathUtils.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Context/Context.h"
-#include <FEXCore/Core/X86Enums.h>
-
-#include <cmath>
-#include <xbyak/xbyak.h>
-
-namespace FEXCore::CPU {
-static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
-#define STATE r14
-
-class DispatchGenerator : public Xbyak::CodeGenerator {
-  public:
-    DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-    bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-    bool HandleSignalPause(int Signal, void *info, void *ucontext);
-
-  CPUBackend::AsmDispatch DispatchPtr;
-  CPUBackend::JITCallback CallbackPtr;
-  FEXCore::Context::Context::IntCallbackReturn ReturnPtr;
-
-  uint64_t ThreadStopHandlerAddress;
-  uint64_t AbsoluteLoopTopAddress;
-  uint64_t ThreadPauseHandlerAddress;
-  FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
-  private:
-    void StoreThreadState(int Signal, void *ucontext);
-    void RestoreThreadState(void *ucontext);
-    std::stack<uint64_t> SignalFrames;
-};
-
-static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->State.RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-}
-
-DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
-  : Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE)
-  , CTX {ctx}
-  , State {Thread} {
-  using namespace Xbyak;
-  using namespace Xbyak::util;
-  DispatchPtr = getCurr<CPUBackend::AsmDispatch>();
-
-  // while (!Thread->State.RunningEvents.ShouldStop.load()) {
-  //    Ptr = FindBlock(RIP)
-  //    if (!Ptr)
-  //      Ptr = CTX->CompileBlock(RIP);
-  //
-  //    if (Ptr)
-  //      Ptr();
-  //    else
-  //    {
-  //      Ptr = FallbackCore->CompileBlock()
-  //      if (Ptr)
-  //        Ptr()
-  //      else {
-  //        ShouldStop = true;
-  //      }
-  //    }
-  // }
-  // Bunch of exit state stuff
-
-  // x86-64 ABI has the stack aligned when /call/ happens
-  // Which means the destination has a misaligned stack at that point
-  push(rbx);
-  push(rbp);
-  push(r12);
-  push(r13);
-  push(r14);
-  push(r15);
-  sub(rsp, 8);
-
-  mov(STATE, rdi);
-
-  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
-  // regardless of where we were in the stack
-  mov(qword [rdi + offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)], rsp);
-
-  Label LoopTop;
-  Label NoBlock;
-  Label ExitBlock;
-  Label ThreadPauseHandler;
-
-  L(LoopTop);
-  AbsoluteLoopTopAddress = getCurr<uint64_t>();
-
-  {
-    mov(r13, Thread->LookupCache->GetPagePointer());
-
-    // Load our RIP
-    mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);
-
-    mov(rax, rdx);
-    mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
-    and_(rax, rbx);
-    shr(rax, 12);
-
-    // Load page pointer
-    mov(rdi, qword [r13 + rax * 8]);
-
-    cmp(rdi, 0);
-    je(NoBlock);
-
-    mov (rax, rdx);
-    and_(rax, 0x0FFF);
-
-    shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
-
-    // check for aliasing
-    mov(rcx, qword [rdi + rax + 8]);
-    cmp(rcx, rdx);
-    jne(NoBlock);
-    
-    // Load the block pointer
-    mov(rax, qword [rdi + rax]);
-
-    cmp(rax, 0);
-    je(NoBlock);
-
-    // Real block if we made it here
-    mov(rdi, STATE);
-    call(rax);
-
-    if (CTX->GetGdbServerStatus()) {
-      // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
-      // This happens when single stepping
-      static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
-      mov(rax, qword [STATE + (offsetof(FEXCore::Core::InternalThreadState, CTX))]);
-
-      // If the value == 0 then branch to the top
-      cmp(dword [rax + (offsetof(FEXCore::Context::Context, Config.RunningMode))], 0);
-      je(LoopTop);
-      // Else we need to pause now
-      jmp(ThreadPauseHandler);
-      ud2();
-    }
-    else {
-      jmp(LoopTop);
-    }
-  }
-
-  {
-    L(ExitBlock);
-    ThreadStopHandlerAddress = getCurr<uint64_t>();
-
-    add(rsp, 8);
-
-    pop(r15);
-    pop(r14);
-    pop(r13);
-    pop(r12);
-    pop(rbp);
-    pop(rbx);
-
-    ret();
-  }
-
-  // Block creation
-  {
-    L(NoBlock);
-
-    using ClassPtrType = uintptr_t (FEXCore::Context::Context::*)(FEXCore::Core::InternalThreadState *, uint64_t);
-    union PtrCast {
-      ClassPtrType ClassPtr;
-      uintptr_t Data;
-    };
-
-    PtrCast Ptr;
-    Ptr.ClassPtr = &FEXCore::Context::Context::CompileBlock;
-
-    // {rdi, rsi, rdx}
-    mov(rdi, reinterpret_cast<uint64_t>(CTX));
-    mov(rsi, STATE);
-    mov(rax, Ptr.Data);
-
-    call(rax);
-
-    // rdx already contains RIP here
-    jmp(LoopTop);
-  }
-
-  {
-    // Pause handler
-    ThreadPauseHandlerAddress = getCurr<uint64_t>();
-    L(ThreadPauseHandler);
-
-    mov(rdi, reinterpret_cast<uintptr_t>(CTX));
-    mov(rsi, STATE);
-    mov(rax, reinterpret_cast<uint64_t>(SleepThread));
-
-    call(rax);
-
-    // XXX: Unsupported atm
-    // uint64_t PauseReturnInstruction = getCurr<uint64_t>();
-    // ud2();
-  }
-
-  {
-    CallbackPtr = getCurr<CPUBackend::JITCallback>();
-
-    push(rbx);
-    push(rbp);
-    push(r12);
-    push(r13);
-    push(r14);
-    push(r15);
-    sub(rsp, 8);
-
-    // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, rdi);
-    // XXX: XMM?
-
-    // Now push the callback return trampoline to the guest stack
-    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    mov(rax, CTX->X86CodeGen.CallbackReturn);
-
-    // Store the trampoline to the guest stack
-    // Guest stack is now correctly misaligned after a regular call instruction
-    sub(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])], 16);
-    mov(rbx, qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])]);
-    mov(qword [rbx], rax);
-
-    // Store RIP to the context state
-    mov(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.rip)], rsi);
-
-    // Back to the loop top now
-    jmp(LoopTop);
-  }
-
-
-  {
-    ReturnPtr = getCurr<FEXCore::Context::Context::IntCallbackReturn>();
-//  using CallbackReturn =  __attribute__((naked)) void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
-
-    // rdi = thread
-    // rsi = rsp
-
-    mov(rsp, rsi);
-
-    // Now jump back to the thunk
-    // XXX: XMM?
-    add(rsp, 8);
-
-    pop(r15);
-    pop(r14);
-    pop(r13);
-    pop(r12);
-    pop(rbp);
-    pop(rbx);
-
-    ret();
-  }
-  ready();
-}
-
-struct ContextBackup {
-  uint64_t StoredCookie;
-  // Host State
-  // RIP and RSP is stored in GPRs here
-  uint64_t GPRs[NGREG];
-  _libc_fpstate FPRState;
-
-  // Guest state
-  int Signal;
-  FEXCore::Core::CPUState GuestState;
-};
-
-void DispatchGenerator::StoreThreadState(int Signal, void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  // We can end up getting a signal at any point in our host state
-  // Jump to a handler that saves all state so we can safely return
-  uint64_t OldSP = _mcontext->gregs[REG_RSP];
-  uintptr_t NewSP = OldSP;
-
-  size_t StackOffset = sizeof(ContextBackup);
-
-  // We need to back up behind the host's red zone
-  // We do this on the guest side as well
-  NewSP -= 128;
-  NewSP -= StackOffset;
-  NewSP = AlignDown(NewSP, 16);
-
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  Context->StoredCookie = 0x4142434445464748ULL;
-
-  // Copy the GPRs
-  memcpy(&Context->GPRs[0], &_mcontext->gregs[0], NGREG * sizeof(_mcontext->gregs[0]));
-  // Copy the FPRState
-  memcpy(&Context->FPRState, _mcontext->fpregs, sizeof(_libc_fpstate));
-
-  // XXX: Save 256bit and 512bit AVX register state
-
-  // Retain the action pointer so we can see it when we return
-  Context->Signal = Signal;
-
-  // Save guest state
-  // We can't guarantee if registers are in context or host GPRs
-  // So we need to save everything
-  memcpy(&Context->GuestState, &State->State, sizeof(FEXCore::Core::CPUState));
-
-  // Set the new SP
-  _mcontext->gregs[REG_RSP] = NewSP;
-
-  SignalFrames.push(NewSP);
-}
-
-void DispatchGenerator::RestoreThreadState(void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  uint64_t OldSP = SignalFrames.top();
-  SignalFrames.pop();
-  uintptr_t NewSP = OldSP;
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  if (Context->StoredCookie != 0x4142434445464748ULL) {
-    LogMan::Msg::D("COOKIE WAS NOT CORRECT!\n");
-    exit(-1);
-  }
-
-  // First thing, reset the guest state
-  memcpy(&State->State, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
-
-  // Now restore host state
-
-  // Copy the GPRs
-  memcpy(&_mcontext->gregs[0], &Context->GPRs[0], NGREG * sizeof(_mcontext->gregs[0]));
-  // Copy the FPRState
-  memcpy(_mcontext->fpregs, &Context->FPRState, sizeof(_libc_fpstate));
-
-  // Restore the previous signal state
-  // This allows recursive signals to properly handle signal masking as we are walking back up the list of signals
-  CTX->SignalDelegation->SetCurrentSignal(Context->Signal);
-}
-
-bool DispatchGenerator::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  StoreThreadState(Signal, ucontext);
-
-  // Set the new PC
-  _mcontext->gregs[REG_RIP] = AbsoluteLoopTopAddress;
-  // Set our state register to point to our guest thread data
-  _mcontext->gregs[REG_R14] = reinterpret_cast<uint64_t>(State);
-
-  uint64_t OldGuestSP = State->State.State.gregs[X86State::REG_RSP];
-  uint64_t NewGuestSP = OldGuestSP;
-
-  if (!(GuestStack->ss_flags & SS_DISABLE)) {
-    // If our guest is already inside of the alternative stack
-    // Then that means we are hitting recursive signals and we need to walk back the stack correctly
-    uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
-    uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
-    if (OldGuestSP >= AltStackBase &&
-        OldGuestSP <= AltStackEnd) {
-      // We are already in the alt stack, the rest of the code will handle adjusting this
-    }
-    else {
-      NewGuestSP = AltStackEnd;
-    }
-  }
-
-  // Back up past the redzone, which is 128bytes
-  // Don't need this offset if we aren't going to be putting siginfo in to it
-  NewGuestSP -= 128;
-
-  State->State.State.gregs[X86State::REG_RDI] = Signal;
-
-  if (GuestAction->sa_flags & SA_SIGINFO) {
-    // XXX: siginfo_t(RSI), ucontext (RDX)
-    State->State.State.gregs[X86State::REG_RSI] = 0;
-    State->State.State.gregs[X86State::REG_RDX] = 0;
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
-  }
-  else {
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
-  }
-
-  // Set up the new SP for stack handling
-  NewGuestSP -= 8;
-  *(uint64_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
-  State->State.State.gregs[X86State::REG_RSP] = NewGuestSP;
-
-  return true;
-}
-
-bool DispatchGenerator::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  FEXCore::Core::SignalEvent SignalReason = State->SignalReason.load();
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_PAUSE) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Store our thread state so we can come back to this
-    StoreThreadState(Signal, ucontext);
-
-    // Set the new PC
-    _mcontext->gregs[REG_RIP] = ThreadPauseHandlerAddress;
-
-    // Set our state register to point to our guest thread data
-    _mcontext->gregs[REG_R14] = reinterpret_cast<uint64_t>(State);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_STOP) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Our thread is stopping
-    // We don't care about anything at this point
-    // Set the stack to our starting location when we entered the core and get out safely
-    _mcontext->gregs[REG_RSP] = State->State.ReturningStackLocation;
-
-    // Set the new PC
-    _mcontext->gregs[REG_RIP] = ThreadStopHandlerAddress;
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_RETURN) {
-    RestoreThreadState(ucontext);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  return false;
-}
-
-void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  Generator = new DispatchGenerator(ctx, Thread);
-  DispatchPtr = Generator->DispatchPtr;
-  CallbackPtr = Generator->CallbackPtr;
-
-  // TODO: It feels wrong to initialize this way
-  ctx->InterpreterCallbackReturn = Generator->ReturnPtr;
-}
-
-bool InterpreterCore::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-}
-
-bool InterpreterCore::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleSignalPause(Signal, info, ucontext);
-}
-
-void InterpreterCore::DeleteAsmDispatch() {
-  delete Generator;
-}
-
-}

External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp

@@ -1,8 +1,17 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
 
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
+
+#define GRD(Node) (IROp->Size <= 4 ? GetDst<RA_32>(Node) : GetDst<RA_64>(Node))
+#define GRS(Node) (IROp->Size <= 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))
+
 static uint64_t LUDIV(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
   __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
   __uint128_t Res = Source / Divisor;
@@ -29,7 +38,7 @@ static int64_t LREM(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(TruncElementPair) {
   auto Op = IROp->C<IR::IROp_TruncElementPair>();
 
@@ -41,7 +50,7 @@ DEF_OP(TruncElementPair) {
       mov(Dst.second, Src.second);
       break;
     }
-    default: LogMan::Msg::A("Unhandled Truncation size: %d", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
   }
 }
 
@@ -54,9 +63,15 @@ DEF_OP(Constant) {
 DEF_OP(EntrypointOffset) {
   auto Op = IROp->C<IR::IROp_EntrypointOffset>();
 
-  auto Constant = IR->GetHeader()->Entry + Op->Offset;
+  auto Constant = Entry + Op->Offset;
   auto Dst = GetReg<RA_64>(Node);
-  LoadConstant(Dst, Constant);
+  uint64_t Mask = ~0ULL;
+  uint8_t OpSize = IROp->Size;
+  if (OpSize == 4) {
+    Mask = 0xFFFF'FFFFULL;
+  }
+
+  LoadConstant(Dst, Constant & Mask);
 }
 
 DEF_OP(InlineConstant) {
@@ -75,8 +90,6 @@ DEF_OP(CycleCounter) {
 #endif
 }
 
-#define GRS(Node) (IROp->Size <= 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))
-
 DEF_OP(Add) {
   auto Op = IROp->C<IR::IROp_Add>();
   uint8_t OpSize = IROp->Size;
@@ -90,7 +103,7 @@ DEF_OP(Add) {
       case 8:
         add(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), Const);
         break;
-      default: LogMan::Msg::A("Unsupported Add size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Add size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -100,7 +113,7 @@ DEF_OP(Add) {
       case 8:
         add(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
         break;
-      default: LogMan::Msg::A("Unsupported Add size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Add size: {}", OpSize);
     }
   }
 }
@@ -116,7 +129,7 @@ DEF_OP(Sub) {
       case 8:
         sub(GRS(Node), GRS(Op->Header.Args[0].ID()), Const);
         break;
-      default: LogMan::Msg::A("Unsupported Sub size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Sub size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -126,7 +139,7 @@ DEF_OP(Sub) {
       case 8:
         sub(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
         break;
-      default: LogMan::Msg::A("Unsupported Sub size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Sub size: {}", OpSize);
     }
   }
 
@@ -142,7 +155,7 @@ DEF_OP(Neg) {
     case 8:
       neg(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unsupported Not size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Neg size: {}", OpSize);
   }
 }
 
@@ -154,12 +167,11 @@ DEF_OP(Mul) {
   switch (OpSize) {
     case 4:
       mul(Dst.W(), GetReg<RA_32>(Op->Header.Args[0].ID()), GetReg<RA_32>(Op->Header.Args[1].ID()));
-      sxtw(Dst, Dst);
     break;
     case 8:
       mul(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Mul size: {}", OpSize);
   }
 }
 
@@ -175,7 +187,7 @@ DEF_OP(UMul) {
     case 8:
       mul(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown UMul size: {}", OpSize);
   }
 }
 
@@ -212,7 +224,7 @@ DEF_OP(Div) {
       sdiv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
     }
-    default: LogMan::Msg::A("Unknown DIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown DIV Size: {}", Size); break;
   }
 }
 
@@ -239,7 +251,7 @@ DEF_OP(UDiv) {
       udiv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown UDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown UDIV Size: {}", Size); break;
   }
 }
 
@@ -286,7 +298,7 @@ DEF_OP(Rem) {
       msub(GetReg<RA_64>(Node), TMP1, Divisor, Dividend);
     break;
     }
-    default: LogMan::Msg::A("Unknown REM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REM Size: {}", OpSize); break;
   }
 }
 
@@ -328,7 +340,7 @@ DEF_OP(URem) {
       msub(GetReg<RA_64>(Node), TMP1, Divisor, Dividend);
     break;
     }
-    default: LogMan::Msg::A("Unknown UREM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown UREM Size: {}", OpSize); break;
   }
 }
 
@@ -340,12 +352,12 @@ DEF_OP(MulH) {
       sxtw(TMP1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       sxtw(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
       mul(TMP1, TMP1, TMP2);
-      sbfx(GetReg<RA_64>(Node), TMP1, 32, 32);
+      ubfx(GetReg<RA_64>(Node), TMP1, 32, 32);
     break;
     case 8:
       smulh(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Sext size: {}", OpSize);
   }
 }
 
@@ -362,7 +374,7 @@ DEF_OP(UMulH) {
     case 8:
       umulh(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Sext size: {}", OpSize);
   }
 }
 
@@ -386,6 +398,19 @@ DEF_OP(And) {
   }
 }
 
+DEF_OP(Andn) {
+  auto Op = IROp->C<IR::IROp_Andn>();
+  const auto& Lhs = Op->Header.Args[0];
+  const auto& Rhs = Op->Header.Args[1];
+  uint64_t Const{};
+
+  if (IsInlineConstant(Rhs, &Const)) {
+    bic(GRS(Node), GRS(Lhs.ID()), Const);
+  } else {
+    bic(GRS(Node), GRS(Lhs.ID()), GRS(Rhs.ID()));
+  }
+}
+
 DEF_OP(Xor) {
   auto Op = IROp->C<IR::IROp_Xor>();
   uint64_t Const;
@@ -398,7 +423,6 @@ DEF_OP(Xor) {
 
 DEF_OP(Lshl) {
   auto Op = IROp->C<IR::IROp_Lshl>();
-  uint8_t OpSize = IROp->Size;
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
     lsl(GRS(Node), GRS(Op->Header.Args[0].ID()), (unsigned int)Const);
@@ -409,7 +433,6 @@ DEF_OP(Lshl) {
 
 DEF_OP(Lshr) {
   auto Op = IROp->C<IR::IROp_Lshr>();
-  uint8_t OpSize = IROp->Size;
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
     lsr(GRS(Node), GRS(Op->Header.Args[0].ID()), (unsigned int)Const);
@@ -460,7 +483,7 @@ DEF_OP(Ror) {
       break;
       }
 
-      default: LogMan::Msg::A("Unhandled ROR size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unhandled ROR size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -473,7 +496,7 @@ DEF_OP(Ror) {
       break;
       }
 
-      default: LogMan::Msg::A("Unhandled ROR size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unhandled ROR size: {}", OpSize);
     }
   }
 }
@@ -492,10 +515,129 @@ DEF_OP(Extr) {
     break;
     }
 
-    default: LogMan::Msg::A("Unhandled EXTR size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unhandled EXTR size: {}", OpSize);
   }
 }
 
+DEF_OP(PDep) {
+  auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  const Register Input = GRS(Op->Args(0).ID());
+  const Register Mask = GRS(Op->Args(1).ID());
+  const Register Dest = GRS(Node);
+
+  const Register ShiftedBitReg = OpSize <= 4 ? TMP1.W() : TMP1;
+  const Register BitReg        = OpSize <= 4 ? TMP2.W() : TMP2;
+  const Register SubMaskReg    = OpSize <= 4 ? TMP3.W() : TMP3;
+  const Register IndexReg      = OpSize <= 4 ? TMP4.W() : TMP4;
+  const Register SizedZero     = OpSize <= 4 ? Register{wzr} : Register{xzr};
+
+  const Register InputReg = OpSize <= 4 ? SRA64[0].W() : SRA64[0];
+  const Register MaskReg  = OpSize <= 4 ? SRA64[1].W() : SRA64[1];
+  const Register DestReg  = OpSize <= 4 ? SRA64[2].W() : SRA64[2];
+  const auto SpillCode    = 1U << InputReg.GetCode() |
+                            1U << MaskReg.GetCode() |
+                            1U << DestReg.GetCode();
+
+  aarch64::Label EarlyExit;
+  aarch64::Label NextBit;
+  aarch64::Label Done;
+
+  cbz(Mask, &EarlyExit);
+  mov(IndexReg, SizedZero);
+
+  // We sadly need to spill regs for this for the time being
+  // TODO: Remove when scratch registers can be allocated
+  //       explicitly.
+  SpillStaticRegs(false, SpillCode);
+  mov(InputReg, Input);
+  mov(MaskReg, Mask);
+  mov(DestReg, SizedZero);
+
+  // Main loop
+  bind(&NextBit);
+  rbit(ShiftedBitReg, MaskReg);
+  clz(ShiftedBitReg, ShiftedBitReg);
+  lsrv(BitReg, InputReg, IndexReg);
+  and_(BitReg, BitReg, 1);
+  sub(SubMaskReg, MaskReg, 1);
+  add(IndexReg, IndexReg, 1);
+  ands(MaskReg, MaskReg, SubMaskReg);
+  lslv(ShiftedBitReg, BitReg, ShiftedBitReg);
+  orr(DestReg, DestReg, ShiftedBitReg);
+  b(&NextBit, Condition::ne);
+  // Store result in a temp so it doesn't get clobbered.
+  // and restore it after the re-fill below.
+  mov(IndexReg, DestReg);
+  // Restore our registers before leaving
+  // TODO: Also remove along with above TODO.
+  FillStaticRegs(false, SpillCode);
+  mov(Dest, IndexReg);
+  b(&Done);
+
+  // Early exit
+  bind(&EarlyExit);
+  mov(Dest, SizedZero);
+
+  // All done with nothing to do.
+  bind(&Done);
+}
+
+DEF_OP(PExt) {
+  auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  const Register Input = GRS(Op->Args(0).ID());
+  const Register Mask = GRS(Op->Args(1).ID());
+  const Register Dest = GRS(Node);
+
+  const Register MaskReg    = OpSize <= 4 ? TMP1.W() : TMP1;
+  const Register BitReg     = OpSize <= 4 ? TMP2.W() : TMP2;
+  const Register SubMaskReg = OpSize <= 4 ? TMP3.W() : TMP3;
+  const Register Offset     = OpSize <= 4 ? TMP4.W() : TMP4;
+  const Register SizedZero  = OpSize <= 4 ? Register{wzr} : Register{xzr};
+
+  aarch64::Label EarlyExit;
+  aarch64::Label NextBit;
+  aarch64::Label Done;
+
+  cbz(Mask, &EarlyExit);
+  mov(MaskReg, Mask);
+  mov(Offset, SizedZero);
+
+  // We sadly need to spill a reg for this for the time being
+  // TODO: Remove when scratch registers can be allocated
+  //       explicitly.
+  SpillStaticRegs(false, 1U << Mask.GetCode());
+  mov(Mask, SizedZero);
+
+  // Main loop
+  bind(&NextBit);
+  rbit(BitReg, MaskReg);
+  clz(BitReg, BitReg);
+  sub(SubMaskReg, MaskReg, 1);
+  ands(MaskReg, SubMaskReg, MaskReg);
+  lsrv(BitReg, Input, BitReg);
+  and_(BitReg, BitReg, 1);
+  lslv(BitReg, BitReg, Offset);
+  add(Offset, Offset, 1);
+  orr(Mask, BitReg, Mask);
+  b(&NextBit, Condition::ne);
+  mov(Dest, Mask);
+  // Restore our mask register before leaving
+  // TODO: Also remove along with above TODO.
+  FillStaticRegs(false, 1U << Mask.GetCode());
+  b(&Done);
+
+  // Early exit
+  bind(&EarlyExit);
+  mov(Dest, SizedZero);
+
+  // All done with nothing to do.
+  bind(&Done);
+}
+
 DEF_OP(LDiv) {
   auto Op = IROp->C<IR::IROp_LDiv>();
   uint8_t OpSize = IROp->Size;
@@ -524,14 +666,10 @@ DEF_OP(LDiv) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LDIV);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LDIV));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -541,7 +679,7 @@ DEF_OP(LDiv) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LDIV Size: {}", Size); break;
   }
 }
 
@@ -571,14 +709,10 @@ DEF_OP(LUDiv) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LUDIV);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LUDIV));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -588,7 +722,7 @@ DEF_OP(LUDiv) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUDIV Size: {}", Size); break;
   }
 }
 
@@ -628,14 +762,10 @@ DEF_OP(LRem) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LREM);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LREM));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -645,7 +775,7 @@ DEF_OP(LRem) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LREM Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LREM Size: {}", Size); break;
   }
 }
 
@@ -682,14 +812,11 @@ DEF_OP(LURem) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LUREM);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LUREM));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
+
       // Fix the stack and any values that were stepped on
       PopDynamicRegsAndLR();
 
@@ -698,7 +825,7 @@ DEF_OP(LURem) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LUREM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUREM Size: {}", OpSize); break;
   }
 }
 
@@ -712,7 +839,7 @@ DEF_OP(Not) {
     case 8:
       mvn(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unsupported Not size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Not size: {}", OpSize);
   }
 }
 
@@ -743,7 +870,7 @@ DEF_OP(Popcount) {
       // fmov has zero extended, unused bytes are zero
       addv(VTMP1.B(), VTMP1.V8B());
       break;
-    default: LogMan::Msg::A("Unsupported Popcount size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Popcount size: {}", OpSize);
   }
 
   auto Dst = GetReg<RA_32>(Node);
@@ -792,7 +919,7 @@ DEF_OP(FindMSB) {
       clz(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()));
       sub(Dst, TMP1, Dst);
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindMSB size: {}", OpSize); break;
   }
 }
 
@@ -813,7 +940,7 @@ DEF_OP(FindTrailingZeros) {
       rbit(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       clz(GetReg<RA_64>(Node), GetReg<RA_64>(Node));
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindTrailingZeros size: {}", OpSize); break;
   }
 }
 
@@ -832,7 +959,7 @@ DEF_OP(CountLeadingZeroes) {
     case 8:
       clz(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeroes size: {}", OpSize); break;
   }
 }
 
@@ -850,7 +977,7 @@ DEF_OP(Rev) {
     case 8:
       rev(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REV size: {}", OpSize); break;
   }
 }
 
@@ -872,15 +999,14 @@ DEF_OP(Bfi) {
       bfi(TMP1, GetReg<RA_64>(Op->Header.Args[1].ID()), Op->lsb, Op->Width);
       mov(GetReg<RA_64>(Node), TMP1);
       break;
-    default: LogMan::Msg::A("Unknown BFI size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown BFI size: {}", OpSize); break;
   }
 }
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
-  uint8_t OpSize = IROp->Size;
-  LogMan::Throw::A(OpSize <= 8, "OpSize is too large for BFE: %d", OpSize);
-  LogMan::Throw::A(Op->Width != 0, "Invalid BFE width of 0");
+  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
+  LOGMAN_THROW_A_FMT(Op->Width != 0, "Invalid BFE width of 0");
 
   auto Dst = GetReg<RA_64>(Node);
   ubfx(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), Op->lsb, Op->Width);
@@ -894,7 +1020,7 @@ DEF_OP(Sbfe) {
   if (OpSize == 8) {
     sbfx(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), Op->lsb, Op->Width);
   } else {
-    LogMan::Msg::D("Unimplemented Sbfe size");
+    LogMan::Msg::DFmt("Unimplemented Sbfe size");
   }
 }
 
@@ -917,15 +1043,15 @@ Condition MapSelectCC(IR::CondClassType Cond) {
   case FEXCore::IR::COND_FLU: return Condition::lt;
   case FEXCore::IR::COND_FGE: return Condition::ge;
   case FEXCore::IR::COND_FLEU:return Condition::le;
-  case FEXCore::IR::COND_FGT: return Condition::hi;
+  case FEXCore::IR::COND_FGT: return Condition::gt;
   case FEXCore::IR::COND_FU:  return Condition::vs;
   case FEXCore::IR::COND_FNU: return Condition::vc;
-  case FEXCore::IR::COND_VS:;
-  case FEXCore::IR::COND_VC:;
+  case FEXCore::IR::COND_VS:
+  case FEXCore::IR::COND_VC:
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
-  LogMan::Msg::A("Unsupported compare type");
+  LOGMAN_MSG_A_FMT("Unsupported compare type");
   return Condition::nv;
   }
 }
@@ -943,9 +1069,9 @@ DEF_OP(Select) {
   } else if (IsFPR(Op->Cmp1.ID())) {
     fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
   } else {
-    LogMan::Msg::A("Select: Expected GPR or FPR");
+    LOGMAN_MSG_A_FMT("Select: Expected GPR or FPR");
   }
-  
+
   auto cc = MapSelectCC(Op->Cond);
 
   uint64_t const_true, const_false;
@@ -954,7 +1080,7 @@ DEF_OP(Select) {
 
   if (is_const_true || is_const_false) {
     if (is_const_false != true || is_const_true != true || const_true != 1 || const_false != 0) {
-      LogMan::Msg::A("Select: Unsupported compare inline parameters");
+      LOGMAN_MSG_A_FMT("Select: Unsupported compare inline parameters");
     }
     cset(GRS(Node), cc);
   } else {
@@ -978,38 +1104,53 @@ DEF_OP(VExtractToGPR) {
     case 8:
       umov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Idx);
     break;
-    default:  LogMan::Msg::A("Unhandled ExtractElementSize: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled ExtractElementSize: {}", OpSize);
   }
 }
 
-DEF_OP(Float_ToGPR_ZU) {
-  LogMan::Msg::D("Unimplemented");
-}
-
 DEF_OP(Float_ToGPR_ZS) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_ZS>();
-  if (Op->Header.ElementSize == 8) {
-    fcvtzs(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).D());
+  aarch64::Register Dst{};
+  aarch64::VRegister Src{};
+  if (Op->SrcElementSize == 8) {
+    Src = GetSrc(Op->Header.Args[0].ID()).D();
   }
   else {
-    fcvtzs(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).S());
+    Src = GetSrc(Op->Header.Args[0].ID()).S();
   }
-}
 
-DEF_OP(Float_ToGPR_U) {
-  LogMan::Msg::D("Unimplemented");
+  if (IROp->Size == 8) {
+    Dst = GetReg<RA_64>(Node);
+  }
+  else {
+    Dst = GetReg<RA_32>(Node);
+  }
+
+  fcvtzs(Dst, Src);
 }
 
 DEF_OP(Float_ToGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_S>();
-  if (Op->Header.ElementSize == 8) {
+
+  aarch64::Register Dst{};
+  aarch64::VRegister Src{};
+  if (Op->SrcElementSize == 8) {
     frinti(VTMP1.D(), GetSrc(Op->Header.Args[0].ID()).D());
-    fcvtzs(GetReg<RA_64>(Node), VTMP1.D());
+    Src = VTMP1.D();
   }
   else {
     frinti(VTMP1.S(), GetSrc(Op->Header.Args[0].ID()).S());
-    fcvtzs(GetReg<RA_32>(Node), VTMP1.S());
+    Src = VTMP1.S();
   }
+
+  if (IROp->Size == 8) {
+    Dst = GetReg<RA_64>(Node);
+  }
+  else {
+    Dst = GetReg<RA_32>(Node);
+  }
+
+  fcvtzs(Dst, Src);
 }
 
 DEF_OP(FCmp) {
@@ -1022,11 +1163,11 @@ DEF_OP(FCmp) {
     fcmp(GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
   }
   auto Dst = GetReg<RA_64>(Node);
-  
+
   bool set = false;
 
   if (Op->Flags & (1 << IR::FCMP_FLAG_EQ)) {
-    LogMan::Throw::A(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
+    LOGMAN_THROW_A_FMT(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
     // EQ or unordered
     cset(Dst, Condition::eq); // Z = 1
     csinc(Dst, Dst, xzr, Condition::vc); // IF !V ? Z : 1
@@ -1057,8 +1198,8 @@ DEF_OP(FCmp) {
 
 #undef DEF_OP
 
-void JITCore::RegisterALUHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterALUHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(TRUNCELEMENTPAIR,  TruncElementPair);
   REGISTER_OP(CONSTANT,          Constant);
   REGISTER_OP(ENTRYPOINTOFFSET,  EntrypointOffset);
@@ -1078,12 +1219,15 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(UMULH,             UMulH);
   REGISTER_OP(OR,                Or);
   REGISTER_OP(AND,               And);
+  REGISTER_OP(ANDN,              Andn);
   REGISTER_OP(XOR,               Xor);
   REGISTER_OP(LSHL,              Lshl);
   REGISTER_OP(LSHR,              Lshr);
   REGISTER_OP(ASHR,              Ashr);
   REGISTER_OP(ROR,               Ror);
   REGISTER_OP(EXTR,              Extr);
+  REGISTER_OP(PDEP,              PDep);
+  REGISTER_OP(PEXT,              PExt);
   REGISTER_OP(LDIV,              LDiv);
   REGISTER_OP(LUDIV,             LUDiv);
   REGISTER_OP(LREM,              LRem);
@@ -1100,9 +1244,7 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(SBFE,              Sbfe);
   REGISTER_OP(SELECT,            Select);
   REGISTER_OP(VEXTRACTTOGPR,     VExtractToGPR);
-  REGISTER_OP(FLOAT_TOGPR_ZU,    Float_ToGPR_ZU);
   REGISTER_OP(FLOAT_TOGPR_ZS,    Float_ToGPR_ZS);
-  REGISTER_OP(FLOAT_TOGPR_U,     Float_ToGPR_U);
   REGISTER_OP(FLOAT_TOGPR_S,     Float_ToGPR_S);
   REGISTER_OP(FCMP,              FCmp);
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(CASPair) {
   auto Op = IROp->C<IR::IROp_CASPair>();
   uint8_t OpSize = IROp->Size;
@@ -13,7 +19,7 @@ DEF_OP(CASPair) {
   auto Desired = GetSrcPair<RA_64>(Op->Header.Args[1].ID());
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[2].ID());
 
-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
     mov(TMP3, Expected.first);
     mov(TMP4, Expected.second);
 
@@ -28,7 +34,7 @@ DEF_OP(CASPair) {
       mov(Dst.first, TMP3);
       mov(Dst.second, TMP4);
       break;
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
   }
   else {
@@ -38,6 +44,7 @@ DEF_OP(CASPair) {
         aarch64::Label LoopNotExpected;
         aarch64::Label LoopExpected;
         bind(&LoopTop);
+
         ldaxp(TMP2.W(), TMP3.W(), MemOperand(MemSrc));
         cmp(TMP2.W(), Expected.first.W());
         ccmp(TMP3.W(), Expected.second.W(), NoFlag, Condition::eq);
@@ -63,6 +70,7 @@ DEF_OP(CASPair) {
         aarch64::Label LoopNotExpected;
         aarch64::Label LoopExpected;
         bind(&LoopTop);
+
         ldaxp(TMP2.X(), TMP3.X(), MemOperand(MemSrc));
         cmp(TMP2.X(), Expected.first.X());
         ccmp(TMP3.X(), Expected.second.X(), NoFlag, Condition::eq);
@@ -83,7 +91,7 @@ DEF_OP(CASPair) {
         bind(&LoopExpected);
         break;
       }
-      default: LogMan::Msg::A("Unsupported: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
   }
 }
@@ -102,14 +110,14 @@ DEF_OP(CAS) {
   auto Desired = GetReg<RA_64>(Op->Header.Args[1].ID());
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[2].ID());
 
-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
     mov(TMP2, Expected);
     switch (OpSize) {
     case 1: casalb(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 2: casalh(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 4: casal(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 8: casal(TMP2.X(), Desired.X(), MemOperand(MemSrc)); break;
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
     mov(GetReg<RA_64>(Node), TMP2);
   }
@@ -200,7 +208,7 @@ DEF_OP(CAS) {
 
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", OpSize);
     }
   }
 }
@@ -210,18 +218,18 @@ DEF_OP(AtomicAdd) {
 
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
-    switch (Op->Size) {
+  if (CTX->HostFeatures.SupportsAtomics) {
+    switch (IROp->Size) {
     case 1: staddlb(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 2: staddlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: staddl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: staddl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -258,7 +266,7 @@ DEF_OP(AtomicAdd) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -268,19 +276,19 @@ DEF_OP(AtomicSub) {
 
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
     neg(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
-    switch (Op->Size) {
+    switch (IROp->Size) {
     case 1: staddlb(TMP2.W(), MemOperand(MemSrc)); break;
     case 2: staddlh(TMP2.W(), MemOperand(MemSrc)); break;
     case 4: staddl(TMP2.W(), MemOperand(MemSrc)); break;
     case 8: staddl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -317,7 +325,7 @@ DEF_OP(AtomicSub) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -327,19 +335,19 @@ DEF_OP(AtomicAnd) {
 
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
     mvn(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
-    switch (Op->Size) {
+    switch (IROp->Size) {
     case 1: stclrlb(TMP2.W(), MemOperand(MemSrc)); break;
     case 2: stclrlh(TMP2.W(), MemOperand(MemSrc)); break;
     case 4: stclrl(TMP2.W(), MemOperand(MemSrc)); break;
     case 8: stclrl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -376,7 +384,7 @@ DEF_OP(AtomicAnd) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -386,18 +394,18 @@ DEF_OP(AtomicOr) {
 
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
-    switch (Op->Size) {
+  if (CTX->HostFeatures.SupportsAtomics) {
+    switch (IROp->Size) {
     case 1: stsetlb(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 2: stsetlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: stsetl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: stsetl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -434,7 +442,7 @@ DEF_OP(AtomicOr) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -444,18 +452,18 @@ DEF_OP(AtomicXor) {
 
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
-    switch (Op->Size) {
+  if (CTX->HostFeatures.SupportsAtomics) {
+    switch (IROp->Size) {
     case 1: steorlb(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 2: steorlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: steorl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: steorl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -492,7 +500,7 @@ DEF_OP(AtomicXor) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -502,43 +510,42 @@ DEF_OP(AtomicSwap) {
 
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
     mov(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
-    switch (Op->Size) {
+    switch (IROp->Size) {
     case 1: swplb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 2: swplh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: swpl(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: swpl(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    mov(TMP3, GetReg<RA_64>(Op->Header.Args[1].ID()));
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxrb(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
-        uxtb(GetReg<RA_64>(Node), TMP2.W());
+        uxtb(GetReg<RA_32>(Node), TMP2.W());
         break;
       }
       case 2: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxrh(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
-        uxtw(GetReg<RA_64>(Node), TMP2.W());
+        uxtw(GetReg<RA_32>(Node), TMP2.W());
         break;
       }
       case 4: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxr(TMP2.W(), MemOperand(MemSrc));
-        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxr(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
         mov(GetReg<RA_32>(Node), TMP2.W());
         break;
@@ -547,12 +554,12 @@ DEF_OP(AtomicSwap) {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxr(TMP2, MemOperand(MemSrc));
-        stlxr(TMP4, TMP3.X(), MemOperand(MemSrc));
+        stlxr(TMP4, GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4, &LoopTop);
         mov(GetReg<RA_64>(Node), TMP2.X());
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -561,18 +568,18 @@ DEF_OP(AtomicFetchAdd) {
   auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
-    switch (Op->Size) {
+  if (CTX->HostFeatures.SupportsAtomics) {
+    switch (IROp->Size) {
     case 1: ldaddalb(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 2: ldaddalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldaddal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldaddal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -613,7 +620,7 @@ DEF_OP(AtomicFetchAdd) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -622,19 +629,19 @@ DEF_OP(AtomicFetchSub) {
   auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
     neg(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
-    switch (Op->Size) {
+    switch (IROp->Size) {
     case 1: ldaddalb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 2: ldaddalh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldaddal(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldaddal(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -675,7 +682,7 @@ DEF_OP(AtomicFetchSub) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -684,19 +691,19 @@ DEF_OP(AtomicFetchAnd) {
   auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
     mvn(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
-    switch (Op->Size) {
+    switch (IROp->Size) {
     case 1: ldclralb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 2: ldclralh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldclral(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldclral(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -737,7 +744,7 @@ DEF_OP(AtomicFetchAnd) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -746,18 +753,18 @@ DEF_OP(AtomicFetchOr) {
   auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
-    switch (Op->Size) {
+  if (CTX->HostFeatures.SupportsAtomics) {
+    switch (IROp->Size) {
     case 1: ldsetalb(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 2: ldsetalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldsetal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldsetal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -798,7 +805,7 @@ DEF_OP(AtomicFetchOr) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
@@ -807,18 +814,18 @@ DEF_OP(AtomicFetchXor) {
   auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
   auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  if (SupportsAtomics) {
-    switch (Op->Size) {
+  if (CTX->HostFeatures.SupportsAtomics) {
+    switch (IROp->Size) {
     case 1: ldeoralb(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 2: ldeoralh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldeoral(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldeoral(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
   else {
     // TMP2-TMP3
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
@@ -859,14 +866,64 @@ DEF_OP(AtomicFetchXor) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
     }
   }
 }
 
+DEF_OP(AtomicFetchNeg) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
+  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+
+  // TMP2-TMP3
+  switch (IROp->Size) {
+    case 1: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxrb(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 2: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxrh(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 4: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxr(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 8: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxr(TMP2, MemOperand(MemSrc));
+      neg(TMP3, TMP2);
+      stlxr(TMP4, TMP3, MemOperand(MemSrc));
+      cbnz(TMP4, &LoopTop);
+      mov(GetReg<RA_64>(Node), TMP2);
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
+  }
+}
+
 #undef DEF_OP
-void JITCore::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterAtomicHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(CASPAIR,        CASPair);
   REGISTER_OP(CAS,            CAS);
   REGISTER_OP(ATOMICADD,      AtomicAdd);
@@ -880,6 +937,7 @@ void JITCore::RegisterAtomicHandlers() {
   REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
   REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
   REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
+  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp

@@ -1,24 +1,33 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
+#include "Interface/Core/LookupCache.h"
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/Core/InternalThreadState.h"
 
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/HLE/SyscallHandler.h>
+#include <FEXCore/Utils/MathUtils.h>
 #include <Interface/HLE/Thunks/Thunks.h>
 
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(GuestCallDirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestCallIndirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestReturn) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(SignalReturn) {
@@ -35,7 +44,7 @@ DEF_OP(CallbackReturn) {
 
   // spill back to CTX
   SpillStaticRegs();
-  
+
   // First we must reset the stack
   ResetStack();
 
@@ -46,9 +55,9 @@ DEF_OP(CallbackReturn) {
   str(w2, MemOperand(x0));
 
   // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
+  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
   add(x2, x2, 8);
-  str(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
+  str(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
 
   PopCalleeSavedRegisters();
 
@@ -67,7 +76,7 @@ DEF_OP(ExitFunction) {
   uint64_t NewRIP;
 
   if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
-    Literal l_BranchHost{ExitFunctionLinkerAddress};
+    Literal l_BranchHost{ThreadSharedData.Dispatcher->ExitFunctionLinkerAddress};
     Literal l_BranchGuest{NewRIP};
 
     ldr(x0, &l_BranchHost);
@@ -77,9 +86,9 @@ DEF_OP(ExitFunction) {
     place(&l_BranchGuest);
   } else {
     RipReg = GetReg<RA_64>(Op->Header.Args[0].ID());
-    
+
     // L1 Cache
-    LoadConstant(x0, State->LookupCache->GetL1Pointer());
+    LoadConstant(x0, ThreadState->LookupCache->GetL1Pointer());
 
     and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
     add(x0, x0, Operand(x3, Shift::LSL, 4));
@@ -90,30 +99,23 @@ DEF_OP(ExitFunction) {
     br(x1);
 
     bind(&FullLookup);
-    LoadConstant(TMP1, AbsoluteLoopTopAddress);
-    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, State.rip)));
+    LoadConstant(TMP1, ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress);
+    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
     br(TMP1);
   }
 }
 
 DEF_OP(Jump) {
-  auto Op = IROp->C<IR::IROp_Jump>();
+  const auto Op = IROp->C<IR::IROp_Jump>();
+  const auto ArgID = Op->Args(0).ID();
 
-  Label *TargetLabel;
-  auto IsTarget = JumpTargets.find(Op->Header.Args[0].ID());
-  if (IsTarget == JumpTargets.end()) {
-    TargetLabel = &JumpTargets.try_emplace(Op->Header.Args[0].ID()).first->second;
-  }
-  else {
-    TargetLabel = &IsTarget->second;
-  }
-  PendingTargetLabel = TargetLabel;
+  PendingTargetLabel = &JumpTargets.try_emplace(ArgID).first->second;
 }
 
 #define GRCMP(Node) (Op->CompareSize == 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))
 #define GRFCMP(Node) (Op->CompareSize == 4 ? GetDst(Node).S() : GetDst(Node).D())
 
-Condition MapBranchCC(IR::CondClassType Cond) {
+static Condition MapBranchCC(IR::CondClassType Cond) {
   switch (Cond.Val) {
   case FEXCore::IR::COND_EQ: return Condition::eq;
   case FEXCore::IR::COND_NEQ: return Condition::ne;
@@ -128,15 +130,15 @@ Condition MapBranchCC(IR::CondClassType Cond) {
   case FEXCore::IR::COND_FLU: return Condition::lt;
   case FEXCore::IR::COND_FGE: return Condition::ge;
   case FEXCore::IR::COND_FLEU:return Condition::le;
-  case FEXCore::IR::COND_FGT: return Condition::hi;
+  case FEXCore::IR::COND_FGT: return Condition::gt;
   case FEXCore::IR::COND_FU:  return Condition::vs;
   case FEXCore::IR::COND_FNU: return Condition::vc;
-  case FEXCore::IR::COND_VS:;
-  case FEXCore::IR::COND_VC:;
+  case FEXCore::IR::COND_VS:
+  case FEXCore::IR::COND_VC:
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
-  LogMan::Msg::A("Unsupported compare type");
+  LOGMAN_MSG_A_FMT("Unsupported compare type");
   return Condition::nv;
   }
 }
@@ -145,51 +147,34 @@ Condition MapBranchCC(IR::CondClassType Cond) {
 DEF_OP(CondJump) {
   auto Op = IROp->C<IR::IROp_CondJump>();
 
-  Label *TrueTargetLabel;
-  Label *FalseTargetLabel;
-
-  auto TrueIter = JumpTargets.find(Op->TrueBlock.ID());
-  auto FalseIter = JumpTargets.find(Op->FalseBlock.ID());
-
-  if (TrueIter == JumpTargets.end()) {
-    TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
-  }
-  else {
-    TrueTargetLabel = &TrueIter->second;
-  }
-
+  Label *TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
 
   uint64_t Const;
-  bool isConst = IsInlineConstant(Op->Cmp2, &Const);
+  const bool isConst = IsInlineConstant(Op->Cmp2, &Const);
 
   if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_EQ) {
-    LogMan::Throw::A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
+    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
     cbz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
   } else if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_NEQ) {
-    LogMan::Throw::A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
+    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
     cbnz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
   } else {
     if (IsGPR(Op->Cmp1.ID())) {
-      if (isConst)
+      if (isConst) {
         cmp(GRCMP(Op->Cmp1.ID()), Const);
-      else
+      } else {
         cmp(GRCMP(Op->Cmp1.ID()), GRCMP(Op->Cmp2.ID()));
+      }
     } else if (IsFPR(Op->Cmp1.ID())) {
       fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
     } else {
-      LogMan::Msg::A("CondJump: Expected GPR or FPR");
+      LOGMAN_MSG_A_FMT("CondJump: Expected GPR or FPR");
     }
 
     b(TrueTargetLabel, MapBranchCC(Op->Cond));
   }
-  
-  if (FalseIter == JumpTargets.end()) {
-    FalseTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
-  }
-  else {
-    FalseTargetLabel = &FalseIter->second;
-  }
-  PendingTargetLabel = FalseTargetLabel;
+
+  PendingTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
 }
 
 DEF_OP(Syscall) {
@@ -217,7 +202,7 @@ DEF_OP(Syscall) {
   blr(x3);
 
   add(sp, sp, SPOffset);
-  
+
   // Result is now in x0
   // Fix the stack and any values that were stepped on
   FillStaticRegs();
@@ -227,6 +212,152 @@ DEF_OP(Syscall) {
   mov(GetReg<RA_64>(Node), x0);
 }
 
+DEF_OP(InlineSyscall) {
+  auto Op = IROp->C<IR::IROp_InlineSyscall>();
+  // Arguments are passed as follows:
+  // X8: SyscallNumber - RA INTERSECT
+  // X0: Arg0 & Return
+  // X1: Arg1
+  // X2: Arg2
+  // X3: Arg3
+  // X4: Arg4 - RA INTERSECT
+  // X5: Arg5 - RA INTERSECT
+  // X6: Arg6 - Doesn't exist in x86-64 land. RA INTERSECT
+
+  // One argument is removed from the SyscallArguments::MAX_ARGS since the first argument was syscall number
+  const static std::array<vixl::aarch64::Register, FEXCore::HLE::SyscallArguments::MAX_ARGS-1> RegArgs = {{
+    x0, x1, x2, x3, x4, x5
+  }};
+
+  bool Intersects{};
+  // We always need to spill x8 since we can't know if it is live at this SSA location
+  uint32_t SpillMask = 1U << 8;
+  std::vector<vixl::aarch64::Register> IntersectRegs(FEXCore::HLE::SyscallArguments::MAX_ARGS);
+  for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
+    if (Op->Header.Args[i].IsInvalid()) break;
+
+    auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
+    if (Reg.GetCode() == x8.GetCode() ||
+        Reg.GetCode() == x4.GetCode() ||
+        Reg.GetCode() == x5.GetCode()) {
+
+      SpillMask |= (1U << Reg.GetCode());
+      Intersects = true;
+    }
+  }
+  // XXX: For some reason spilling only the x4, x5, and x8 registers was causing issues
+  // Come back to this once investigation reveals why it fails the gvisor ioctl test
+  // For now override to all GPRs
+  SpillMask = ~0U;
+
+  // Ordering is incredibly important here
+  // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
+  // Only spill the registers that intersect with our usage
+  SpillStaticRegs(false, SpillMask);
+
+  // Now that we are spilled, store in the state that we are in a syscall
+  // Still without overwriting registers that matter
+  // 16bit LoadConstant to be a single instruction
+  // We must always spill at least one register (x8) so this value always has a bit set
+  // This gives the signal handler a value to check to see if we are in a syscall at all
+  LoadConstant(x0, SpillMask & 0xFFFF);
+  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+
+  // Now that we have claimed to be a syscall we can set up the arguments
+  if (Intersects) {
+    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
+      if (Op->Header.Args[i].IsInvalid()) break;
+
+      if (CTX->Config.Is64BitMode()) {
+        auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
+        // In the case of intersection with x4, x5, or x8 then these are currently SRA
+        // for registers RAX, RBX, and RSI. Which have just been spilled
+        // Just load back from the context. Could be slightly smarter but this is fairly uncommon
+        if (Reg.GetCode() == x8.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
+        }
+        else if (Reg.GetCode() == x4.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
+        }
+        else if (Reg.GetCode() == x5.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
+        }
+      }
+    }
+
+    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
+      if (Op->Header.Args[i].IsInvalid()) break;
+
+      if (CTX->Config.Is64BitMode()) {
+        auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
+        // In the case of intersection with x4, x5, or x8 then these are currently SRA
+        // for registers RAX, RBX, and RSI. Which have just been spilled
+        // Just load back from the context. Could be slightly smarter but this is fairly uncommon
+        if (Reg.GetCode() == x8.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
+        }
+        else if (Reg.GetCode() == x4.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
+        }
+        else if (Reg.GetCode() == x5.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
+        }
+        else {
+          mov(RegArgs[i], Reg);
+        }
+      }
+      else {
+        auto Reg = GetReg<RA_32>(Op->Header.Args[i].ID());
+        if (Reg.GetCode() == w8.GetCode()) {
+          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
+        }
+        else if (Reg.GetCode() == w4.GetCode()) {
+          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
+        }
+        else if (Reg.GetCode() == w5.GetCode()) {
+          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
+        }
+        else {
+          uxtw(RegArgs[i].W(), Reg);
+        }
+      }
+    }
+  }
+  else {
+    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
+      if (Op->Header.Args[i].IsInvalid()) break;
+
+      if (CTX->Config.Is64BitMode()) {
+        mov(RegArgs[i], GetReg<RA_64>(Op->Header.Args[i].ID()));
+      }
+      else {
+        uxtw(RegArgs[i], GetReg<RA_64>(Op->Header.Args[i].ID()));
+      }
+    }
+  }
+
+  LoadConstant(x8, Op->HostSyscallNumber);
+  svc(0);
+  // On updated signal mask we can receive a signal RIGHT HERE
+
+  // Now that we are done in the syscall we need to carefully peel back the state
+  // First unspill the registers from before
+  FillStaticRegs(false, SpillMask);
+
+  // Now the registers we've spilled are back in their original host registers
+  // We can safely claim we are no longer in a syscall
+  str(xzr, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+
+  // Result is now in x0
+  // Move result to its destination register
+  if (CTX->Config.Is64BitMode()) {
+    mov(GetReg<RA_64>(Node), x0);
+  }
+  else {
+    uxtw(GetReg<RA_64>(Node), x0);
+  }
+}
+
 DEF_OP(Thunk) {
   auto Op = IROp->C<IR::IROp_Thunk>();
   // Arguments are passed as follows:
@@ -239,34 +370,29 @@ DEF_OP(Thunk) {
 
   mov(x0, GetReg<RA_64>(Op->Header.Args[0].ID()));
 
-#if _M_X86_64
-  ERROR_AND_DIE("JIT: OP_THUNK not supported with arm simulator")
-#else
-  auto thunkFn = State->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
+  auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
   LoadConstant(x2, (uintptr_t)thunkFn);
   blr(x2);
-#endif
 
   PopDynamicRegsAndLR();
-  
+
   FillStaticRegs(); // load from ctx after ra64 refill
 }
 
-
 DEF_OP(ValidateCode) {
   auto Op = IROp->C<IR::IROp_ValidateCode>();
-  uint8_t *OldCode = (uint8_t *)&Op->CodeOriginalLow;
+  const auto *OldCode = (const uint8_t *)&Op->CodeOriginalLow;
   int len = Op->CodeLength;
   int idx = 0;
 
   LoadConstant(GetReg<RA_64>(Node), 0);
-  LoadConstant(x0, IR->GetHeader()->Entry + Op->Offset);
+  LoadConstant(x0, Entry + Op->Offset);
   LoadConstant(x1, 1);
-  
+
   while (len >= 8)
   {
     ldr(x2, MemOperand(x0, idx));
-    LoadConstant(x3, *(uint32_t *)(OldCode + idx));
+    LoadConstant(x3, *(const uint32_t *)(OldCode + idx));
     cmp(x2, x3);
     csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
     len -= 8;
@@ -275,7 +401,7 @@ DEF_OP(ValidateCode) {
   while (len >= 4)
   {
     ldr(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(uint32_t *)(OldCode + idx));
+    LoadConstant(w3, *(const uint32_t *)(OldCode + idx));
     cmp(w2, w3);
     csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
     len -= 4;
@@ -284,7 +410,7 @@ DEF_OP(ValidateCode) {
   while (len >= 2)
   {
     ldrh(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(uint16_t *)(OldCode + idx));
+    LoadConstant(w3, *(const uint16_t *)(OldCode + idx));
     cmp(w2, w3);
     csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
     len -= 2;
@@ -293,7 +419,7 @@ DEF_OP(ValidateCode) {
   while (len >= 1)
   {
     ldrb(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(uint8_t *)(OldCode + idx));
+    LoadConstant(w3, *(const uint8_t *)(OldCode + idx));
     cmp(w2, w3);
     csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
     len -= 1;
@@ -302,17 +428,16 @@ DEF_OP(ValidateCode) {
 }
 
 DEF_OP(RemoveCodeEntry) {
-  auto Op = IROp->C<IR::IROp_RemoveCodeEntry>();
   // Arguments are passed as follows:
   // X0: Thread
   // X1: RIP
 
   PushDynamicRegsAndLR();
-  
+
   mov(x0, STATE);
-  LoadConstant(x1, IR->GetHeader()->Entry);
- 
-  LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntry));
+  LoadConstant(x1, Entry);
+
+  LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
   SpillStaticRegs();
   blr(x2);
   FillStaticRegs();
@@ -323,15 +448,17 @@ DEF_OP(RemoveCodeEntry) {
 
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
-  
+
   PushDynamicRegsAndLR();
 
   // x0 = CPUID Handler
   // x1 = CPUID Function
+  // x2 = CPUID Leaf
   LoadConstant(x0, reinterpret_cast<uint64_t>(&CTX->CPUID));
   mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
+  mov(x2, GetReg<RA_64>(Op->Header.Args[1].ID()));
 
-  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t);
+  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t, uint32_t);
   union PtrCast {
     ClassPtrType ClassPtr;
     uintptr_t Data;
@@ -354,8 +481,8 @@ DEF_OP(CPUID) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterBranchHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
   REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
   REGISTER_OP(GUESTRETURN,       GuestReturn);
@@ -365,6 +492,7 @@ void JITCore::RegisterBranchHandlers() {
   REGISTER_OP(JUMP,              Jump);
   REGISTER_OP(CONDJUMP,          CondJump);
   REGISTER_OP(SYSCALL,           Syscall);
+  REGISTER_OP(INLINESYSCALL,     InlineSyscall);
   REGISTER_OP(THUNK,             Thunk);
   REGISTER_OP(VALIDATECODE,      ValidateCode);
   REGISTER_OP(REMOVECODEENTRY,   RemoveCodeEntry);

External/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(VInsGPR) {
   auto Op = IROp->C<IR::IROp_VInsGPR>();
   mov(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
@@ -25,7 +31,7 @@ DEF_OP(VInsGPR) {
       ins(GetDst(Node).V2D(), Op->Index, GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -33,11 +39,11 @@ DEF_OP(VCastFromGPR) {
   auto Op = IROp->C<IR::IROp_VCastFromGPR>();
   switch (Op->Header.ElementSize) {
     case 1:
-      uxtb(TMP1.W(), GetReg<RA_32>(Op->Header.Args[0].ID()).W());
+      uxtb(TMP1.W(), GetReg<RA_32>(Op->Header.Args[0].ID()));
       fmov(GetDst(Node).S(), TMP1.W());
       break;
     case 2:
-      uxth(TMP1.W(), GetReg<RA_32>(Op->Header.Args[0].ID()).W());
+      uxth(TMP1.W(), GetReg<RA_32>(Op->Header.Args[0].ID()));
       fmov(GetDst(Node).S(), TMP1.W());
       break;
     case 4:
@@ -46,14 +52,10 @@ DEF_OP(VCastFromGPR) {
     case 8:
       fmov(GetDst(Node).D(), GetReg<RA_64>(Op->Header.Args[0].ID()).X());
       break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown castGPR element size: {}", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Float_FromGPR_U) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
   uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
@@ -89,20 +91,7 @@ DEF_OP(Float_FToF) {
       fcvt(GetDst(Node).S(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
     }
-    default: LogMan::Msg::A("Unknown FCVT sizes: 0x%x", Conv);
-  }
-}
-
-DEF_OP(Vector_UToF) {
-  auto Op = IROp->C<IR::IROp_Vector_UToF>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      ucvtf(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-    break;
-    case 8:
-      ucvtf(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown FCVT sizes: 0x{:x}", Conv);
   }
 }
 
@@ -115,20 +104,7 @@ DEF_OP(Vector_SToF) {
     case 8:
       scvtf(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
-  }
-}
-
-DEF_OP(Vector_FToZU) {
-  auto Op = IROp->C<IR::IROp_Vector_FToZU>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      fcvtzu(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-    break;
-    case 8:
-      fcvtzu(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -141,22 +117,7 @@ DEF_OP(Vector_FToZS) {
     case 8:
       fcvtzs(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
-  }
-}
-
-DEF_OP(Vector_FToU) {
-  auto Op = IROp->C<IR::IROp_Vector_FToU>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      frinti(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-      fcvtzu(GetDst(Node).V4S(), GetDst(Node).V4S());
-    break;
-    case 8:
-      frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-      fcvtzu(GetDst(Node).V2D(), GetDst(Node).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -171,7 +132,7 @@ DEF_OP(Vector_FToS) {
       frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
       fcvtzs(GetDst(Node).V2D(), GetDst(Node).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -188,25 +149,78 @@ DEF_OP(Vector_FToF) {
       fcvtn(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2D());
       break;
     }
-    default: LogMan::Msg::A("Unknown Conversion Type : 0%04x", Conv); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF Type : 0x{:04x}", Conv); break;
+  }
+}
+
+DEF_OP(Vector_FToI) {
+  auto Op = IROp->C<IR::IROp_Vector_FToI>();
+  switch (Op->Round) {
+    case FEXCore::IR::Round_Nearest.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintn(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintn(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Negative_Infinity.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintm(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintm(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Positive_Infinity.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintp(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintp(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Towards_Zero.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintz(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintz(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Host.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frinti(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterConversionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(VINSGPR,         VInsGPR);
   REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_U, Float_FromGPR_U);
   REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
   REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_UTOF,     Vector_UToF);
   REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZU,    Vector_FToZU);
   REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOU,     Vector_FToU);
   REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
   REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
+  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -48,7 +54,7 @@ DEF_OP(AESDecLast) {
 DEF_OP(AESKeyGenAssist) {
 	auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
 
-  aarch64::Label Constant;
+  aarch64::Literal ConstantLiteral (0x0C030609'0306090CULL, 0x040B0E01'0B0E0104ULL);
   aarch64::Label PastConstant;
 
   // Do a "regular" AESE step
@@ -57,8 +63,7 @@ DEF_OP(AESKeyGenAssist) {
   aese(VTMP1.V16B(), VTMP2.V16B());
 
   // Do a table shuffle to undo ShiftRows
-  adr(TMP1.X(), &Constant);
-  ldr(VTMP3, MemOperand(TMP1.X()));
+  ldr(VTMP3, &ConstantLiteral);
 
   // Now EOR in the RCON
   if (Op->RCON) {
@@ -74,24 +79,39 @@ DEF_OP(AESKeyGenAssist) {
   }
 
   b(&PastConstant);
-  bind(&Constant);
-  dc32(0x0B0E0104);
-  dc32(0x040B0E01);
-  dc32(0x0306090C);
-  dc32(0x0C030609);
+  place(&ConstantLiteral);
   bind(&PastConstant);
 }
 
+DEF_OP(CRC32) {
+  auto Op = IROp->C<IR::IROp_CRC32>();
+  switch (Op->SrcSize) {
+    case 1:
+      crc32cb(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      break;
+    case 2:
+      crc32ch(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      break;
+    case 4:
+      crc32cw(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      break;
+    case 8:
+      crc32cx(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_64>(Op->Src2.ID()));
+      break;
+    default: LOGMAN_MSG_A_FMT("Unknown CRC32 size: {}", Op->SrcSize);
+  }
+}
+
 #undef DEF_OP
-void JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterEncryptionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(VAESIMC,     AESImc);
   REGISTER_OP(VAESENC,     AESEnc);
   REGISTER_OP(VAESENCLAST, AESEncLast);
   REGISTER_OP(VAESDEC,     AESDec);
   REGISTER_OP(VAESDECLAST, AESDecLast);
   REGISTER_OP(VAESKEYGENASSIST, AESKeyGenAssist);
-
+  REGISTER_OP(CRC32,             CRC32);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/FlagOps.cpp

@@ -1,18 +1,24 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
   ubfx(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), Op->Flag, 1);
 }
 
 #undef DEF_OP
-void JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterFlagHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(GETHOSTFLAG, GetHostFlag);
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #pragma once
 
-#include "Interface/Core/LookupCache.h"
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
 #include "aarch64/disasm-aarch64.h"
 #include "aarch64/assembler-aarch64.h"
 
@@ -29,80 +35,50 @@ namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
 
-// All but x29 are caller saved
-const std::array<aarch64::Register, 16> SRA64 = {
-  x4, x5, x6, x7, x8, x9, x10, x11,
-  x12, x18, x17, x16, x15, x14, x13, x29
-};
-
-// All are callee saved
-const std::array<aarch64::Register, 9> RA64 = {
-  x20, x21, x22, x23, x24, x25, x26, x27,
-  x19
-};
-
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4>  RA64Pair = {{
-  {x20, x21},
-  {x22, x23},
-  {x24, x25},
-  {x26, x27},
-}};
-
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4> RA32Pair = {{
-  {w20, w21},
-  {w22, w23},
-  {w24, w25},
-  {w26, w27},
-}};
-
-// All are caller saved
-const std::array<aarch64::VRegister, 16> SRAFPR = {
-  v16, v17, v18, v19, v20, v21, v22, v23,
-  v24, v25, v26, v27, v28, v29, v30, v31
-};
-
-//  v8..v15 = (lower 64bits) Callee saved
-const std::array<aarch64::VRegister, 12> RAFPR = {
-/*v0,  v1,  v2,  v3,*/v4,  v5,  v6,  v7,  // v0 ~ v3 are used as temps
-  v8,  v9,  v10, v11, v12, v13, v14, v15
-};
-
-class JITCore final : public CPUBackend, public vixl::aarch64::Assembler  {
+class Arm64JITCore final : public CPUBackend, public Arm64Emitter  {
 public:
   struct CodeBuffer {
     uint8_t *Ptr;
     size_t Size;
   };
 
-  explicit JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread);
+  explicit Arm64JITCore(FEXCore::Context::Context *ctx,
+                        FEXCore::Core::InternalThreadState *Thread,
+                        bool CompileThread);
+  ~Arm64JITCore() override;
 
-  ~JITCore() override;
-  std::string GetName() override { return "JIT"; }
-  void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
+  [[nodiscard]] std::string GetName() override { return "JIT"; }
 
-  void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
+  [[nodiscard]] void *CompileCode(uint64_t Entry,
+                                  FEXCore::IR::IRListView const *IR,
+                                  FEXCore::Core::DebugData *DebugData,
+                                  FEXCore::IR::RegisterAllocationData *RAData) override;
 
-  bool NeedsOpDispatch() override { return true; }
+  [[nodiscard]] void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
+
+  [[nodiscard]] bool NeedsOpDispatch() override { return true; }
 
   void ClearCache() override;
 
-  bool HandleSIGILL(int Signal, void *info, void *ucontext);
-  bool HandleSIGBUS(int Signal, void *info, void *ucontext);
-  bool HandleSignalPause(int Signal, void *info, void *ucontext);
-  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-
   static constexpr size_t INITIAL_CODE_SIZE = 1024 * 1024 * 16;
-  static CodeBuffer AllocateNewCodeBuffer(size_t Size);
+  [[nodiscard]] CodeBuffer AllocateNewCodeBuffer(size_t Size);
 
   void CopyNecessaryDataForCompileThread(CPUBackend *Original) override;
+  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true, bool IncludeCompileService = true) const override {
+    return Dispatcher->IsAddressInJITCode(Address, IncludeDispatcher, IncludeCompileService);
+  }
 
 private:
+  FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
+
+  std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
   Label *PendingTargetLabel;
   FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
+  FEXCore::Core::InternalThreadState *ThreadState;
   FEXCore::IR::IRListView const *IR;
+  uint64_t Entry;
 
-  std::map<IR::OrderedNodeWrapper::NodeOffsetType, aarch64::Label> JumpTargets;
+  std::map<IR::NodeID, aarch64::Label> JumpTargets;
 
   /**
    * @name Register Allocation
@@ -126,33 +102,39 @@ private:
   constexpr static uint8_t RA_FPR = 2;
 
   template<uint8_t RAType>
-  aarch64::Register GetReg(uint32_t Node);
+  [[nodiscard]] aarch64::Register GetReg(IR::NodeID Node) const;
 
   template<>
-  aarch64::Register GetReg<RA_32>(uint32_t Node);
+  [[nodiscard]] aarch64::Register GetReg<RA_32>(IR::NodeID Node) const;
   template<>
-  aarch64::Register GetReg<RA_64>(uint32_t Node);
+  [[nodiscard]] aarch64::Register GetReg<RA_64>(IR::NodeID Node) const;
 
   template<uint8_t RAType>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair(uint32_t Node);
+  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair(IR::NodeID Node) const;
 
   template<>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(uint32_t Node);
+  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(IR::NodeID Node) const;
   template<>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(uint32_t Node);
+  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(IR::NodeID Node) const;
 
-  aarch64::VRegister GetSrc(uint32_t Node);
-  aarch64::VRegister GetDst(uint32_t Node);
+  [[nodiscard]] aarch64::VRegister GetSrc(IR::NodeID Node) const;
+  [[nodiscard]] aarch64::VRegister GetDst(IR::NodeID Node) const;
 
-  FEXCore::IR::RegisterClassType GetRegClass(uint32_t Node);
+  [[nodiscard]] FEXCore::IR::RegisterClassType GetRegClass(IR::NodeID Node) const;
 
-  bool IsFPR(uint32_t Node);
-  bool IsGPR(uint32_t Node);
+  [[nodiscard]] IR::PhysicalRegister GetPhys(IR::NodeID Node) const;
 
-  MemOperand GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale);
+  [[nodiscard]] bool IsFPR(IR::NodeID Node) const;
+  [[nodiscard]] bool IsGPR(IR::NodeID Node) const;
 
-  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr);
-  bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value);
+  [[nodiscard]] MemOperand GenerateMemOperand(uint8_t AccessSize,
+                                              aarch64::Register Base,
+                                              IR::OrderedNodeWrapper Offset,
+                                              IR::MemOffsetType OffsetType,
+                                              uint8_t OffsetScale);
+
+  [[nodiscard]] bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr) const;
+  [[nodiscard]] bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const;
 
   struct LiveRange {
     uint32_t Begin;
@@ -162,9 +144,6 @@ private:
 #if DEBUG
   vixl::aarch64::Decoder Decoder;
 #endif
-  vixl::aarch64::CPU CPU;
-  bool SupportsAtomics{};
-  bool SupportsRCPC{};
 
   void EmplaceNewCodeBuffer(CodeBuffer Buffer) {
     CurrentCodeBuffer = &CodeBuffers.emplace_back(Buffer);
@@ -181,8 +160,6 @@ private:
   // For code safety we can't delete code buffers until outside of all signals
   std::vector<CodeBuffer> CodeBuffers{};
 
-  // This is the codebuffer that our dispatcher lives in
-  CodeBuffer DispatcherCodeBuffer{};
   // This is the current code buffer that we are tracking
   CodeBuffer *CurrentCodeBuffer{};
 
@@ -190,61 +167,27 @@ private:
   static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 128;
   static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 2;
 
-  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true);
-
 #if DEBUG
   vixl::aarch64::Disassembler Disasm;
 #endif
 
-  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
-
-  void CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread);
-  void PushCalleeSavedRegisters();
-  void PopCalleeSavedRegisters();
-
-  static uint64_t ExitFunctionLink(JITCore *core, FEXCore::Core::InternalThreadState *Thread, uint64_t *record);
-
-  /**
-   * @name Dispatch Helper functions
-   * @{ */
-  uint64_t AbsoluteLoopTopAddressFillSRA{};
-  uint64_t AbsoluteLoopTopAddress{};
-  uint64_t ThreadPauseHandlerAddressSpillSRA{};
-  uint64_t ExitFunctionLinkerAddress{};
-  uint64_t ThreadPauseHandlerAddress{};
-
-  uint64_t ThreadStopHandlerAddressSpillSRA{};
-  uint64_t ThreadStopHandlerAddress{};
-  uint64_t PauseReturnInstruction{};
-
-  uint32_t SignalHandlerRefCounter{};
-
-  void StoreThreadState(int Signal, void *ucontext);
-  void RestoreThreadState(void *ucontext);
-  /**  @} */
+  static uint64_t ExitFunctionLink(Arm64JITCore *core, FEXCore::Core::CpuStateFrame *Frame, uint64_t *record);
 
   struct CompilerSharedData {
     uint64_t SignalReturnInstruction{};
+    uint64_t UnimplementedInstructionAddress{};
+    uint64_t OverflowExceptionInstructionAddress{};
 
     uint32_t *SignalHandlerRefCounterPtr{};
+    FEXCore::CPU::Dispatcher *Dispatcher{};
   };
 
   CompilerSharedData ThreadSharedData;
   IR::RegisterAllocationPass *RAPass;
   IR::RegisterAllocationData *RAData;
 
-  uint32_t SpillSlots{};
-
-  void SpillStaticRegs();
-  void FillStaticRegs();
-
-  void PushDynamicRegsAndLR();
-  void PopDynamicRegsAndLR();
-
-  void ResetStack();
-
-  using OpHandler = void (JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
-  std::array<OpHandler, FEXCore::IR::IROps::OP_LAST + 1> OpHandlers {};
+  using OpHandler = void (Arm64JITCore::*)(IR::IROp_Header *IROp, IR::NodeID Node);
+  std::array<OpHandler, IR::IROps::OP_LAST + 1> OpHandlers {};
   void RegisterALUHandlers();
   void RegisterAtomicHandlers();
   void RegisterBranchHandlers();
@@ -255,7 +198,7 @@ private:
   void RegisterMoveHandlers();
   void RegisterVectorHandlers();
   void RegisterEncryptionHandlers();
-#define DEF_OP(x) void Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 
   ///< Unhandled handler
   DEF_OP(Unhandled);
@@ -283,6 +226,7 @@ private:
   DEF_OP(UMulH);
   DEF_OP(Or);
   DEF_OP(And);
+  DEF_OP(Andn);
   DEF_OP(Xor);
   DEF_OP(Lshl);
   DEF_OP(Lshr);
@@ -290,6 +234,8 @@ private:
   DEF_OP(Rol);
   DEF_OP(Ror);
   DEF_OP(Extr);
+  DEF_OP(PDep);
+  DEF_OP(PExt);
   DEF_OP(LDiv);
   DEF_OP(LUDiv);
   DEF_OP(LRem);
@@ -309,7 +255,6 @@ private:
   DEF_OP(VExtractToGPR);
   DEF_OP(Float_ToGPR_ZU);
   DEF_OP(Float_ToGPR_ZS);
-  DEF_OP(Float_ToGPR_U);
   DEF_OP(Float_ToGPR_S);
   DEF_OP(FCmp);
 
@@ -327,6 +272,7 @@ private:
   DEF_OP(AtomicFetchAnd);
   DEF_OP(AtomicFetchOr);
   DEF_OP(AtomicFetchXor);
+  DEF_OP(AtomicFetchNeg);
 
   ///< Branch ops
   DEF_OP(GuestCallDirect);
@@ -338,6 +284,7 @@ private:
   DEF_OP(Jump);
   DEF_OP(CondJump);
   DEF_OP(Syscall);
+  DEF_OP(InlineSyscall);
   DEF_OP(Thunk);
   DEF_OP(ValidateCode);
   DEF_OP(RemoveCodeEntry);
@@ -346,22 +293,19 @@ private:
   ///< Conversion ops
   DEF_OP(VInsGPR);
   DEF_OP(VCastFromGPR);
-  DEF_OP(Float_FromGPR_U);
   DEF_OP(Float_FromGPR_S);
   DEF_OP(Float_FToF);
-  DEF_OP(Vector_UToF);
   DEF_OP(Vector_SToF);
-  DEF_OP(Vector_FToZU);
   DEF_OP(Vector_FToZS);
-  DEF_OP(Vector_FToU);
   DEF_OP(Vector_FToS);
   DEF_OP(Vector_FToF);
+  DEF_OP(Vector_FToI);
 
   ///< Flag ops
   DEF_OP(GetHostFlag);
 
   ///< Memory ops
-    DEF_OP(LoadContext);
+  DEF_OP(LoadContext);
   DEF_OP(StoreContext);
   DEF_OP(LoadRegister);
   DEF_OP(StoreRegister);
@@ -375,8 +319,12 @@ private:
   DEF_OP(StoreMem);
   DEF_OP(LoadMemTSO);
   DEF_OP(StoreMemTSO);
+  DEF_OP(ParanoidLoadMemTSO);
+  DEF_OP(ParanoidStoreMemTSO);
   DEF_OP(VLoadMemElement);
   DEF_OP(VStoreMemElement);
+  DEF_OP(CacheLineClear);
+  DEF_OP(CacheLineZero);
 
   ///< Misc ops
   DEF_OP(EndBlock);
@@ -387,6 +335,7 @@ private:
   DEF_OP(Print);
   DEF_OP(GetRoundingMode);
   DEF_OP(SetRoundingMode);
+  DEF_OP(ProcessorID);
 
   ///< Move ops
   DEF_OP(ExtractElementPair);
@@ -402,6 +351,7 @@ private:
   DEF_OP(SplatVector4);
   DEF_OP(VMov);
   DEF_OP(VAnd);
+  DEF_OP(VBic);
   DEF_OP(VOr);
   DEF_OP(VXor);
   DEF_OP(VAdd);
@@ -412,8 +362,10 @@ private:
   DEF_OP(VSQSub);
   DEF_OP(VAddP);
   DEF_OP(VAddV);
+  DEF_OP(VUMinV);
   DEF_OP(VURAvg);
   DEF_OP(VAbs);
+  DEF_OP(VPopcount);
   DEF_OP(VFAdd);
   DEF_OP(VFAddP);
   DEF_OP(VFSub);
@@ -433,6 +385,8 @@ private:
   DEF_OP(VSMax);
   DEF_OP(VZip);
   DEF_OP(VZip2);
+  DEF_OP(VUnZip);
+  DEF_OP(VUnZip2);
   DEF_OP(VBSL);
   DEF_OP(VCMPEQ);
   DEF_OP(VCMPEQZ);
@@ -455,6 +409,7 @@ private:
   DEF_OP(VInsElement);
   DEF_OP(VInsScalarElement);
   DEF_OP(VExtractElement);
+  DEF_OP(VDupElement);
   DEF_OP(VExtr);
   DEF_OP(VSLI);
   DEF_OP(VSRI);
@@ -477,6 +432,7 @@ private:
   DEF_OP(VSMull);
   DEF_OP(VUMull2);
   DEF_OP(VSMull2);
+  DEF_OP(VUABDL);
   DEF_OP(VTBL1);
 
   ///< Encryption ops
@@ -486,6 +442,7 @@ private:
   DEF_OP(AESDec);
   DEF_OP(AESDecLast);
   DEF_OP(AESKeyGenAssist);
+  DEF_OP(CRC32);
 #undef DEF_OP
 };
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp

@@ -1,10 +1,17 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
+#include <FEXCore/Utils/CompilerDefs.h>
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 
 DEF_OP(LoadContext) {
   auto Op = IROp->C<IR::IROp_LoadContext>();
@@ -23,7 +30,7 @@ DEF_OP(LoadContext) {
     case 8:
       ldr(GetReg<RA_64>(Node), MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
   else {
@@ -44,7 +51,7 @@ DEF_OP(LoadContext) {
     case 16:
       ldr(Dst, MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
 }
@@ -66,7 +73,7 @@ DEF_OP(StoreContext) {
     case 8:
       str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
   else {
@@ -87,7 +94,7 @@ DEF_OP(StoreContext) {
     case 16:
       str(Src, MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
 }
@@ -95,61 +102,60 @@ DEF_OP(StoreContext) {
 
 DEF_OP(LoadRegister) {
   auto Op = IROp->C<IR::IROp_LoadRegister>();
-  uint8_t OpSize = IROp->Size;
 
   if (Op->Class == IR::GPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.gregs[0])) / 8;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0])) / 8;
     auto regOffs = Op->Offset & 7;
 
-    LogMan::Throw::A(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRA64.size(), "out of range regId");
 
     auto reg = SRA64[regId];
-    
+
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, regOffs * 8, 8);
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, 0, 16);
         break;
 
       case 4:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_32>(Node), reg.W());
         break;
 
       case 8:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_64>(Node), reg);
         break;
     }
   } else if (Op->Class == IR::FPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.xmm[0][0])) / 16;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0])) / 16;
     auto regOffs = Op->Offset & 15;
 
-    LogMan::Throw::A(regId < SRAFPR.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "out of range regId");
 
     auto guest = SRAFPR[regId];
     auto host = GetSrc(Node);
 
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         mov(host.B(), guest.B());
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         fmov(host.H(), guest.H());
         break;
 
       case 4:
-        LogMan::Throw::A((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             fmov(host.S(), guest.S());
@@ -159,7 +165,7 @@ DEF_OP(LoadRegister) {
         break;
 
       case 8:
-        LogMan::Throw::A((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             mov(host.D(), guest.D());
@@ -169,56 +175,54 @@ DEF_OP(LoadRegister) {
         break;
 
       case 16:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (host.GetCode() != guest.GetCode())
           mov(host.Q(), guest.Q());
         break;
     }
   } else {
-    LogMan::Throw::A(false, "Unhandled Op->Class %d", Op->Class);
+    LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class);
   }
 }
 
 DEF_OP(StoreRegister) {
   auto Op = IROp->C<IR::IROp_StoreRegister>();
-  uint8_t OpSize = IROp->Size;
-
 
   if (Op->Class == IR::GPRClass) {
     auto regId = Op->Offset / 8 - 1;
     auto regOffs = Op->Offset & 7;
 
-    LogMan::Throw::A(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRA64.size(), "out of range regId");
 
     auto reg = SRA64[regId];
-    
+
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), regOffs * 8, 8);
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 16);
         break;
-        
+
       case 4:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 32);
         break;
 
       case 8:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Op->Value.ID()).GetCode() != reg.GetCode())
           mov(reg, GetReg<RA_64>(Op->Value.ID()));
         break;
     }
   } else if (Op->Class == IR::FPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.xmm[0][0])) / 16;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0])) / 16;
     auto regOffs = Op->Offset & 15;
 
-    LogMan::Throw::A(regId < SRAFPR.size(), "regId out of range");
+    LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "regId out of range");
 
     auto guest = SRAFPR[regId];
     auto host = GetSrc(Op->Value.ID());
@@ -229,35 +233,35 @@ DEF_OP(StoreRegister) {
         break;
 
       case 2:
-        LogMan::Throw::A((regOffs & 1) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 1) == 0, "unexpected regOffs");
         ins(guest.V8H(), regOffs/2, host.V8H(), 0);
         break;
 
       case 4:
-        LogMan::Throw::A((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs");
         ins(guest.V4S(), regOffs/4, host.V4S(), 0);
         break;
 
       case 8:
-        LogMan::Throw::A((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs");
         ins(guest.V2D(), regOffs / 8, host.V2D(), 0);
         break;
 
       case 16:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (guest.GetCode() != host.GetCode())
           mov(guest.Q(), host.Q());
         break;
     }
   } else {
-    LogMan::Throw::A(false, "Unhandled Op->Class %d", Op->Class);
+    LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class);
   }
 }
 
 
 DEF_OP(LoadContextIndexed) {
   auto Op = IROp->C<IR::IROp_LoadContextIndexed>();
-  size_t size = Op->Size;
+  size_t size = IROp->Size;
   auto index = GetReg<RA_64>(Op->Header.Args[0].ID());
 
   if (Op->Class == FEXCore::IR::GPRClass) {
@@ -284,15 +288,17 @@ DEF_OP(LoadContextIndexed) {
         ldr(GetReg<RA_64>(Node), MemOperand(TMP1, Op->BaseOffset));
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", IROp->Size);
+        break;
       }
       break;
     }
     case 16:
-      LogMan::Msg::A("Invalid Class load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid Class load of size 16");
       break;
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
   else {
@@ -329,19 +335,21 @@ DEF_OP(LoadContextIndexed) {
         }
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", IROp->Size);
+        break;
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
 
 DEF_OP(StoreContextIndexed) {
   auto Op = IROp->C<IR::IROp_StoreContextIndexed>();
-  size_t size = Op->Size;
+  size_t size = IROp->Size;
   auto index = GetReg<RA_64>(Op->Header.Args[1].ID());
 
   if (Op->Class == FEXCore::IR::GPRClass) {
@@ -370,15 +378,17 @@ DEF_OP(StoreContextIndexed) {
         str(value, MemOperand(TMP1, Op->BaseOffset));
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", IROp->Size);
+        break;
       }
       break;
     }
     case 16:
-      LogMan::Msg::A("Invalid Class load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid Class store of size 16");
       break;
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
   else {
@@ -417,12 +427,14 @@ DEF_OP(StoreContextIndexed) {
         }
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", IROp->Size);
+        break;
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -430,7 +442,7 @@ DEF_OP(StoreContextIndexed) {
 DEF_OP(SpillRegister) {
   auto Op = IROp->C<IR::IROp_SpillRegister>();
   uint8_t OpSize = IROp->Size;
-  uint32_t SlotOffset = Op->Slot * 16 + 16;
+  uint32_t SlotOffset = Op->Slot * 16;
 
   if (Op->Class == FEXCore::IR::GPRClass) {
     switch (OpSize) {
@@ -450,7 +462,7 @@ DEF_OP(SpillRegister) {
       str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -466,17 +478,17 @@ DEF_OP(SpillRegister) {
       str(GetSrc(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled SpillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled SpillRegister class: {}", Op->Class.Val);
   }
 }
 
 DEF_OP(FillRegister) {
   auto Op = IROp->C<IR::IROp_FillRegister>();
   uint8_t OpSize = IROp->Size;
-  uint32_t SlotOffset = Op->Slot * 16 + 16;
+  uint32_t SlotOffset = Op->Slot * 16;
 
   if (Op->Class == FEXCore::IR::GPRClass) {
     switch (OpSize) {
@@ -496,7 +508,7 @@ DEF_OP(FillRegister) {
       ldr(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -512,10 +524,10 @@ DEF_OP(FillRegister) {
       ldr(GetDst(Node), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled FillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled FillRegister class: {}", Op->Class.Val);
   }
 }
 
@@ -530,12 +542,12 @@ DEF_OP(StoreFlag) {
   strb(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag));
 }
 
-MemOperand JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) {
+MemOperand Arm64JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) {
   if (Offset.IsInvalid()) {
     return MemOperand(Base);
   } else {
     if (OffsetScale != 1 && OffsetScale != AccessSize) {
-        LogMan::Msg::A("Unhandled GenerateMemOperand OffsetScale: %d", OffsetScale);
+        LOGMAN_MSG_A_FMT("Unhandled GenerateMemOperand OffsetScale: {}", OffsetScale);
     }
     uint64_t Const;
     if (IsInlineConstant(Offset, &Const)) {
@@ -547,21 +559,23 @@ MemOperand JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Bas
         case IR::MEM_OFFSET_UXTW.Val: return MemOperand(Base, RegOffset.W(), Extend::UXTW, (int)std::log2(OffsetScale) );
         case IR::MEM_OFFSET_SXTW.Val: return MemOperand(Base, RegOffset.W(), Extend::SXTW, (int)std::log2(OffsetScale) );
 
-        default: LogMan::Msg::A("Unhandled GenerateMemOperand OffsetType: %d", OffsetType.Val); break;
+        default: LOGMAN_MSG_A_FMT("Unhandled GenerateMemOperand OffsetType: {}", OffsetType.Val); break;
       }
     }
   }
+
+  FEX_UNREACHABLE;
 }
 
 DEF_OP(LoadMem) {
   auto Op = IROp->C<IR::IROp_LoadMem>();
 
   auto MemReg = GetReg<RA_64>(Op->Header.Args[0].ID());
-  auto MemSrc = GenerateMemOperand(Op->Size, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+  auto MemSrc = GenerateMemOperand(IROp->Size, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
 
   if (Op->Class == FEXCore::IR::GPRClass) {
     auto Dst = GetReg<RA_64>(Node);
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1:
         ldrb(Dst, MemSrc);
         break;
@@ -574,12 +588,12 @@ DEF_OP(LoadMem) {
       case 8:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", IROp->Size);
     }
   }
   else {
     auto Dst = GetDst(Node);
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1:
         ldr(Dst.B(), MemSrc);
         break;
@@ -595,7 +609,7 @@ DEF_OP(LoadMem) {
       case 16:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", IROp->Size);
     }
   }
 }
@@ -606,11 +620,11 @@ DEF_OP(LoadMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LogMan::Msg::A("LoadMemTSO: No offset allowed");
+    LOGMAN_MSG_A_FMT("LoadMemTSO: No offset allowed");
   }
 
-  if (SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
-    if (Op->Size == 1) {
+  if (CTX->HostFeatures.SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
+    if (IROp->Size == 1) {
       // 8bit load is always aligned to natural alignment
       auto Dst = GetReg<RA_64>(Node);
       ldaprb(Dst, MemSrc);
@@ -619,7 +633,7 @@ DEF_OP(LoadMemTSO) {
       // Aligned
       auto Dst = GetReg<RA_64>(Node);
       nop();
-      switch (Op->Size) {
+      switch (IROp->Size) {
         case 2:
           ldaprh(Dst, MemSrc);
           break;
@@ -629,13 +643,13 @@ DEF_OP(LoadMemTSO) {
         case 8:
           ldapr(Dst, MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", IROp->Size);
       }
       nop();
     }
   }
   else if (Op->Class == FEXCore::IR::GPRClass) {
-    if (Op->Size == 1) {
+    if (IROp->Size == 1) {
       // 8bit load is always aligned to natural alignment
       auto Dst = GetReg<RA_64>(Node);
       ldarb(Dst, MemSrc);
@@ -644,7 +658,7 @@ DEF_OP(LoadMemTSO) {
       // Aligned
       auto Dst = GetReg<RA_64>(Node);
       nop();
-      switch (Op->Size) {
+      switch (IROp->Size) {
         case 2:
           ldarh(Dst, MemSrc);
           break;
@@ -654,7 +668,7 @@ DEF_OP(LoadMemTSO) {
         case 8:
           ldar(Dst, MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", IROp->Size);
       }
       nop();
     }
@@ -662,7 +676,7 @@ DEF_OP(LoadMemTSO) {
   else {
     dmb(InnerShareable, BarrierAll);
     auto Dst = GetDst(Node);
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 2:
         ldr(Dst.H(), MemSrc);
         break;
@@ -675,7 +689,7 @@ DEF_OP(LoadMemTSO) {
       case 16:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", IROp->Size);
     }
     dmb(InnerShareable, BarrierAll);
   }
@@ -686,10 +700,10 @@ DEF_OP(StoreMem) {
 
   auto MemReg = GetReg<RA_64>(Op->Header.Args[0].ID());
 
-  auto MemSrc = GenerateMemOperand(Op->Size, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+  auto MemSrc = GenerateMemOperand(IROp->Size, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
 
   if (Op->Class == FEXCore::IR::GPRClass) {
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1:
         strb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
         break;
@@ -702,12 +716,12 @@ DEF_OP(StoreMem) {
       case 8:
         str(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", IROp->Size);
     }
   }
   else {
     auto Src = GetSrc(Op->Header.Args[1].ID());
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1:
         str(Src.B(), MemSrc);
         break;
@@ -723,7 +737,7 @@ DEF_OP(StoreMem) {
       case 16:
         str(Src, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", IROp->Size);
     }
   }
 }
@@ -733,17 +747,17 @@ DEF_OP(StoreMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LogMan::Msg::A("StoreMemTSO: No offset allowed");
+    LOGMAN_MSG_A_FMT("StoreMemTSO: No offset allowed");
   }
 
   if (Op->Class == FEXCore::IR::GPRClass) {
-    if (Op->Size == 1) {
+    if (IROp->Size == 1) {
       // 8bit load is always aligned to natural alignment
       stlrb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
     }
     else {
       nop();
-      switch (Op->Size) {
+      switch (IROp->Size) {
         case 2:
           stlrh(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
           break;
@@ -753,7 +767,7 @@ DEF_OP(StoreMemTSO) {
         case 8:
           stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", IROp->Size);
       }
       nop();
     }
@@ -761,7 +775,7 @@ DEF_OP(StoreMemTSO) {
   else {
     dmb(InnerShareable, BarrierAll);
     auto Src = GetSrc(Op->Header.Args[1].ID());
-    switch (Op->Size) {
+    switch (IROp->Size) {
       case 1:
         str(Src.B(), MemSrc);
         break;
@@ -777,23 +791,186 @@ DEF_OP(StoreMemTSO) {
       case 16:
         str(Src, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", IROp->Size);
     }
     dmb(InnerShareable, BarrierAll);
   }
 }
 
+DEF_OP(ParanoidLoadMemTSO) {
+  auto Op = IROp->C<IR::IROp_LoadMemTSO>();
+
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+
+  if (!Op->Offset.IsInvalid()) {
+    LOGMAN_MSG_A_FMT("ParanoidLoadMemTSO: No offset allowed");
+  }
+
+  if (Op->Class == FEXCore::IR::GPRClass) {
+    if (IROp->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      auto Dst = GetReg<RA_64>(Node);
+      ldarb(Dst, MemSrc);
+    }
+    else {
+      auto Dst = GetReg<RA_64>(Node);
+      switch (IROp->Size) {
+        case 2:
+          ldarh(Dst, MemSrc);
+          break;
+        case 4:
+          ldar(Dst.W(), MemSrc);
+          break;
+        case 8:
+          ldar(Dst, MemSrc);
+          break;
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", IROp->Size);
+      }
+    }
+  }
+  else {
+    auto Dst = GetDst(Node);
+    switch (IROp->Size) {
+      case 2:
+        ldarh(TMP1.W(), MemSrc);
+        fmov(Dst.H(), TMP1.W());
+        break;
+      case 4:
+        ldar(TMP1.W(), MemSrc);
+        fmov(Dst.S(), TMP1.W());
+        break;
+      case 8:
+        ldar(TMP1, MemSrc);
+        fmov(Dst.D(), TMP1);
+        break;
+      case 16:
+        nop();
+        ldaxp(TMP1, TMP2, MemSrc);
+        clrex();
+        mov(Dst.V2D(), 0, TMP1);
+        mov(Dst.V2D(), 1, TMP2);
+        break;
+      default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", IROp->Size);
+    }
+  }
+}
+
+DEF_OP(ParanoidStoreMemTSO) {
+  auto Op = IROp->C<IR::IROp_StoreMemTSO>();
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+
+  if (!Op->Offset.IsInvalid()) {
+    LOGMAN_MSG_A_FMT("ParanoidStoreMemTSO: No offset allowed");
+  }
+
+  if (Op->Class == FEXCore::IR::GPRClass) {
+    if (IROp->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      stlrb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+    }
+    else {
+      switch (IROp->Size) {
+        case 2:
+          stlrh(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        case 4:
+          stlr(GetReg<RA_32>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        case 8:
+          stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", IROp->Size);
+      }
+    }
+  }
+  else {
+    auto Src = GetSrc(Op->Header.Args[1].ID());
+    if (IROp->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      mov(TMP1.W(), Src.V16B(), 0);
+      stlrb(TMP1, MemSrc);
+    }
+    else {
+      switch (IROp->Size) {
+        case 2:
+          mov(TMP1.W(), Src.V8H(), 0);
+          stlrh(TMP1, MemSrc);
+          break;
+        case 4:
+          mov(TMP1.W(), Src.V4S(), 0);
+          stlr(TMP1.W(), MemSrc);
+          break;
+        case 8:
+          mov(TMP1, Src.V2D(), 0);
+          stlr(TMP1, MemSrc);
+          break;
+        case 16: {
+          // Move vector to GPRs
+          mov(TMP1, Src.V2D(), 0);
+          mov(TMP2, Src.V2D(), 1);
+          Label B;
+          bind(&B);
+
+          // ldaxp must not have both the destination registers be the same
+          ldaxp(xzr, TMP3, MemSrc); // <- Can hit SIGBUS. Overwritten with DMB
+          stlxp(TMP3, TMP1, TMP2, MemSrc); // <- Can also hit SIGBUS
+          cbnz(TMP3, &B); // < Overwritten with DMB
+          break;
+        }
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", IROp->Size);
+      }
+    }
+  }
+}
+
 DEF_OP(VLoadMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VStoreMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
+}
+
+DEF_OP(CacheLineClear) {
+  auto Op = IROp->C<IR::IROp_CacheLineClear>();
+
+  auto MemReg = GetReg<RA_64>(Op->Header.Args[0].ID());
+
+  // Clear dcache only
+  // icache doesn't matter here since the guest application shouldn't be calling clflush on JIT code.
+  mov(TMP1, MemReg);
+  for (size_t i = 0; i < std::max(1U, CTX->HostFeatures.DCacheLineSize / 64U); ++i) {
+    dc(DataCacheOp::CVAU, TMP1);
+    add(TMP1, TMP1, CTX->HostFeatures.DCacheLineSize);
+  }
+  dsb(InnerShareable, BarrierAll);
+}
+
+DEF_OP(CacheLineZero) {
+  auto Op = IROp->C<IR::IROp_CacheLineZero>();
+
+  auto MemReg = GetReg<RA_64>(Op->Header.Args[0].ID());
+
+  if (CTX->HostFeatures.SupportsCLZERO) {
+    // We can use this instruction directly
+    dc(DataCacheOp::ZVA, MemReg);
+  }
+  else {
+    // We must walk the cacheline ourselves
+    // Force cacheline alignment
+    and_(TMP1, MemReg, ~(CPUIDEmu::CACHELINE_SIZE - 1));
+    // This will end up being four STPs
+    // Depending on uarch it could be slightly more efficient in instructions emitted
+    // and uops to use vector pair STP, but we want the non-temporal bit specifically here
+    for (size_t i = 0; i < CPUIDEmu::CACHELINE_SIZE; i += 16) {
+      stnp(xzr, xzr, MemOperand(TMP1, i, Offset));
+    }
+  }
 }
 
 #undef DEF_OP
-void JITCore::RegisterMemoryHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMemoryHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(LOADCONTEXT,         LoadContext);
   REGISTER_OP(STORECONTEXT,        StoreContext);
   REGISTER_OP(LOADREGISTER,        LoadRegister);
@@ -806,10 +983,18 @@ void JITCore::RegisterMemoryHandlers() {
   REGISTER_OP(STOREFLAG,           StoreFlag);
   REGISTER_OP(LOADMEM,             LoadMem);
   REGISTER_OP(STOREMEM,            StoreMem);
-  REGISTER_OP(LOADMEMTSO,          LoadMemTSO);
-  REGISTER_OP(STOREMEMTSO,         StoreMemTSO);
+  if (ParanoidTSO()) {
+    REGISTER_OP(LOADMEMTSO,          ParanoidLoadMemTSO);
+    REGISTER_OP(STOREMEMTSO,         ParanoidStoreMemTSO);
+  }
+  else {
+    REGISTER_OP(LOADMEMTSO,          LoadMemTSO);
+    REGISTER_OP(STOREMEMTSO,         StoreMemTSO);
+  }
   REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
   REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
+  REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
+  REGISTER_OP(CACHELINEZERO,       CacheLineZero);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp

@@ -1,10 +1,23 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
+static void PrintValue(uint64_t Value) {
+  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
+}
+
+static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
+  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
+}
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 
 DEF_OP(Fence) {
   auto Op = IROp->C<IR::IROp_Fence>();
@@ -18,41 +31,54 @@ DEF_OP(Fence) {
     case IR::Fence_Store.Val:
       dmb(FullSystem, BarrierWrites);
       break;
-    default: LogMan::Msg::A("Unknown Fence: %d", Op->Fence); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
   }
 }
 
 DEF_OP(Break) {
   auto Op = IROp->C<IR::IROp_Break>();
   switch (Op->Reason) {
-    case 0: // Hard fault
-    case 5: // Guest ud2
+    case FEXCore::IR::Break_Unimplemented: // Hard fault
+    case FEXCore::IR::Break_Interrupt: // Guest ud2
       hlt(4);
       break;
-    case 4: { // HLT
+    case FEXCore::IR::Break_Overflow: // overflow
+      ResetStack();
+      LoadConstant(TMP1, ThreadSharedData.Dispatcher->OverflowExceptionInstructionAddress);
+      br(TMP1);
+      break;
+    case FEXCore::IR::Break_Halt: { // HLT
       // Time to quit
       // Set our stack to the starting stack location
-      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)));
+      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)));
       add(sp, TMP1, 0);
 
       // Now we need to jump to the thread stop handler
-      LoadConstant(TMP1, ThreadStopHandlerAddressSpillSRA);
+      LoadConstant(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddressSpillSRA);
       br(TMP1);
       break;
     }
-    case 6: { // INT3
+    case FEXCore::IR::Break_Interrupt3: { // INT3
       ResetStack();
 
-      LoadConstant(TMP1, ThreadPauseHandlerAddressSpillSRA);
+      LoadConstant(TMP1, ThreadSharedData.Dispatcher->ThreadPauseHandlerAddressSpillSRA);
       br(TMP1);
       break;
     }
-    default: LogMan::Msg::A("Unknown Break reason: %d", Op->Reason);
+    case FEXCore::IR::Break_InvalidInstruction:
+    {
+      ResetStack();
+
+      LoadConstant(TMP1, ThreadSharedData.Dispatcher->UnimplementedInstructionAddress);
+      br(TMP1);
+
+      break;
+    }
+    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
   }
 }
 
 DEF_OP(GetRoundingMode) {
-  auto Op = IROp->C<IR::IROp_GetRoundingMode>();
   auto Dst = GetReg<RA_64>(Node);
   mrs(Dst, FPCR);
   lsr(Dst, Dst,  22);
@@ -110,9 +136,83 @@ DEF_OP(SetRoundingMode) {
   msr(FPCR, TMP1);
 }
 
+DEF_OP(Print) {
+  auto Op = IROp->C<IR::IROp_Print>();
+
+  PushDynamicRegsAndLR();
+
+  if (IsGPR(Op->Header.Args[0].ID())) {
+    mov(x0, GetReg<RA_64>(Op->Header.Args[0].ID()));
+    LoadConstant(x3, reinterpret_cast<uint64_t>(PrintValue));
+  }
+  else {
+    fmov(x0, GetSrc(Op->Header.Args[0].ID()).V1D());
+    // Bug in vixl that source vector needs to b V1D rather than V2D?
+    fmov(x1, GetSrc(Op->Header.Args[0].ID()).V1D(), 1);
+    LoadConstant(x3, reinterpret_cast<uint64_t>(PrintVectorValue));
+  }
+  SpillStaticRegs();
+  blr(x3);
+  FillStaticRegs();
+
+  PopDynamicRegsAndLR();
+}
+
+DEF_OP(ProcessorID) {
+  // We always need to spill x8 since we can't know if it is live at this SSA location
+  uint32_t SpillMask = 1U << 8;
+
+  // Ordering is incredibly important here
+  // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
+  // Only spill the registers that intersect with our usage
+  SpillStaticRegs(false, SpillMask);
+
+  // Now that we are spilled, store in the state that we are in a syscall
+  // Still without overwriting registers that matter
+  // 16bit LoadConstant to be a single instruction
+  // We must always spill at least one register (x8) so this value always has a bit set
+  // This gives the signal handler a value to check to see if we are in a syscall at all
+  LoadConstant(x0, SpillMask & 0xFFFF);
+  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+
+  // Allocate some temporary space for storing the uint32_t CPU and Node IDs
+  sub(sp, sp, 16);
+
+  // Load the getcpu syscall number
+  LoadConstant(x8, SYS_getcpu);
+
+  // CPU pointer in x0
+  add(x0, sp, 0);
+  // Node in x1
+  add(x1, sp, 4);
+
+  svc(0);
+  // On updated signal mask we can receive a signal RIGHT HERE
+
+  // Load the values returned by the kernel
+  ldp(w0, w1, MemOperand(sp));
+  // Deallocate stack space
+  sub(sp, sp, 16);
+
+  // Now that we are done in the syscall we need to carefully peel back the state
+  // First unspill the registers from before
+  FillStaticRegs(false, SpillMask);
+
+  // Now the registers we've spilled are back in their original host registers
+  // We can safely claim we are no longer in a syscall
+  str(xzr, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+
+
+  // Now store the result in the destination in the expected format
+  // uint32_t Res = (node << 12) | cpu;
+  // CPU is in w0
+  // Node is in w1
+  orr(GetReg<RA_64>(Node), x0, Operand(x1, LSL, 12));
+}
+
 #undef DEF_OP
-void JITCore::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMiscHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(DUMMY,      NoOp);
   REGISTER_OP(IRHEADER,   NoOp);
   REGISTER_OP(CODEBLOCK,  NoOp);
@@ -122,10 +222,11 @@ void JITCore::RegisterMiscHandlers() {
   REGISTER_OP(BREAK,      Break);
   REGISTER_OP(PHI,        NoOp);
   REGISTER_OP(PHIVALUE,   NoOp);
-  REGISTER_OP(PRINT,      Unhandled);
+  REGISTER_OP(PRINT,      Print);
   REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
   REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
   REGISTER_OP(INVALIDATEFLAGS,   NoOp);
+  REGISTER_OP(PROCESSORID,   ProcessorID);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(ExtractElementPair) {
   auto Op = IROp->C<IR::IROp_ExtractElementPair>();
   switch (Op->Header.Size) {
@@ -20,7 +26,7 @@ DEF_OP(ExtractElementPair) {
       mov (GetReg<RA_64>(Node), Regs[Op->Element]);
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 }
 
@@ -46,7 +52,7 @@ DEF_OP(CreateElementPair) {
       RegTmp = x0;
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 
   if (Dst.first.GetCode() != RegSecond.GetCode()) {
@@ -68,8 +74,8 @@ DEF_OP(Mov) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMoveHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
   REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
   REGISTER_OP(MOV,                Mov);

External/FEXCore/Source/Interface/Core/JIT/JITCore.h

@@ -1,5 +1,7 @@
 #pragma once
 
+#include <memory>
+
 namespace FEXCore::Context {
 struct Context;
 }
@@ -11,5 +13,11 @@ struct InternalThreadState;
 namespace FEXCore::CPU {
 class CPUBackend;
 
-FEXCore::CPU::CPUBackend *CreateJITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
-}
+[[nodiscard]] std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::Context *ctx,
+                                                           FEXCore::Core::InternalThreadState *Thread,
+                                                           bool CompileThread);
+
+[[nodiscard]] std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::Context *ctx,
+                                                             FEXCore::Core::InternalThreadState *Thread,
+                                                             bool CompileThread);
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp

@@ -1,8 +1,26 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
+
+#include <FEXCore/IR/IR.h>
+#include <FEXCore/Utils/LogManager.h>
+
+#include <array>
+#include <stdint.h>
+#include <utility>
+#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+
+#define GRS(Node) (IROp->Size <= 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))
+#define GRD(Node) (IROp->Size <= 4 ? GetDst<RA_32>(Node) : GetDst<RA_64>(Node))
+#define GRCMP(Node) (Op->CompareSize == 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))
+
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(TruncElementPair) {
   auto Op = IROp->C<IR::IROp_TruncElementPair>();
 
@@ -14,7 +32,7 @@ DEF_OP(TruncElementPair) {
       mov(Dst.second, Src.second);
       break;
     }
-    default: LogMan::Msg::A("Unhandled Truncation size: %d", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
   }
 }
 
@@ -26,8 +44,14 @@ DEF_OP(Constant) {
 DEF_OP(EntrypointOffset) {
   auto Op = IROp->C<IR::IROp_EntrypointOffset>();
 
-  auto Constant = IR->GetHeader()->Entry + Op->Offset;
-  mov(GetDst<RA_64>(Node), Constant);
+  auto Constant = Entry + Op->Offset;
+  uint64_t Mask = ~0ULL;
+  uint8_t OpSize = IROp->Size;
+  if (OpSize == 4) {
+    Mask = 0xFFFF'FFFFULL;
+  }
+
+  mov(GetDst<RA_64>(Node), Constant & Mask);
 }
 
 DEF_OP(InlineConstant) {
@@ -64,7 +88,7 @@ DEF_OP(Add) {
     case 8:
       add(rax, Const);
       break;
-    default:  LogMan::Msg::A("Unhandled Add size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Add size: {}", OpSize);
       break;
     }
   } else {
@@ -75,7 +99,7 @@ DEF_OP(Add) {
     case 8:
       add(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled Add size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Add size: {}", OpSize);
       break;
     }
   }
@@ -97,7 +121,7 @@ DEF_OP(Sub) {
     case 8:
       sub(rax, Const);
       break;
-    default:  LogMan::Msg::A("Unhandled Sub size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Sub size: {}", OpSize);
       break;
     }
   } else {
@@ -108,7 +132,7 @@ DEF_OP(Sub) {
     case 8:
       sub(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled Sub size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Sub size: {}", OpSize);
       break;
     }
   }
@@ -130,7 +154,7 @@ DEF_OP(Neg) {
     Src = GetSrc<RA_64>(Op->Header.Args[0].ID());
     Dst = GetDst<RA_64>(Node);
     break;
-  default:  LogMan::Msg::A("Unhandled Neg size: %d", OpSize);
+  default:  LOGMAN_MSG_A_FMT("Unhandled Neg size: {}", OpSize);
     break;
   }
   mov(Dst, Src);
@@ -154,7 +178,7 @@ DEF_OP(Mul) {
     imul(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(Dst, rax);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown Mul size: {}", OpSize);
   }
 }
 
@@ -173,7 +197,7 @@ DEF_OP(UMul) {
     mul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rax);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown UMul size: {}", OpSize);
   }
 }
 
@@ -212,7 +236,7 @@ DEF_OP(Div) {
     mov(GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV Size: %d", Size); break;
+  default: LOGMAN_MSG_A_FMT("Unknown DIV Size: {}", Size); break;
   }
 }
 
@@ -255,7 +279,7 @@ DEF_OP(UDiv) {
     mov(GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV OpSize: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown UDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -292,7 +316,7 @@ DEF_OP(Rem) {
     mov(GetDst<RA_64>(Node), rdx);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV Size: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown Rem Size: {}", OpSize); break;
   }
 }
 
@@ -335,7 +359,7 @@ DEF_OP(URem) {
     mov(GetDst<RA_64>(Node), rdx);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV OpSize: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown URem OpSize: {}", OpSize); break;
   }
 }
 
@@ -354,7 +378,7 @@ DEF_OP(MulH) {
     imul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rdx);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown MulH size: {}", OpSize);
   }
 }
 
@@ -373,7 +397,7 @@ DEF_OP(UMulH) {
     mul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rdx);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown UMulH size: {}", OpSize);
   }
 }
 
@@ -404,6 +428,25 @@ DEF_OP(And) {
   mov(Dst, rax);
 }
 
+DEF_OP(Andn) {
+  auto Op = IROp->C<IR::IROp_Andn>();
+  const auto& Lhs = Op->Header.Args[0];
+  const auto& Rhs = Op->Header.Args[1];
+  auto Dst = GRD(Node);
+
+  uint64_t Const{};
+  if (IsInlineConstant(Rhs, &Const)) {
+    mov(Dst, GRS(Lhs.ID()));
+    and_(Dst, ~Const);
+  } else {
+    const auto Temp = IROp->Size <= 4 ? Xbyak::Reg{rax.cvt32()} : Xbyak::Reg{rax};
+    mov(Temp, GRS(Rhs.ID()));
+    not_(Temp);
+    and_(Temp, GRS(Lhs.ID()));
+    mov(Dst, Temp);
+  }
+}
+
 DEF_OP(Xor) {
   auto Op = IROp->C<IR::IROp_Xor>();
   auto Dst = GetDst<RA_64>(Node);
@@ -435,7 +478,7 @@ DEF_OP(Lshl) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shl(GetDst<RA_64>(Node), Const);
         break;
-      default: LogMan::Msg::A("Unknown LSHL Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown LSHL Size: {}\n", OpSize); break;
     };
   } else {
     mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -450,7 +493,7 @@ DEF_OP(Lshl) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shl(GetDst<RA_64>(Node), cl);
         break;
-      default: LogMan::Msg::A("Unknown LSHL Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown LSHL Size: {}\n", OpSize); break;
     };
   }
 }
@@ -482,7 +525,7 @@ DEF_OP(Lshr) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shr(GetDst<RA_64>(Node), Const);
         break;
-      default: LogMan::Msg::A("Unknown Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Size: {}\n", OpSize); break;
     };
 
   } else {
@@ -506,7 +549,7 @@ DEF_OP(Lshr) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shr(GetDst<RA_64>(Node), cl);
         break;
-      default: LogMan::Msg::A("Unknown Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Size: {}\n", OpSize); break;
     };
   }
 }
@@ -540,7 +583,7 @@ DEF_OP(Ashr) {
       mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       sar(GetDst<RA_64>(Node), Const);
     break;
-    default: LogMan::Msg::A("Unknown ASHR Size: %d\n", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown ASHR Size: {}\n", OpSize); break;
     };
 
   } else {
@@ -565,7 +608,7 @@ DEF_OP(Ashr) {
       mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       sar(GetDst<RA_64>(Node), cl);
     break;
-    default: LogMan::Msg::A("Unknown ASHR Size: %d\n", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown ASHR Size: {}\n", OpSize); break;
     };
   }
 }
@@ -590,7 +633,7 @@ DEF_OP(Ror) {
         ror(rax, Const);
       break;
       }
-      default: LogMan::Msg::A("Unknown ROR Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown ROR Size: {}\n", OpSize); break;
     }
   } else {
     mov (rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -606,7 +649,7 @@ DEF_OP(Ror) {
         ror(rax, cl);
       break;
       }
-      default: LogMan::Msg::A("Unknown ROR Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown ROR Size: {}\n", OpSize); break;
     }
   }
   mov(GetDst<RA_64>(Node), rax);
@@ -634,6 +677,36 @@ DEF_OP(Extr) {
   }
 }
 
+DEF_OP(PDep) {
+  const auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  const auto Input = GRS(Op->Args(0).ID());
+  const auto Mask  = GRS(Op->Args(1).ID());
+  const auto Dest  = GRD(Node);
+
+  if (OpSize == 4) {
+    pdep(Dest.cvt32(), Input.cvt32(), Mask.cvt32());
+  } else {
+    pdep(Dest.cvt64(), Input.cvt64(), Mask.cvt64());
+  }
+}
+
+DEF_OP(PExt) {
+  const auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  const auto Input = GRS(Op->Args(0).ID());
+  const auto Mask  = GRS(Op->Args(1).ID());
+  const auto Dest  = GRD(Node);
+
+  if (OpSize == 4) {
+    pext(Dest.cvt32(), Input.cvt32(), Mask.cvt32());
+  } else {
+    pext(Dest.cvt64(), Input.cvt64(), Mask.cvt64());
+  }
+}
+
 DEF_OP(LDiv) {
   auto Op = IROp->C<IR::IROp_LDiv>();
   uint8_t OpSize = IROp->Size;
@@ -662,7 +735,7 @@ DEF_OP(LDiv) {
       mov(GetDst<RA_64>(Node), rax);
       break;
     }
-    default: LogMan::Msg::A("Unknown LDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -694,7 +767,7 @@ DEF_OP(LUDiv) {
       mov(GetDst<RA_64>(Node), rax);
       break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -726,7 +799,7 @@ DEF_OP(LRem) {
       mov(GetDst<RA_64>(Node), rdx);
       break;
     }
-    default: LogMan::Msg::A("Unknown LREM OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LREM OpSize: {}", OpSize); break;
   }
 }
 
@@ -758,7 +831,7 @@ DEF_OP(LURem) {
       mov(GetDst<RA_64>(Node), rdx);
       break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUREM OpSize: {}", OpSize); break;
   }
 }
 
@@ -823,7 +896,7 @@ DEF_OP(FindMSB) {
     case 8:
       bsr(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown OpSize: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown FindMSB OpSize: {}", OpSize);
   }
 }
 
@@ -847,7 +920,7 @@ DEF_OP(FindTrailingZeros) {
       mov(rax, 0x40);
       cmovz(GetDst<RA_64>(Node), rax);
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindTrailingZeros size: {}", OpSize); break;
   }
 }
 
@@ -870,7 +943,7 @@ DEF_OP(CountLeadingZeroes) {
         lzcnt(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         break;
       }
-      default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeros size: {}", OpSize); break;
     }
   }
   else {
@@ -909,7 +982,7 @@ DEF_OP(CountLeadingZeroes) {
         mov(GetDst<RA_64>(Node), rax);
         break;
       }
-      default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeros size: {}", OpSize); break;
     }
   }
 }
@@ -931,7 +1004,7 @@ DEF_OP(Rev) {
       mov (GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       bswap(GetDst<RA_64>(Node).cvt64());
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REV size: {}", OpSize); break;
   }
 }
 
@@ -964,9 +1037,7 @@ DEF_OP(Bfi) {
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
-  uint8_t OpSize = IROp->Size;
-
-  LogMan::Throw::A(OpSize <= 8, "OpSize is too large for BFE: %d", OpSize);
+  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
 
   auto Dst = GetDst<RA_64>(Node);
 
@@ -1037,10 +1108,6 @@ DEF_OP(Sbfe) {
   }
 }
 
-#define GRS(Node) (IROp->Size <= 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))
-#define GRD(Node) (IROp->Size <= 4 ? GetDst<RA_32>(Node) : GetDst<RA_64>(Node))
-#define GRCMP(Node) (Op->CompareSize == 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))
-
 DEF_OP(Select) {
   auto Op = IROp->C<IR::IROp_Select>();
   auto Dst = GRD(Node);
@@ -1067,7 +1134,7 @@ DEF_OP(Select) {
 
   if (is_const_true || is_const_false) {
     if (is_const_false != true || is_const_true != true || const_true != 1 || const_false != 0) {
-      LogMan::Msg::A("Select: Unsupported compare inline parameters");
+      LOGMAN_MSG_A_FMT("Select: Unsupported compare inline parameters");
     }
     (this->*SetCC)(al);
     movzx(Dst, al);
@@ -1098,46 +1165,67 @@ DEF_OP(VExtractToGPR) {
       pextrq(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Idx);
     break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
-DEF_OP(Float_ToGPR_ZU) {
-  LogMan::Msg::D("Unimplemented");
-}
-
 DEF_OP(Float_ToGPR_ZS) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_ZS>();
-  if (Op->Header.ElementSize == 8) {
-    cvttsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-  else {
-    cvttss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-}
 
-DEF_OP(Float_ToGPR_U) {
-  LogMan::Msg::D("Unimplemented");
+  uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
+  switch (Conv) {
+    case 0x0804: // int64_t <- float
+      cvttss2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0808: // int64_t <- double
+      cvttsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0404: // int32_t <- float
+      cvttss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0408: // int32_t <- double
+      cvttsd2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+  }
 }
 
 DEF_OP(Float_ToGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_S>();
-  if (Op->Header.ElementSize == 8) {
-    cvtsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-  else {
-    cvtss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+  uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
+  switch (Conv) {
+    case 0x0804: // int64_t <- float
+      cvtss2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0808: // int64_t <- double
+      cvtsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0404: // int32_t <- float
+      cvtss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0408: // int32_t <- double
+      cvtsd2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
   }
 }
 
 DEF_OP(FCmp) {
   auto Op = IROp->C<IR::IROp_FCmp>();
 
-  if (Op->ElementSize == 4) {
-    ucomiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+  if (Op->Flags & (1 << IR::FCMP_FLAG_UNORDERED)) {
+    if (Op->ElementSize == 4) {
+      ucomiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
+    else {
+      ucomisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
   }
   else {
-    ucomisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    if (Op->ElementSize == 4) {
+      comiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
+    else {
+      comisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
   }
   mov (rdx, 0);
 
@@ -1168,8 +1256,8 @@ DEF_OP(FCmp) {
 
 #undef DEF_OP
 
-void JITCore::RegisterALUHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterALUHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(TRUNCELEMENTPAIR,  TruncElementPair);
   REGISTER_OP(CONSTANT,          Constant);
   REGISTER_OP(ENTRYPOINTOFFSET,  EntrypointOffset);
@@ -1189,12 +1277,15 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(UMULH,             UMulH);
   REGISTER_OP(OR,                Or);
   REGISTER_OP(AND,               And);
+  REGISTER_OP(ANDN,              Andn);
   REGISTER_OP(XOR,               Xor);
   REGISTER_OP(LSHL,              Lshl);
   REGISTER_OP(LSHR,              Lshr);
   REGISTER_OP(ASHR,              Ashr);
   REGISTER_OP(ROR,               Ror);
   REGISTER_OP(EXTR,              Extr);
+  REGISTER_OP(PDEP,              PDep);
+  REGISTER_OP(PEXT,              PExt);
   REGISTER_OP(LDIV,              LDiv);
   REGISTER_OP(LUDIV,             LUDiv);
   REGISTER_OP(LREM,              LRem);
@@ -1211,9 +1302,7 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(SBFE,              Sbfe);
   REGISTER_OP(SELECT,            Select);
   REGISTER_OP(VEXTRACTTOGPR,     VExtractToGPR);
-  REGISTER_OP(FLOAT_TOGPR_ZU,    Float_ToGPR_ZU);
   REGISTER_OP(FLOAT_TOGPR_ZS,    Float_ToGPR_ZS);
-  REGISTER_OP(FLOAT_TOGPR_U,     Float_ToGPR_U);
   REGISTER_OP(FLOAT_TOGPR_S,     Float_ToGPR_S);
   REGISTER_OP(FCMP,              FCmp);
 #undef REGISTER_OP

External/FEXCore/Source/Interface/Core/JIT/x86_64/AtomicOps.cpp

@@ -1,8 +1,21 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
+
+#include <FEXCore/IR/IR.h>
+#include <FEXCore/Utils/LogManager.h>
+
+#include <array>
+#include <stdint.h>
+#include <utility>
+#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(CASPair) {
   auto Op = IROp->C<IR::IROp_CAS>();
   uint8_t OpSize = IROp->Size;
@@ -49,7 +62,7 @@ DEF_OP(CASPair) {
       mov(Dst.second, rdx);
     break;
     }
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
   }
 }
 
@@ -68,7 +81,6 @@ DEF_OP(CAS) {
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[2].ID());
 
-  mov(rdx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
   mov(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
 
   // RCX now contains pointer
@@ -76,31 +88,31 @@ DEF_OP(CAS) {
   // RDX contains our desired
 
   lock();
-
   switch (OpSize) {
   case 1: {
-    cmpxchg(byte [MemReg], dl);
-    movzx(rax, al);
+    cmpxchg(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+    movzx(GetDst<RA_64>(Node), al);
   break;
   }
   case 2: {
-    cmpxchg(word [MemReg], dx);
-    movzx(rax, ax);
+    cmpxchg(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+    movzx(GetDst<RA_64>(Node), ax);
   break;
   }
   case 4: {
-    cmpxchg(dword [MemReg], edx);
+    cmpxchg(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+    // RAX now contains the result
+    mov (GetDst<RA_64>(Node), eax);
   break;
   }
   case 8: {
-    cmpxchg(qword [MemReg], rdx);
+    cmpxchg(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    // RAX now contains the result
+    mov (GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unsupported: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
   }
-
-  // RAX now contains the result
-  mov (GetDst<RA_64>(Node), rax);
 }
 
 DEF_OP(AtomicAdd) {
@@ -109,7 +121,7 @@ DEF_OP(AtomicAdd) {
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
 
   lock();
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1:
       add(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
       break;
@@ -122,7 +134,7 @@ DEF_OP(AtomicAdd) {
     case 8:
       add(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
   }
 }
 
@@ -131,7 +143,7 @@ DEF_OP(AtomicSub) {
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
   lock();
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1:
       sub(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
       break;
@@ -144,7 +156,7 @@ DEF_OP(AtomicSub) {
     case 8:
       sub(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
   }
 }
 
@@ -153,7 +165,7 @@ DEF_OP(AtomicAnd) {
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
   lock();
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1:
       and_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
       break;
@@ -166,7 +178,7 @@ DEF_OP(AtomicAnd) {
     case 8:
       and_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
   }
 }
 
@@ -175,7 +187,7 @@ DEF_OP(AtomicOr) {
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
   lock();
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1:
       or_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
       break;
@@ -188,7 +200,7 @@ DEF_OP(AtomicOr) {
     case 8:
       or_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
   }
 }
 
@@ -197,7 +209,7 @@ DEF_OP(AtomicXor) {
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
   lock();
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1:
       xor_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
       break;
@@ -210,7 +222,7 @@ DEF_OP(AtomicXor) {
     case 8:
       xor_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
   }
 }
 
@@ -220,19 +232,19 @@ DEF_OP(AtomicSwap) {
   Xbyak::Reg MemReg = rax;
   mov(MemReg, GetSrc<RA_64>(Op->Header.Args[0].ID()));
 
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1:
-      mov(GetDst<RA_8>(Node), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      movzx(GetDst<RA_64>(Node), GetSrc<RA_8>(Op->Header.Args[1].ID()));
       lock();
       xchg(byte [MemReg], GetDst<RA_8>(Node));
       break;
     case 2:
-      mov(GetDst<RA_16>(Node), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      movzx(GetDst<RA_64>(Node), GetSrc<RA_16>(Op->Header.Args[1].ID()));
       lock();
       xchg(word [MemReg], GetDst<RA_16>(Node));
       break;
     case 4:
-      mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      mov(GetDst<RA_64>(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()));
       lock();
       xchg(dword [MemReg], GetDst<RA_32>(Node));
       break;
@@ -241,7 +253,7 @@ DEF_OP(AtomicSwap) {
       lock();
       xchg(qword [MemReg], GetDst<RA_64>(Node));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicSwap size: {}", IROp->Size);
   }
 }
 
@@ -249,15 +261,15 @@ DEF_OP(AtomicFetchAdd) {
   auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1:
-      mov(cl, GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      movzx(rcx, GetSrc<RA_8>(Op->Header.Args[1].ID()));
       lock();
       xadd(byte [MemReg], cl);
       movzx(GetDst<RA_32>(Node), cl);
       break;
     case 2:
-      mov(cx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      movzx(rcx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
       lock();
       xadd(word [MemReg], cx);
       movzx(GetDst<RA_32>(Node), cx);
@@ -266,7 +278,7 @@ DEF_OP(AtomicFetchAdd) {
       mov(ecx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
       lock();
       xadd(dword [MemReg], ecx);
-      mov(GetDst<RA_32>(Node), ecx);
+      mov(GetDst<RA_64>(Node), ecx);
       break;
     case 8:
       mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -274,7 +286,7 @@ DEF_OP(AtomicFetchAdd) {
       xadd(qword [MemReg], rcx);
       mov(GetDst<RA_64>(Node), rcx);
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchAdd size: {}", IROp->Size);
   }
 }
 
@@ -282,7 +294,7 @@ DEF_OP(AtomicFetchSub) {
   auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1:
       mov(cl, GetSrc<RA_8>(Op->Header.Args[1].ID()));
       neg(cl);
@@ -311,7 +323,7 @@ DEF_OP(AtomicFetchSub) {
       xadd(qword [MemReg], rcx);
       mov(GetDst<RA_64>(Node), rcx);
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchSub size: {}", IROp->Size);
   }
 }
 
@@ -321,7 +333,7 @@ DEF_OP(AtomicFetchAnd) {
   // TMP1 = rax
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
 
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1: {
       mov(TMP1.cvt8(), byte [MemReg]);
 
@@ -389,7 +401,7 @@ DEF_OP(AtomicFetchAnd) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchAnd size: {}", IROp->Size);
   }
 }
 
@@ -398,7 +410,7 @@ DEF_OP(AtomicFetchOr) {
 
   // TMP1 = rax
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1: {
       mov(TMP1.cvt8(), byte [MemReg]);
 
@@ -466,7 +478,7 @@ DEF_OP(AtomicFetchOr) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchOr size: {}", IROp->Size);
   }
 }
 
@@ -475,7 +487,7 @@ DEF_OP(AtomicFetchXor) {
 
   // TMP1 = rax
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
-  switch (Op->Size) {
+  switch (IROp->Size) {
     case 1: {
       mov(TMP1.cvt8(), byte [MemReg]);
 
@@ -543,13 +555,89 @@ DEF_OP(AtomicFetchXor) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchXor size: {}", IROp->Size);
+  }
+}
+
+DEF_OP(AtomicFetchNeg) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
+
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  switch (IROp->Size) {
+    case 1: {
+      mov(TMP1.cvt8(), byte [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt8(), TMP1.cvt8());
+      mov(TMP3.cvt8(), TMP1.cvt8());
+      neg(TMP2.cvt8());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
+      jne(Loop);
+      // Result is the previous value from memory, which is currently in TMP3
+      movzx(GetDst<RA_64>(Node), TMP3.cvt8());
+      break;
+    }
+    case 2: {
+      mov(TMP1.cvt16(), word [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt16(), TMP1.cvt16());
+      mov(TMP3.cvt16(), TMP1.cvt16());
+      neg(TMP2.cvt16());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      movzx(GetDst<RA_64>(Node), TMP3.cvt16());
+      break;
+    }
+    case 4: {
+      mov(TMP1.cvt32(), dword [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt32(), TMP1.cvt32());
+      mov(TMP3.cvt32(), TMP1.cvt32());
+      neg(TMP2.cvt32());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      mov(GetDst<RA_32>(Node), TMP3.cvt32());
+      break;
+    }
+    case 8: {
+      mov(TMP1.cvt64(), qword [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt64(), TMP1.cvt64());
+      mov(TMP3.cvt64(), TMP1.cvt64());
+      neg(TMP2.cvt64());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      mov(GetDst<RA_64>(Node), TMP3.cvt64());
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchNeg size: {}", IROp->Size);
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterAtomicHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(CASPAIR,        CASPair);
   REGISTER_OP(CAS,            CAS);
   REGISTER_OP(ATOMICADD,      AtomicAdd);
@@ -563,6 +651,7 @@ void JITCore::RegisterAtomicHandlers() {
   REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
   REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
   REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
+  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp

@@ -1,22 +1,44 @@
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
 
+#include "Interface/Context/Context.h"
+#include "Interface/Core/CPUID.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/LookupCache.h"
+#include "Interface/Core/JIT/x86_64/JITClass.h"
+#include "Interface/HLE/Thunks/Thunks.h"
+
+#include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>
+#include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/HLE/SyscallHandler.h>
-#include <Interface/HLE/Thunks/Thunks.h>
+#include <FEXCore/IR/IR.h>
+#include <FEXCore/Utils/LogManager.h>
+
+#include <array>
+#include <memory>
+#include <stddef.h>
+#include <stdint.h>
+#include <unordered_map>
+#include <utility>
+#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(GuestCallDirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestCallIndirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestReturn) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(SignalReturn) {
@@ -40,7 +62,7 @@ DEF_OP(CallbackReturn) {
   sub(dword [rax], 1);
 
   // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  add(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])], 8);
+  add(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])], 8);
 
   // Now jump back to the thunk
   // XXX: XMM?
@@ -75,12 +97,12 @@ DEF_OP(ExitFunction) {
     jmp(qword[rax]);
 
     L(l_BranchHost);
-    dq(ExitFunctionLinkerAddress);
+    dq(ThreadSharedData.Dispatcher->ExitFunctionLinkerAddress);
     L(l_BranchGuest);
     dq(NewRIP);
   } else {
     Xbyak::Reg RipReg = GetSrc<RA_64>(Op->NewRIP.ID());
-    
+
     // L1 Cache
     mov(rcx, ThreadState->LookupCache->GetL1Pointer());
     mov(rax, RipReg);
@@ -89,14 +111,14 @@ DEF_OP(ExitFunction) {
     shl(rax, 4);
 
     Xbyak::RegExp LookupBase = rcx + rax;
-  
+
     cmp(qword[LookupBase + 8], RipReg);
     jne(FullLookup);
     jmp(qword[LookupBase + 0]);
 
     L(FullLookup);
-    mov(rax, AbsoluteLoopTopAddress);
-    mov(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.rip)], RipReg);
+    mov(rax, ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress);
+    mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.rip)], RipReg);
     jmp(rax);
   }
 
@@ -106,18 +128,10 @@ DEF_OP(ExitFunction) {
 }
 
 DEF_OP(Jump) {
-  auto Op = IROp->C<IR::IROp_Jump>();
+  const auto Op = IROp->C<IR::IROp_Jump>();
+  const auto ArgID = Op->Args(0).ID();
 
-  Label *TargetLabel;
-  auto IsTarget = JumpTargets.find(Op->Header.Args[0].ID());
-  if (IsTarget == JumpTargets.end()) {
-    TargetLabel = &JumpTargets.try_emplace(Op->Header.Args[0].ID()).first->second;
-  }
-  else {
-    TargetLabel = &IsTarget->second;
-  }
-
-  PendingTargetLabel = TargetLabel;
+  PendingTargetLabel = &JumpTargets.try_emplace(ArgID).first->second;
 }
 
 #define GRCMP(Node) (Op->CompareSize == 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))
@@ -125,18 +139,7 @@ DEF_OP(Jump) {
 DEF_OP(CondJump) {
   auto Op = IROp->C<IR::IROp_CondJump>();
 
-  Label *TrueTargetLabel;
-  Label *FalseTargetLabel;
-
-  auto TrueIter = JumpTargets.find(Op->TrueBlock.ID());
-  auto FalseIter = JumpTargets.find(Op->FalseBlock.ID());
-
-  if (TrueIter == JumpTargets.end()) {
-    TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
-  }
-  else {
-    TrueTargetLabel = &TrueIter->second;
-  }
+  Label *TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
 
   if (IsGPR(Op->Cmp1.ID())) {
     uint64_t Const;
@@ -146,24 +149,18 @@ DEF_OP(CondJump) {
       cmp(GRCMP(Op->Cmp1.ID()), GRCMP(Op->Cmp2.ID()));
     }
   } else if (IsFPR(Op->Cmp1.ID())) {
-    if (Op->CompareSize  == 4)
+    if (Op->CompareSize == 4) {
       ucomiss(GetSrc(Op->Cmp1.ID()), GetSrc(Op->Cmp2.ID()));
-    else
+    } else {
       ucomisd(GetSrc(Op->Cmp1.ID()), GetSrc(Op->Cmp2.ID()));
+    }
   }
 
   auto [_, __, JCC] = GetCC(Op->Cond);
 
   (this->*JCC)(*TrueTargetLabel, T_NEAR);
 
-  if (FalseIter == JumpTargets.end()) {
-    FalseTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
-  }
-  else {
-    FalseTargetLabel = &FalseIter->second;
-  }
-
-  PendingTargetLabel = FalseTargetLabel;
+  PendingTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
 }
 
 DEF_OP(Syscall) {
@@ -227,7 +224,7 @@ DEF_OP(Thunk) {
     sub(rsp, 8); // Align
 
   mov(rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
-  
+
   auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
 
   mov(rax, reinterpret_cast<uintptr_t>(thunkFn));
@@ -242,28 +239,28 @@ DEF_OP(Thunk) {
 
 DEF_OP(ValidateCode) {
   auto Op = IROp->C<IR::IROp_ValidateCode>();
-  uint8_t* OldCode = (uint8_t*)&Op->CodeOriginalLow;
+  const auto* OldCode = (const uint8_t*)&Op->CodeOriginalLow;
   int len = Op->CodeLength;
   int idx = 0;
 
   xor_(GetDst<RA_64>(Node), GetDst<RA_64>(Node));
-  mov(rax, IR->GetHeader()->Entry + Op->Offset);
+  mov(rax, Entry + Op->Offset);
   mov(rbx, 1);
   while (len >= 4) {
-    cmp(dword[rax + idx], *(uint32_t*)(OldCode + idx));
+    cmp(dword[rax + idx], *(const uint32_t*)(OldCode + idx));
     cmovne(GetDst<RA_64>(Node), rbx);
     len-=4;
     idx+=4;
   }
   while (len >= 2) {
-    mov(rcx, *(uint16_t*)(OldCode + idx));
+    mov(rcx, *(const uint16_t*)(OldCode + idx));
     cmp(word[rax + idx], cx);
     cmovne(GetDst<RA_64>(Node), rbx);
     len-=2;
     idx+=2;
   }
   while (len >= 1) {
-    cmp(byte[rax + idx], *(uint8_t*)(OldCode + idx));
+    cmp(byte[rax + idx], *(const uint8_t*)(OldCode + idx));
     cmovne(GetDst<RA_64>(Node), rbx);
     len-=1;
     idx+=1;
@@ -271,8 +268,6 @@ DEF_OP(ValidateCode) {
 }
 
 DEF_OP(RemoveCodeEntry) {
-  auto Op = IROp->C<IR::IROp_RemoveCodeEntry>();
-
   auto NumPush = RA64.size();
 
   for (auto &Reg : RA64)
@@ -282,11 +277,11 @@ DEF_OP(RemoveCodeEntry) {
     sub(rsp, 8); // Align
 
   mov(rdi, STATE);
-  mov(rax, IR->GetHeader()->Entry); // imm64 move
+  mov(rax, Entry); // imm64 move
   mov(rsi, rax);
 
 
-  mov(rax, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntry));
+  mov(rax, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
   call(rax);
 
   if (NumPush & 1)
@@ -299,7 +294,7 @@ DEF_OP(RemoveCodeEntry) {
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
 
-  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t Function);
+  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t Function, uint32_t Leaf);
   union {
     ClassPtrType ClassPtr;
     uint64_t Raw;
@@ -315,7 +310,9 @@ DEF_OP(CPUID) {
   //
   // Result: RAX, RDX. 4xi32
 
-  mov (rsi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  // rsi can be in the source registers, so copy argument to edx first
+  mov (edx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
+  mov (esi, GetSrc<RA_32>(Op->Header.Args[0].ID()));
   mov (rdi, reinterpret_cast<uint64_t>(&CTX->CPUID));
 
   auto NumPush = RA64.size();
@@ -341,8 +338,8 @@ DEF_OP(CPUID) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterBranchHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
   REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
   REGISTER_OP(GUESTRETURN,       GuestReturn);

External/FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp

@@ -1,9 +1,21 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
+
+#include <FEXCore/IR/IR.h>
+#include <FEXCore/Utils/LogManager.h>
+
+#include <array>
+#include <stdint.h>
+#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(VInsGPR) {
   auto Op = IROp->C<IR::IROp_VInsGPR>();
   movapd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
@@ -25,7 +37,7 @@ DEF_OP(VInsGPR) {
       pinsrq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[1].ID()), Op->Index);
       break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -46,14 +58,10 @@ DEF_OP(VCastFromGPR) {
     case 8:
       vmovq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()).cvt64());
       break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown VCastFromGPR element size: {}", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Float_FromGPR_U) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
   uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
@@ -89,14 +97,10 @@ DEF_OP(Float_FToF) {
       cvtsd2ss(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown FCVT sizes: 0x%x", Conv);
+    default: LOGMAN_MSG_A_FMT("Unknown Float_FToF sizes: 0x{:x}", Conv);
   }
 }
 
-DEF_OP(Vector_UToF) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_SToF) {
   auto Op = IROp->C<IR::IROp_Vector_SToF>();
   switch (Op->Header.ElementSize) {
@@ -115,14 +119,10 @@ DEF_OP(Vector_SToF) {
       cvtsi2sd(xmm15, rax);
       movlhps(GetDst(Node), xmm15);
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Vector_FToZU) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_FToZS) {
   auto Op = IROp->C<IR::IROp_Vector_FToZS>();
   switch (Op->Header.ElementSize) {
@@ -132,14 +132,10 @@ DEF_OP(Vector_FToZS) {
     case 8:
       cvttpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Vector_FToU) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_FToS) {
   auto Op = IROp->C<IR::IROp_Vector_FToS>();
   switch (Op->Header.ElementSize) {
@@ -149,7 +145,7 @@ DEF_OP(Vector_FToS) {
     case 8:
       cvtpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -166,25 +162,54 @@ DEF_OP(Vector_FToF) {
       cvtpd2ps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown Conversion Type : 0%04x", Conv); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF conversion type : 0x{:04x}", Conv); break;
+  }
+}
+
+DEF_OP(Vector_FToI) {
+  auto Op = IROp->C<IR::IROp_Vector_FToI>();
+  uint8_t RoundMode{};
+
+  switch (Op->Round) {
+    case FEXCore::IR::Round_Nearest.Val:
+      RoundMode = 0b0000'0'0'00;
+    break;
+    case FEXCore::IR::Round_Negative_Infinity.Val:
+      RoundMode = 0b0000'0'0'01;
+    break;
+    case FEXCore::IR::Round_Positive_Infinity.Val:
+      RoundMode = 0b0000'0'0'10;
+    break;
+    case FEXCore::IR::Round_Towards_Zero.Val:
+      RoundMode = 0b0000'0'0'11;
+    break;
+    case FEXCore::IR::Round_Host.Val:
+      RoundMode = 0b0000'0'1'00;
+    break;
+  }
+
+  switch (Op->Header.ElementSize) {
+    case 4:
+      roundps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), RoundMode);
+    break;
+    case 8:
+      roundpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), RoundMode);
+    break;
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterConversionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(VINSGPR,         VInsGPR);
   REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_U, Float_FromGPR_U);
   REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
   REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_UTOF,     Vector_UToF);
   REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZU,    Vector_FToZU);
   REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOU,     Vector_FToU);
   REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
   REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
+  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/EncryptionOps.cpp

@@ -1,8 +1,19 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
+
+#include <FEXCore/IR/IR.h>
+
+#include <array>
+#include <stdint.h>
+#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -34,16 +45,46 @@ DEF_OP(AESKeyGenAssist) {
   vaeskeygenassist(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), Op->RCON);
 }
 
+DEF_OP(CRC32) {
+  auto Op = IROp->C<IR::IROp_CRC32>();
+  switch (IROp->Size) {
+  case 4:
+    mov(TMP1, GetSrc<RA_32>(Op->Header.Args[1].ID()));
+    mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Header.Args[0].ID()));
+  break;
+  case 8:
+    mov(TMP1, GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  break;
+  default: LOGMAN_MSG_A_FMT("Unknown CRC32 size: {}", IROp->Size);
+  }
+
+  switch (Op->SrcSize) {
+    case 1:
+      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt8());
+      break;
+    case 2:
+      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt16());
+      break;
+    case 4:
+      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt32());
+      break;
+    case 8:
+      crc32(GetDst<RA_64>(Node).cvt64(), TMP1.cvt64());
+      break;
+  }
+}
+
 #undef DEF_OP
-void JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterEncryptionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(VAESIMC,     AESImc);
   REGISTER_OP(VAESENC,     AESEnc);
   REGISTER_OP(VAESENCLAST, AESEncLast);
   REGISTER_OP(VAESDEC,     AESDec);
   REGISTER_OP(VAESDECLAST, AESDecLast);
   REGISTER_OP(VAESKEYGENASSIST, AESKeyGenAssist);
-
+  REGISTER_OP(CRC32,             CRC32);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/FlagOps.cpp

@@ -1,9 +1,20 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
+
+#include <FEXCore/IR/IR.h>
+
+#include <array>
+#include <stdint.h>
+#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
 
@@ -14,8 +25,8 @@ DEF_OP(GetHostFlag) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterFlagHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(GETHOSTFLAG, GetHostFlag);
 #undef REGISTER_OP
 }