Docs: Update for release FEX-2306

FEXConfig: Removes Emulated CPU cores option

.github/workflows/ccpp.yml

@@ -14,6 +14,7 @@ env:
   CC: clang
   CXX: clang++
   FEX_FORCE32BITALLOCATOR: 1
+  FEX_ENABLEAVX: 1
 
 jobs:
   build:
@@ -24,7 +25,7 @@ jobs:
       fail-fast: false
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Set runner label
       run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
@@ -72,6 +73,11 @@ jobs:
       # Execute the build.  You can specify a specific target with "--target <NAME>"
       run: cmake --build . --config $BUILD_TYPE
 
+    - name: Install
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target install
+
     - name: ASM Tests
       working-directory: ${{runner.workspace}}/build
       shell: bash
@@ -166,6 +172,17 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_APITests.log || true
 
+    - name: ARMEmitter tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target emitter_tests
+
+    - name: ARMEmitter Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ARMEmitterTests.log || true
+
     - name: FEXLinuxTests
       working-directory: ${{runner.workspace}}/build
       shell: bash
@@ -188,12 +205,6 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ThunkgenTests.log || true
 
-    - name: Install
-      if: matrix.arch[1] == 'x64'
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      run: cmake --build . --config $BUILD_TYPE --target install
-
     - name: Test GL No-Thunks
       if: matrix.arch[1] == 'x64'
       working-directory: ${{runner.workspace}}/build
@@ -230,13 +241,19 @@ jobs:
       # ASM tests get quite close to 10MB
       run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
 
+    - name: Remove old SHM regions
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: cmake --build . --config $BUILD_TYPE --target remove_old_shm_regions
+
     - name: Set runner name
       if: ${{ always() }}
       run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
 
     - name: Upload results
       if: ${{ always() }}
-      uses: 'actions/upload-artifact@v2'
+      uses: 'actions/upload-artifact@v3'
       with:
         name: Results-${{ env.runner_name }}
         path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log

.github/workflows/glibc_fault.yml

@@ -0,0 +1,196 @@
+name: GLIBC fault test
+# This workflow file is the same as the `Build + Test` with some key differences
+# - Runs on any x86 and ARM64 runner
+# - Disables the glibc jemalloc compile option
+# - Enables the glibc allocator fault option
+# - Disables gvisor tests to reduce stress on CI machines (tmp/shm tests overwhelm them)
+# - Disables thunk tests since they are incompatible with glibc fault allocator
+# - Disables ARMEmitter tests (We don't want to fault test vixl's disassembler)
+
+on:
+  push:
+    branches:
+      - main
+  pull_request:
+    branches:
+      - main
+
+env:
+  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
+  BUILD_TYPE: Release
+  CC: clang
+  CXX: clang++
+  FEX_FORCE32BITALLOCATOR: 1
+  FEX_ENABLEAVX: 1
+
+jobs:
+  build:
+    runs-on: ${{ matrix.arch }}
+    strategy:
+      matrix:
+        # Run on an x86 device and any ARM runner.
+        arch: [[self-hosted, x64], [self-hosted, ARM64]]
+      fail-fast: false
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
+    - name: Set rootfs paths
+      run: |
+        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+
+    - name: Update RootFS cache
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
+
+    - name : submodule checkout
+      # Need to update submodules
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
+
+    - name: Clean Build Environment
+      run: rm -Rf ${{runner.workspace}}/build
+
+    - name: Create Build Environment
+      # Some projects don't allow in-source building, so create a separate build directory
+      # We'll use this as our working directory for all subsequent commands
+      run: cmake -E make_directory ${{runner.workspace}}/build
+
+    - name: Configure CMake
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Note the current convention is to use the -S and -B options here to specify source
+      # and build directories, but this is only available with CMake 3.13 and higher.
+      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True -DBUILD_FEX_LINUX_TESTS=True -DENABLE_GLIBC_ALLOCATOR_HOOK_FAULT=True -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+
+    - name: Build
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the build.  You can specify a specific target with "--target <NAME>"
+      run: cmake --build . --config $BUILD_TYPE
+
+    - name: Install
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target install
+
+    - name: ASM Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+
+    - name: IR Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target ir_tests
+
+    - name: IR Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
+
+    - name: Posix Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the posixtest
+      run: cmake --build . --config $BUILD_TYPE --target posix_tests
+
+    - name: Posix Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_Posix.log || true
+
+    - name: gcc target tests 64
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_64
+
+    - name: GCC64 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC64.log || true
+
+    - name: gcc target tests 32
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_32
+
+    - name: GCC32 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC32.log || true
+
+    - name: APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target api_tests
+
+    - name: APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_APITests.log || true
+
+    - name: FEXLinuxTests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target fex_linux_tests_all
+
+    - name: FEXLinuxTests Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXLinuxTests.log || true
+
+    - name: Truncate test results
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Cap out the log files at 20M in case something crash spins and dumps fault text
+      # ASM tests get quite close to 10MB
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+
+    - name: Remove old SHM regions
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: cmake --build . --config $BUILD_TYPE --target remove_old_shm_regions
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+

.github/workflows/vixl_simulator.yml

@@ -13,6 +13,7 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
+  FEX_ENABLEAVX: 1
 
 jobs:
   build:
@@ -24,7 +25,7 @@ jobs:
       fail-fast: false
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Set runner label
       run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
@@ -110,7 +111,7 @@ jobs:
 
     - name: Upload results
       if: ${{ always() }}
-      uses: 'actions/upload-artifact@v2'
+      uses: 'actions/upload-artifact@v3'
       with:
         name: Results-${{ env.runner_name }}
         path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log

.gitmodules

@@ -3,7 +3,7 @@
 	path = External/vixl
 	url = https://github.com/FEX-Emu/vixl.git
 [submodule "External/cpp-optparse"]
-	path = External/cpp-optparse
+	path = Source/Common/cpp-optparse
 	url = https://github.com/Sonicadvance1/cpp-optparse
 [submodule "External/imgui"]
 	path = External/imgui
@@ -48,8 +48,11 @@
 [submodule "External/robin-map"]
 	shallow = true
 	path = External/robin-map
-	url = https://github.com/Tessil/robin-map.git
+	url = https://github.com/FEX-Emu/robin-map.git
 [submodule "External/Vulkan-Headers"]
 	shallow = true
 	path = External/Vulkan-Headers
 	url = https://github.com/KhronosGroup/Vulkan-Headers.git
+[submodule "External/jemalloc_glibc"]
+	path = External/jemalloc_glibc
+	url = https://github.com/FEX-Emu/jemalloc.git

CMakeLists.txt

@@ -7,7 +7,7 @@ CHECK_INCLUDE_FILES ("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
 option(BUILD_TESTS "Build unit tests to ensure sanity" TRUE)
 option(BUILD_FEX_LINUX_TESTS "Build FEXLinuxTests, requires x86 compiler" FALSE)
 option(BUILD_THUNKS "Build thunks" FALSE)
-option(BUILD_CLANG_THUNKS "Build thunks with clang" FALSE)
+option(ENABLE_CLANG_THUNKS "Build thunks with clang" FALSE)
 option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
 option(ENABLE_IWYU "Enables include what you use program" FALSE)
 option(ENABLE_LTO "Enable LTO with compilation" TRUE)
@@ -18,10 +18,10 @@ option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
 option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
 option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_GDB_SYMBOLS "Enables GDBSymbols integration support" ${HAVE_GDB_JIT_READER_H})
-option(ENABLE_VISUAL_DEBUGGER "Enables the visual debugger for compiling" FALSE)
 option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
 option(ENABLE_WERROR "Enables -Werror" FALSE)
 option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
+option(ENABLE_JEMALLOC_GLIBC_ALLOC "Enables jemalloc glibc allocator" TRUE)
 option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
 option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
 option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
@@ -29,13 +29,23 @@ option(ENABLE_INTERPRETER "Enables FEX's Interpreter" FALSE)
 option(ENABLE_CCACHE "Enables ccache for compile caching" TRUE)
 option(ENABLE_TERMUX_BUILD "Forces building for Termux on a non-Termux build machine" FALSE)
 option(ENABLE_VIXL_SIMULATOR "Forces the FEX JIT to use the VIXL simulator" FALSE)
+option(ENABLE_VIXL_DISASSEMBLER "Enables debug disassembler output with VIXL" FALSE)
+option(COMPILE_VIXL_DISASSEMBLER "Compiles the vixl disassembler in to vixl" FALSE)
 option(ENABLE_FEXCORE_PROFILER "Enables use of the FEXCore timeline profiling capabilities" FALSE)
 set (FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend you want to use for the FEXCore profiler")
+option(ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT "Enables glibc memory allocation hooking with fault for CI testing")
 
 set (X86_32_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_32.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting i686")
 set (X86_64_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_64.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting x86_64")
 set (DATA_DIRECTORY "${CMAKE_INSTALL_PREFIX}/share/fex-emu" CACHE PATH "global data directory")
 
+string(FIND ${CMAKE_BASE_NAME} mingw CONTAINS_MINGW)
+if (NOT CONTAINS_MINGW EQUAL -1)
+  message (STATUS "Mingw build")
+  set (MINGW_BUILD TRUE)
+  set (ENABLE_JEMALLOC FALSE)
+endif()
+
 if (ENABLE_FEXCORE_PROFILER)
   add_definitions(-DENABLE_FEXCORE_PROFILER=1)
   string(TOUPPER "${FEXCORE_PROFILER_BACKEND}" FEXCORE_PROFILER_BACKEND)
@@ -47,6 +57,14 @@ if (ENABLE_FEXCORE_PROFILER)
   endif()
 endif()
 
+if (ENABLE_JEMALLOC_GLIBC_ALLOC AND ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  message(FATAL_ERROR "Can't have both glibc fault allocator and jemalloc glibc allocator enabled at the same time")
+endif()
+
+if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  add_definitions(-DGLIBC_ALLOCATOR_FAULT=1)
+endif()
+
 # uninstall target
 if(NOT TARGET uninstall)
   configure_file(
@@ -176,7 +194,22 @@ if (ENABLE_TSAN)
   link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
 endif()
 
+if (ENABLE_JEMALLOC_GLIBC_ALLOC)
+  # The glibc jemalloc subproject which hooks the glibc allocator.
+  # Required for thunks to work.
+  # All host native libraries will use this allocator, while *most* other FEX internal allocations will use the other jemalloc allocator.
+  add_definitions(-DENABLE_JEMALLOC_GLIBC=1)
+  add_subdirectory(External/jemalloc_glibc/)
+else()
+  message (STATUS
+    " jemalloc glibc allocator disabled!\n"
+    " This is not a recommended configuration!\n"
+    " This will very explicitly break thunk execution!\n"
+    " Use at your own risk!")
+endif()
+
 if (ENABLE_JEMALLOC)
+  # The jemalloc subproject that all FEXCore fextl objects allocate through.
   add_definitions(-DENABLE_JEMALLOC=1)
   add_subdirectory(External/jemalloc/)
   include_directories(External/jemalloc/pregen/include/)
@@ -196,6 +229,11 @@ set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-poin
 
 include_directories(External/robin-map/include/)
 
+if (BUILD_TESTS)
+  # Enable vixl disassembler if tests are enabled.
+  set(COMPILE_VIXL_DISASSEMBLER TRUE)
+endif()
+
 add_subdirectory(External/vixl/)
 include_directories(External/vixl/src/)
 
@@ -223,9 +261,6 @@ if (BUILD_TESTS)
   include(Catch)
 endif()
 
-add_subdirectory(External/cpp-optparse/)
-include_directories(External/cpp-optparse/)
-
 add_subdirectory(External/fmt/)
 
 add_subdirectory(External/imgui/)

Data/AppConfig/VC_redist.x64.exe.json

@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "x86dec_SynchronizeRIPOnAllBlocks": "1"
-  }
-}

Data/AppConfig/VC_redist.x86.exe.json

@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "x86dec_SynchronizeRIPOnAllBlocks": "1"
-  }
-}

Data/AppConfig/client.json

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "HideHypervisorBit": "1"
+  }
+}

Data/AppConfig/vcredist_x64.exe.json

@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "x86dec_SynchronizeRIPOnAllBlocks": "1"
-  }
-}

Data/AppConfig/vcredist_x86.exe.json

@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "x86dec_SynchronizeRIPOnAllBlocks": "1"
-  }
-}

Data/ThunksDB.json

@@ -6,10 +6,10 @@
         "X11"
       ],
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGL.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGL.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGL.so.1.2.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGL.so.1.7.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGL.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGL.so.1",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGL.so.1.2.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGL.so.1.7.0"
       ]
     },
     "GLESv2": {
@@ -18,17 +18,17 @@
         "X11"
       ],
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGLESv2.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGLESv2.so.2",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGLESv2.so.2.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGLESv2.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGLESv2.so.2",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGLESv2.so.2.0.0"
       ]
     },
     "X11": {
       "Library": "libX11-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libX11.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libX11.so.6",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libX11.so.6.4.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libX11.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libX11.so.6",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libX11.so.6.4.0"
       ]
     },
     "Vulkan": {
@@ -37,8 +37,8 @@
         "xcb"
       ],
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libvulkan.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libvulkan.so.1",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libvulkan.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libvulkan.so.1",
         "@HOME@/.local/share/Steam/ubuntu12_32/steam-runtime/pinned_libs_64/libvulkan.so.1"
       ],
       "Comment": [
@@ -48,129 +48,137 @@
     "xcb": {
       "Library": "libxcb-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb.so.1.1.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb.so.1",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb.so.1.1.0"
       ]
     },
     "xcb-dri2": {
-      "Library": "libxcb_dri2-guest.so",
+      "Library": "libxcb-dri2-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri2.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri2.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri2.so.0.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri2.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri2.so.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri2.so.0.0.0"
       ]
     },
     "xcb-dri3": {
-      "Library": "libxcb_dri3-guest.so",
+      "Library": "libxcb-dri3-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri3.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri3.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri3.so.0.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri3.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri3.so.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri3.so.0.0.0"
       ]
     },
     "xcb-xfixes": {
-      "Library": "libxcb_xfixes-guest.so",
+      "Library": "libxcb-xfixes-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-xfixes.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-xfixes.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-xfixes.so.0.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-xfixes.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-xfixes.so.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-xfixes.so.0.0.0"
       ]
     },
     "xcb-shm": {
-      "Library": "libxcb_shm-guest.so",
+      "Library": "libxcb-shm-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-shm.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-shm.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-shm.so.0.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-shm.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-shm.so.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-shm.so.0.0.0"
       ]
     },
     "xcb-sync": {
-      "Library": "libxcb_sync-guest.so",
+      "Library": "libxcb-sync-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-sync.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-sync.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-sync.so.1.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-sync.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-sync.so.1",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-sync.so.1.0.0"
       ]
     },
     "xcb-randr": {
-      "Library": "libxcb_randr-guest.so",
+      "Library": "libxcb-randr-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-randr.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-randr.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-randr.so.0.1.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-randr.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-randr.so.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-randr.so.0.1.0"
       ]
     },
     "xcb-present": {
-      "Library": "libxcb_present-guest.so",
+      "Library": "libxcb-present-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-present.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-present.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-present.so.0.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-present.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-present.so.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-present.so.0.0.0"
       ]
     },
     "xcb-glx": {
-      "Library": "libxcb_glx-guest.so",
+      "Library": "libxcb-glx-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-glx.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-glx.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-glx.so.0.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-glx.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-glx.so.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-glx.so.0.0.0"
       ]
     },
     "xshmfence": {
-      "Library": "libshmfence-guest.so",
+      "Library": "libxshmfence-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxshmfence.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxshmfence.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxshmfence.so.1.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxshmfence.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxshmfence.so.1",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxshmfence.so.1.0.0"
       ]
     },
     "drm": {
       "Library": "libdrm-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libdrm.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libdrm.so.2",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libdrm.so.2.4.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libdrm.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libdrm.so.2",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libdrm.so.2.4.0"
       ]
     },
     "asound": {
       "Library": "libasound-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libasound.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libasound.so.2",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libasound.so.2.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libasound.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libasound.so.2",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libasound.so.2.0.0"
       ]
     },
     "Xrender": {
       "Library": "libXrender-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXrender.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXrender.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXrender.so.1.3.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXrender.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXrender.so.1",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXrender.so.1.3.0"
       ]
     },
     "Xext": {
       "Library": "libXext-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXext.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXext.so.6",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXext.so.6.4.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXext.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXext.so.6",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXext.so.6.4.0"
       ]
     },
     "Xfixes": {
       "Library": "libXfixes-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXfixes.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXfixes.so.3",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXfixes.so.3.1.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXfixes.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXfixes.so.3",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXfixes.so.3.1.0"
       ]
     },
     "OpenCL": {
       "Library" : "libOpenCL-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libOpenCL.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libOpenCL.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libOpenCL.so.1.0.0"
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libOpenCL.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libOpenCL.so.1",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libOpenCL.so.1.0.0"
+      ]
+    },
+    "WaylandClient": {
+      "Library" : "libwayland-client-guest.so",
+      "Overlay": [
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libwayland-client.so",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libwayland-client.so.0",
+        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libwayland-client.so.0.20.0"
       ]
     },
     "":{}

External/FEXCore/CMakeLists.txt

@@ -77,8 +77,13 @@ configure_file(
 
 include_directories(${CMAKE_BINARY_DIR}/generated)
 
+add_compile_options(-fno-exceptions)
 add_subdirectory(Source/)
 
 install (DIRECTORY include/FEXCore ${CMAKE_BINARY_DIR}/include/FEXCore
   DESTINATION include
   COMPONENT Development)
+
+if (BUILD_TESTS)
+  add_subdirectory(unittests/)
+endif()

External/FEXCore/Scripts/config_generator.py

@@ -22,10 +22,10 @@ def print_header():
 #define OPT_UINT64(group, enum, json, default) OPT_BASE(uint64_t, group, enum, json, default)
 #endif
 #ifndef OPT_STR
-#define OPT_STR(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#define OPT_STR(group, enum, json, default) OPT_BASE(fextl::string, group, enum, json, default)
 #endif
 #ifndef OPT_STRARRAY
-#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(fextl::string, group, enum, json, default)
 #endif
 
 '''
@@ -371,13 +371,16 @@ def print_parse_argloader_options(options):
 
             value_type = op_vals["Type"]
             NeedsString = False
-            conversion_func = "std::to_string"
+            conversion_func = "fextl::fmt::format(\"{}\", "
             if ("ArgumentHandler" in op_vals):
                 NeedsString = True
-                conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
+                conversion_func = "FEXCore::Config::Handler::{0}(".format(op_vals["ArgumentHandler"])
             if (value_type == "str"):
                 NeedsString = True
-                conversion_func = ""
+                conversion_func = "("
+            if (value_type == "bool"):
+                # boolean values need a decimal specifier. Otherwise fmt prints strings.
+                conversion_func = "fextl::fmt::format(\"{:d}\", "
 
             if (value_type == "strarray"):
                 # these need a bit more help
@@ -387,11 +390,11 @@ def print_parse_argloader_options(options):
                 output_argloader.write("\t}\n")
             else:
                 if (NeedsString):
-                    output_argloader.write("\tstd::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                    output_argloader.write("\tfextl::string UserValue = Options[\"{0}\"];\n".format(op_key))
                 else:
                     output_argloader.write("\t{0} UserValue = Options.get(\"{1}\");\n".format(value_type, op_key))
 
-                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}(UserValue));\n".format(op_key.upper(), conversion_func))
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}UserValue));\n".format(op_key.upper(), conversion_func))
             output_argloader.write("}\n")
 
     output_argloader.write("#endif\n")

External/FEXCore/Scripts/json_ir_generator.py

@@ -281,9 +281,7 @@ def print_ir_structs(defines):
     output_file.write("\tvoid* Data[0];\n")
     output_file.write("\tIROps Op;\n\n")
     output_file.write("\tuint8_t Size;\n")
-    output_file.write("\tuint8_t NumArgs;\n")
-    output_file.write("\tuint8_t ElementSize : 7;\n")
-    output_file.write("\tbool HasDest : 1;\n")
+    output_file.write("\tuint8_t ElementSize;\n")
 
     output_file.write("\ttemplate<typename T>\n")
     output_file.write("\tT const* C() const { return reinterpret_cast<T const*>(Data); }\n")
@@ -358,8 +356,10 @@ def print_ir_sizes():
 
     output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] std::string_view const& GetName(IROps Op);\n")
     output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetArgs(IROps Op);\n")
+    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetRAArgs(IROps Op);\n")
     output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
     output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool HasSideEffects(IROps Op);\n")
+    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool GetHasDest(IROps Op);\n")
 
     output_file.write("#undef IROP_SIZES\n")
     output_file.write("#endif\n\n")
@@ -417,7 +417,7 @@ def print_ir_getname():
 def print_ir_getraargs():
     output_file.write("#ifdef IROP_GETRAARGS_IMPL\n")
 
-    output_file.write("constexpr std::array<uint8_t, OP_LAST + 1> IRArgs = {\n")
+    output_file.write("constexpr std::array<uint8_t, OP_LAST + 1> IRRAArgs = {\n")
     for op in IROps:
         SSAArgs = op.SSAArgNum
 
@@ -430,6 +430,18 @@ def print_ir_getraargs():
 
     output_file.write("};\n\n")
 
+
+    output_file.write("constexpr std::array<uint8_t, OP_LAST + 1> IRArgs = {\n")
+    for op in IROps:
+        SSAArgs = op.SSAArgNum
+        output_file.write("\t{},\n".format(SSAArgs))
+
+    output_file.write("};\n\n")
+
+    output_file.write("uint8_t GetRAArgs(IROps Op) {\n")
+    output_file.write("  return IRRAArgs[Op];\n")
+    output_file.write("}\n")
+
     output_file.write("uint8_t GetArgs(IROps Op) {\n")
     output_file.write("  return IRArgs[Op];\n")
     output_file.write("}\n")
@@ -453,6 +465,25 @@ def print_ir_hassideeffects():
     output_file.write("#undef IROP_HASSIDEEFFECTS_IMPL\n")
     output_file.write("#endif\n\n")
 
+def print_ir_gethasdest():
+    output_file.write("#ifdef IROP_GETHASDEST_IMPL\n")
+
+    output_file.write("constexpr std::array<bool, OP_LAST + 1> IRDest = {\n")
+    for op in IROps:
+        if op.HasDest:
+            output_file.write("\ttrue,\n")
+        else:
+            output_file.write("\tfalse,\n")
+
+    output_file.write("};\n\n")
+
+    output_file.write("bool GetHasDest(IROps Op) {\n")
+    output_file.write("  return IRDest[Op];\n")
+    output_file.write("}\n")
+
+    output_file.write("#undef IROP_GETHASDEST_IMPL\n")
+    output_file.write("#endif\n\n")
+
 # Print out IR argument printing
 def print_ir_arg_printer():
     output_file.write("#ifdef IROP_ARGPRINTER_HELPER\n")
@@ -547,13 +578,13 @@ def print_ir_allocator_helpers():
 
     output_file.write("\tuint8_t GetOpElements(const OrderedNode *Op) const {\n")
     output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
-    output_file.write("\t\tLOGMAN_THROW_A_FMT(HeaderOp->HasDest, \"Op {} has no dest\\n\", GetName(HeaderOp->Op));\n")
+    output_file.write("\t\tLOGMAN_THROW_A_FMT(OpHasDest(Op), \"Op {} has no dest\\n\", GetName(HeaderOp->Op));\n")
     output_file.write("\t\treturn HeaderOp->Size / HeaderOp->ElementSize;\n")
     output_file.write("\t}\n\n")
 
     output_file.write("\tbool OpHasDest(const OrderedNode *Op) const {\n")
     output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
-    output_file.write("\t\treturn HeaderOp->HasDest;\n")
+    output_file.write("\t\treturn GetHasDest(HeaderOp->Op);\n")
     output_file.write("\t}\n\n")
 
     output_file.write("\tIROps GetOpType(const OrderedNode *Op) const {\n")
@@ -631,8 +662,6 @@ def print_ir_allocator_helpers():
 
                     output_file.write("\t\tOp.first->Header.Size = InferSize;\n")
 
-            output_file.write("\t\tOp.first->Header.NumArgs = {};\n".format(op.SSAArgNum))
-
             # Some ops without a destination still need an operating size
             # Effectively reusing the destination size value for operation size
             if op.DestSize != None:
@@ -643,9 +672,6 @@ def print_ir_allocator_helpers():
             else:
                 output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / ({});\n".format(op.NumElements))
 
-            if (op.HasDest):
-                output_file.write("\t\tOp.first->Header.HasDest = true;\n")
-
             # Insert validation here
             if op.EmitValidation != None:
                 output_file.write("\t\t#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED\n")
@@ -733,6 +759,7 @@ print_ir_reg_classes()
 print_ir_getname()
 print_ir_getraargs()
 print_ir_hassideeffects()
+print_ir_gethasdest()
 print_ir_arg_printer()
 print_ir_allocator_helpers()
 print_ir_parser_switch_helper()

External/FEXCore/Source/CMakeLists.txt

@@ -1,13 +1,19 @@
 set (MAN_DIR ${CMAKE_INSTALL_PREFIX}/share/man CACHE PATH "MAN_DIR")
 
 set (FEXCORE_BASE_SRCS
-  Common/Paths.cpp
   Interface/Config/Config.cpp
+  Utils/Allocator.cpp
+  Utils/CPUInfo.cpp
   Utils/FileLoading.cpp
   Utils/ForcedAssert.cpp
   Utils/LogManager.cpp
   )
 
+if (NOT MINGW_BUILD)
+  list(APPEND FEXCORE_BASE_SRCS
+    Utils/Allocator/64BitAllocator.cpp)
+endif()
+
 set (SRCS
   Common/JitSymbols.cpp
   Common/SoftFloat-3e/extF80_add.c
@@ -99,12 +105,11 @@ set (SRCS
   Interface/Core/X86Tables.cpp
   Interface/Core/X86DebugInfo.cpp
   Interface/Core/X86HelperGen.cpp
-  Interface/Core/ArchHelpers/Arm64_stubs.cpp
   Interface/Core/ArchHelpers/Arm64Emitter.cpp
   Interface/Core/Dispatcher/Dispatcher.cpp
   Interface/Core/Dispatcher/X86Dispatcher.cpp
   Interface/Core/Dispatcher/Arm64Dispatcher.cpp
-  Interface/Core/Interpreter/InterpreterFallbacks.cpp
+  Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp
   Interface/Core/X86Tables/BaseTables.cpp
   Interface/Core/X86Tables/DDDTables.cpp
   Interface/Core/X86Tables/EVEXTables.cpp
@@ -135,17 +140,25 @@ set (SRCS
   Interface/IR/Passes/PhiValidation.cpp
   Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
   Interface/IR/Passes/DeadStoreElimination.cpp
-  Interface/IR/Passes/StaticRegisterAllocationPass.cpp
   Interface/IR/Passes/RegisterAllocationPass.cpp
   Interface/IR/Passes/SyscallOptimization.cpp
-  Utils/Allocator.cpp
-  Utils/Allocator/64BitAllocator.cpp
   Utils/NetStream.cpp
   Utils/Telemetry.cpp
   Utils/Threads.cpp
   Utils/Profiler.cpp
   )
 
+if (_M_ARM_64)
+  list(APPEND SRCS Utils/ArchHelpers/Arm64.cpp)
+else()
+  list(APPEND SRCS Utils/ArchHelpers/Arm64_stubs.cpp)
+endif()
+
+if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  list(APPEND FEXCORE_BASE_SRCS
+    Utils/AllocatorOverride.cpp)
+endif()
+
 if (ENABLE_INTERPRETER)
   list(APPEND SRCS
     Interface/Core/Interpreter/InterpreterCore.cpp
@@ -163,11 +176,6 @@ if (ENABLE_INTERPRETER)
     Interface/Core/Interpreter/VectorOps.cpp)
 endif()
 
-if(_M_ARM_64)
-  list(APPEND SRCS
-    Interface/Core/ArchHelpers/Arm64.cpp)
-endif()
-
 set(DEFINES -DTHREAD_LOCAL=_Thread_local)
 
 if (_M_X86_64)
@@ -183,6 +191,10 @@ if (ENABLE_VIXL_SIMULATOR)
   list(APPEND DEFINES -DVIXL_SIMULATOR=1 -DVIXL_INCLUDE_SIMULATOR_AARCH64=1)
 endif()
 
+if (ENABLE_VIXL_DISASSEMBLER)
+  list(APPEND DEFINES -DVIXL_DISASSEMBLER=1)
+endif()
+
 if (ENABLE_JIT_X86_64)
   list(APPEND SRCS
     Interface/Core/JIT/x86_64/JIT.cpp
@@ -219,11 +231,22 @@ if (ENABLE_JIT_ARM64)
     )
 endif()
 
-set (LIBS fmt::fmt vixl dl xxhash tiny-json FEXHeaderUtils)
+set (LIBS fmt::fmt vixl xxhash tiny-json FEXHeaderUtils)
+
+if (NOT MINGW_BUILD)
+  list (APPEND LIBS dl)
+else()
+  list (APPEND LIBS synchronization)
+endif()
+
 if (ENABLE_JEMALLOC)
   list (APPEND LIBS FEX_jemalloc)
 endif()
 
+if (ENABLE_JEMALLOC_GLIBC_ALLOC)
+  list (APPEND LIBS FEX_jemalloc_glibc)
+endif()
+
 # Generate config
 configure_file(
   ${CMAKE_CURRENT_SOURCE_DIR}/Interface/Config/Config.json.in
@@ -328,7 +351,7 @@ function(AddDefaultOptionsToTarget Name)
   target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")
 
   target_compile_definitions(${Name} PRIVATE ${DEFINES})
-  add_dependencies(${Name} CONFIG_INC)
+  add_dependencies(${Name} CONFIG_INC IR_INC)
 
   target_compile_options(${Name}
     PRIVATE
@@ -370,7 +393,6 @@ AddDefaultOptionsToTarget(FEXCore_Base)
 
 function(AddObject Name Type)
   add_library(${Name} ${Type} ${SRCS})
-  add_dependencies(${Name} IR_INC)
 
   target_link_libraries(${Name} FEXCore_Base)
   AddDefaultOptionsToTarget(${Name})
@@ -382,6 +404,16 @@ function(AddLibrary Name Type)
   add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
   target_link_libraries(${Name} FEXCore_Base)
   set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+  if (MINGW_BUILD)
+    # Mingw build isn't building a linux shared library, so it can't have a SONAME.
+    set_target_properties(${Name} PROPERTIES NO_SONAME ON)
+    # Change the suffixes otherwise cmake continues using .a and .so
+    if (${Type} STREQUAL SHARED)
+      set_target_properties(${Name} PROPERTIES SUFFIX ".dll")
+    elseif(${Type} STREQUAL STATIC)
+      set_target_properties(${Name} PROPERTIES SUFFIX ".lib")
+    endif()
+  endif()
 
   AddDefaultOptionsToTarget(${Name})
 endfunction()
@@ -390,10 +422,12 @@ AddObject(${PROJECT_NAME}_object OBJECT)
 AddLibrary(${PROJECT_NAME} STATIC)
 AddLibrary(${PROJECT_NAME}_shared SHARED)
 
-install(TARGETS ${PROJECT_NAME} ${PROJECT_NAME}_shared
-  LIBRARY
-    DESTINATION lib
-    COMPONENT Libraries
-  ARCHIVE
-    DESTINATION lib
-    COMPONENT Libraries)
+if (NOT MINGW_BUILD)
+  install(TARGETS ${PROJECT_NAME} ${PROJECT_NAME}_shared
+    LIBRARY
+      DESTINATION lib
+      COMPONENT Libraries
+    ARCHIVE
+      DESTINATION lib
+      COMPONENT Libraries)
+endif()

External/FEXCore/Source/Common/JitSymbols.cpp

@@ -1,64 +1,85 @@
+#include <FEXCore/fextl/fmt.h>
+
 #include "Common/JitSymbols.h"
 
-#include <string>
+#include <fcntl.h>
 #include <unistd.h>
 
-#include <fmt/format.h>
-
 namespace FEXCore {
-  JITSymbols::JITSymbols() : fp{nullptr, std::fclose} {
+  JITSymbols::JITSymbols() {
   }
 
-  JITSymbols::~JITSymbols() = default;
-
-  void JITSymbols::InitFile() {
-    const auto PerfMap = fmt::format("/tmp/perf-{}.map", getpid());
-
-    fp.reset(fopen(PerfMap.c_str(), "wb"));
-    if (fp) {
-      // Disable buffering on this file
-      setvbuf(fp.get(), nullptr, _IONBF, 0);
+  JITSymbols::~JITSymbols() {
+    if (fd != -1) {
+      close(fd);
     }
   }
 
+  void JITSymbols::InitFile() {
+    // We can't use FILE here since we must be robust against forking processes closing our FD from under us.
+    const auto PerfMap = fextl::fmt::format("/tmp/perf-{}.map", getpid());
+
+    fd = open(PerfMap.c_str(), O_CREAT | O_TRUNC | O_WRONLY | O_APPEND, 0644);
+  }
+
   void JITSymbols::Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
-    if (!fp) return;
+    if (fd == -1) return;
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
+    const auto Buffer = fextl::fmt::format("{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
   }
 
   void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
-    if (!fp) return;
+    if (fd == -1) return;
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
+    const auto Buffer = fextl::fmt::format("{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
   }
 
   void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset) {
-    if (!fp) return;
+    if (fd == -1) return;
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
+    const auto Buffer = fextl::fmt::format("{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
   }
 
   void JITSymbols::RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
-    if (!fp) return;
+    if (fd == -1) return;
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} {}\n", HostAddr, CodeSize, Name);
+    const auto Buffer = fextl::fmt::format("{} {:x} {}\n", HostAddr, CodeSize, Name);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
   }
 
   void JITSymbols::RegisterJITSpace(const void *HostAddr, uint32_t CodeSize) {
-    if (!fp) return;
+    if (fd == -1) return;
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} FEXJIT\n", HostAddr, CodeSize);
+    const auto Buffer = fextl::fmt::format("{} {:x} FEXJIT\n", HostAddr, CodeSize);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
   }
 
 } // namespace FEXCore

External/FEXCore/Source/Common/JitSymbols.h

@@ -19,8 +19,6 @@ public:
   void RegisterJITSpace(const void *HostAddr, uint32_t CodeSize);
 
 private:
-  using FILEPtr = std::unique_ptr<FILE, decltype(&std::fclose)>;
-
-  FILEPtr fp;
+  int fd{-1};
 };
 }

External/FEXCore/Source/Common/Paths.cpp

@@ -1,91 +0,0 @@
-#include "Common/Paths.h"
-#include <FEXCore/Utils/LogManager.h>
-
-#include <cstdlib>
-#include <filesystem>
-#include <memory>
-#include <pwd.h>
-#include <system_error>
-#include <unistd.h>
-
-namespace FEXCore::Paths {
-  std::unique_ptr<std::string> CachePath;
-  std::unique_ptr<std::string> EntryCache;
-
-  char const* FindUserHomeThroughUID() {
-    auto passwd = getpwuid(geteuid());
-    if (passwd) {
-      return passwd->pw_dir;
-    }
-    return nullptr;
-  }
-
-  const char *GetHomeDirectory() {
-    char const *HomeDir = getenv("HOME");
-
-    // Try to get home directory from uid
-    if (!HomeDir) {
-      HomeDir = FindUserHomeThroughUID();
-    }
-
-    // try the PWD
-    if (!HomeDir) {
-      HomeDir = getenv("PWD");
-    }
-
-    // Still doesn't exit? You get local
-    if (!HomeDir) {
-      HomeDir = ".";
-    }
-
-    return HomeDir;
-  }
-
-  void InitializePaths() {
-    CachePath = std::make_unique<std::string>();
-    EntryCache = std::make_unique<std::string>();
-
-    char const *HomeDir = getenv("HOME");
-
-    if (!HomeDir) {
-      HomeDir = getenv("PWD");
-    }
-
-    if (!HomeDir) {
-      HomeDir = ".";
-    }
-
-    char *XDGDataDir = getenv("XDG_DATA_DIR");
-    if (XDGDataDir) {
-      *CachePath = XDGDataDir;
-    }
-    else {
-      if (HomeDir) {
-        *CachePath = HomeDir;
-      }
-    }
-
-    *CachePath += "/.fex-emu/";
-    *EntryCache = *CachePath + "/EntryCache/";
-
-    std::error_code ec{};
-    // Ensure the folder structure is created for our Data
-    if (!std::filesystem::exists(*EntryCache, ec) &&
-        !std::filesystem::create_directories(*EntryCache, ec)) {
-      LogMan::Msg::DFmt("Couldn't create EntryCache directory: '{}'", *EntryCache);
-    }
-  }
-
-  void ShutdownPaths() {
-    CachePath.reset();
-    EntryCache.reset();
-  }
-
-  std::string GetCachePath() {
-    return *CachePath;
-  }
-
-  std::string GetEntryCachePath() {
-    return *EntryCache;
-  }
-}

External/FEXCore/Source/Common/Paths.h

@@ -1,12 +0,0 @@
-#pragma once
-#include <string>
-
-namespace FEXCore::Paths {
-  void InitializePaths();
-  void ShutdownPaths();
-
-  const char *GetHomeDirectory();
-
-  std::string GetCachePath();
-  std::string GetEntryCachePath();
-}

External/FEXCore/Source/Common/SoftFloat.h

@@ -2,19 +2,19 @@
 
 #include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/sstream.h>
+#include <FEXCore/fextl/string.h>
 
 #include <cmath>
 #include <cstring>
 #include <stdint.h>
-#include <string>
-#include <sstream>
 
 extern "C" {
 #include "SoftFloat-3e/platform.h"
 #include "SoftFloat-3e/softfloat.h"
 }
 
-struct X80SoftFloat {
+struct FEX_PACKED X80SoftFloat {
 #ifdef _M_X86_64
 // Define this to push some operations to x87
 // Only useful to see if precision loss is killing something
@@ -32,22 +32,28 @@ struct X80SoftFloat {
 #else
 #error No 128bit float for this target!
 #endif
-  struct __attribute__((packed)) {
-    uint64_t Significand : 64;
-    uint16_t Exponent    : 15;
-    unsigned Sign        : 1;
-  };
+
+#ifndef _WIN32
+#define LIBRARY_PRECISION BIGFLOAT
+#else
+// Mingw Win32 libraries don't have `__float128` helpers. Needs to use a lower precision.
+#define LIBRARY_PRECISION double
+#endif
+
+  uint64_t Significand : 64;
+  uint16_t Exponent    : 15;
+  uint16_t Sign        : 1;
 
   X80SoftFloat() { memset(this, 0, sizeof(*this)); }
-  X80SoftFloat(unsigned _Sign, uint16_t _Exponent, uint64_t _Significand)
+  X80SoftFloat(uint16_t _Sign, uint16_t _Exponent, uint64_t _Significand)
     : Significand {_Significand}
     , Exponent {_Exponent}
     , Sign {_Sign}
     {
   }
 
-  std::string str() const {
-    std::ostringstream string;
+  fextl::string str() const {
+    fextl::ostringstream string;
     string << std::hex << Sign;
     string << "_" << Exponent;
     string << "_" << (Significand >> 63);
@@ -262,7 +268,7 @@ struct X80SoftFloat {
     return Result;
 #else
     X80SoftFloat Int = FRNDINT(rhs, softfloat_round_minMag);
-    BIGFLOAT Src2_d = Int;
+    LIBRARY_PRECISION Src2_d = Int;
     Src2_d = exp2l(Src2_d);
     X80SoftFloat Src2_X80 = Src2_d;
     X80SoftFloat Result = extF80_mul(lhs, Src2_X80);
@@ -286,8 +292,8 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src1_d = lhs;
-    BIGFLOAT Result = exp2l(Src1_d);
+    LIBRARY_PRECISION Src1_d = lhs;
+    LIBRARY_PRECISION Result = exp2l(Src1_d);
     Result -= 1.0;
     return Result;
 #endif
@@ -311,9 +317,9 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src1_d = lhs;
-    BIGFLOAT Src2_d = rhs;
-    BIGFLOAT Tmp = Src2_d * log2l(Src1_d);
+    LIBRARY_PRECISION Src1_d = lhs;
+    LIBRARY_PRECISION Src2_d = rhs;
+    LIBRARY_PRECISION Tmp = Src2_d * log2l(Src1_d);
     return Tmp;
 #endif
   }
@@ -336,9 +342,9 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src1_d = lhs;
-    BIGFLOAT Src2_d = rhs;
-    BIGFLOAT Tmp = atan2l(Src1_d, Src2_d);
+    LIBRARY_PRECISION Src1_d = lhs;
+    LIBRARY_PRECISION Src2_d = rhs;
+    LIBRARY_PRECISION Tmp = atan2l(Src1_d, Src2_d);
     return Tmp;
 #endif
   }
@@ -360,7 +366,7 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs;
     Src_d = tanl(Src_d);
     return Src_d;
 #endif
@@ -382,7 +388,7 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs;
     Src_d = sinl(Src_d);
     return Src_d;
 #endif
@@ -404,7 +410,7 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs;
     Src_d = cosl(Src_d);
     return Src_d;
 #endif
@@ -439,6 +445,7 @@ struct X80SoftFloat {
     return FEXCore::BitCast<double>(Result);
   }
 
+#ifndef _WIN32
   operator BIGFLOAT() const {
 #if BIGFLOATSIZE == 16
     const float128_t Result = extF80_to_f128(*this);
@@ -449,6 +456,7 @@ struct X80SoftFloat {
     return result;
 #endif
   }
+#endif
 
   operator int16_t() const {
     auto rv = extF80_to_i32(*this, softfloat_roundingMode, false);
@@ -517,6 +525,7 @@ struct X80SoftFloat {
     *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
   }
 
+#ifndef _WIN32
   X80SoftFloat(BIGFLOAT rhs) {
 #if BIGFLOATSIZE == 16
     *this = f128_to_extF80(FEXCore::BitCast<float128_t>(rhs));
@@ -524,6 +533,7 @@ struct X80SoftFloat {
     *this = FEXCore::BitCast<long double>(rhs);
 #endif
   }
+#endif
 
   X80SoftFloat(const int16_t rhs) {
     *this = i32_to_extF80(rhs);
@@ -562,4 +572,9 @@ private:
   static constexpr uint32_t ExponentBias = 16383;
 };
 
+#ifndef _WIN32
 static_assert(sizeof(X80SoftFloat) == 10, "tword must be 10bytes in size");
+#else
+// Padding on this extends to 16-bytes rather than 10-bytes on WIN32.
+static_assert(sizeof(X80SoftFloat) == 16, "tword must be 16bytes in size");
+#endif

External/FEXCore/Source/Common/StringConv.h

@@ -1,48 +1,49 @@
 #pragma once
+#include <FEXCore/fextl/string.h>
+
 #include <cstdint>
-#include <string>
 #include <string_view>
 #include <optional>
 
 namespace FEXCore::StrConv {
   [[maybe_unused]] static bool Conv(std::string_view Value, bool *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtoull(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, uint8_t *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtoul(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, uint16_t *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtoul(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, uint32_t *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtoul(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, int32_t *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtol(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, uint64_t *Result) {
-    *Result = std::stoull(std::string(Value), nullptr, 0);
-    return true;
-  }
-  [[maybe_unused]] static bool Conv(std::string_view Value, std::string *Result) {
-    *Result = Value;
+    *Result = std::strtoull(Value.data(), nullptr, 0);
     return true;
   }
   template <typename T,
     typename = std::enable_if<std::is_enum<T>::value, T>>
   [[maybe_unused]] static bool Conv(std::string_view Value, T *Result) {
-    *Result = static_cast<T>(std::stoull(std::string(Value), nullptr, 0));
+    *Result = static_cast<T>(std::stoull(Value.data(), nullptr, 0));
     return true;
   }
 
+  [[maybe_unused]] static bool Conv(std::string_view Value, fextl::string *Result) {
+    *Result = Value;
+    return true;
+  }
 }

External/FEXCore/Source/Common/StringUtils.h

@@ -1,11 +1,11 @@
 #pragma once
-#include <string>
+#include <FEXCore/fextl/string.h>
 
 namespace FEXCore::StringUtils {
   // Trim the left side of the string of whitespace and new lines
-  [[maybe_unused]] static std::string LeftTrim(std::string String, std::string TrimTokens = " \t\n\r") {
-    size_t pos = std::string::npos;
-    if ((pos = String.find_first_not_of(TrimTokens)) != std::string::npos) {
+  [[maybe_unused]] static fextl::string LeftTrim(fextl::string String, std::string_view TrimTokens = " \t\n\r") {
+    size_t pos = fextl::string::npos;
+    if ((pos = String.find_first_not_of(TrimTokens)) != fextl::string::npos) {
       String.erase(0, pos);
     }
 
@@ -13,9 +13,9 @@ namespace FEXCore::StringUtils {
   }
 
   // Trim the right side of the string of whitespace and new lines
-  [[maybe_unused]] static std::string RightTrim(std::string String, std::string TrimTokens = " \t\n\r") {
-    size_t pos = std::string::npos;
-    if ((pos = String.find_last_not_of(TrimTokens)) != std::string::npos) {
+  [[maybe_unused]] static fextl::string RightTrim(fextl::string String, std::string_view TrimTokens = " \t\n\r") {
+    size_t pos = fextl::string::npos;
+    if ((pos = String.find_last_not_of(TrimTokens)) != fextl::string::npos) {
       String.erase(String.begin() + pos + 1, String.end());
     }
 
@@ -23,7 +23,8 @@ namespace FEXCore::StringUtils {
   }
 
   // Trim both the left and right of the string of whitespace and new lines
-  [[maybe_unused]] static std::string Trim(std::string String, std::string TrimTokens = " \t\n\r") {
-    return RightTrim(LeftTrim(String, TrimTokens), TrimTokens);
+  [[maybe_unused]] static fextl::string Trim(fextl::string String, std::string_view TrimTokens = " \t\n\r") {
+    return RightTrim(LeftTrim(std::move(String), TrimTokens), TrimTokens);
   }
+
 }

External/FEXCore/Source/Interface/Config/Config.cpp

@@ -1,36 +1,36 @@
 #include "Common/StringConv.h"
 #include "Common/StringUtils.h"
-#include "Common/Paths.h"
-#include "Utils/FileLoading.h"
 
 #include <FEXCore/Config/Config.h>
+#include <FEXCore/Utils/Allocator.h>
+#include <FEXCore/Utils/CPUInfo.h>
+#include <FEXCore/Utils/FileLoading.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/fmt.h>
+#include <FEXCore/fextl/list.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/unordered_map.h>
+#include <FEXCore/fextl/vector.h>
+#include <FEXHeaderUtils/Filesystem.h>
 
 #include <array>
 #include <assert.h>
 #include <cstdlib>
-#include <filesystem>
-#include <fstream>
 #include <functional>
-#include <map>
-#include <memory>
-#include <list>
 #include <optional>
 #include <stddef.h>
 #include <stdint.h>
-#include <string>
 #include <string_view>
-#include <sys/sysinfo.h>
 #include <system_error>
 #include <type_traits>
-#include <unordered_map>
 #include <utility>
-#include <vector>
 
 #include <tiny-json.h>
 
 namespace FEXCore::Context {
-  struct Context;
+  class Context;
 }
 
 namespace FEXCore::Config {
@@ -45,13 +45,13 @@ namespace DefaultValues {
 namespace JSON {
   struct JsonAllocator {
     jsonPool_t PoolObject;
-    std::unique_ptr<std::list<json_t>> json_objects;
+    fextl::unique_ptr<fextl::list<json_t>> json_objects;
   };
   static_assert(offsetof(JsonAllocator, PoolObject) == 0, "This needs to be at offset zero");
 
   json_t* PoolInit(jsonPool_t* Pool) {
     JsonAllocator* alloc = reinterpret_cast<JsonAllocator*>(Pool);
-    alloc->json_objects = std::make_unique<std::list<json_t>>();
+    alloc->json_objects = fextl::make_unique<fextl::list<json_t>>();
     return &*alloc->json_objects->emplace(alloc->json_objects->end());
   }
 
@@ -60,8 +60,8 @@ namespace JSON {
     return &*alloc->json_objects->emplace(alloc->json_objects->end());
   }
 
-  static void LoadJSonConfig(const std::string &Config, std::function<void(const char *Name, const char *ConfigSring)> Func) {
-    std::vector<char> Data;
+  static void LoadJSonConfig(const fextl::string &Config, std::function<void(const char *Name, const char *ConfigSring)> Func) {
+    fextl::vector<char> Data;
     if (!FEXCore::FileLoading::LoadFile(Data, Config)) {
       return;
     }
@@ -107,114 +107,83 @@ namespace JSON {
   }
 }
 
-  std::string GetDataDirectory() {
-    std::string DataDir{};
+  enum Paths {
+    PATH_DATA_DIR = 0,
+    PATH_CONFIG_DIR_LOCAL,
+    PATH_CONFIG_DIR_GLOBAL,
+    PATH_CONFIG_FILE_LOCAL,
+    PATH_CONFIG_FILE_GLOBAL,
+    PATH_LAST,
+  };
+  static std::array<fextl::string, Paths::PATH_LAST> Paths;
 
-    char const *HomeDir = Paths::GetHomeDirectory();
-    char const *DataXDG = getenv("XDG_DATA_HOME");
-    char const *DataOverride = getenv("FEX_APP_DATA_LOCATION");
-    if (DataOverride) {
-      // Data override will override the complete directory
-      DataDir = DataOverride;
-    }
-    else {
-      DataDir = DataXDG ?: HomeDir;
-      DataDir += "/.fex-emu/";
-    }
-    return DataDir;
+  void SetDataDirectory(const std::string_view Path) {
+    Paths[PATH_DATA_DIR] = Path;
   }
 
-  std::string GetConfigDirectory(bool Global) {
-    std::string ConfigDir;
-    if (Global) {
-      ConfigDir = GLOBAL_DATA_DIRECTORY;
-    }
-    else {
-      char const *HomeDir = Paths::GetHomeDirectory();
-      char const *ConfigXDG = getenv("XDG_CONFIG_HOME");
-      char const *ConfigOverride = getenv("FEX_APP_CONFIG_LOCATION");
-      if (ConfigOverride) {
-        // Config override completely overrides the config directory
-        ConfigDir = ConfigOverride;
-      }
-      else {
-        ConfigDir = ConfigXDG ? ConfigXDG : HomeDir;
-        ConfigDir += "/.fex-emu/";
-      }
-
-      // Ensure the folder structure is created for our configuration
-      std::error_code ec{};
-      if (!std::filesystem::exists(ConfigDir, ec) &&
-          !std::filesystem::create_directories(ConfigDir, ec)) {
-        // Let's go local in this case
-        return "./";
-      }
-    }
-
-    return ConfigDir;
+  void SetConfigDirectory(const std::string_view Path, bool Global) {
+    Paths[PATH_CONFIG_DIR_LOCAL + Global] = Path;
   }
 
-  std::string GetConfigFileLocation(bool Global) {
-    std::string ConfigFile{};
-    if (Global) {
-      ConfigFile = GetConfigDirectory(true) + "Config.json";
-    }
-    else {
-      const char *AppConfig = getenv("FEX_APP_CONFIG");
-      if (AppConfig) {
-        // App config environment variable overwrites only the config file
-        ConfigFile = AppConfig;
-      }
-      else {
-        ConfigFile = GetConfigDirectory(false) + "Config.json";
-      }
-    }
-    return ConfigFile;
+  void SetConfigFileLocation(const std::string_view Path, bool Global) {
+    Paths[PATH_CONFIG_FILE_LOCAL + Global] = Path;
   }
 
-  std::string GetApplicationConfig(const std::string &Filename, bool Global) {
-    std::string ConfigFile = GetConfigDirectory(Global);
+  fextl::string const& GetDataDirectory() {
+    return Paths[PATH_DATA_DIR];
+  }
+
+  fextl::string const& GetConfigDirectory(bool Global) {
+    return Paths[PATH_CONFIG_DIR_LOCAL + Global];
+  }
+
+  fextl::string const& GetConfigFileLocation(bool Global) {
+    return Paths[PATH_CONFIG_FILE_LOCAL + Global];
+  }
+
+  fextl::string GetApplicationConfig(const std::string_view Program, bool Global) {
+    fextl::string ConfigFile = GetConfigDirectory(Global);
 
-    std::error_code ec{};
     if (!Global &&
-        !std::filesystem::exists(ConfigFile, ec) &&
-        !std::filesystem::create_directories(ConfigFile, ec)) {
+        !FHU::Filesystem::Exists(ConfigFile) &&
+        !FHU::Filesystem::CreateDirectories(ConfigFile)) {
       LogMan::Msg::DFmt("Couldn't create config directory: '{}'", ConfigFile);
       // Let's go local in this case
-      return "./" + Filename + ".json";
+      return fextl::fmt::format("./{}.json", Program);
     }
 
     ConfigFile += "AppConfig/";
 
     // Attempt to create the local folder if it doesn't exist
     if (!Global &&
-        !std::filesystem::exists(ConfigFile, ec) &&
-        !std::filesystem::create_directories(ConfigFile, ec)) {
+        !FHU::Filesystem::Exists(ConfigFile) &&
+        !FHU::Filesystem::CreateDirectories(ConfigFile)) {
       // Let's go local in this case
-      return "./" + Filename + ".json";
+      return fextl::fmt::format("./{}.json", Program);
     }
 
-    ConfigFile += Filename + ".json";
-    return ConfigFile;
+    return fextl::fmt::format("{}{}.json", ConfigFile, Program);
   }
 
   void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
   }
 
-  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, std::string const &Config) {
+  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, fextl::string const &Config) {
   }
 
   uint64_t GetConfig(FEXCore::Context::Context *CTX, ConfigOption Option) {
     return 0;
   }
 
-  static std::map<FEXCore::Config::LayerType, std::unique_ptr<FEXCore::Config::Layer>> ConfigLayers;
+  static fextl::map<FEXCore::Config::LayerType, fextl::unique_ptr<FEXCore::Config::Layer>> ConfigLayers;
   static FEXCore::Config::Layer *Meta{};
 
-  constexpr std::array<FEXCore::Config::LayerType, 7> LoadOrder = {
+  constexpr std::array<FEXCore::Config::LayerType, 9> LoadOrder = {
     FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN,
     FEXCore::Config::LayerType::LAYER_MAIN,
+    FEXCore::Config::LayerType::LAYER_GLOBAL_STEAM_APP,
     FEXCore::Config::LayerType::LAYER_GLOBAL_APP,
+    FEXCore::Config::LayerType::LAYER_LOCAL_STEAM_APP,
     FEXCore::Config::LayerType::LAYER_LOCAL_APP,
     FEXCore::Config::LayerType::LAYER_ARGUMENTS,
     FEXCore::Config::LayerType::LAYER_ENVIRONMENT,
@@ -266,17 +235,17 @@ namespace JSON {
     }
 
     // If an environment variable exists in both current meta and in the incoming layer then the meta layer value is overwritten
-    std::unordered_map<std::string, std::string> LookupMap;
+    fextl::unordered_map<fextl::string, fextl::string> LookupMap;
     const auto AddToMap = [&LookupMap](FEXCore::Config::LayerValue const &Value) {
       for (const auto &EnvVar : Value) {
         const auto ItEq = EnvVar.find_first_of('=');
-        if (ItEq == std::string::npos) {
+        if (ItEq == fextl::string::npos) {
           // Broken environment variable
           // Skip
           continue;
         }
-        auto Key = std::string(EnvVar.begin(), EnvVar.begin() + ItEq);
-        auto Value = std::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
+        auto Key = fextl::string(EnvVar.begin(), EnvVar.begin() + ItEq);
+        auto Value = fextl::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
 
         // Add the key to the map, overwriting whatever previous value was there
         LookupMap.insert_or_assign(std::move(Key), std::move(Value));
@@ -309,7 +278,7 @@ namespace JSON {
   }
 
   void Initialize() {
-    AddLayer(std::make_unique<MetaLayer>(FEXCore::Config::LayerType::LAYER_TOP));
+    AddLayer(fextl::make_unique<MetaLayer>(FEXCore::Config::LayerType::LAYER_TOP));
     Meta = ConfigLayers.begin()->second.get();
   }
 
@@ -327,16 +296,15 @@ namespace JSON {
     }
   }
 
-  std::string ExpandPath(std::string const &ContainerPrefix, std::string PathName) {
+  fextl::string ExpandPath(fextl::string const &ContainerPrefix, fextl::string PathName) {
     if (PathName.empty()) {
       return {};
     }
 
-    std::filesystem::path Path{PathName};
 
     // Expand home if it exists
-    if (Path.is_relative()) {
-      std::string Home = getenv("HOME") ?: "";
+    if (FHU::Filesystem::IsRelative(PathName)) {
+      fextl::string Home = getenv("HOME") ?: "";
       // Home expansion only works if it is the first character
       // This matches bash behaviour
       if (PathName.at(0) == '~') {
@@ -345,12 +313,15 @@ namespace JSON {
       }
 
       // Expand relative path to absolute
-      Path = std::filesystem::absolute(Path);
+      char ExistsTempPath[PATH_MAX];
+      char *RealPath = FHU::Filesystem::Absolute(PathName.c_str(), ExistsTempPath);
+      if (RealPath) {
+        PathName = RealPath;
+      }
 
       // Only return if it exists
-      std::error_code ec{};
-      if (std::filesystem::exists(Path, ec)) {
-        return Path;
+      if (FHU::Filesystem::Exists(PathName)) {
+        return PathName;
       }
     }
     else {
@@ -366,9 +337,9 @@ namespace JSON {
       // HostThunks: $CMAKE_INSTALL_PREFIX/lib/fex-emu/HostThunks/
       // GuestThunks: $CMAKE_INSTALL_PREFIX/share/fex-emu/GuestThunks/
       if (!ContainerPrefix.empty() && !PathName.empty()) {
-        if (!std::filesystem::exists(PathName)) {
+        if (!FHU::Filesystem::Exists(PathName)) {
           auto ContainerPath = ContainerPrefix + PathName;
-          if (std::filesystem::exists(ContainerPath)) {
+          if (FHU::Filesystem::Exists(ContainerPath)) {
             return ContainerPath;
           }
         }
@@ -377,15 +348,15 @@ namespace JSON {
     return {};
   }
 
+  constexpr char ContainerManager[] = "/run/host/container-manager";
 
-  std::string FindContainer() {
+  fextl::string FindContainer() {
     // We only support pressure-vessel at the moment
-    const static std::string ContainerManager = "/run/host/container-manager";
-    if (std::filesystem::exists(ContainerManager)) {
-      std::vector<char> Manager{};
+    if (FHU::Filesystem::Exists(ContainerManager)) {
+      fextl::vector<char> Manager{};
       if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
         // Trim the whitespace, may contain a newline
-        std::string ManagerStr = Manager.data();
+        fextl::string ManagerStr = Manager.data();
         ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
         return ManagerStr;
       }
@@ -393,14 +364,13 @@ namespace JSON {
     return {};
   }
 
-  std::string FindContainerPrefix() {
+  fextl::string FindContainerPrefix() {
     // We only support pressure-vessel at the moment
-    const static std::string ContainerManager = "/run/host/container-manager";
-    if (std::filesystem::exists(ContainerManager)) {
-      std::vector<char> Manager{};
+    if (FHU::Filesystem::Exists(ContainerManager)) {
+      fextl::vector<char> Manager{};
       if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
         // Trim the whitespace, may contain a newline
-        std::string ManagerStr = Manager.data();
+        fextl::string ManagerStr = Manager.data();
         ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
         if (strncmp(ManagerStr.data(), "pressure-vessel", Manager.size()) == 0) {
           // We are running inside of pressure vessel
@@ -422,7 +392,7 @@ namespace JSON {
       FEX_CONFIG_OPT(Cores, THREADS);
       if (Cores == 0) {
         // When the number of emulated CPU cores is zero then auto detect
-        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THREADS, std::to_string(get_nprocs_conf()));
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THREADS, fextl::fmt::format("{}", FEXCore::CPUInfo::CalculateNumberOfCPUs()));
       }
     }
 
@@ -441,7 +411,7 @@ namespace JSON {
 #endif
       if (Core > MaxCoreNumber || Core < MinCoreNumber) {
         // Sanitize the core option by setting the core to the JIT if invalid
-        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, std::to_string(FEXCore::Config::CONFIG_IRJIT));
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, fextl::fmt::format("{}", static_cast<uint32_t>(FEXCore::Config::CONFIG_IRJIT)));
       }
     }
 
@@ -455,8 +425,8 @@ namespace JSON {
       }
     }
 
-    std::string ContainerPrefix { FindContainerPrefix() };
-    auto ExpandPathIfExists = [&ContainerPrefix](FEXCore::Config::ConfigOption Config, std::string PathName) {
+    fextl::string ContainerPrefix { FindContainerPrefix() };
+    auto ExpandPathIfExists = [&ContainerPrefix](FEXCore::Config::ConfigOption Config, fextl::string PathName) {
       auto NewPath = ExpandPath(ContainerPrefix, PathName);
       if (!NewPath.empty()) {
         FEXCore::Config::EraseSet(Config, NewPath);
@@ -465,16 +435,15 @@ namespace JSON {
 
     if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_ROOTFS)) {
       FEX_CONFIG_OPT(PathName, ROOTFS);
-      auto ExpandedString = ExpandPath(ContainerPrefix, PathName());
+      auto ExpandedString = ExpandPath(ContainerPrefix,PathName());
       if (!ExpandedString.empty()) {
         // Adjust the path if it ended up being relative
         FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, ExpandedString);
       }
       else if (!PathName().empty()) {
         // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
-        std::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
-        std::error_code ec{};
-        if (std::filesystem::exists(NamedRootFS, ec)) {
+        fextl::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
+        if (FHU::Filesystem::Exists(NamedRootFS)) {
           FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NamedRootFS);
         }
       }
@@ -496,9 +465,8 @@ namespace JSON {
       }
       else if (!PathName().empty()) {
         // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
-        std::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
-        std::error_code ec{};
-        if (std::filesystem::exists(NamedConfig, ec)) {
+        fextl::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
+        if (FHU::Filesystem::Exists(NamedConfig)) {
           FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, NamedConfig);
         }
       }
@@ -512,11 +480,11 @@ namespace JSON {
 
     if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_SINGLESTEP)) {
       // Single stepping also enforces single instruction size blocks
-      Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, std::to_string(1u));
+      Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, "1");
     }
   }
 
-  void AddLayer(std::unique_ptr<FEXCore::Config::Layer> _Layer) {
+  void AddLayer(fextl::unique_ptr<FEXCore::Config::Layer> _Layer) {
     ConfigLayers.emplace(_Layer->GetLayerType(), std::move(_Layer));
   }
 
@@ -528,7 +496,7 @@ namespace JSON {
     return Meta->All(Option);
   }
 
-  std::optional<std::string*> Get(ConfigOption Option) {
+  std::optional<fextl::string*> Get(ConfigOption Option) {
     return Meta->Get(Option);
   }
 
@@ -569,7 +537,7 @@ namespace JSON {
   }
 
   template<>
-  std::string Value<std::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string Default) {
+  fextl::string Value<fextl::string>::GetIfExists(FEXCore::Config::ConfigOption Option, fextl::string Default) {
     auto Value = FEXCore::Config::Get(Option);
     if (Value) {
       return **Value;
@@ -580,13 +548,13 @@ namespace JSON {
   }
 
   template<>
-  std::string Value<std::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string_view Default) {
+  fextl::string Value<fextl::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string_view Default) {
     auto Value = FEXCore::Config::Get(Option);
     if (Value) {
       return **Value;
     }
     else {
-      return std::string(Default);
+      return fextl::string(Default);
     }
   }
 
@@ -601,39 +569,39 @@ namespace JSON {
   template uint64_t Value<uint64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint64_t Default);
 
   // Constructor
-  template Value<std::string>::Value(FEXCore::Config::ConfigOption _Option, std::string Default);
+  template Value<fextl::string>::Value(FEXCore::Config::ConfigOption _Option, fextl::string Default);
   template Value<bool>::Value(FEXCore::Config::ConfigOption _Option, bool Default);
   template Value<uint8_t>::Value(FEXCore::Config::ConfigOption _Option, uint8_t Default);
   template Value<uint64_t>::Value(FEXCore::Config::ConfigOption _Option, uint64_t Default);
 
   template<typename T>
-  void Value<T>::GetListIfExists(FEXCore::Config::ConfigOption Option, std::list<std::string> *List) {
+  void Value<T>::GetListIfExists(FEXCore::Config::ConfigOption Option, fextl::list<fextl::string> *List) {
     auto Value = FEXCore::Config::All(Option);
     List->clear();
     if (Value) {
       *List = **Value;
     }
   }
-  template void Value<std::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, std::list<std::string> *List);
+  template void Value<fextl::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, fextl::list<fextl::string> *List);
 
   // Application loaders
   class MainLoader final : public FEXCore::Config::OptionMapper {
   public:
     explicit MainLoader(FEXCore::Config::LayerType Type);
-    explicit MainLoader(std::string ConfigFile);
+    explicit MainLoader(fextl::string ConfigFile);
     void Load() override;
 
   private:
-    std::string Config;
+    fextl::string Config;
   };
 
   class AppLoader final : public FEXCore::Config::OptionMapper {
   public:
-    explicit AppLoader(const std::string& Filename, bool Global);
+    explicit AppLoader(const fextl::string& Filename, FEXCore::Config::LayerType Type);
     void Load();
 
   private:
-    std::string Config;
+    fextl::string Config;
   };
 
   class EnvLoader final : public FEXCore::Config::Layer {
@@ -645,11 +613,11 @@ namespace JSON {
     char *const *envp;
   };
 
-  static const std::map<std::string, FEXCore::Config::ConfigOption, std::less<>> ConfigLookup = {{
+  static const fextl::map<fextl::string, FEXCore::Config::ConfigOption, std::less<>> ConfigLookup = {{
 #define OPT_BASE(type, group, enum, json, default) {#json, FEXCore::Config::ConfigOption::CONFIG_##enum},
 #include <FEXCore/Config/ConfigValues.inl>
   }};
-  static const std::vector<std::pair<const char*, FEXCore::Config::ConfigOption>> EnvConfigLookup = {{
+  static const fextl::vector<std::pair<const char*, FEXCore::Config::ConfigOption>> EnvConfigLookup = {{
 #define OPT_BASE(type, group, enum, json, default) {"FEX_" #enum, FEXCore::Config::ConfigOption::CONFIG_##enum},
 #include <FEXCore/Config/ConfigValues.inl>
   }};
@@ -670,7 +638,7 @@ namespace JSON {
     , Config{FEXCore::Config::GetConfigFileLocation(Type == FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN)} {
   }
 
-  MainLoader::MainLoader(std::string ConfigFile)
+  MainLoader::MainLoader(fextl::string ConfigFile)
     : FEXCore::Config::OptionMapper(FEXCore::Config::LayerType::LAYER_MAIN)
     , Config{std::move(ConfigFile)} {
   }
@@ -681,8 +649,10 @@ namespace JSON {
     });
   }
 
-  AppLoader::AppLoader(const std::string& Filename, bool Global)
-    : FEXCore::Config::OptionMapper(Global ? FEXCore::Config::LayerType::LAYER_GLOBAL_APP : FEXCore::Config::LayerType::LAYER_LOCAL_APP) {
+  AppLoader::AppLoader(const fextl::string& Filename, FEXCore::Config::LayerType Type)
+    : FEXCore::Config::OptionMapper(Type) {
+    const bool Global = Type == FEXCore::Config::LayerType::LAYER_GLOBAL_STEAM_APP ||
+                        Type == FEXCore::Config::LayerType::LAYER_GLOBAL_APP;
     Config = FEXCore::Config::GetApplicationConfig(Filename, Global);
 
     // Immediately load so we can reload the meta layer
@@ -701,12 +671,13 @@ namespace JSON {
   }
 
   void EnvLoader::Load() {
-    std::unordered_map<std::string_view, std::string_view> EnvMap;
+    using EnvMapType = fextl::unordered_map<std::string_view, std::string_view>;
+    EnvMapType EnvMap;
 
     for(const char *const *pvar=envp; pvar && *pvar; pvar++) {
       std::string_view Var(*pvar);
       size_t pos = Var.rfind('=');
-      if (std::string::npos == pos)
+      if (fextl::string::npos == pos)
         continue;
 
       std::string_view Key = Var.substr(0,pos);
@@ -715,10 +686,10 @@ namespace JSON {
 #define ENVLOADER
 #include <FEXCore/Config/ConfigOptions.inl>
 
-      EnvMap[Key]=Value;
+      EnvMap[Key] = Value;
     }
 
-    std::function GetVar = [=](const std::string_view id)  -> std::optional<std::string_view> {
+    auto GetVar = [](EnvMapType &EnvMap, const std::string_view id)  -> std::optional<std::string_view> {
       if (EnvMap.find(id) != EnvMap.end())
         return EnvMap.at(id);
 
@@ -735,31 +706,31 @@ namespace JSON {
     std::optional<std::string_view> Value;
 
     for (auto &it : EnvConfigLookup) {
-      if ((Value = GetVar(it.first)).has_value()) {
-        Set(it.second, std::string(*Value));
+      if ((Value = GetVar(EnvMap, it.first)).has_value()) {
+        Set(it.second, fextl::string(*Value));
       }
     }
   }
 
-  std::unique_ptr<FEXCore::Config::Layer> CreateGlobalMainLayer() {
-    return std::make_unique<FEXCore::Config::MainLoader>(FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN);
+  fextl::unique_ptr<FEXCore::Config::Layer> CreateGlobalMainLayer() {
+    return fextl::make_unique<FEXCore::Config::MainLoader>(FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN);
   }
 
-  std::unique_ptr<FEXCore::Config::Layer> CreateMainLayer(std::string const *File) {
+  fextl::unique_ptr<FEXCore::Config::Layer> CreateMainLayer(fextl::string const *File) {
     if (File) {
-      return std::make_unique<FEXCore::Config::MainLoader>(*File);
+      return fextl::make_unique<FEXCore::Config::MainLoader>(*File);
     }
     else {
-      return std::make_unique<FEXCore::Config::MainLoader>(FEXCore::Config::LayerType::LAYER_MAIN);
+      return fextl::make_unique<FEXCore::Config::MainLoader>(FEXCore::Config::LayerType::LAYER_MAIN);
     }
   }
 
-  std::unique_ptr<FEXCore::Config::Layer> CreateAppLayer(const std::string& Filename, bool Global) {
-    return std::make_unique<FEXCore::Config::AppLoader>(Filename, Global);
+  fextl::unique_ptr<FEXCore::Config::Layer> CreateAppLayer(const fextl::string& Filename, FEXCore::Config::LayerType Type) {
+    return fextl::make_unique<FEXCore::Config::AppLoader>(Filename, Type);
   }
 
-  std::unique_ptr<FEXCore::Config::Layer> CreateEnvironmentLayer(char *const _envp[]) {
-    return std::make_unique<FEXCore::Config::EnvLoader>(_envp);
+  fextl::unique_ptr<FEXCore::Config::Layer> CreateEnvironmentLayer(char *const _envp[]) {
+    return fextl::make_unique<FEXCore::Config::EnvLoader>(_envp);
   }
 }
 

External/FEXCore/Source/Interface/Config/Config.json.in

@@ -16,10 +16,11 @@
       },
       "Multiblock": {
         "Type": "bool",
-        "Default": "true",
+        "Default": "false",
         "ShortArg": "m",
         "Desc": [
-          "Controls multiblock code compilation"
+          "Controls multiblock code compilation",
+          "Can cause long JIT compilation times and stutter"
         ]
       },
       "MaxInst": {
@@ -52,7 +53,7 @@
       },
       "EnableAVX": {
         "Type": "bool",
-        "Default": "true",
+        "Default": "false",
         "Desc": [
           "Determines whether or not we use the expanded register file for AVX or not"
         ]
@@ -90,6 +91,13 @@
           "Folder to find the guest-side thunking libraries."
         ]
       },
+      "ThunkHostLibs32": {
+        "Type": "str",
+        "Default": "@CMAKE_INSTALL_PREFIX@/lib/fex-emu/HostThunks_32/",
+        "Desc": [
+          "Folder to find the 32-bit host-side thunking libraries."
+        ]
+      },
       "ThunkGuestLibs32": {
         "Type": "str",
         "Default": "@CMAKE_INSTALL_PREFIX@/share/fex-emu/GuestThunks_32/",
@@ -232,6 +240,17 @@
           "Also needs x86_64-linux-gnu-objdump in PATH.",
           "Can be very slow."
         ]
+      },
+      "InjectLibSegFault": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Sets the environment variable LD_PRELOAD=libSegFault.so",
+          "This allows the user to very easily enable libSegFault without dealing with environment variables",
+          "Very useful for applications that have launch scripts that set the variable to nothing at launch",
+          "Set this in an application configuration for injecting in to only specific applications.",
+          "\tNote: If x86/x86_64 libSegFault.so isn't installed then this option won't work."
+        ]
       }
     },
     "Logging": {
@@ -324,14 +343,12 @@
           "Useful for a process that keeps restarting and doesn't work"
         ]
       },
-      "x86dec_SynchronizeRIPOnAllBlocks": {
+      "HideHypervisorBit": {
         "Type": "bool",
         "Default": "false",
         "Desc": [
-          "An application that uses try-catch or longjump extensively needs the ability to do context aware state flushing",
-          "In the case of FEX's block-linking, it won't always ensure that RIP is synchronized.",
-          "If an exception occurs and RIP isn't synchronized, then FEX's exception stack restore may not long jump as expected",
-          "Can be useful for Wine applications that rely on stack unwinding"
+          "Hides the hypervisor CPUID bit when set.",
+          "Should only be used for applications that have issues with this set."
         ]
       }
     },

External/FEXCore/Source/Interface/Context/Context.cpp

@@ -1,4 +1,3 @@
-#include "Common/Paths.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Core.h"
 #include "Interface/Core/OpcodeDispatcher.h"
@@ -19,221 +18,80 @@ namespace FEXCore::HLE {
 
 namespace FEXCore::Context {
   void InitializeStaticTables(OperatingMode Mode) {
-    FEXCore::Paths::InitializePaths();
     X86Tables::InitializeInfoTables(Mode);
     IR::InstallOpcodeHandlers(Mode);
   }
 
-  void ShutdownStaticTables() {
-    FEXCore::Paths::ShutdownPaths();
+  fextl::unique_ptr<FEXCore::Context::Context> FEXCore::Context::Context::CreateNewContext() {
+    return fextl::make_unique<FEXCore::Context::ContextImpl>();
   }
 
-  FEXCore::Context::Context *CreateNewContext() {
-    return new FEXCore::Context::Context{};
+  bool FEXCore::Context::ContextImpl::InitializeContext() {
+    return FEXCore::CPU::CreateCPUCore(this);
   }
 
-  bool InitializeContext(FEXCore::Context::Context *CTX) {
-    return FEXCore::CPU::CreateCPUCore(CTX);
+  void FEXCore::Context::ContextImpl::SetExitHandler(ExitHandler handler) {
+    CustomExitHandler = std::move(handler);
   }
 
-  void DestroyContext(FEXCore::Context::Context *CTX) {
-    if (CTX->ParentThread) {
-      CTX->DestroyThread(CTX->ParentThread);
-    }
-    delete CTX;
+  ExitHandler FEXCore::Context::ContextImpl::GetExitHandler() const {
+    return CustomExitHandler;
   }
 
-  FEXCore::Core::InternalThreadState* InitCore(FEXCore::Context::Context *CTX, uint64_t InitialRIP, uint64_t StackPointer) {
-    return CTX->InitCore(InitialRIP, StackPointer);
+  void FEXCore::Context::ContextImpl::Stop() {
+    Stop(false);
   }
 
-  void SetExitHandler(FEXCore::Context::Context *CTX, ExitHandler handler) {
-    CTX->CustomExitHandler = std::move(handler);
+  void FEXCore::Context::ContextImpl::CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
+    CompileBlock(Thread->CurrentFrame, GuestRIP);
   }
 
-  ExitHandler GetExitHandler(const FEXCore::Context::Context *CTX) {
-    return CTX->CustomExitHandler;
+  FEXCore::Context::ExitReason FEXCore::Context::ContextImpl::GetExitReason() {
+    return ParentThread->ExitReason;
   }
 
-  void Run(FEXCore::Context::Context *CTX) {
-    CTX->Run();
+  bool FEXCore::Context::ContextImpl::IsDone() const {
+    return IsPaused();
   }
 
-  void Step(FEXCore::Context::Context *CTX) {
-    CTX->Step();
+  void FEXCore::Context::ContextImpl::GetCPUState(FEXCore::Core::CPUState *State) const {
+    memcpy(State, ParentThread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
   }
 
-  void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
-    Thread->CTX->CompileBlock(Thread->CurrentFrame, GuestRIP);
+  void FEXCore::Context::ContextImpl::SetCPUState(const FEXCore::Core::CPUState *State) {
+    memcpy(ParentThread->CurrentFrame, State, sizeof(FEXCore::Core::CPUState));
   }
 
-  FEXCore::Context::ExitReason RunUntilExit(FEXCore::Context::Context *CTX) {
-    return CTX->RunUntilExit();
+  void FEXCore::Context::ContextImpl::SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) {
+    CustomCPUFactory = std::move(Factory);
   }
 
-  int GetProgramStatus(const FEXCore::Context::Context *CTX) {
-    return CTX->GetProgramStatus();
-  }
-
-  FEXCore::Context::ExitReason GetExitReason(const FEXCore::Context::Context *CTX) {
-    return CTX->ParentThread->ExitReason;
-  }
-
-  bool IsDone(const FEXCore::Context::Context *CTX) {
-    return CTX->IsPaused();
-  }
-
-  void GetCPUState(const FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
-    memcpy(State, CTX->ParentThread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
-  }
-
-  void SetCPUState(FEXCore::Context::Context *CTX, const FEXCore::Core::CPUState *State) {
-    memcpy(CTX->ParentThread->CurrentFrame, State, sizeof(FEXCore::Core::CPUState));
-  }
-
-  void Pause(FEXCore::Context::Context *CTX) {
-    CTX->Pause();
-  }
-
-  void Stop(FEXCore::Context::Context *CTX) {
-    CTX->Stop(false);
-  }
-
-  void SetCustomCPUBackendFactory(FEXCore::Context::Context *CTX, CustomCPUFactoryType Factory) {
-    CTX->CustomCPUFactory = std::move(Factory);
-  }
-
-  bool AddVirtualMemoryMapping([[maybe_unused]] FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t VirtualAddress, [[maybe_unused]] uint64_t PhysicalAddress, [[maybe_unused]] uint64_t Size) {
+  bool FEXCore::Context::ContextImpl::AddVirtualMemoryMapping([[maybe_unused]] uint64_t VirtualAddress, [[maybe_unused]] uint64_t PhysicalAddress, [[maybe_unused]] uint64_t Size) {
     return false;
   }
 
-  void RegisterExternalSyscallVisitor(FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t Syscall, [[maybe_unused]] FEXCore::HLE::SyscallVisitor *Visitor) {
+  HostFeatures FEXCore::Context::ContextImpl::GetHostFeatures() const {
+    return HostFeatures;
   }
 
-  HostFeatures GetHostFeatures(const FEXCore::Context::Context *CTX) {
-    return CTX->HostFeatures;
+  void FEXCore::Context::ContextImpl::SetSignalDelegator(FEXCore::SignalDelegator *_SignalDelegation) {
+    SignalDelegation = _SignalDelegation;
   }
 
-  void HandleCallback(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
-    CTX->HandleCallback(Thread, RIP);
+  void FEXCore::Context::ContextImpl::SetSyscallHandler(FEXCore::HLE::SyscallHandler *Handler) {
+    SyscallHandler = Handler;
+    SourcecodeResolver = Handler->GetSourcecodeResolver();
   }
 
-  void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
-      CTX->RegisterHostSignalHandler(Signal, std::move(Func), Required);
+  FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunction(uint32_t Function, uint32_t Leaf) {
+    return CPUID.RunFunction(Function, Leaf);
   }
 
-  void RegisterFrontendHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
-    CTX->RegisterFrontendHostSignalHandler(Signal, std::move(Func), Required);
+  FEXCore::CPUID::XCRResults FEXCore::Context::ContextImpl::RunXCRFunction(uint32_t Function) {
+    return CPUID.RunXCRFunction(Function);
   }
 
-  FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) {
-    return CTX->CreateThread(NewThreadState, ParentTID);
+  FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
+    return CPUID.RunFunctionName(Function, Leaf, CPU);
   }
-
-  void ExecutionThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    return CTX->ExecutionThread(Thread);
-  }
-
-  void InitializeThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    return CTX->InitializeThread(Thread);
-  }
-
-  void RunThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    CTX->RunThread(Thread);
-  }
-
-  void StopThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    CTX->StopThread(Thread);
-  }
-
-  void DestroyThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    CTX->DestroyThread(Thread);
-  }
-
-  void CleanupAfterFork(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    CTX->CleanupAfterFork(Thread);
-  }
-  
-  void SetSignalDelegator(FEXCore::Context::Context *CTX, FEXCore::SignalDelegator *SignalDelegation) {
-    CTX->SignalDelegation = SignalDelegation;
-  }
-
-  void SetSyscallHandler(FEXCore::Context::Context *CTX, FEXCore::HLE::SyscallHandler *Handler) {
-    CTX->SyscallHandler = Handler;
-    CTX->SourcecodeResolver = Handler->GetSourcecodeResolver();
-  }
-
-  FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf) {
-    return CTX->CPUID.RunFunction(Function, Leaf);
-  }
-
-  FEX_DEFAULT_VISIBILITY FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf, uint32_t CPU) {
-    return CTX->CPUID.RunFunctionName(Function, Leaf, CPU);
-  }
-
-  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<int(const std::string&)> CacheReader) {
-    CTX->SetAOTIRLoader(CacheReader);
-  }
-
-  void SetAOTIRWriter(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) {
-    CTX->SetAOTIRWriter(CacheWriter);
-  }
-
-  void SetAOTIRRenamer(FEXCore::Context::Context *CTX, std::function<void(const std::string&)> CacheRenamer) {
-    CTX->SetAOTIRRenamer(CacheRenamer);
-  }
-
-  void FinalizeAOTIRCache(FEXCore::Context::Context *CTX) {
-    CTX->FinalizeAOTIRCache();
-  }
-
-  void WriteFilesWithCode(FEXCore::Context::Context *CTX, std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
-    CTX->WriteFilesWithCode(Writer);
-  }
-
-  IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(FEXCore::Context::Context *CTX, const std::string &Name) {
-    return CTX->LoadAOTIRCacheEntry(Name);
-  }
-  void UnloadAOTIRCacheEntry(FEXCore::Context::Context *CTX, IR::AOTIRCacheEntry *Entry) {
-    return CTX->UnloadAOTIRCacheEntry(Entry);
-  }
-
-  CustomIRResult AddCustomIREntrypoint(FEXCore::Context::Context *CTX, uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator, void *Data) {
-    return CTX->AddCustomIREntrypoint(Entrypoint, Handler, Creator, Data);
-  }
-
-  void AppendThunkDefinitions(FEXCore::Context::Context *CTX, std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) {
-    CTX->AppendThunkDefinitions(Definitions);
-  }
-
-namespace Debug {
-  void CompileRIP(FEXCore::Context::Context *CTX, uint64_t RIP) {
-    CTX->CompileRIP(CTX->ParentThread, RIP);
-  }
-  uint64_t GetThreadCount(FEXCore::Context::Context *CTX) {
-    return CTX->GetThreadCount();
-  }
-
-  FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(FEXCore::Context::Context *CTX, uint64_t Thread) {
-    return CTX->GetRuntimeStatsForThread(Thread);
-  }
-
-  bool GetDebugDataForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::Core::DebugData *Data) {
-    return CTX->GetDebugDataForRIP(RIP, Data);
-  }
-
-  bool FindHostCodeForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, uint8_t **Code) {
-    return CTX->FindHostCodeForRIP(RIP, Code);
-  }
-
-  // XXX:
-  // bool FindIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList **ir) {
-  //   return CTX->FindIRForRIP(RIP, ir);
-  // }
-
-  // void SetIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir) {
-  //   CTX->SetIRForRIP(RIP, ir);
-  // }
-}
-
 }

External/FEXCore/Source/Interface/Context/Context.h

@@ -1,7 +1,6 @@
 #pragma once
 
 #include "Common/JitSymbols.h"
-#include "FEXHeaderUtils/ScopedSignalMask.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/X86HelperGen.h"
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
@@ -14,24 +13,25 @@
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/DeferredSignalMutex.h>
 #include <FEXCore/Utils/Event.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/set.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/unordered_map.h>
+#include <FEXCore/fextl/vector.h>
 #include <FEXHeaderUtils/Syscalls.h>
 #include <stdint.h>
 
-
 #include <atomic>
 #include <condition_variable>
 #include <functional>
 #include <istream>
-#include <map>
 #include <memory>
 #include <mutex>
 #include <shared_mutex>
 #include <stddef.h>
-#include <string>
-#include <unordered_map>
 #include <queue>
-#include <vector>
 
 namespace FEXCore {
 class CodeLoader;
@@ -70,7 +70,128 @@ namespace FEXCore::Context {
     MODE_SINGLESTEP = 1,
   };
 
-  struct Context {
+  class ContextImpl final : public FEXCore::Context::Context {
+    public:
+      // Context base class implementation.
+      bool InitializeContext() override;
+
+      FEXCore::Core::InternalThreadState* InitCore(uint64_t InitialRIP, uint64_t StackPointer) override;
+
+      void SetExitHandler(ExitHandler handler) override;
+      ExitHandler GetExitHandler() const override;
+
+      void Pause() override;
+      void Run() override;
+      void Stop() override;
+      void Step() override;
+
+      ExitReason RunUntilExit() override;
+
+      void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) override;
+
+      int GetProgramStatus() const override;
+
+      ExitReason GetExitReason() override;
+
+      bool IsDone() const override;
+
+      void GetCPUState(FEXCore::Core::CPUState *State) const override;
+      void SetCPUState(const FEXCore::Core::CPUState *State) override;
+
+      void SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) override;
+
+      bool AddVirtualMemoryMapping(uint64_t VirtualAddress, uint64_t PhysicalAddress, uint64_t Size) override;
+
+      HostFeatures GetHostFeatures() const override;
+
+      void HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) override;
+
+      uint64_t RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState *Thread, uint64_t HostPC) override;
+
+      /**
+       * @brief Used to create FEX thread objects in preparation for creating a true OS thread. Does set a TID or PID.
+       *
+       * @param NewThreadState The initial thread state to setup for our state
+       * @param ParentTID The PID that was the parent thread that created this
+       *
+       * @return The InternalThreadState object that tracks all of the emulated thread's state
+       *
+       * Usecases:
+       *  OS thread Creation:
+       *    - Thread = CreateThread(NewState, PPID);
+       *    - InitializeThread(Thread);
+       *  OS fork (New thread created with a clone of thread state):
+       *    - clone{2, 3}
+       *    - Thread = CreateThread(CopyOfThreadState, PPID);
+       *    - ExecutionThread(Thread); // Starts executing without creating another host thread
+       *  Thunk callback executing guest code from native host thread
+       *    - Thread = CreateThread(NewState, PPID);
+       *    - InitializeThreadTLSData(Thread);
+       *    - HandleCallback(Thread, RIP);
+       */
+      FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) override;
+
+      // Public for threading
+      void ExecutionThread(FEXCore::Core::InternalThreadState *Thread) override;
+      /**
+       * @brief Initializes the OS thread object and prepares to start executing on that new OS thread
+       *
+       * @param Thread The internal FEX thread state object
+       *
+       * The OS thread will wait until RunThread is executed
+       */
+      void InitializeThread(FEXCore::Core::InternalThreadState *Thread) override;
+      /**
+       * @brief Starts the OS thread object to start executing guest code
+       *
+       * @param Thread The internal FEX thread state object
+       */
+      void RunThread(FEXCore::Core::InternalThreadState *Thread) override;
+      void StopThread(FEXCore::Core::InternalThreadState *Thread) override;
+      /**
+       * @brief Destroys this FEX thread object and stops tracking it internally
+       *
+       * @param Thread The internal FEX thread state object
+       */
+      void DestroyThread(FEXCore::Core::InternalThreadState *Thread) override;
+      void CleanupAfterFork(FEXCore::Core::InternalThreadState *Thread) override;
+      void SetSignalDelegator(FEXCore::SignalDelegator *SignalDelegation) override;
+      void SetSyscallHandler(FEXCore::HLE::SyscallHandler *Handler) override;
+
+      FEXCore::CPUID::FunctionResults RunCPUIDFunction(uint32_t Function, uint32_t Leaf) override;
+      FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) override;
+      FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) override;
+
+      FEXCore::IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(const fextl::string& Name) override;
+      void UnloadAOTIRCacheEntry(FEXCore::IR::AOTIRCacheEntry *Entry) override;
+
+      void SetAOTIRLoader(std::function<int(const fextl::string&)> CacheReader) override {
+        IRCaptureCache.SetAOTIRLoader(CacheReader);
+      }
+      void SetAOTIRWriter(std::function<fextl::unique_ptr<AOTIRWriter>(const fextl::string&)> CacheWriter) override {
+        IRCaptureCache.SetAOTIRWriter(CacheWriter);
+      }
+      void SetAOTIRRenamer(std::function<void(const fextl::string&)> CacheRenamer) override {
+        IRCaptureCache.SetAOTIRRenamer(CacheRenamer);
+      }
+
+      void FinalizeAOTIRCache() override {
+        IRCaptureCache.FinalizeAOTIRCache();
+      }
+      void WriteFilesWithCode(std::function<void(const fextl::string& fileid, const fextl::string& filename)> Writer) override {
+        IRCaptureCache.WriteFilesWithCode(Writer);
+      }
+      void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length) override;
+      void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length, std::function<void(uint64_t start, uint64_t Length)> callback) override;
+      void MarkMemoryShared() override;
+
+      void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) override;
+      // returns false if a handler was already registered
+      CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator = nullptr, void *Data = nullptr) override;
+
+      void AppendThunkDefinitions(fextl::vector<FEXCore::IR::ThunkDefinition> const& Definitions) override;
+
+    public:
     friend class FEXCore::HLE::SyscallHandler;
   #ifdef JIT_ARM64
     friend class FEXCore::CPU::Arm64JITCore;
@@ -105,6 +226,7 @@ namespace FEXCore::Context {
       FEX_CONFIG_OPT(MaxInstPerBlock, MAXINST);
       FEX_CONFIG_OPT(RootFSPath, ROOTFS);
       FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
+      FEX_CONFIG_OPT(ThunkHostLibsPath32, THUNKHOSTLIBS32);
       FEX_CONFIG_OPT(ThunkConfigFile, THUNKCONFIG);
       FEX_CONFIG_OPT(DumpIR, DUMPIR);
       FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
@@ -115,15 +237,13 @@ namespace FEXCore::Context {
       FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
       FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
       FEX_CONFIG_OPT(x87ReducedPrecision, X87REDUCEDPRECISION);
-      FEX_CONFIG_OPT(x86dec_SynchronizeRIPOnAllBlocks, X86DEC_SYNCHRONIZERIPONALLBLOCKS);
-      FEX_CONFIG_OPT(EnableAVX, ENABLEAVX);
     } Config;
 
     FEXCore::HostFeatures HostFeatures;
 
     std::mutex ThreadCreationMutex;
-    FEXCore::Core::InternalThreadState* ParentThread;
-    std::vector<FEXCore::Core::InternalThreadState*> Threads;
+    FEXCore::Core::InternalThreadState* ParentThread{};
+    fextl::vector<FEXCore::Core::InternalThreadState*> Threads;
     std::atomic_bool CoreShuttingDown{false};
     bool NeedToCheckXID{true};
 
@@ -139,48 +259,39 @@ namespace FEXCore::Context {
     FEXCore::CPUIDEmu CPUID;
     FEXCore::HLE::SyscallHandler *SyscallHandler{};
     FEXCore::HLE::SourcecodeResolver *SourcecodeResolver{};
-    std::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
-    std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
+    fextl::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
+    fextl::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
 
     CustomCPUFactoryType CustomCPUFactory;
     FEXCore::Context::ExitHandler CustomExitHandler;
 
 #ifdef BLOCKSTATS
-    std::unique_ptr<FEXCore::BlockSamplingData> BlockData;
+    fextl::unique_ptr<FEXCore::BlockSamplingData> BlockData;
 #endif
 
     SignalDelegator *SignalDelegation{};
     X86GeneratedCode X86CodeGen;
 
-    Context();
-    ~Context();
+    ContextImpl();
+    ~ContextImpl();
 
-    FEXCore::Core::InternalThreadState* InitCore(uint64_t InitialRIP, uint64_t StackPointer);
-    FEXCore::Context::ExitReason RunUntilExit();
-    int GetProgramStatus() const;
     bool IsPaused() const { return !Running; }
-    void Pause();
-    void Run();
     void WaitForThreadsToRun();
-    void Step();
     void Stop(bool IgnoreCurrentThread);
     void WaitForIdle();
-    void StopThread(FEXCore::Core::InternalThreadState *Thread);
     void SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event);
 
     bool GetGdbServerStatus() const { return DebugServer != nullptr; }
     void StartGdbServer();
     void StopGdbServer();
-    void HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
-    void RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
-    void RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
 
     static void ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
     static void ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker);
 
     template<auto Fn>
     static uint64_t ThreadExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {
-      FHU::ScopedSignalMaskWithSharedLock lk(Frame->Thread->CTX->CodeInvalidationMutex);
+      auto Thread = Frame->Thread;
+      ScopedDeferredSignalWithSharedLock lk(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
 
       return Fn(Frame, record);
     }
@@ -189,26 +300,16 @@ namespace FEXCore::Context {
     // Must be called from owning thread
     static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
       auto Thread = Frame->Thread;
-      
+
       LogMan::Throw::AFmt(Thread->ThreadManager.GetTID() == FHU::Syscalls::gettid(), "Must be called from owning thread {}, not {}", Thread->ThreadManager.GetTID(), FHU::Syscalls::gettid());
 
-      FHU::ScopedSignalMaskWithUniqueLock lk(Thread->CTX->CodeInvalidationMutex);
+      ScopedDeferredSignalWithUniqueLock lk(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
 
       ThreadRemoveCodeEntry(Thread, GuestRIP);
     }
 
-    // returns false if a handler was already registered
-    CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator, void *Data);
-
     void RemoveCustomIREntrypoint(uintptr_t Entrypoint);
 
-    // Debugger interface
-    void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
-    uint64_t GetThreadCount() const;
-    FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(uint64_t Thread);
-    bool GetDebugDataForRIP(uint64_t RIP, FEXCore::Core::DebugData *Data);
-    bool FindHostCodeForRIP(uint64_t RIP, uint8_t **Code);
-
     struct GenerateIRResult {
       FEXCore::IR::IRListView* IRList;
       FEXCore::IR::RegisterAllocationData::UniquePtr RAData;
@@ -235,29 +336,6 @@ namespace FEXCore::Context {
     void CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
 
     // Used for thread creation from syscalls
-    /**
-     * @brief Used to create FEX thread objects in preparation for creating a true OS thread. Does set a TID or PID.
-     *
-     * @param NewThreadState The initial thread state to setup for our state
-     * @param ParentTID The PID that was the parent thread that created this
-     *
-     * @return The InternalThreadState object that tracks all of the emulated thread's state
-     *
-     * Usecases:
-     *  OS thread Creation:
-     *    - Thread = CreateThread(NewState, PPID);
-     *    - InitializeThread(Thread);
-     *  OS fork (New thread created with a clone of thread state):
-     *    - clone{2, 3}
-     *    - Thread = CreateThread(CopyOfThreadState, PPID);
-     *    - ExecutionThread(Thread); // Starts executing without creating another host thread
-     *  Thunk callback executing guest code from native host thread
-     *    - Thread = CreateThread(NewState, PPID);
-     *    - InitializeThreadTLSData(Thread);
-     *    - HandleCallback(Thread, RIP);
-     */
-    FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID);
-
     /**
      * @brief Initializes TID, PID and TLS data for a thread
      *
@@ -265,76 +343,57 @@ namespace FEXCore::Context {
      */
     void InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread);
 
-    /**
-     * @brief Initializes the OS thread object and prepares to start executing on that new OS thread
-     *
-     * @param Thread The internal FEX thread state object
-     *
-     * The OS thread will wait until RunThread is executed
-     */
-    void InitializeThread(FEXCore::Core::InternalThreadState *Thread);
-
-    /**
-     * @brief Starts the OS thread object to start executing guest code
-     *
-     * @param Thread The internal FEX thread state object
-     */
-    void RunThread(FEXCore::Core::InternalThreadState *Thread);
-
-    /**
-     * @brief Destroys this FEX thread object and stops tracking it internally
-     *
-     * @param Thread The internal FEX thread state object
-     */
-    void DestroyThread(FEXCore::Core::InternalThreadState *Thread);
     void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread);
 
-    void CleanupAfterFork(FEXCore::Core::InternalThreadState *ExceptForThread);
-
-    std::vector<FEXCore::Core::InternalThreadState*>* GetThreads() { return &Threads; }
+    fextl::vector<FEXCore::Core::InternalThreadState*>* GetThreads() { return &Threads; }
 
     uint8_t GetGPRSize() const { return Config.Is64BitMode ? 8 : 4; }
 
-    IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(const std::string &filename);
-    void UnloadAOTIRCacheEntry(IR::AOTIRCacheEntry *Entry);
-
     FEXCore::JITSymbols Symbols;
 
-    // Public for threading
-    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);
+    void GetVDSOSigReturn(VDSOSigReturn *VDSOPointers) override {
+      if (VDSOPointers->VDSO_kernel_sigreturn == nullptr) {
+        VDSOPointers->VDSO_kernel_sigreturn = reinterpret_cast<void*>(X86CodeGen.sigreturn_32);
+      }
 
-    void FinalizeAOTIRCache() {
-      IRCaptureCache.FinalizeAOTIRCache();
+      if (VDSOPointers->VDSO_kernel_rt_sigreturn == nullptr) {
+        VDSOPointers->VDSO_kernel_rt_sigreturn = reinterpret_cast<void*>(X86CodeGen.rt_sigreturn_32);
+      }
     }
 
-    void WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
-      IRCaptureCache.WriteFilesWithCode(Writer);
+    void IncrementIdleRefCount() override {
+      ++IdleWaitRefCount;
     }
 
-    void SetAOTIRLoader(std::function<int(const std::string&)> CacheReader) {
-      IRCaptureCache.SetAOTIRLoader(CacheReader);
+    FEXCore::Utils::PooledAllocatorVirtual OpDispatcherAllocator;
+    FEXCore::Utils::PooledAllocatorVirtual FrontendAllocator;
+
+    // If Atomic-based TSO emulation is enabled or not.
+    bool IsAtomicTSOEnabled() const { return AtomicTSOEmulationEnabled; }
+
+    void SetHardwareTSOSupport(bool HardwareTSOSupported) override {
+      SupportsHardwareTSO = HardwareTSOSupported;
+      UpdateAtomicTSOEmulationConfig();
     }
 
-    void SetAOTIRWriter(std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) {
-      IRCaptureCache.SetAOTIRWriter(CacheWriter);
-    }
+    void EnableExitOnHLT() override { ExitOnHLT = true; }
 
-    void SetAOTIRRenamer(std::function<void(const std::string&)> CacheRenamer) {
-      IRCaptureCache.SetAOTIRRenamer(CacheRenamer);
-    }
-
-    void AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions);
-
-    FEXCore::Utils::PooledAllocatorMMap OpDispatcherAllocator;
-    FEXCore::Utils::PooledAllocatorMMap FrontendAllocator;
-
-    void MarkMemoryShared();
-
-    bool IsTSOEnabled() { return (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled; }
+    bool ExitOnHLTEnabled() const { return ExitOnHLT; }
 
   protected:
     void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread);
 
+    void UpdateAtomicTSOEmulationConfig() {
+      if (SupportsHardwareTSO) {
+        // If the hardware supports TSO then we don't need to emulate it through atomics.
+        AtomicTSOEmulationEnabled = false;
+      }
+      else {
+        // Atomic TSO emulation only enabled if the config option is enabled.
+        AtomicTSOEmulationEnabled = (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled;
+      }
+    }
+
   private:
     /**
      * @brief Does some final thread initialization
@@ -362,17 +421,20 @@ namespace FEXCore::Context {
 
     // Entry Cache
     std::mutex ExitMutex;
-    std::unique_ptr<GdbServer> DebugServer;
+    fextl::unique_ptr<GdbServer> DebugServer;
 
     IR::AOTIRCaptureCache IRCaptureCache;
-    std::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;
+    fextl::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;
 
     bool StartPaused = false;
     bool IsMemoryShared = false;
+    bool SupportsHardwareTSO = false;
+    bool AtomicTSOEmulationEnabled = true;
+    bool ExitOnHLT = false;
     FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
 
     std::shared_mutex CustomIRMutex;
-    std::unordered_map<uint64_t, std::tuple<std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)>, void *, void *>> CustomIRHandlers;
+    fextl::unordered_map<uint64_t, std::tuple<std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)>, void *, void *>> CustomIRHandlers;
     FEXCore::CPU::CPUBackendFeatures BackendFeatures;
     FEXCore::CPU::DispatcherConfig DispatcherConfig;
   };

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -1,9 +1,12 @@
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "FEXCore/Utils/AllocatorHooks.h"
+#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Context/Context.h"
 #include "Interface/HLE/Thunks/Thunks.h"
 
 #include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
 
@@ -19,39 +22,45 @@
 namespace FEXCore::CPU {
 
 // We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
-Arm64Emitter::Arm64Emitter(FEXCore::Context::Context *ctx, size_t size)
-  : vixl::aarch64::Assembler(size ? (byte*)FEXCore::Allocator::mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0) : reinterpret_cast<byte*>(~0ULL),
-                             size,
-                             vixl::aarch64::PositionDependentCode)
+Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, size_t size)
+  : Emitter(size ? (uint8_t*)FEXCore::Allocator::VirtualAlloc(size, true) : nullptr, size)
   , EmitterCTX {ctx} {
   CPU.SetUp();
 
-#ifdef VIXL_SIMULATOR
-  auto Features = vixl::CPUFeatures::All();
-#else
-  auto Features = vixl::CPUFeatures::InferFromOS();
-  if (ctx->HostFeatures.SupportsAtomics) {
-    // Hypervisor can hide this on the c630?
-    Features.Combine(vixl::CPUFeatures::Feature::kLORegions);
+  // Number of register available is dependent on what operating mode the proccess is in.
+  if (EmitterCTX->Config.Is64BitMode()) {
+    ConfiguredGPRs = NumGPRs64;
+    ConfiguredSRAGPRs = NumSRAGPRs64;
+    ConfiguredGPRPairs = NumGPRPairs64;
+    ConfiguredFPRs = NumFPRs64;
+    ConfiguredSRAFPRs = NumSRAFPRs64;
+    ConfiguredDynamicGPRs = NumGPRs64 - NumGPRs64; // Will be zero, just to be consistent with 32-bit side
+    ConfiguredDynamicRegisterBase = nullptr;
+  }
+  else {
+    ConfiguredGPRs = NumGPRs32;
+    ConfiguredSRAGPRs = NumSRAGPRs32;
+    ConfiguredGPRPairs = NumGPRPairs32;
+    ConfiguredFPRs = NumFPRs32;
+    ConfiguredSRAFPRs = NumSRAFPRs32;
+    ConfiguredDynamicGPRs = NumGPRs32 - NumGPRs64; // Will be 8
+    ConfiguredDynamicRegisterBase = &RA64[9];
   }
-#endif
-
-  SetCPUFeatures(Features);
 }
 
 Arm64Emitter::~Arm64Emitter() {
-  auto CodeBuffer = GetBuffer();
-  if (CodeBuffer->GetCapacity()) {
-    FEXCore::Allocator::munmap(CodeBuffer->GetStartAddress<void*>(), CodeBuffer->GetCapacity());
+  auto BufferSize = GetBufferSize();
+  if (BufferSize) {
+    FEXCore::Allocator::VirtualFree(GetBufferBase(), BufferSize);
   }
 }
 
-void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant, bool NOPPad) {
-  bool Is64Bit = Reg.IsX();
+void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad) {
+  bool Is64Bit = s == ARMEmitter::Size::i64Bit;
   int Segments = Is64Bit ? 4 : 2;
 
   if (Is64Bit && ((~Constant)>> 16) == 0) {
-    movn(Reg, (~Constant) & 0xFFFF);
+    movn(s, Reg, (~Constant) & 0xFFFF);
 
     if (NOPPad) {
       nop(); nop(); nop();
@@ -98,17 +107,17 @@ void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant,
       else {
         // Need to use ADRP + ADD
         adrp(Reg, AlignedOffset >> 12);
-        add(Reg, Reg, Constant & 0xFFF);
+        add(s, Reg, Reg, Constant & 0xFFF);
         NumMoves = 2;
       }
     }
   }
   else {
-    movz(Reg, (Constant) & 0xFFFF, 0);
+    movz(s, Reg, (Constant) & 0xFFFF, 0);
     for (int i = 1; i < Segments; ++i) {
       uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
       if (Part) {
-        movk(Reg, Part, i * 16);
+        movk(s, Reg, Part, i * 16);
         ++NumMoves;
       }
     }
@@ -124,126 +133,149 @@ void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant,
 void Arm64Emitter::PushCalleeSavedRegisters() {
   // We need to save pairs of registers
   // We save r19-r30
-  MemOperand PairOffset(sp, -16, PreIndex);
-  const std::array<std::pair<vixl::aarch64::Register, vixl::aarch64::Register>, 6> CalleeSaved = {{
-    {x19, x20},
-    {x21, x22},
-    {x23, x24},
-    {x25, x26},
-    {x27, x28},
-    {x29, x30},
+  const fextl::vector<std::pair<ARMEmitter::XRegister, ARMEmitter::XRegister>> CalleeSaved = {{
+#ifdef _WIN32
+    // Platform register, Just save it twice to make logic easy.
+    {ARMEmitter::XReg::x18, ARMEmitter::XReg::x18},
+#endif
+    {ARMEmitter::XReg::x19, ARMEmitter::XReg::x20},
+    {ARMEmitter::XReg::x21, ARMEmitter::XReg::x22},
+    {ARMEmitter::XReg::x23, ARMEmitter::XReg::x24},
+    {ARMEmitter::XReg::x25, ARMEmitter::XReg::x26},
+    {ARMEmitter::XReg::x27, ARMEmitter::XReg::x28},
+    {ARMEmitter::XReg::x29, ARMEmitter::XReg::x30},
   }};
 
   for (auto &RegPair : CalleeSaved) {
-    stp(RegPair.first, RegPair.second, PairOffset);
+    stp<ARMEmitter::IndexType::PRE>(RegPair.first, RegPair.second, ARMEmitter::Reg::rsp, -16);
   }
 
   // Additionally we need to store the lower 64bits of v8-v15
   // Here's a fun thing, we can use two ST4 instructions to store everything
   // We just need a single sub to sp before that
   const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v8, v9, v10, v11},
-    {v12, v13, v14, v15},
+    std::tuple<ARMEmitter::DRegister,
+               ARMEmitter::DRegister,
+               ARMEmitter::DRegister,
+               ARMEmitter::DRegister>, 2> FPRs = {{
+    {ARMEmitter::DReg::d8, ARMEmitter::DReg::d9, ARMEmitter::DReg::d10, ARMEmitter::DReg::d11},
+    {ARMEmitter::DReg::d12, ARMEmitter::DReg::d13, ARMEmitter::DReg::d14, ARMEmitter::DReg::d15},
   }};
 
   uint32_t VectorSaveSize = sizeof(uint64_t) * 8;
-  sub(sp, sp, VectorSaveSize);
+  sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, VectorSaveSize);
   // SP supporting move
   // We just saved x19 so it is safe
-  add(x19, sp, 0);
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r19, ARMEmitter::Reg::rsp, 0);
 
-  MemOperand QuadOffset(x19, 32, PostIndex);
   for (auto &RegQuad : FPRs) {
-    st4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
+    st4(ARMEmitter::SubRegSize::i64Bit,
+        std::get<0>(RegQuad),
+        std::get<1>(RegQuad),
+        std::get<2>(RegQuad),
+        std::get<3>(RegQuad),
         0,
-        QuadOffset);
+        ARMEmitter::Reg::r19,
+        32);
   }
 }
 
 void Arm64Emitter::PopCalleeSavedRegisters() {
   const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v12, v13, v14, v15},
-    {v8, v9, v10, v11},
+    std::tuple<ARMEmitter::DRegister,
+               ARMEmitter::DRegister,
+               ARMEmitter::DRegister,
+               ARMEmitter::DRegister>, 2> FPRs = {{
+    {ARMEmitter::DReg::d12, ARMEmitter::DReg::d13, ARMEmitter::DReg::d14, ARMEmitter::DReg::d15},
+    {ARMEmitter::DReg::d8, ARMEmitter::DReg::d9, ARMEmitter::DReg::d10, ARMEmitter::DReg::d11},
   }};
 
-  MemOperand QuadOffset(sp, 32, PostIndex);
   for (auto &RegQuad : FPRs) {
-    ld4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
+    ld4(ARMEmitter::SubRegSize::i64Bit,
+        std::get<0>(RegQuad),
+        std::get<1>(RegQuad),
+        std::get<2>(RegQuad),
+        std::get<3>(RegQuad),
         0,
-        QuadOffset);
+        ARMEmitter::Reg::rsp,
+        32);
   }
 
-  MemOperand PairOffset(sp, 16, PostIndex);
-  const std::array<std::pair<vixl::aarch64::Register, vixl::aarch64::Register>, 6> CalleeSaved = {{
-    {x29, x30},
-    {x27, x28},
-    {x25, x26},
-    {x23, x24},
-    {x21, x22},
-    {x19, x20},
+  const fextl::vector<std::pair<ARMEmitter::XRegister, ARMEmitter::XRegister>> CalleeSaved = {{
+    {ARMEmitter::XReg::x29, ARMEmitter::XReg::x30},
+    {ARMEmitter::XReg::x27, ARMEmitter::XReg::x28},
+    {ARMEmitter::XReg::x25, ARMEmitter::XReg::x26},
+    {ARMEmitter::XReg::x23, ARMEmitter::XReg::x24},
+    {ARMEmitter::XReg::x21, ARMEmitter::XReg::x22},
+    {ARMEmitter::XReg::x19, ARMEmitter::XReg::x20},
+#ifdef _WIN32
+    // Platform register.
+    {ARMEmitter::XReg::x18, ARMEmitter::XReg::zr},
+#endif
   }};
 
   for (auto &RegPair : CalleeSaved) {
-    ldp(RegPair.first, RegPair.second, PairOffset);
+    ldp<ARMEmitter::IndexType::POST>(RegPair.first, RegPair.second, ARMEmitter::Reg::rsp, 16);
   }
 }
 
+void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) {
+  if (!StaticRegisterAllocation()) {
+    return;
+  }
 
-void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) {
-  if (StaticRegisterAllocation()) {
-    for (size_t i = 0; i < SRA64.size(); i+=2) {
-      auto Reg1 = SRA64[i];
-      auto Reg2 = SRA64[i+1];
-      if (((1U << Reg1.GetCode()) & GPRSpillMask) &&
-          ((1U << Reg2.GetCode()) & GPRSpillMask)) {
-        stp(Reg1, Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
-      }
-      else if (((1U << Reg1.GetCode()) & GPRSpillMask)) {
-        str(Reg1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
-      }
-      else if (((1U << Reg2.GetCode()) & GPRSpillMask)) {
-        str(Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1])));
-      }
+  for (size_t i = 0; i < ConfiguredSRAGPRs; i+=2) {
+    auto Reg1 = SRA64[i];
+    auto Reg2 = SRA64[i+1];
+    if (((1U << Reg1.Idx()) & GPRSpillMask) &&
+        ((1U << Reg2.Idx()) & GPRSpillMask)) {
+      stp<ARMEmitter::IndexType::OFFSET>(Reg1.X(), Reg2.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i]));
     }
+    else if (((1U << Reg1.Idx()) & GPRSpillMask)) {
+      str(Reg1.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i]));
+    }
+    else if (((1U << Reg2.Idx()) & GPRSpillMask)) {
+      str(Reg2.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1]));
+    }
+  }
 
-    if (FPRs) {
-      if (EmitterCTX->HostFeatures.SupportsAVX) {
-        for (size_t i = 0; i < SRAFPR.size(); i++) {
-          const auto Reg = SRAFPR[i];
+  if (FPRs) {
+    if (EmitterCTX->HostFeatures.SupportsAVX) {
+      for (size_t i = 0; i < ConfiguredSRAFPRs; i++) {
+        const auto Reg = SRAFPR[i];
 
-          if (((1U << Reg.GetCode()) & FPRSpillMask) != 0) {
-            mov(TMP4, offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
-            st1b(Reg.Z().VnB(), PRED_TMP_32B, SVEMemOperand(STATE, TMP4));
-          }
+        if (((1U << Reg.Idx()) & FPRSpillMask) != 0) {
+          mov(ARMEmitter::Size::i64Bit, TMP4.R(), offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
+          st1b<ARMEmitter::SubRegSize::i8Bit>(Reg.Z(), PRED_TMP_32B, STATE.R(), TMP4.R());
         }
-      } else {
-        for (size_t i = 0; i < SRAFPR.size(); i += 2) {
+      }
+    } else {
+      if (GPRSpillMask && FPRSpillMask == ~0U) {
+        // Optimize the common case where we can spill four registers per instruction
+        // Load the sse offset in to the temporary register
+        add(ARMEmitter::Size::i64Bit, TmpReg, STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[0][0]));
+        for (size_t i = 0; i < ConfiguredSRAFPRs; i += 4) {
+          const auto Reg1 = SRAFPR[i];
+          const auto Reg2 = SRAFPR[i + 1];
+          const auto Reg3 = SRAFPR[i + 2];
+          const auto Reg4 = SRAFPR[i + 3];
+          st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64);
+        }
+      }
+      else {
+        for (size_t i = 0; i < ConfiguredSRAFPRs; i += 2) {
           const auto Reg1 = SRAFPR[i];
           const auto Reg2 = SRAFPR[i + 1];
 
-          if (((1U << Reg1.GetCode()) & FPRSpillMask) &&
-              ((1U << Reg2.GetCode()) & FPRSpillMask)) {
-            stp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
+          if (((1U << Reg1.Idx()) & FPRSpillMask) &&
+              ((1U << Reg2.Idx()) & FPRSpillMask)) {
+            stp<ARMEmitter::IndexType::OFFSET>(Reg1.Q(), Reg2.Q(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0]));
           }
-          else if (((1U << Reg1.GetCode()) & FPRSpillMask)) {
-            str(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
+          else if (((1U << Reg1.Idx()) & FPRSpillMask)) {
+            str(Reg1.Q(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0]));
           }
-          else if (((1U << Reg2.GetCode()) & FPRSpillMask)) {
-            str(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i+1][0])));
+          else if (((1U << Reg2.Idx()) & FPRSpillMask)) {
+            str(Reg2.Q(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i+1][0]));
           }
         }
       }
@@ -252,126 +284,153 @@ void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t GPRSpillMask, uint32_t FP
 }
 
 void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRFillMask) {
-  if (StaticRegisterAllocation()) {
-    for (size_t i = 0; i < SRA64.size(); i+=2) {
-      auto Reg1 = SRA64[i];
-      auto Reg2 = SRA64[i+1];
-      if (((1U << Reg1.GetCode()) & GPRFillMask) &&
-          ((1U << Reg2.GetCode()) & GPRFillMask)) {
-        ldp(Reg1, Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
-      }
-      else if (((1U << Reg1.GetCode()) & GPRFillMask)) {
-        ldr(Reg1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
-      }
-      else if (((1U << Reg2.GetCode()) & GPRFillMask)) {
-        ldr(Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1])));
-      }
-    }
+  if (!StaticRegisterAllocation()) {
+    return;
+  }
 
-    if (FPRs) {
-      if (EmitterCTX->HostFeatures.SupportsAVX) {
-        // Set up predicate registers.
-        // We don't bother spilling these in SpillStaticRegs,
-        // since all that matters is we restore them on a fill.
-        // It's not a concern if they get trounced by something else.
-        ptrue(PRED_TMP_16B.VnB(), SVE_VL16);
-        ptrue(PRED_TMP_32B.VnB(), SVE_VL32);
+  if (FPRs) {
+    if (EmitterCTX->HostFeatures.SupportsAVX) {
+      // Set up predicate registers.
+      // We don't bother spilling these in SpillStaticRegs,
+      // since all that matters is we restore them on a fill.
+      // It's not a concern if they get trounced by something else.
+      ptrue<ARMEmitter::SubRegSize::i8Bit>(PRED_TMP_16B, ARMEmitter::PredicatePattern::SVE_VL16);
+      ptrue<ARMEmitter::SubRegSize::i8Bit>(PRED_TMP_32B, ARMEmitter::PredicatePattern::SVE_VL32);
 
-        for (size_t i = 0; i < SRAFPR.size(); i++) {
-          const auto Reg = SRAFPR[i];
-
-          if (((1U << Reg.GetCode()) & FPRFillMask) != 0) {
-            mov(TMP4, offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
-            ld1b(Reg.Z().VnB(), PRED_TMP_32B.Zeroing(), SVEMemOperand(STATE, TMP4));
-          }
+      for (size_t i = 0; i < ConfiguredSRAFPRs; i++) {
+        const auto Reg = SRAFPR[i];
+        if (((1U << Reg.Idx()) & FPRFillMask) != 0) {
+          mov(ARMEmitter::Size::i64Bit, TMP4.R(), offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
+          ld1b<ARMEmitter::SubRegSize::i8Bit>(Reg.Z(), PRED_TMP_32B.Zeroing(), STATE.R(), TMP4.R());
         }
-      } else {
-        for (size_t i = 0; i < SRAFPR.size(); i += 2) {
+      }
+    } else {
+      if (GPRFillMask && FPRFillMask == ~0U) {
+        // Optimize the common case where we can fill four registers per instruction.
+        // Use one of the filling static registers before we fill it.
+        auto TmpReg = SRA64[FindFirstSetBit(GPRFillMask)];
+
+        // Load the sse offset in to the temporary register
+        add(ARMEmitter::Size::i64Bit, TmpReg, STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[0][0]));
+        for (size_t i = 0; i < ConfiguredSRAFPRs; i += 4) {
+          const auto Reg1 = SRAFPR[i];
+          const auto Reg2 = SRAFPR[i + 1];
+          const auto Reg3 = SRAFPR[i + 2];
+          const auto Reg4 = SRAFPR[i + 3];
+          ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64);
+        }
+      }
+      else {
+        for (size_t i = 0; i < ConfiguredSRAFPRs; i += 2) {
           const auto Reg1 = SRAFPR[i];
           const auto Reg2 = SRAFPR[i + 1];
 
-          if (((1U << Reg1.GetCode()) & FPRFillMask) &&
-              ((1U << Reg2.GetCode()) & FPRFillMask)) {
-            ldp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
+          if (((1U << Reg1.Idx()) & FPRFillMask) &&
+              ((1U << Reg2.Idx()) & FPRFillMask)) {
+            ldp<ARMEmitter::IndexType::OFFSET>(Reg1.Q(), Reg2.Q(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0]));
           }
-          else if (((1U << Reg1.GetCode()) & FPRFillMask)) {
-            ldr(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
+          else if (((1U << Reg1.Idx()) & FPRFillMask)) {
+            ldr(Reg1.Q(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0]));
           }
-          else if (((1U << Reg2.GetCode()) & FPRFillMask)) {
-            ldr(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i+1][0])));
+          else if (((1U << Reg2.Idx()) & FPRFillMask)) {
+            ldr(Reg2.Q(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i+1][0]));
           }
         }
       }
     }
   }
+
+  for (size_t i = 0; i < ConfiguredSRAGPRs; i+=2) {
+    auto Reg1 = SRA64[i];
+    auto Reg2 = SRA64[i+1];
+    if (((1U << Reg1.Idx()) & GPRFillMask) &&
+        ((1U << Reg2.Idx()) & GPRFillMask)) {
+      ldp<ARMEmitter::IndexType::OFFSET>(Reg1.X(), Reg2.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i]));
+    }
+    else if ((1U << Reg1.Idx()) & GPRFillMask) {
+      ldr(Reg1.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i]));
+    }
+    else if ((1U << Reg2.Idx()) & GPRFillMask) {
+      ldr(Reg2.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1]));
+    }
+  }
 }
 
-void Arm64Emitter::PushDynamicRegsAndLR() {
+void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
   const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
-  const auto GPRSize = (RA64.size() + 1) * Core::CPUState::GPR_REG_SIZE;
+  const auto GPRSize = (ConfiguredDynamicGPRs + 1) * Core::CPUState::GPR_REG_SIZE;
   const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE
                                     : Core::CPUState::XMM_SSE_REG_SIZE;
-  const auto FPRSize = RAFPR.size() * FPRRegSize;
+  const auto FPRSize = ConfiguredFPRs * FPRRegSize;
   const uint64_t SPOffset = AlignUp(GPRSize + FPRSize, 16);
 
-  sub(sp, sp, SPOffset);
-  int i = 0;
+  sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, SPOffset);
+
+  // rsp capable move
+  add(ARMEmitter::Size::i64Bit, TmpReg, ARMEmitter::Reg::rsp, 0);
 
   if (CanUseSVE) {
-    for (const auto& RA : RAFPR) {
-      mov(TMP4, i * 8);
-      st1b(RA.Z().VnB(), PRED_TMP_32B, SVEMemOperand(sp, TMP4));
-      i += 4;
+    for (size_t i = 0; i < ConfiguredFPRs; i += 4) {
+      const auto Reg1 = RAFPR[i];
+      const auto Reg2 = RAFPR[i + 1];
+      const auto Reg3 = RAFPR[i + 2];
+      const auto Reg4 = RAFPR[i + 3];
+      st4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B, TmpReg, 0);
+      add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 4);
     }
   } else {
-    for (const auto& RA : RAFPR) {
-      str(RA.Q(), MemOperand(sp, i * 8));
-      i += 2;
+    LOGMAN_THROW_AA_FMT(ConfiguredFPRs % 4 == 0, "Needs to have multiple of 4 FPRs for RA");
+    for (size_t i = 0; i < ConfiguredFPRs; i += 4) {
+      const auto Reg1 = RAFPR[i];
+      const auto Reg2 = RAFPR[i + 1];
+      const auto Reg3 = RAFPR[i + 2];
+      const auto Reg4 = RAFPR[i + 3];
+      st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64);
     }
   }
 
-#if 0 // All GPRs should be caller saved
-  for (const auto& RA : RA64) {
-    str(RA, MemOperand(sp, i * 8));
-    i++;
+  if (ConfiguredDynamicRegisterBase) {
+    for (size_t i = 0; i < ConfiguredDynamicGPRs; i += 2) {
+      const auto Reg1 = ConfiguredDynamicRegisterBase[i];
+      const auto Reg2 = ConfiguredDynamicRegisterBase[i + 1];
+      stp<ARMEmitter::IndexType::POST>(Reg1.X(), Reg2.X(), TmpReg, 16);
+    }
   }
-#endif
 
-  str(lr, MemOperand(sp, i * 8));
+  str(ARMEmitter::XReg::lr, TmpReg, 0);
 }
 
 void Arm64Emitter::PopDynamicRegsAndLR() {
   const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
-  const auto GPRSize = (RA64.size() + 1) * Core::CPUState::GPR_REG_SIZE;
-  const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE
-                                    : Core::CPUState::XMM_SSE_REG_SIZE;
-  const auto FPRSize = RAFPR.size() * FPRRegSize;
-  const uint64_t SPOffset = AlignUp(GPRSize + FPRSize, 16);
-  int i = 0;
 
   if (CanUseSVE) {
-    for (const auto& RA : RAFPR) {
-      mov(TMP4, i * 8);
-      ld1b(RA.Z().VnB(), PRED_TMP_32B.Zeroing(), SVEMemOperand(sp, TMP4));
-      i += 4;
+    for (size_t i = 0; i < ConfiguredFPRs; i += 4) {
+      const auto Reg1 = RAFPR[i];
+      const auto Reg2 = RAFPR[i + 1];
+      const auto Reg3 = RAFPR[i + 2];
+      const auto Reg4 = RAFPR[i + 3];
+      ld4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp);
+      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 4);
     }
   } else {
-    for (const auto& RA : RAFPR) {
-      ldr(RA.Q(), MemOperand(sp, i * 8));
-      i += 2;
+    for (size_t i = 0; i < ConfiguredFPRs; i += 4) {
+      const auto Reg1 = RAFPR[i];
+      const auto Reg2 = RAFPR[i + 1];
+      const auto Reg3 = RAFPR[i + 2];
+      const auto Reg4 = RAFPR[i + 3];
+      ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), ARMEmitter::Reg::rsp, 64);
     }
   }
 
-#if 0 // All GPRs should be caller saved
-  for (const auto& RA : RA64) {
-    ldr(RA, MemOperand(sp, i * 8));
-    i++;
+  if (ConfiguredDynamicRegisterBase) {
+    for (size_t i = 0; i < ConfiguredDynamicGPRs; i += 2) {
+      const auto Reg1 = ConfiguredDynamicRegisterBase[i];
+      const auto Reg2 = ConfiguredDynamicRegisterBase[i + 1];
+      ldp<ARMEmitter::IndexType::POST>(Reg1.X(), Reg2.X(), ARMEmitter::Reg::rsp, 16);
+    }
   }
-#endif
 
-  ldr(lr, MemOperand(sp, i * 8));
-
-  add(sp, sp, SPOffset);
+  ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
 }
 
 void Arm64Emitter::Align16B() {

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h

@@ -1,5 +1,9 @@
 #pragma once
 
+#include "FEXCore/Utils/EnumUtils.h"
+#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
+#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
+
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/ObjectCache/Relocations.h"
 
@@ -8,6 +12,9 @@
 #include <aarch64/cpu-aarch64.h>
 #include <aarch64/operands-aarch64.h>
 #include <platform-vixl.h>
+#ifdef VIXL_DISASSEMBLER
+#include <aarch64/disasm-aarch64.h>
+#endif
 #ifdef VIXL_SIMULATOR
 #include <aarch64/simulator-aarch64.h>
 #include <aarch64/simulator-constants-aarch64.h>
@@ -21,98 +28,179 @@
 #include <utility>
 
 namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
+// Register x18 is unused in the current configuration.
+// This is due to it being a platform register on wine platforms.
+// TODO: Allow x18 register allocation in the future to gain one more register.
 
-// All but x29 are caller saved
-const std::array<aarch64::Register, 16> SRA64 = {
-  x4, x5, x6, x7, x8, x9, x10, x11,
-  x12, x18, x17, x16, x15, x14, x13, x29
+// All but x19 and x29 are caller saved
+constexpr std::array<FEXCore::ARMEmitter::Register, 16> SRA64 = {
+  FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
+  FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7,
+  FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r9,
+  FEXCore::ARMEmitter::Reg::r10, FEXCore::ARMEmitter::Reg::r11,
+  // Registers that don't exist on 32-bit
+  FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13,
+  FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15,
+  FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
+  FEXCore::ARMEmitter::Reg::r19, FEXCore::ARMEmitter::Reg::r29
 };
 
-// All are callee saved
-const std::array<aarch64::Register, 9> RA64 = {
-  x20, x21, x22, x23, x24, x25, x26, x27,
-  x19
+constexpr std::array<FEXCore::ARMEmitter::Register, 9 + 8> RA64 = {
+  // All these callee saved
+  FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21,
+  FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23,
+  FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25,
+  FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27,
+  FEXCore::ARMEmitter::Reg::r30,
+
+  // Registers only available on 32-bit
+  // All these are caller saved (except for r19).
+  FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13,
+  FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15,
+  FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
+  FEXCore::ARMEmitter::Reg::r19, FEXCore::ARMEmitter::Reg::r29
 };
 
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4>  RA64Pair = {{
-  {x20, x21},
-  {x22, x23},
-  {x24, x25},
-  {x26, x27},
-}};
+constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 4 + 3> RA64Pair = {{
+  {FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21},
+  {FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23},
+  {FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25},
+  {FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27},
 
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4> RA32Pair = {{
-  {w20, w21},
-  {w22, w23},
-  {w24, w25},
-  {w26, w27},
+  // Registers only available on 32-bit
+  {FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13},
+  {FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15},
+  {FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17}
 }};
 
 // All are caller saved
-const std::array<aarch64::VRegister, 16> SRAFPR = {
-  v16, v17, v18, v19, v20, v21, v22, v23,
-  v24, v25, v26, v27, v28, v29, v30, v31
+constexpr std::array<FEXCore::ARMEmitter::VRegister, 16> SRAFPR = {
+  FEXCore::ARMEmitter::VReg::v16, FEXCore::ARMEmitter::VReg::v17,
+  FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19,
+  FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21,
+  FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23,
+
+  // Registers that don't exist on 32-bit
+  FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25,
+  FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
+  FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29,
+  FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31
 };
 
 //  v8..v15 = (lower 64bits) Callee saved
-const std::array<aarch64::VRegister, 12> RAFPR = {
-/*v0,  v1,  v2,  v3,*/v4,  v5,  v6,  v7,  // v0 ~ v3 are used as temps
-  v8,  v9,  v10, v11, v12, v13, v14, v15
+constexpr std::array<FEXCore::ARMEmitter::VRegister, 12 + 8> RAFPR = {
+  // v0 ~ v3 are used as temps.
+  // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
+  // FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
+
+  FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
+  FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+  FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
+  FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11,
+  FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
+  FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+
+  // Registers only available on 32-bit
+  FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25,
+  FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
+  FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29,
+  FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31
 };
 
 // Contains the address to the currently available CPU state
-#define STATE x28
+constexpr auto STATE = FEXCore::ARMEmitter::XReg::x28;
 
 // GPR temporaries. Only x3 can be used across spill boundaries
 // so if these ever need to change, be very careful about that.
-#define TMP1 x0
-#define TMP2 x1
-#define TMP3 x2
-#define TMP4 x3
+constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x0;
+constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x1;
+constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x2;
+constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x3;
 
 // Vector temporaries
-#define VTMP1 v1
-#define VTMP2 v2
-#define VTMP3 v3
+constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v0;
+constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1;
+constexpr auto VTMP3 = FEXCore::ARMEmitter::VReg::v2;
+constexpr auto VTMP4 = FEXCore::ARMEmitter::VReg::v3;
 
 // Predicate register temporaries (used when AVX support is enabled)
 // PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1.
 // PRED_TMP_32B indicates a predicate register that indicates the first 32 bytes set to 1.
-#define PRED_TMP_16B p6
-#define PRED_TMP_32B p7
+constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_16B = FEXCore::ARMEmitter::PReg::p6;
+constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_32B = FEXCore::ARMEmitter::PReg::p7;
 
 // This class contains common emitter utility functions that can
 // be used by both Arm64 JIT and ARM64 Dispatcher
-class Arm64Emitter : public vixl::aarch64::Assembler {
+class Arm64Emitter : public FEXCore::ARMEmitter::Emitter {
 protected:
-  Arm64Emitter(FEXCore::Context::Context *ctx, size_t size);
+  Arm64Emitter(FEXCore::Context::ContextImpl *ctx, size_t size);
   ~Arm64Emitter();
 
-  FEXCore::Context::Context *EmitterCTX;
+  FEXCore::Context::ContextImpl *EmitterCTX;
   vixl::aarch64::CPU CPU;
-  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant, bool NOPPad = false);
+
+  uint32_t ConfiguredGPRs;
+  uint32_t ConfiguredSRAGPRs;
+  uint32_t ConfiguredGPRPairs;
+  uint32_t ConfiguredFPRs;
+  uint32_t ConfiguredSRAFPRs;
+  uint32_t ConfiguredDynamicGPRs;
+  const FEXCore::ARMEmitter::Register *ConfiguredDynamicRegisterBase{};
+
+  /**
+   * @name Register Allocation
+   * @{ */
+  // 64-bit gets removal of additional pairs
+  constexpr static uint32_t NumGPRs64       = RA64.size() - 8;
+  constexpr static uint32_t NumSRAGPRs64    = SRA64.size();
+  constexpr static uint32_t NumFPRs64       = RAFPR.size() - 8;
+  constexpr static uint32_t NumSRAFPRs64    = SRAFPR.size();
+  constexpr static uint32_t NumGPRPairs64   = RA64Pair.size() - 3;
+
+  // 32-bit gets full array of GPR registers
+  // SRA registers remove the additional 8
+  constexpr static uint32_t NumGPRs32       = RA64.size();
+  constexpr static uint32_t NumSRAGPRs32    = SRA64.size() - 8;
+  constexpr static uint32_t NumFPRs32       = RAFPR.size();
+  constexpr static uint32_t NumSRAFPRs32    = SRAFPR.size() - 8;
+  constexpr static uint32_t NumGPRPairs32   = RA64Pair.size();
+
+  constexpr static uint32_t RegisterClasses = 6;
+
+  constexpr static uint64_t GPRBase = (0ULL << 32);
+  constexpr static uint64_t FPRBase = (1ULL << 32);
+  constexpr static uint64_t GPRPairBase = (2ULL << 32);
+
+  /**  @} */
+
+  constexpr static uint8_t RA_32 = 0;
+  constexpr static uint8_t RA_64 = 1;
+  constexpr static uint8_t RA_FPR = 2;
+
+  void LoadConstant(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false);
+
 
   // NOTE: These functions WILL clobber the register TMP4 if AVX support is enabled
   //       and FPRs are being spilled or filled. If only GPRs are spilled/filled, then
   //       TMP4 is left alone.
-  void SpillStaticRegs(bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
+  void SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
   void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U);
 
-  static constexpr uint32_t CALLER_GPR_MASK = 0b0011'1111'1111'1111'1111;
+  // Register 0-18 + 29 + 30 are caller saved
+  static constexpr uint32_t CALLER_GPR_MASK = 0b0110'0000'0000'0111'1111'1111'1111'1111U;
 
   // This isn't technically true because the lower 64-bits of v8..v15 are callee saved
   // We can't guarantee only the lower 64bits are used so flush everything
   static constexpr uint32_t CALLER_FPR_MASK = ~0U;
 
-  void PushDynamicRegsAndLR();
+  void PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg);
   void PopDynamicRegsAndLR();
 
   void PushCalleeSavedRegisters();
   void PopCalleeSavedRegisters();
 
   void Align16B();
+
 #ifdef VIXL_SIMULATOR
   // Generates a vixl simulator runtime call.
   //
@@ -124,61 +212,64 @@ protected:
   // 2) Simulator wrapper handler
   // 3) Function to call
   // 4) Style of the function call (Call versus tail-call)
+
   template<typename R, typename... P>
   void GenerateRuntimeCall(R (*Function)(P...)) {
     uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));
+      &(vixl::aarch64::Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));
 
     uintptr_t FunctionAddress = reinterpret_cast<uintptr_t>(Function);
 
-    hlt(kRuntimeCallOpcode);
+    hlt(vixl::aarch64::kRuntimeCallOpcode);
 
     // Simulator wrapper address pointer.
-    dc(SimulatorWrapperAddress);
+    dc64(SimulatorWrapperAddress);
 
     // Runtime function address to call
-    dc(FunctionAddress);
+    dc64(FunctionAddress);
 
     // Call type
-    dc32(kCallRuntime);
+    dc32(vixl::aarch64::kCallRuntime);
   }
 
   template<typename R, typename... P>
-  void GenerateIndirectRuntimeCall(vixl::aarch64::Register Reg) {
+  void GenerateIndirectRuntimeCall(ARMEmitter::Register Reg) {
     uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));
+      &(vixl::aarch64::Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));
 
-    hlt(kIndirectRuntimeCallOpcode);
+    hlt(vixl::aarch64::kIndirectRuntimeCallOpcode);
 
     // Simulator wrapper address pointer.
-    dc(SimulatorWrapperAddress);
+    dc64(SimulatorWrapperAddress);
 
     // Register that contains the function to call
-    dc(Reg.GetCode());
+    dc32(Reg.Idx());
 
     // Call type
-    dc32(kCallRuntime);
+    dc32(vixl::aarch64::kCallRuntime);
   }
 
   template<>
-  void GenerateIndirectRuntimeCall<float, __uint128_t>(vixl::aarch64::Register Reg) {
+  void GenerateIndirectRuntimeCall<float, __uint128_t>(ARMEmitter::Register Reg) {
     uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(Simulator::RuntimeCallStructHelper<float, __uint128_t>::Wrapper));
+      &(vixl::aarch64::Simulator::RuntimeCallStructHelper<float, __uint128_t>::Wrapper));
 
-    hlt(kIndirectRuntimeCallOpcode);
+    hlt(vixl::aarch64::kIndirectRuntimeCallOpcode);
 
     // Simulator wrapper address pointer.
-    dc(SimulatorWrapperAddress);
+    dc64(SimulatorWrapperAddress);
 
     // Register that contains the function to call
-    dc(Reg.GetCode());
+    dc32(Reg.Idx());
 
     // Call type
-    dc32(kCallRuntime);
+    dc32(vixl::aarch64::kCallRuntime);
   }
 
 #endif
-
+#ifdef VIXL_DISASSEMBLER
+  vixl::aarch64::PrintDisassembler Disasm {stderr};
+#endif
   FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
 };
 

External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl

@@ -0,0 +1,991 @@
+/* ALU instruction emitters.
+ *
+ * Almost all of these operations have `ARMEmitter::Size` as their first argument.
+ * This allows both 32-bit and 64-bit selection of how that instruction is going to operate.
+ *
+ * Some emitter operations explicitly use `XRegister` or `WRegister`.
+ * This is usually due to the instruction only supporting one operating size.
+ * Although in some cases is a minor convenience without any performance implications.
+ *
+ * FEX-Emu ALU operations usually have a 32-bit or 64-bit operating size encoded in the IR operation,
+ * This allows FEX to use a single helper function which decodes to both handlers.
+ */
+private:
+  static bool IsADRRange(int64_t Imm) {
+    return Imm >= -1048576 && Imm <= 1048575;
+  }
+  static bool IsADRPRange(int64_t Imm) {
+    return Imm >= -4294967296 && Imm <= 4294963200;
+  }
+  static bool IsADRPAligned(int64_t Imm) {
+    return (Imm & 0xFFF) == 0;
+  }
+public:
+  // PC relative
+  void adr(FEXCore::ARMEmitter::Register rd, uint32_t Imm) {
+    constexpr uint32_t Op = 0b0001'0000 << 24;
+    DataProcessing_PCRel_Imm(Op, rd, Imm);
+  }
+
+  void adr(FEXCore::ARMEmitter::Register rd, BackwardLabel const* Label) {
+    int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+    LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large");
+
+    constexpr uint32_t Op = 0b0001'0000 << 24;
+    DataProcessing_PCRel_Imm(Op, rd, Imm);
+  }
+  void adr(FEXCore::ARMEmitter::Register rd, ForwardLabel *Label) {
+    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::ADR });
+    constexpr uint32_t Op = 0b0001'0000 << 24;
+    DataProcessing_PCRel_Imm(Op, rd, 0);
+  }
+
+  void adr(FEXCore::ARMEmitter::Register rd, BiDirectionalLabel *Label) {
+    if (Label->Backward.Location) {
+      adr(rd, &Label->Backward);
+    }
+    else {
+      adr(rd, &Label->Forward);
+    }
+  }
+
+  void adrp(FEXCore::ARMEmitter::Register rd, uint32_t Imm) {
+    constexpr uint32_t Op = 0b1001'0000 << 24;
+    DataProcessing_PCRel_Imm(Op, rd, Imm);
+  }
+
+  void adrp(FEXCore::ARMEmitter::Register rd, BackwardLabel const* Label) {
+    int64_t Imm = reinterpret_cast<int64_t>(Label->Location) - (GetCursorAddress<int64_t>() & ~0xFFFLL);
+    LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large");
+
+    constexpr uint32_t Op = 0b1001'0000 << 24;
+    DataProcessing_PCRel_Imm(Op, rd, Imm);
+  }
+  void adrp(FEXCore::ARMEmitter::Register rd, ForwardLabel *Label) {
+    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::ADRP });
+    constexpr uint32_t Op = 0b1001'0000 << 24;
+    DataProcessing_PCRel_Imm(Op, rd, 0);
+  }
+
+  void adrp(FEXCore::ARMEmitter::Register rd, BiDirectionalLabel *Label) {
+    if (Label->Backward.Location) {
+      adrp(rd, &Label->Backward);
+    }
+    else {
+      adrp(rd, &Label->Forward);
+    }
+  }
+
+  void LongAddressGen(FEXCore::ARMEmitter::Register rd, BackwardLabel const* Label) {
+    int64_t Imm = reinterpret_cast<int64_t>(Label->Location) - (GetCursorAddress<int64_t>());
+    if (IsADRRange(Imm)) {
+      // If the range is in ADR range then we can just use ADR.
+      adr(rd, Label);
+    }
+    else if (IsADRPRange(Imm)) {
+      int64_t ADRPImm = (reinterpret_cast<int64_t>(Label->Location) & ~0xFFFLL)
+        - (GetCursorAddress<int64_t>() & ~0xFFFLL);
+
+      // If the range is in the ADRP range then we can use ADRP.
+      bool NeedsOffset = !IsADRPAligned(reinterpret_cast<uint64_t>(Label->Location));
+      uint64_t AlignedOffset = reinterpret_cast<uint64_t>(Label->Location) & 0xFFFULL;
+
+      // First emit ADRP
+      adrp(rd, ADRPImm >> 12);
+
+      if (NeedsOffset) {
+        // Now even an add
+        add(ARMEmitter::Size::i64Bit, rd, rd, AlignedOffset);
+      }
+    }
+    else {
+      LOGMAN_MSG_A_FMT("Unscaled offset too large");
+      FEX_UNREACHABLE;
+    }
+  }
+  void LongAddressGen(FEXCore::ARMEmitter::Register rd, ForwardLabel* Label) {
+    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::LONG_ADDRESS_GEN });
+    // Emit a register index and a nop. These will be backpatched.
+    dc32(rd.Idx());
+    nop();
+  }
+
+  void LongAddressGen(FEXCore::ARMEmitter::Register rd, BiDirectionalLabel *Label) {
+    if (Label->Backward.Location) {
+      LongAddressGen(rd, &Label->Backward);
+    }
+    else {
+      LongAddressGen(rd, &Label->Forward);
+    }
+  }
+
+  // Add/subtract immediate
+  void add(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
+    constexpr uint32_t Op = 0b0001'0001'0 << 23;
+    DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
+  }
+
+  void adds(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
+    constexpr uint32_t Op = 0b0011'0001'0 << 23;
+    DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
+  }
+
+  void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
+    constexpr uint32_t Op = 0b0101'0001'0 << 23;
+    DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
+  }
+
+  void cmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
+    constexpr uint32_t Op = 0b0111'0001'0 << 23;
+    DataProcessing_AddSub_Imm(Op, s, FEXCore::ARMEmitter::Reg::rsp, rn, Imm, LSL12);
+  }
+
+  void subs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
+    constexpr uint32_t Op = 0b0111'0001'0 << 23;
+    DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
+  }
+
+  // Logical immediate
+  void and_(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    uint32_t n, immr, imms;
+    [[maybe_unused]] const auto IsImm = vixl::aarch64::Assembler::IsImmLogical(Imm,
+                           RegSizeInBits(s),
+                           &n,
+                           &imms,
+                           &immr);
+    LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
+    and_(s, rd, rn, n, immr, imms);
+  }
+
+  void bic(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    and_(s, rd, rn, ~Imm);
+  }
+
+  void ands(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    uint32_t n, immr, imms;
+    [[maybe_unused]] const auto IsImm = vixl::aarch64::Assembler::IsImmLogical(Imm,
+                           RegSizeInBits(s),
+                           &n,
+                           &imms,
+                           &immr);
+    LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
+    ands(s, rd, rn, n, immr, imms);
+  }
+
+  void bics(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    ands(s, rd, rn, ~Imm);
+  }
+
+  void orr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    uint32_t n, immr, imms;
+    [[maybe_unused]] const auto IsImm = vixl::aarch64::Assembler::IsImmLogical(Imm,
+                           RegSizeInBits(s),
+                           &n,
+                           &imms,
+                           &immr);
+    LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
+    orr(s, rd, rn, n, immr, imms);
+  }
+
+  void eor(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    uint32_t n, immr, imms;
+    [[maybe_unused]] const auto IsImm = vixl::aarch64::Assembler::IsImmLogical(Imm,
+                           RegSizeInBits(s),
+                           &n,
+                           &imms,
+                           &immr);
+    LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
+    eor(s, rd, rn, n, immr, imms);
+  }
+
+  // Move wide immediate
+  void movn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) {
+    LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid");
+    LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned");
+
+    constexpr uint32_t Op = 0b001'0010'100 << 21;
+    DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4);
+  }
+  void mov(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm) {
+    movz(s, rd, Imm, 0);
+  }
+  void mov(FEXCore::ARMEmitter::XRegister rd, uint32_t Imm) {
+    movz(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), Imm, 0);
+  }
+  void mov(FEXCore::ARMEmitter::WRegister rd, uint32_t Imm) {
+    movz(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), Imm, 0);
+  }
+
+  void movz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) {
+    LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid");
+    LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned");
+
+    constexpr uint32_t Op = 0b101'0010'100 << 21;
+    DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4);
+  }
+  void movk(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) {
+    LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid");
+    LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned");
+
+    constexpr uint32_t Op = 0b111'0010'100 << 21;
+    DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4);
+  }
+
+  void movn(FEXCore::ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) {
+    movn(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset);
+  }
+  void movz(FEXCore::ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) {
+    movz(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset);
+  }
+  void movk(FEXCore::ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) {
+    movk(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset);
+  }
+  void movn(FEXCore::ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) {
+    movn(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset);
+  }
+  void movz(FEXCore::ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) {
+    movz(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset);
+  }
+  void movk(FEXCore::ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) {
+    movk(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset);
+  }
+
+  // Bitfield
+  void sxtb(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    sbfm(s, rd, rn, 0, 7);
+  }
+  void sxth(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    sbfm(s, rd, rn, 0, 15);
+  }
+  void sxtw(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn) {
+    sbfm(ARMEmitter::Size::i64Bit, rd, rn.X(), 0, 31);
+  }
+  void sbfx(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t lsb, uint32_t width) {
+    LOGMAN_THROW_A_FMT(width > 0, "sbfx needs width > 0");
+    LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to sbfx a region larger than the register");
+    sbfm(s, rd, rn, lsb, lsb + width - 1);
+  }
+  void asr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t shift) {
+    LOGMAN_THROW_A_FMT(shift <= RegSizeInBits(s), "Tried to asr a region larger than the register");
+    sbfm(s, rd, rn, shift, RegSizeInBits(s) - 1);
+  }
+
+  void uxtb(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    ubfm(s, rd, rn, 0, 7);
+  }
+  void uxth(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    ubfm(s, rd, rn, 0, 15);
+  }
+  void uxtw(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    ubfm(s, rd, rn, 0, 31);
+  }
+
+  void ubfm(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t immr, uint32_t imms) {
+    constexpr uint32_t Op = 0b0101'0011'00 << 22;
+    DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms);
+  }
+
+  void lsl(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t shift) {
+    const auto RegSize = RegSizeInBits(s);
+    LOGMAN_THROW_A_FMT(shift < RegSize, "Tried to lsl a region larger than the register");
+    ubfm(s, rd, rn, (RegSize - shift) % RegSize, RegSize - shift - 1);
+  }
+  void lsr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t shift) {
+    const auto RegSize = RegSizeInBits(s);
+    LOGMAN_THROW_A_FMT(shift < RegSize, "Tried to lsr a region larger than the register");
+    ubfm(s, rd, rn, shift, RegSize - 1);
+  }
+  void ubfx(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t lsb, uint32_t width) {
+    LOGMAN_THROW_A_FMT(width > 0, "ubfx needs width > 0");
+    LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to ubfx a region larger than the register");
+    ubfm(s, rd, rn, lsb, lsb + width - 1);
+  }
+
+  void bfi(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t lsb, uint32_t width) {
+    const auto RegSize = RegSizeInBits(s);
+    LOGMAN_THROW_A_FMT(width > 0, "bfi needs width > 0");
+    LOGMAN_THROW_A_FMT((lsb + width) <= RegSize, "Tried to bfi a region larger than the register");
+    bfm(s, rd, rn, (RegSize - lsb) & (RegSize - 1), width - 1);
+  }
+
+  // Extract
+  void extr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, uint32_t Imm) {
+    constexpr uint32_t Op = 0b001'0011'100 << 21;
+    LOGMAN_THROW_A_FMT(Imm < RegSizeInBits(s), "Tried to extr a region larger than the register");
+    DataProcessing_Extract(Op, s, rd, rn, rm, Imm);
+  }
+
+  void ror(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm) {
+    extr(s, rd, rn, rn, Imm);
+  }
+
+  // Data processing - 2 source
+  void udiv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0000'10U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+  void sdiv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0000'11U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+
+  void lslv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0010'00U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+  void lsrv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0010'01U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+  void asrv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0010'10U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+  void rorv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0010'11U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+  void crc32b(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0100'00U << 10);
+    DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
+  }
+  void crc32h(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0100'01U << 10);
+    DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
+  }
+  void crc32w(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0100'10U << 10);
+    DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
+  }
+  void crc32cb(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0101'00U << 10);
+    DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
+  }
+  void crc32ch(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0101'01U << 10);
+    DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
+  }
+  void crc32cw(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0101'10U << 10);
+    DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
+  }
+  void subp(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0000'00U << 10);
+    DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm);
+  }
+  void irg(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0001'00U << 10);
+    DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm);
+  }
+  void gmi(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0001'01U << 10);
+    DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm);
+  }
+  void pacga(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0011'00U << 10);
+    DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm);
+  }
+  void crc32x(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0100'11U << 10);
+    DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm);
+  }
+  void crc32cx(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0101'11U << 10);
+    DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm);
+  }
+  void subps(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = (0b011'1010'110U << 21) |
+                        (0b0000'00U << 10);
+    DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm);
+  }
+
+  // Data processing - 1 source
+  void rbit(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0000'00U << 10);
+    DataProcessing_1Source(Op, s, rd, rn);
+  }
+  void rev16(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0000'01U << 10);
+    DataProcessing_1Source(Op, s, rd, rn);
+  }
+  void rev(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0000'10U << 10);
+    DataProcessing_1Source(Op, FEXCore::ARMEmitter::Size::i32Bit, rd, rn);
+  }
+  void rev32(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0000'10U << 10);
+    DataProcessing_1Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn);
+  }
+  void clz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0001'00U << 10);
+    DataProcessing_1Source(Op, s, rd, rn);
+  }
+  void cls(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0001'01U << 10);
+    DataProcessing_1Source(Op, s, rd, rn);
+  }
+  void rev(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0000'11U << 10);
+    DataProcessing_1Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn);
+  }
+  void rev(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0000'10U << 10) |
+                        (s == ARMEmitter::Size::i64Bit ? (1U << 10) : 0);
+    DataProcessing_1Source(Op, s, rd, rn);
+  }
+
+
+  // TODO: PAUTH
+
+  // Logical - shifted register
+  void mov(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    orr(s, rd, FEXCore::ARMEmitter::Reg::zr, rn, ARMEmitter::ShiftType::LSL, 0);
+  }
+  void mov(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn) {
+    orr(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), FEXCore::ARMEmitter::Reg::zr, rn.R(), ARMEmitter::ShiftType::LSL, 0);
+  }
+  void mov(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn) {
+    orr(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), FEXCore::ARMEmitter::Reg::zr, rn.R(), ARMEmitter::ShiftType::LSL, 0);
+  }
+
+  void mvn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    orn(s, rd, FEXCore::ARMEmitter::Reg::zr, rn, Shift, amt);
+  }
+
+  void and_(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    constexpr uint32_t Op = 0b000'1010'000U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void ands(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    constexpr uint32_t Op = 0b110'1010'000U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void bic(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    constexpr uint32_t Op = 0b000'1010'001U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void bics(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    constexpr uint32_t Op = 0b110'1010'001U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void orr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    constexpr uint32_t Op = 0b010'1010'000U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+
+  void orn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    constexpr uint32_t Op = 0b010'1010'001U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void eor(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    constexpr uint32_t Op = 0b100'1010'000U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void eon(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    constexpr uint32_t Op = 0b100'1010'001U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+
+  // AddSub - shifted register
+  void add(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    add(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
+  }
+  void adds(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    adds(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
+  }
+  void sub(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    sub(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
+  }
+  void neg(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    sub(rd, FEXCore::ARMEmitter::XReg::zr, rm, Shift, amt);
+  }
+  void cmp(FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    subs(ARMEmitter::Size::i64Bit, FEXCore::ARMEmitter::Reg::rsp, rn.R(), rm.R(), Shift, amt);
+  }
+  void subs(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    subs(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
+  }
+  void negs(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    subs(rd, FEXCore::ARMEmitter::XReg::zr, rm, Shift, amt);
+  }
+
+  void add(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    add(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
+  }
+  void adds(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    adds(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
+  }
+  void sub(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    sub(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
+  }
+  void neg(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    sub(rd, FEXCore::ARMEmitter::WReg::zr, rm, Shift, amt);
+  }
+  void cmp(FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    subs(ARMEmitter::Size::i32Bit, FEXCore::ARMEmitter::Reg::rsp, rn.R(), rm.R(), Shift, amt);
+  }
+  void subs(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    subs(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
+  }
+  void negs(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    subs(rd, FEXCore::ARMEmitter::WReg::zr, rm, Shift, amt);
+  }
+
+  void add(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
+    constexpr uint32_t Op = 0b000'1011'000U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void adds(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
+    constexpr uint32_t Op = 0b010'1011'000U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
+    constexpr uint32_t Op = 0b100'1011'000U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void neg(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    sub(s, rd, FEXCore::ARMEmitter::Reg::zr, rm, Shift, amt);
+  }
+  void cmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    subs(s, FEXCore::ARMEmitter::Reg::zr, rn, rm, Shift, amt);
+  }
+
+  void subs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
+    constexpr uint32_t Op = 0b110'1011'000U << 21;
+    DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
+  }
+  void negs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    subs(s, rd, FEXCore::ARMEmitter::Reg::zr, rm, Shift, amt);
+  }
+
+  // AddSub - extended register
+  void add(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
+    LOGMAN_THROW_AA_FMT(Shift <= 4, "Shift amount is too large");
+    constexpr uint32_t Op = 0b000'1011'001U << 21;
+    DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
+  }
+  void adds(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
+    constexpr uint32_t Op = 0b010'1011'001U << 21;
+    DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
+  }
+  void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
+    constexpr uint32_t Op = 0b100'1011'001U << 21;
+    DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
+  }
+  void subs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
+    constexpr uint32_t Op = 0b110'1011'001U << 21;
+    DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
+  }
+  void cmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
+    constexpr uint32_t Op = 0b110'1011'001U << 21;
+    DataProcessing_Extended_Reg(Op, s, FEXCore::ARMEmitter::Reg::zr, rn, rm, Option, Shift);
+  }
+
+  // AddSub - with carry
+  void adc(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = 0b0001'1010'000U << 21;
+    DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0);
+  }
+  void adcs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = 0b0011'1010'000U << 21;
+    DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0);
+  }
+  void sbc(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = 0b0101'1010'000U << 21;
+    DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0);
+  }
+  void sbcs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = 0b0111'1010'000U << 21;
+    DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0);
+  }
+
+  // Rotate right into flags
+  void rmif(XRegister rn, uint32_t shift, uint32_t mask) {
+    LOGMAN_THROW_AA_FMT(shift <= 63, "Shift must be within 0-63. Shift: {}", shift);
+    LOGMAN_THROW_AA_FMT(mask <= 15, "Mask must be within 0-15. Mask: {}", mask);
+
+    uint32_t Op = 0b1011'1010'0000'0000'0000'0100'0000'0000;
+    Op |= rn.Idx() << 5;
+    Op |= shift << 15;
+    Op |= mask;
+
+    dc32(Op);
+  }
+
+  // Evaluate into flags
+  void setf8(WRegister rn) {
+    constexpr uint32_t Op = 0b0011'1010'0000'0000'0000'1000'0000'1101;
+    EvaluateIntoFlags(Op, 0, rn);
+  }
+  void setf16(WRegister rn) {
+    constexpr uint32_t Op = 0b0011'1010'0000'0000'0000'1000'0000'1101;
+    EvaluateIntoFlags(Op, 1, rn);
+  }
+
+  // Conditional compare - register
+  void ccmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) {
+    constexpr uint32_t Op = 0b0011'1010'010 << 21;
+    ConditionalCompare(Op, 0, 0b00, 0, s, rn, rm, flags, Cond);
+  }
+  void ccmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) {
+    constexpr uint32_t Op = 0b0011'1010'010 << 21;
+    ConditionalCompare(Op, 1, 0b00, 0, s, rn, rm, flags, Cond);
+  }
+
+  // Conditional compare - immediate
+  void ccmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, uint32_t rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) {
+    LOGMAN_THROW_A_FMT((rm & ~0b1'1111) == 0, "Comparison imm too large");
+    constexpr uint32_t Op = 0b0011'1010'010 << 21;
+    ConditionalCompare(Op, 0, 0b10, 0, s, rn, rm, flags, Cond);
+  }
+  void ccmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, uint32_t rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) {
+    LOGMAN_THROW_A_FMT((rm & ~0b1'1111) == 0, "Comparison imm too large");
+    constexpr uint32_t Op = 0b0011'1010'010 << 21;
+    ConditionalCompare(Op, 1, 0b10, 0, s, rn, rm, flags, Cond);
+  }
+
+  // Conditional select
+  void csel(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Condition Cond) {
+    constexpr uint32_t Op = 0b0001'1010'100 << 21;
+    ConditionalCompare(Op, 0, 0b00, s, rd, rn, rm, Cond);
+  }
+  void cset(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Condition Cond) {
+    constexpr uint32_t Op = 0b0001'1010'100 << 21;
+    ConditionalCompare(Op, 0, 0b01, s, rd, FEXCore::ARMEmitter::Reg::zr, FEXCore::ARMEmitter::Reg::zr, static_cast<FEXCore::ARMEmitter::Condition>(FEXCore::ToUnderlying(Cond) ^ FEXCore::ToUnderlying(FEXCore::ARMEmitter::Condition::CC_NE)));
+  }
+  void csinc(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Condition Cond) {
+    constexpr uint32_t Op = 0b0001'1010'100 << 21;
+    ConditionalCompare(Op, 0, 0b01, s, rd, rn, rm, Cond);
+  }
+  void csinv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Condition Cond) {
+    constexpr uint32_t Op = 0b0001'1010'100 << 21;
+    ConditionalCompare(Op, 1, 0b00, s, rd, rn, rm, Cond);
+  }
+  void csneg(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Condition Cond) {
+    constexpr uint32_t Op = 0b0001'1010'100 << 21;
+    ConditionalCompare(Op, 1, 0b01, s, rd, rn, rm, Cond);
+  }
+
+  // Data processing - 3 source
+  void madd(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Register ra) {
+    constexpr uint32_t Op = 0b001'1011'000U << 21;
+    DataProcessing_3Source(Op, 0, s, rd, rn, rm, ra);
+  }
+  void mul(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    madd(s, rd, rn, rm, XReg::zr);
+  }
+  void msub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Register ra) {
+    constexpr uint32_t Op = 0b001'1011'000U << 21;
+    DataProcessing_3Source(Op, 1, s, rd, rn, rm, ra);
+  }
+  void mneg(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    msub(s, rd, rn, rm, XReg::zr);
+  }
+  void smaddl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::XRegister ra) {
+    constexpr uint32_t Op = 0b001'1011'001U << 21;
+    DataProcessing_3Source(Op, 0, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, ra);
+  }
+  void smull(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    smaddl(rd, rn, rm, XReg::zr);
+  }
+  void smsubl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::XRegister ra) {
+    constexpr uint32_t Op = 0b001'1011'001U << 21;
+    DataProcessing_3Source(Op, 1, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, ra);
+  }
+  void smnegl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    smsubl(rd, rn, rm, XReg::zr);
+  }
+  void smulh(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = 0b001'1011'010U << 21;
+    DataProcessing_3Source(Op, 0, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, FEXCore::ARMEmitter::Reg::zr);
+  }
+  void umaddl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::XRegister ra) {
+    constexpr uint32_t Op = 0b001'1011'101U << 21;
+    DataProcessing_3Source(Op, 0, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, ra);
+  }
+  void umull(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    umaddl(rd, rn, rm, XReg::zr);
+  }
+  void umsubl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::XRegister ra) {
+    constexpr uint32_t Op = 0b001'1011'101U << 21;
+    DataProcessing_3Source(Op, 1, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, ra);
+  }
+  void umnegl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) {
+    umsubl(rd, rn, rm, XReg::zr);
+  }
+  void umulh(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
+    constexpr uint32_t Op = 0b001'1011'110U << 21;
+    DataProcessing_3Source(Op, 0, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, FEXCore::ARMEmitter::Reg::zr);
+  }
+
+private:
+  void and_(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
+    constexpr uint32_t Op = 0b001'0010'00 << 22;
+    DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
+  }
+  void ands(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
+    constexpr uint32_t Op = 0b111'0010'00 << 22;
+    DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
+  }
+  void orr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
+    constexpr uint32_t Op = 0b011'0010'00 << 22;
+    DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
+  }
+  void eor(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
+    constexpr uint32_t Op = 0b101'0010'00 << 22;
+    DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
+  }
+
+  void sbfm(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t immr, uint32_t imms) {
+    constexpr uint32_t Op = 0b0001'0011'00 << 22;
+    DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms);
+  }
+  void bfm(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t immr, uint32_t imms) {
+    constexpr uint32_t Op = 0b0011'0011'00 << 22;
+    DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms);
+  }
+  // 4.1.64 - Data processing - Immediate
+  void DataProcessing_PCRel_Imm(uint32_t Op, FEXCore::ARMEmitter::Register rd, uint32_t Imm) {
+    // Ensure the immediate is masked.
+    Imm &= 0b1'1111'1111'1111'1111'1111U;
+
+    uint32_t Instr = Op;
+
+    Instr |= (Imm & 0b11) << 29;
+    Instr |= (Imm >> 2) << 5;
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  void DataProcessing_AddSub_Imm(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12) {
+    bool TooLarge = (Imm & ~0b1111'1111'1111U) != 0;
+    if (TooLarge && !LSL12 && ((Imm >> 12) & ~0b1111'1111'1111U) == 0) {
+      // We can convert an immediate
+      TooLarge = false;
+      LSL12 = true;
+      Imm >>= 12;
+    }
+    LOGMAN_THROW_AA_FMT(TooLarge == false, "Imm amount too large: 0x{:x}", Imm);
+
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= LSL12 << 22;
+    Instr |= Imm << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  // Move Wide
+  void DataProcessing_MoveWide(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= Imm << 5;
+    Instr |= Offset << 21;
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  // Logical immediate
+  void DataProcessing_Logical_Imm(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= n << 22;
+    Instr |= immr << 16;
+    Instr |= imms << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  void DataProcessing_Extract(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, uint32_t Imm) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    // Current ARMv8 spec hardcodes SF == N for this class of instructions.
+    // Anythign else is undefined behaviour.
+    const uint32_t N  = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 22) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= N;
+    Instr |= Encode_rm(rm);
+    Instr |= Imm << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  // Data-processing - 2 source
+  void DataProcessing_2Source(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= Encode_rm(rm);
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  // Data processing - 1 source
+  template<typename T>
+  void DataProcessing_1Source(uint32_t Op, FEXCore::ARMEmitter::Size s, T rd, T rn) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  // AddSub - shifted register
+  void DataProcessing_Shifted_Reg(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift, uint32_t amt) {
+    LOGMAN_THROW_AA_FMT((amt & ~0b11'1111U) == 0, "Shift amount too large");
+
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= FEXCore::ToUnderlying(Shift) << 22;
+    Instr |= Encode_rm(rm);
+    Instr |= static_cast<uint32_t>(amt) << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  // AddSub - extended register
+  void DataProcessing_Extended_Reg(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= Encode_rm(rm);
+    Instr |= FEXCore::ToUnderlying(Option) << 13;
+    Instr |= static_cast<uint32_t>(Shift) << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+  // Conditional compare - register
+  template<typename T>
+  void ConditionalCompare(uint32_t Op, uint32_t o1, uint32_t o2, uint32_t o3, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, T rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= o1 << 30;
+    Instr |= Encode_rm(rm);
+    Instr |= FEXCore::ToUnderlying(Cond) << 12;
+    Instr |= o2 << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= o3 << 4;
+    Instr |= FEXCore::ToUnderlying(flags);
+
+    dc32(Instr);
+  }
+
+  template<typename T>
+  void ConditionalCompare(uint32_t Op, uint32_t o1, uint32_t o2, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, T rm, FEXCore::ARMEmitter::Condition Cond) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= o1 << 30;
+    Instr |= Encode_rm(rm);
+    Instr |= FEXCore::ToUnderlying(Cond) << 12;
+    Instr |= o2 << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  // Data-processing - 3 source
+  void DataProcessing_3Source(uint32_t Op, uint32_t Op0, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Register ra) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = Op;
+
+    Instr |= SF;
+    Instr |= Encode_rm(rm);
+    Instr |= Op0 << 15;
+    Instr |= Encode_ra(ra);
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
+  void EvaluateIntoFlags(uint32_t op, uint32_t size, WRegister rn) {
+    uint32_t Instr = op;
+    Instr |= size << 14;
+    Instr |= rn.Idx() << 5;
+    dc32(Instr);
+  }
+
+

External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/BranchOps.inl

@@ -0,0 +1,322 @@
+/* Branch instruction emitters.
+ *
+ * Most of these instructions will use `BackwardLabel`, `ForwardLabel`, or `BiDirectionLabel` to determine where a branch targets.
+ */
+public:
+  // Branches, Exception Generating and System instructions
+  public:
+    // Conditional branch immediate
+    ///< Branch conditional
+    void b(FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+      constexpr uint32_t Op = 0b0101'010 << 25;
+      Branch_Conditional(Op, 0, 0, Cond, Imm);
+    }
+    void b(FEXCore::ARMEmitter::Condition Cond, BackwardLabel const* Label) {
+      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+      constexpr uint32_t Op = 0b0101'010 << 25;
+      Branch_Conditional(Op, 0, 0, Cond, Imm >> 2);
+    }
+    void b(FEXCore::ARMEmitter::Condition Cond, ForwardLabel *Label) {
+      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::BC });
+      constexpr uint32_t Op = 0b0101'010 << 25;
+      Branch_Conditional(Op, 0, 0, Cond, 0);
+    }
+
+    void b(FEXCore::ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
+      if (Label->Backward.Location) {
+        b(Cond, &Label->Backward);
+      }
+      else {
+        b(Cond, &Label->Forward);
+      }
+    }
+
+    ///< Branch consistent conditional
+    void bc(FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+      constexpr uint32_t Op = 0b0101'010 << 25;
+      Branch_Conditional(Op, 0, 1, Cond, Imm);
+    }
+    void bc(FEXCore::ARMEmitter::Condition Cond, BackwardLabel const* Label) {
+      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+      constexpr uint32_t Op = 0b0101'010 << 25;
+      Branch_Conditional(Op, 0, 1, Cond, Imm >> 2);
+    }
+
+    void bc(FEXCore::ARMEmitter::Condition Cond, ForwardLabel *Label) {
+      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::BC });
+      constexpr uint32_t Op = 0b0101'010 << 25;
+      Branch_Conditional(Op, 0, 1, Cond, 0);
+    }
+
+    void bc(FEXCore::ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
+      if (Label->Backward.Location) {
+        bc(Cond, &Label->Backward);
+      }
+      else {
+        bc(Cond, &Label->Forward);
+      }
+    }
+
+    // Unconditional branch register
+    void br(FEXCore::ARMEmitter::Register rn) {
+      constexpr uint32_t Op = 0b1101011 << 25 |
+                              0b0'000 << 21 |   // opc
+                              0b1'1111 << 16 |  // op2
+                              0b0000'00 << 10 | // op3
+                              0b0'0000;         // op4
+
+      UnconditionalBranch(Op, rn);
+    }
+    void blr(FEXCore::ARMEmitter::Register rn) {
+      constexpr uint32_t Op = 0b1101011 << 25 |
+                              0b0'001 << 21 |   // opc
+                              0b1'1111 << 16 |  // op2
+                              0b0000'00 << 10 | // op3
+                              0b0'0000;         // op4
+
+      UnconditionalBranch(Op, rn);
+    }
+    void ret(FEXCore::ARMEmitter::Register rn = FEXCore::ARMEmitter::Reg::r30) {
+      constexpr uint32_t Op = 0b1101011 << 25 |
+                              0b0'010 << 21 |   // opc
+                              0b1'1111 << 16 |  // op2
+                              0b0000'00 << 10 | // op3
+                              0b0'0000;         // op4
+
+      UnconditionalBranch(Op, rn);
+    }
+
+    // Unconditional branch immediate
+    void b(uint32_t Imm) {
+      constexpr uint32_t Op = 0b0001'01 << 26;
+
+      UnconditionalBranch(Op, Imm);
+    }
+    void b(BackwardLabel const* Label) {
+      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+      LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+      constexpr uint32_t Op = 0b0001'01 << 26;
+
+      UnconditionalBranch(Op, Imm >> 2);
+    }
+    void b(ForwardLabel *Label) {
+      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::B });
+      constexpr uint32_t Op = 0b0001'01 << 26;
+
+      UnconditionalBranch(Op, 0);
+    }
+
+    void b(BiDirectionalLabel *Label) {
+      if (Label->Backward.Location) {
+        b(&Label->Backward);
+      }
+      else {
+        b(&Label->Forward);
+      }
+    }
+
+    void bl(uint32_t Imm) {
+      constexpr uint32_t Op = 0b1001'01 << 26;
+
+      UnconditionalBranch(Op, Imm);
+    }
+
+    void bl(BackwardLabel const* Label) {
+      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+      LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+      constexpr uint32_t Op = 0b1001'01 << 26;
+
+      UnconditionalBranch(Op, Imm >> 2);
+    }
+    void bl(ForwardLabel *Label) {
+      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::B });
+      constexpr uint32_t Op = 0b1001'01 << 26;
+
+      UnconditionalBranch(Op, 0);
+    }
+
+    void bl(BiDirectionalLabel *Label) {
+      if (Label->Backward.Location) {
+        bl(&Label->Backward);
+      }
+      else {
+        bl(&Label->Forward);
+      }
+    }
+
+    // Compare and branch
+    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
+      constexpr uint32_t Op = 0b0011'0100 << 24;
+
+      CompareAndBranch(Op, s, rt, Imm);
+    }
+
+    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BackwardLabel const* Label) {
+      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+
+      constexpr uint32_t Op = 0b0011'0100 << 24;
+
+      CompareAndBranch(Op, s, rt, Imm >> 2);
+    }
+
+    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, ForwardLabel *Label) {
+      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::BC });
+
+      constexpr uint32_t Op = 0b0011'0100 << 24;
+
+      CompareAndBranch(Op, s, rt, 0);
+    }
+
+    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BiDirectionalLabel *Label) {
+      if (Label->Backward.Location) {
+        cbz(s, rt, &Label->Backward);
+      }
+      else {
+        cbz(s, rt, &Label->Forward);
+      }
+    }
+
+    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
+      constexpr uint32_t Op = 0b0011'0101 << 24;
+
+      CompareAndBranch(Op, s, rt, Imm);
+    }
+
+    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BackwardLabel const* Label) {
+      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+
+      constexpr uint32_t Op = 0b0011'0101 << 24;
+
+      CompareAndBranch(Op, s, rt, Imm >> 2);
+    }
+
+    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, ForwardLabel *Label) {
+      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::BC });
+
+      constexpr uint32_t Op = 0b0011'0101 << 24;
+
+      CompareAndBranch(Op, s, rt, 0);
+    }
+
+    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BiDirectionalLabel *Label) {
+      if (Label->Backward.Location) {
+        cbnz(s, rt, &Label->Backward);
+      }
+      else {
+        cbnz(s, rt, &Label->Forward);
+      }
+    }
+
+    // Test and branch immediate
+    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+      constexpr uint32_t Op = 0b0011'0110 << 24;
+
+      TestAndBranch(Op, rt, Bit, Imm);
+    }
+    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
+      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+      LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+
+      constexpr uint32_t Op = 0b0011'0110 << 24;
+
+      TestAndBranch(Op, rt, Bit, Imm >> 2);
+    }
+    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, ForwardLabel *Label) {
+      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::TEST_BRANCH });
+
+      constexpr uint32_t Op = 0b0011'0110 << 24;
+
+      TestAndBranch(Op, rt, Bit, 0);
+    }
+
+    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
+      if (Label->Backward.Location) {
+        tbz(rt, Bit, &Label->Backward);
+      }
+      else {
+        tbz(rt, Bit, &Label->Forward);
+      }
+    }
+
+    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+      constexpr uint32_t Op = 0b0011'0111 << 24;
+
+      TestAndBranch(Op, rt, Bit, Imm);
+    }
+    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
+      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+      LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+
+      constexpr uint32_t Op = 0b0011'0111 << 24;
+
+      TestAndBranch(Op, rt, Bit, Imm >> 2);
+    }
+    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, ForwardLabel *Label) {
+      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::TEST_BRANCH });
+      constexpr uint32_t Op = 0b0011'0111 << 24;
+
+      TestAndBranch(Op, rt, Bit, 0);
+    }
+
+    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
+      if (Label->Backward.Location) {
+        tbnz(rt, Bit, &Label->Backward);
+      }
+      else {
+        tbnz(rt, Bit, &Label->Forward);
+      }
+    }
+
+private:
+    // Conditional branch immediate
+    void Branch_Conditional(uint32_t Op, uint32_t Op1, uint32_t Op0, FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+      uint32_t Instr = Op;
+
+      Instr |= Op1 << 24;
+      Instr |= (Imm & 0x7'FFFF) << 5;
+      Instr |= Op0 << 4;
+      Instr |= FEXCore::ToUnderlying(Cond);
+
+      dc32(Instr);
+    }
+
+    // Unconditional branch register
+    void UnconditionalBranch(uint32_t Op, FEXCore::ARMEmitter::Register rn) {
+      uint32_t Instr = Op;
+      Instr |= Encode_rn(rn);
+      dc32(Instr);
+    }
+
+    // Unconditional branch - immediate
+    void UnconditionalBranch(uint32_t Op, uint32_t Imm) {
+      uint32_t Instr = Op;
+      Instr |= Imm & 0x3FF'FFFF;
+      dc32(Instr);
+    }
+
+    // Compare and branch
+    void CompareAndBranch(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
+      const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+      uint32_t Instr = Op;
+
+      Instr |= SF;
+      Instr |= (Imm & 0x7'FFFF) << 5;
+      Instr |= Encode_rt(rt);
+      dc32(Instr);
+    }
+
+    // Test and branch - immediate
+    void TestAndBranch(uint32_t Op, FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+      uint32_t Instr = Op;
+
+      Instr |= (Bit >> 5) << 31;
+      Instr |= (Bit & 0b1'1111) << 19;
+      Instr |= (Imm & 0x3FFF) << 5;
+      Instr |= Encode_rt(rt);
+      dc32(Instr);
+    }

External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Buffer.h

@@ -0,0 +1,105 @@
+#pragma once
+#include <cstddef>
+#include <cstdint>
+#include <cstring>
+
+namespace FEXCore::ARMEmitter {
+  class Buffer {
+    public:
+      Buffer() {
+        SetBuffer(nullptr, 0);
+      }
+
+      Buffer(uint8_t* Base, uint64_t BaseSize) {
+        SetBuffer(Base, BaseSize);
+      }
+
+      void SetBuffer(uint8_t* Base, uint64_t BaseSize) {
+        BufferBase = Base;
+        CurrentOffset = BufferBase;
+        Size = BaseSize;
+      }
+
+      void dc8(uint8_t Data) {
+        decltype(Data) *Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
+        *Memory = Data;
+        CurrentOffset += sizeof(Data);
+      }
+
+      void dc16(uint16_t Data) {
+        decltype(Data) *Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
+        *Memory = Data;
+        CurrentOffset += sizeof(Data);
+      }
+
+      void dc32(uint32_t Data) {
+        decltype(Data) *Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
+        *Memory = Data;
+        CurrentOffset += sizeof(Data);
+      }
+
+      void dc64(uint64_t Data) {
+        decltype(Data) *Memory = reinterpret_cast<decltype(Data)*>(CurrentOffset);
+        *Memory = Data;
+        CurrentOffset += sizeof(Data);
+      }
+      void EmitString(const char *String) {
+        const auto StringLength = strlen(String);
+        memcpy(CurrentOffset, String, StringLength);
+        CurrentOffset += StringLength;
+      }
+
+      void Align() {
+        // Align the buffer to instruction size
+        auto CurrentAlignment = reinterpret_cast<uint64_t>(CurrentOffset) & 0b11;
+        if (!CurrentAlignment) {
+          return;
+        }
+        CurrentOffset += 4 - CurrentAlignment;
+      }
+
+      template<typename T>
+      T GetCursorAddress() const {
+        return reinterpret_cast<T>(CurrentOffset);
+      }
+
+      static void ClearICache(void* Begin, std::size_t Length) {
+        __builtin___clear_cache(static_cast<char*>(Begin), static_cast<char*>(Begin) + Length);
+      }
+
+      size_t GetCursorOffset() const {
+        return static_cast<size_t>(CurrentOffset - BufferBase);
+      }
+
+      uint8_t *GetBufferBase() const {
+        return BufferBase;
+      }
+
+      void CursorIncrement(size_t Size) {
+        CurrentOffset += Size;
+      }
+
+      void SetCursorOffset(size_t Offset) {
+        CurrentOffset = BufferBase + Offset;
+      }
+
+      uint64_t GetBufferSize() const {
+        return Size;
+      }
+
+      template<typename T>
+      size_t GetCursorOffsetFromAddress(const T* Address) const {
+        return static_cast<size_t>(reinterpret_cast<const uint8_t*>(Address) - BufferBase);
+      }
+
+    protected:
+
+      void ResetBuffer() {
+        CurrentOffset = BufferBase;
+      }
+
+      uint8_t* BufferBase;
+      uint8_t* CurrentOffset;
+      uint64_t Size;
+  };
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Emitter.h

@@ -0,0 +1,780 @@
+#pragma once
+
+#include "Interface/Core/ArchHelpers/CodeEmitter/Buffer.h"
+#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
+
+#include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/EnumUtils.h>
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/vector.h>
+
+#include <aarch64/assembler-aarch64.h>
+
+#include <cstdint>
+#include <utility>
+#include <type_traits>
+
+/*
+ * Welcome to FEX-Emu's custom AArch64 emitter.
+ * This was written specifically to avoid the performance cost of the vixl emitter.
+ *
+ * There are some specific design constraints in this design to target a couple features:
+ *   - High performance
+ *   - Low CPU cache performance hit
+ *   - Significantly reduced code footprint
+ *   - Low number of branches
+ *
+ * These requirements are mostly achieved by removing a bunch of developer conveniences
+ * that vixl provides. The developer needs to take a lot of care to not shoot themselves in the foot.
+ *
+ * Misc design decisions:
+ * - Registers are encoded as basic uint32_t enums.
+ *   - Converting between different registers is zero-cost.
+ *   - Passing around as arguments are as cheap as registers
+ *     - Contrast to vixl where every register requires living on the stack.
+ *   - Registers can get encoded in to instructions with a simple `BFM` instruction.
+ *
+ * - Instructions are very simply emitted, allowing direct inlining most of the time.
+ *   - These are simple enough that multiple back-to-back instructions get optimized to 128-bit load-store operations.
+ *     - Contrast to vixl where pretty much no instruction emitter gets inlined.
+ *
+ * - Instruction emitters are /mostly/ unsized. Most instructions take a size argument first, which gets encoded
+ *   directly in to the instruction.
+ *   - Contrast to vixl where the register arguments are how the instructions determine operating size.
+ *   - Size argument allows FEX to use `CSEL` to select a size at runtime, instead of branching.
+ *   - Some instructions are explicitly sized based on register type. Read comments in the respective `inl` files to
+ *     see why.
+ *     Some scalar/vector operations are an example of this.
+ *
+ * - Almost zero helper functions.
+ *   - Primary exception to this rule is load-store operations. These will use a helper to make
+ *     it easier to select the correct load-store instruction. Mostly because these are a nightmare selecting
+ *     the right instruction.
+ */
+namespace FEXCore::ARMEmitter {
+  /*
+   * This `Size` enum is used for most ALU operations.
+   * These follow the AArch64 encoding style in most cases.
+   */
+  enum class Size : uint32_t {
+    i32Bit = 0,
+    i64Bit,
+  };
+
+  // This allows us to get the `Size` enum in bits.
+  [[nodiscard]]
+  constexpr size_t RegSizeInBits(Size size) {
+    return size_t{32} << FEXCore::ToUnderlying(size);
+  }
+
+  /* This `SubRegSize` enum is used for most ASIMD operations.
+   * These follow the AArch64 encoding style in most cases.
+   */
+  enum class SubRegSize : uint32_t {
+    i8Bit   = 0b00,
+    i16Bit  = 0b01,
+    i32Bit  = 0b10,
+    i64Bit  = 0b11,
+    i128Bit = 0b100,
+  };
+
+  // This allows us to get the `SubRegSize` in bits.
+  [[nodiscard]]
+  constexpr size_t SubRegSizeInBits(SubRegSize size) {
+    return size_t{8} << FEXCore::ToUnderlying(size);
+  }
+
+  /* This `ScalarRegSize` enum is used for most scalar float
+   * operations.
+   *
+   * This is specifically duplicated from `SubRegSize` to have strongly
+   * typed functions.
+   *
+   * `ScalarRegSize` specifically doesn't have `i128Bit` because scalar operations
+   * can't operate at 128-bit.
+   */
+  enum class ScalarRegSize : uint32_t {
+    i8Bit   = 0b00,
+    i16Bit  = 0b01,
+    i32Bit  = 0b10,
+    i64Bit  = 0b11,
+  };
+
+  // This allows us to get the `ScalarRegSize` in bits.
+  [[nodiscard]]
+  constexpr size_t ScalarRegSizeInBits(ScalarRegSize size) {
+    return size_t{8} << FEXCore::ToUnderlying(size);
+  }
+
+  /* This `VectorRegSizePair` union allows us to have an overlapping type
+   * to select a scalar operation or a vector depending on which operation
+   * we pass in.
+   * Useful in FEX's vector operations that behave as scalar or vector
+   * depending on various factors. But since the operation will have the sa,e
+   * element size, we want to choose the operation more easily
+   */
+  union VectorRegSizePair {
+    ScalarRegSize Scalar;
+    SubRegSize Vector;
+  };
+
+  // This allows us to create a `VectorRegSizePair` union.
+  [[nodiscard]]
+  constexpr VectorRegSizePair ToVectorSizePair(SubRegSize size) {
+    return VectorRegSizePair {.Vector = size};
+  }
+  [[nodiscard]]
+  constexpr VectorRegSizePair ToVectorSizePair(ScalarRegSize size) {
+    return VectorRegSizePair {.Scalar = size};
+  }
+
+  // This `ShiftType` enum is used for ALU shift-register encoded instructions.
+  enum class ShiftType : uint32_t {
+    LSL = 0,
+    LSR,
+    ASR,
+    ROR,
+  };
+
+  // This `ExtendedType` enum is used for ALU extended-register encoded instructions.
+  enum class ExtendedType : uint32_t {
+    UXTB = 0b000,
+    UXTH = 0b001,
+    UXTW = 0b010,
+    UXTX = 0b011,
+    SXTB = 0b100,
+    SXTH = 0b101,
+    SXTW = 0b110,
+    SXTX = 0b111,
+    LSL_32 = UXTW,
+    LSL_64 = UXTX,
+  };
+
+  // This `Condition` enum is used for various conditional instructions.
+  enum class Condition : uint32_t {
+    // Meaning:   Int                    - Float
+    CC_EQ = 0, // Equal                  - Equal
+    CC_NE,     // Not Eq                 - Not Eq or unordered
+    CC_CS,     // Carry set              - Greater than, equal, or unordered
+    CC_CC,     // Carry clear            - Less than
+    CC_MI,     // Minus/Negative         - Less than
+    CC_PL,     // Plus, positive or zero - GT, equal, or unordered
+    CC_VS,     // Overflow               - Unordered
+    CC_VC,     // No Overflow            - Ordered
+    CC_HI,     // Unsigned higher        - GT, or unordered
+    CC_LS,     // Unsigned lower or same - LT or EQ
+    CC_GE,     // Signed GT or EQ        - GT or EQ
+    CC_LT,     // Signed LT              - LT or Unordered
+    CC_GT,     // Signed GT              - GT
+    CC_LE,     // Signed LT or EQ        - LT, EQ, or Unordered
+    CC_AL,     // Always                 - Always
+    CC_NV,     // Always                 - Always
+
+    // Aliases
+    CC_HS = CC_CS,
+    CC_LO = CC_CC,
+  };
+
+  /*
+   * This `StatusFlags` enum is used for conditional compare encoded instructions.
+   * These directly encode to the `nzcv` flags.
+   */
+  enum class StatusFlags : uint32_t {
+    None = 0,
+    Flag_V = 0b0001,
+    Flag_C = 0b0010,
+    Flag_Z = 0b0100,
+    Flag_N = 0b1000,
+
+    Flag_NZCV = Flag_N | Flag_Z | Flag_C | Flag_V,
+  };
+
+
+  /*
+   * This `IndexType` enum is used for load-store instructions.
+   * Not all load-store instructions use this, so the user needs to be careful.
+   */
+  enum class IndexType {
+    POST,
+    OFFSET,
+    PRE,
+
+    UNPRIVILEGED,
+  };
+
+  /* This `SVEMemOperand` class is used for the helper SVE load-store instructions.
+   * Load-store instructions are quite expressive, so having a helper that handles these differences is worth it.
+   */
+  class SVEMemOperand final {
+    public:
+      SVEMemOperand(XRegister rn, XRegister rm = XReg::zr)
+        : rn {rn}
+        , MetaType {
+          .ScalarScalarType {
+            .Header = { .MemType = TYPE_SCALAR_SCALAR },
+            .rm = rm,
+          }
+        } {}
+      SVEMemOperand(XRegister rn, int32_t imm = 0)
+        : rn {rn}
+        , MetaType {
+          .ScalarImmType {
+            .Header = { .MemType = TYPE_SCALAR_IMM },
+            .Imm = imm,
+          }
+        } {}
+
+      Register rn;
+      enum Type {
+        TYPE_SCALAR_SCALAR,
+        TYPE_SCALAR_IMM,
+        TYPE_SCALAR_VECTOR,
+        TYPE_VECTOR_IMM,
+      };
+      struct HeaderStruct {
+        Type MemType;
+      };
+
+      union {
+        HeaderStruct Header;
+        struct {
+          HeaderStruct Header;
+          Register rm;
+        } ScalarScalarType;
+
+        struct {
+          HeaderStruct Header;
+          int32_t Imm;
+        } ScalarImmType;
+
+        struct {
+          HeaderStruct Header;
+          ZRegister zm;
+          // TODO: Implement support for modifier
+        } ScalarVectorType;
+
+        struct {
+          HeaderStruct Header;
+          // rn will be a ZRegister
+          int32_t Imm;
+        } VectorImmType;
+      } MetaType;
+  };
+
+  /* This `ExtendedMemOperand` class is used for the helper load-store instructions.
+   * Load-store instructions are quite expressive, so having a helper that handles these differences is worth it.
+   */
+  class ExtendedMemOperand final {
+    public:
+      ExtendedMemOperand(XRegister rn, XRegister rm = XReg::zr, ExtendedType Option = ExtendedType::LSL_64, uint32_t Shift = 0)
+        : rn {rn}
+        , MetaType {
+          .ExtendedType {
+            .Header = { .MemType = TYPE_EXTENDED },
+            .rm = rm,
+            .Option = Option,
+            .Shift = Shift,
+          }
+        } {}
+      ExtendedMemOperand(XRegister rn, IndexType Index = IndexType::OFFSET, int32_t Imm = 0)
+        : rn {rn}
+        , MetaType {
+          .ImmType {
+            .Header = { .MemType = TYPE_IMM },
+            .Index = Index,
+            .Imm = Imm,
+          }
+        } {}
+
+      Register rn;
+      enum Type {
+        TYPE_EXTENDED,
+        TYPE_IMM,
+      };
+      struct HeaderStruct {
+        Type MemType;
+      };
+      union {
+        HeaderStruct Header;
+        struct {
+          HeaderStruct Header;
+          Register rm;
+          ExtendedType Option;
+          uint32_t Shift;
+        } ExtendedType;
+        struct {
+          HeaderStruct Header;
+          IndexType Index;
+          int32_t Imm;
+        } ImmType;
+      } MetaType;
+  };
+
+  template<uint32_t op0, uint32_t op1, uint32_t CRn, uint32_t CRm, uint32_t op2>
+  constexpr uint32_t GenSystemReg() {
+    return op0 << 19 |
+      op1 << 16 |
+      CRn << 12 |
+      CRm << 8 |
+      op2 << 5;
+  };
+
+  // This `SystemRegister` enum is used for the mrs/msr instructions.
+  enum class SystemRegister : uint32_t {
+    CTR_EL0    = GenSystemReg<0b11, 0b011, 0b0000, 0b0000, 0b001>(),
+    DCZID_EL0  = GenSystemReg<0b11, 0b011, 0b0000, 0b0000, 0b111>(),
+    TPIDR_EL0  = GenSystemReg<0b11, 0b011, 0b1101, 0b0000, 0b010>(),
+    RNDR       = GenSystemReg<0b11, 0b011, 0b0010, 0b0100, 0b000>(),
+    RNDRRS     = GenSystemReg<0b11, 0b011, 0b0010, 0b0100, 0b001>(),
+    NZCV       = GenSystemReg<0b11, 0b011, 0b0100, 0b0010, 0b000>(),
+    FPCR       = GenSystemReg<0b11, 0b011, 0b0100, 0b0100, 0b000>(),
+    CNTFRQ_EL0 = GenSystemReg<0b11, 0b011, 0b1110, 0b0000, 0b000>(),
+    CNTVCT_EL0 = GenSystemReg<0b11, 0b011, 0b1110, 0b0000, 0b010>(),
+  };
+
+  template<uint32_t op1, uint32_t CRm, uint32_t op2>
+  constexpr uint32_t GenDCReg() {
+    return op1 << 16 |
+      CRm << 8 |
+      op2 << 5;
+  };
+
+  // This `DataCacheOperation` enum is used for the dc instruction.
+  enum class DataCacheOperation : uint32_t {
+    IVAC  = GenDCReg<0b000, 0b0110, 0b001>(),
+    ISW   = GenDCReg<0b000, 0b0110, 0b010>(),
+    CSW   = GenDCReg<0b000, 0b1010, 0b010>(),
+    CISW  = GenDCReg<0b000, 0b1110, 0b010>(),
+    ZVA   = GenDCReg<0b011, 0b0100, 0b001>(),
+    CVAC  = GenDCReg<0b011, 0b1010, 0b001>(),
+    CVAU  = GenDCReg<0b011, 0b1011, 0b001>(),
+    CIVAC = GenDCReg<0b011, 0b1110, 0b001>(),
+
+    // MTE2
+    IGVAC  = GenDCReg<0b000, 0b0110, 0b011>(),
+    IGSW   = GenDCReg<0b000, 0b0110, 0b100>(),
+    IGDVAC = GenDCReg<0b000, 0b0110, 0b101>(),
+    IGDSW  = GenDCReg<0b000, 0b0110, 0b110>(),
+    CGSW   = GenDCReg<0b000, 0b1010, 0b100>(),
+    CGDSW  = GenDCReg<0b000, 0b1010, 0b110>(),
+    CIGSW  = GenDCReg<0b000, 0b1110, 0b100>(),
+    CIGDSW = GenDCReg<0b000, 0b1110, 0b110>(),
+
+    // MTE
+    GVA      = GenDCReg<0b011, 0b0100, 0b011>(),
+    GZVA     = GenDCReg<0b011, 0b0100, 0b100>(),
+    CGVAC    = GenDCReg<0b011, 0b1010, 0b011>(),
+    CGDVAC   = GenDCReg<0b011, 0b1010, 0b101>(),
+    CGVAP    = GenDCReg<0b011, 0b1100, 0b011>(),
+    CGDVAP   = GenDCReg<0b011, 0b1100, 0b101>(),
+    CGVADP   = GenDCReg<0b011, 0b1101, 0b011>(),
+    CGDVADP  = GenDCReg<0b011, 0b1101, 0b101>(),
+    CIGVAC   = GenDCReg<0b011, 0b1110, 0b011>(),
+    CIGDVAC  = GenDCReg<0b011, 0b1110, 0b101>(),
+
+    // DPB
+    CVAP = GenDCReg<0b011, 0b1100, 0b001>(),
+
+    // DPB2
+    CVADP = GenDCReg<0b011, 0b1101, 0b001>(),
+  };
+
+  template<uint32_t CRm, uint32_t op2>
+  constexpr uint32_t GenHintBarrierReg() {
+    return CRm << 8 |
+      op2 << 5;
+  }
+
+  // This `HintRegister` enum is used for the hint instruction.
+  enum class HintRegister : uint32_t {
+    NOP   = GenHintBarrierReg<0b0000, 0b000>(),
+    YIELD = GenHintBarrierReg<0b0000, 0b001>(),
+    WFE   = GenHintBarrierReg<0b0000, 0b010>(),
+    WFI   = GenHintBarrierReg<0b0000, 0b011>(),
+    SEV   = GenHintBarrierReg<0b0000, 0b100>(),
+    SEVL  = GenHintBarrierReg<0b0000, 0b101>(),
+    DGH   = GenHintBarrierReg<0b0000, 0b110>(),
+    CSDB  = GenHintBarrierReg<0b0010, 0b100>(),
+  };
+
+  // This `BarrierRegister` enum is used for the various barrier instructions.
+  enum class BarrierRegister : uint32_t {
+    CLREX   = GenHintBarrierReg<0b0000, 0b010>(),
+    TCOMMIT = GenHintBarrierReg<0b0000, 0b011>(),
+    DSB     = GenHintBarrierReg<0b0000, 0b100>(),
+    DMB     = GenHintBarrierReg<0b0000, 0b101>(),
+    ISB     = GenHintBarrierReg<0b0000, 0b110>(),
+    SB      = GenHintBarrierReg<0b0000, 0b111>(),
+  };
+
+  // This `BarrierScope` enum is used for the dsb/dmb instructions.
+  enum class BarrierScope : uint32_t {
+    // Outer shareable
+    OSHLD  = 0b0001,
+    OSHST  = 0b0010,
+    OSH    = 0b0011,
+    // Non shareable
+    NSHLD  = 0b0101,
+    NSHST  = 0b0110,
+    NSH    = 0b0111,
+    // Inner shareable
+    ISHLD  = 0b1001,
+    ISHST  = 0b1010,
+    ISH    = 0b1011,
+    // Full System visibility
+    LD     = 0b1101,
+    ST     = 0b1110,
+    SY     = 0b1111,
+  };
+
+  // This `Prefetch` enum is used for prefetch instructions.
+  enum class Prefetch : uint32_t {
+    // Prefetch for load
+    PLDL1KEEP = 0b00000,
+    PLDL1STRM = 0b00001,
+    PLDL2KEEP = 0b00010,
+    PLDL2STRM = 0b00011,
+    PLDL3KEEP = 0b00100,
+    PLDL3STRM = 0b00101,
+
+    // Preload instructions
+    PLIL1KEEP = 0b01000,
+    PLIL1STRM = 0b01001,
+    PLIL2KEEP = 0b01010,
+    PLIL2STRM = 0b01011,
+    PLIL3KEEP = 0b01100,
+    PLIL3STRM = 0b01101,
+
+    // Preload for store
+    PSTL1KEEP = 0b10000,
+    PSTL1STRM = 0b10001,
+    PSTL2KEEP = 0b10010,
+    PSTL2STRM = 0b10011,
+    PSTL3KEEP = 0b10100,
+    PSTL3STRM = 0b10101,
+  };
+
+  // This `PredicatePattern` enun is used for some SVE instructions.
+  enum class PredicatePattern : uint32_t {
+    SVE_POW2  = 0b00000,
+    SVE_VL1   = 0b00001,
+    SVE_VL2   = 0b00010,
+    SVE_VL3   = 0b00011,
+    SVE_VL4   = 0b00100,
+    SVE_VL5   = 0b00101,
+    SVE_VL6   = 0b00110,
+    SVE_VL7   = 0b00111,
+    SVE_VL8   = 0b01000,
+    SVE_VL16  = 0b01001,
+    SVE_VL32  = 0b01010,
+    SVE_VL64  = 0b01011,
+    SVE_VL128 = 0b01100,
+    SVE_VL256 = 0b01101,
+    SVE_MUL4  = 0b11101,
+    SVE_MUL3  = 0b11110,
+    SVE_ALL   = 0b11111,
+  };
+
+  /* This `BackwardLabel` struct used for retaining a location for PC-Relative instructions.
+   * This is specifically a label for a target that is logically `below` an instruction that uses it.
+   * Which means that a branch would jump backwards.
+   */
+  struct BackwardLabel {
+    uint8_t *Location{};
+  };
+
+  /* This `ForwardLabel` struct used for retaining a location for PC-Relative instructions.
+   * This is specifically a label for a target that is logically `above` an instruction that uses it.
+   * Which means that a branch would jump forwards.
+   *
+   * This can be bound to multiple instructions, so it needs a vector for each bind instruction type.
+   */
+  struct ForwardLabel {
+    struct Instructions {
+      enum class InstType {
+        ADR,
+        ADRP,
+        B,
+        BC,
+        TEST_BRANCH,
+        RELATIVE_LOAD,
+        LONG_ADDRESS_GEN,
+      };
+      uint8_t *Location{};
+      InstType Type;
+    };
+    fextl::vector<Instructions> Insts{};
+  };
+
+  /* This `BiDirectionalLabel` struct used for retaining a location for PC-Relative instructions.
+   * This is specifically a label for a target that is in either direction of an instruction that uses it.
+   * Which means a branch could jump backwards or forwards depending on situation.
+   */
+  struct BiDirectionalLabel {
+    BackwardLabel Backward;
+    ForwardLabel Forward;
+  };
+
+  // Some FCMA ASIMD instructions support a rotation argument.
+  enum class Rotation : uint32_t {
+    ROTATE_0   = 0b00,
+    ROTATE_90  = 0b01,
+    ROTATE_180 = 0b10,
+    ROTATE_270 = 0b11,
+  };
+
+  // Concept for contraining some instructions to accept only an XRegister or WRegister.
+  // Particularly for operations that differ encodings depending on which one is used.
+  template <typename T>
+  concept IsXOrWRegister = std::is_same_v<T, XRegister> || std::is_same_v<T, WRegister>;
+
+  // Whether or not a given set of vector registers are sequential
+  // in increasing order as far as the register file is concerned (modulo its size)
+  //
+  // For example, a set of registers like:
+  //
+  // v1,  v2, v3 and
+  // v31, v0, v1
+  //
+  // would both be considered sequential sequences, and some instructions in particular
+  // limit register lists to these kind of sequences.
+  //
+  template <typename T, typename... Args>
+  constexpr bool AreVectorsSequential(T first, const Args&... args) {
+    // Ensure we always have a pair of registers to compare against.
+    static_assert(sizeof...(args) >= 1, "Number of arguments must be greater than 1");
+
+    const auto fn = [](auto& lhs, const auto& rhs) {
+      const auto result = ((lhs.Idx() + 1) % 32) == rhs.Idx();
+      lhs = rhs;
+      return result;
+    };
+
+    return (fn(first, args) && ...);
+  }
+
+  // This is an emitter that is designed around the smallest code bloat as possible.
+  // Eschewing most developer convenience in order to keep code as small as possible.
+
+  // Choices:
+  // - Size of ops passed as an argument rather than template to let the compiler use csel instead of branching.
+  // - Registers are unsized so they can be passed in a GPR and not need conversion operations
+  class Emitter : public FEXCore::ARMEmitter::Buffer {
+  public:
+    Emitter() = default;
+
+    Emitter(uint8_t* Base, uint64_t BaseSize)
+      : Buffer (Base, BaseSize) {
+    }
+
+    // Bind a backward label to an address.
+    // Address that is bound is the current emitter location.
+    void Bind(BackwardLabel *Label) {
+      LOGMAN_THROW_AA_FMT(Label->Location == nullptr, "Trying to bind a label twice");
+      Label->Location = GetCursorAddress<uint8_t*>();
+    }
+
+    // Bind a forward label to a location.
+    // This walks all the instructions in the label's vector.
+    // Then backpatching all instructions that have used the label.
+    template<bool WarnAboutEmpty = false>
+    void Bind(ForwardLabel *Label) {
+      if constexpr (WarnAboutEmpty) {
+        LOGMAN_THROW_A_FMT(Label->Insts.empty() == false, "Binding forward label that didn't have any instructions using it");
+      }
+      uint8_t *CurrentAddress = GetCursorAddress<uint8_t*>();
+      for (const auto &Inst : Label->Insts) {
+        // Patch up the instructions
+        switch (Inst.Type) {
+          case ForwardLabel::Instructions::InstType::ADR: {
+            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
+            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+            LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large");
+            uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
+            uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
+            uint32_t Inst = *Instruction & ~InstMask;
+            Inst |= (Offset & 0b11) << 29;
+            Inst |= (Offset >> 2) << 5;
+            *Instruction = Inst;
+            break;
+          }
+          case ForwardLabel::Instructions::InstType::ADRP: {
+            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
+            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+            LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large");
+            Imm >>= 12;
+            uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
+            uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
+            uint32_t Inst = *Instruction & ~InstMask;
+            Inst |= (Offset & 0b11) << 29;
+            Inst |= (Offset >> 2) << 5;
+            *Instruction = Inst;
+            break;
+          }
+
+          case ForwardLabel::Instructions::InstType::B: {
+            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
+            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+            LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+            Imm >>= 2;
+            uint32_t InstMask = 0x3FF'FFFF;
+            uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+            uint32_t Inst = *Instruction & ~InstMask;
+            Inst |= Offset;
+            *Instruction = Inst;
+
+            break;
+          }
+
+          case ForwardLabel::Instructions::InstType::TEST_BRANCH: {
+            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
+            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+            LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+            Imm >>= 2;
+            uint32_t InstMask = 0x3FFF;
+            uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+            uint32_t Inst = *Instruction & ~(InstMask << 5);
+            Inst |= Offset << 5;
+            *Instruction = Inst;
+
+            break;
+          }
+          case ForwardLabel::Instructions::InstType::BC:
+          case ForwardLabel::Instructions::InstType::RELATIVE_LOAD: {
+            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
+            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+            LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+            Imm >>= 2;
+            uint32_t InstMask = 0x7'FFFF;
+            uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+            uint32_t Inst = *Instruction & ~(InstMask << 5);
+            Inst |= Offset << 5;
+            *Instruction = Inst;
+            break;
+          }
+          case ForwardLabel::Instructions::InstType::LONG_ADDRESS_GEN: {
+            uint32_t *Instructions = reinterpret_cast<uint32_t*>(Inst.Location);
+            int64_t ImmInstOne = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[0]);
+            int64_t ImmInstTwo = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[1]);
+            auto OriginalOffset = GetCursorOffset();
+
+            auto InstOffset = GetCursorOffsetFromAddress(Instructions);
+            SetCursorOffset(InstOffset);
+
+            // We encoded the destination register in to the first instruction space.
+            // Read it back.
+            ARMEmitter::Register DestReg(Instructions[0]);
+
+            if (IsADRRange(ImmInstTwo)) {
+              // If within ADR range from the second instruction, then we can emit NOP+ADR
+              nop();
+              adr(DestReg, static_cast<uint32_t>(ImmInstTwo) & 0x7FFF);
+            }
+            else if (IsADRPRange(ImmInstOne)) {
+
+              // If within ADRP range from the first instruction, then we are /definitely/ in range for the second instruction.
+              // First check if we are in non-offset range for second instruction.
+              if (IsADRPAligned(reinterpret_cast<uint64_t>(CurrentAddress))) {
+                // We can emit nop + adrp
+                nop();
+                adrp(DestReg, static_cast<uint32_t>(ImmInstTwo >> 12) & 0x7FFF);
+              }
+              else {
+                // Not aligned, need adrp + add
+                adrp(DestReg, static_cast<uint32_t>(ImmInstOne >> 12) & 0x7FFF);
+                add(ARMEmitter::Size::i64Bit, DestReg, DestReg, ImmInstOne & 0xFFF);
+              }
+            }
+            else {
+              LOGMAN_MSG_A_FMT("Unscaled offset is too large");
+              FEX_UNREACHABLE;
+            }
+
+            SetCursorOffset(OriginalOffset);
+            break;
+          }
+          default: LOGMAN_MSG_A_FMT("Unexpected inst type in label fixup");
+        }
+      }
+    }
+
+    // Bind a bidirectional location to a location.
+    // Binds both forwards and backwards depending on how the label was used.
+    void Bind(BiDirectionalLabel *Label) {
+      if (!Label->Backward.Location) {
+        Bind(&Label->Backward);
+      }
+      Bind<false>(&Label->Forward);
+    }
+
+  public:
+  // TODO: Implement SME when it matters.
+#include "Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl"
+#include "Interface/Core/ArchHelpers/CodeEmitter/BranchOps.inl"
+#include "Interface/Core/ArchHelpers/CodeEmitter/LoadstoreOps.inl"
+#include "Interface/Core/ArchHelpers/CodeEmitter/SystemOps.inl"
+#include "Interface/Core/ArchHelpers/CodeEmitter/ScalarOps.inl"
+#include "Interface/Core/ArchHelpers/CodeEmitter/ASIMDOps.inl"
+#include "Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl"
+
+  private:
+    template<typename T>
+    uint32_t Encode_ra(T Reg) const {
+      return Reg.Idx() << 10;
+    }
+    uint32_t Encode_ra(uint32_t Reg) const {
+      return Reg << 10;
+    }
+    template<typename T>
+    uint32_t Encode_rt2(T Reg) const {
+      return Reg.Idx() << 10;
+    }
+    template<>
+    uint32_t Encode_rt2(uint32_t Reg) const {
+      return Reg << 10;
+    }
+    template<typename T>
+    uint32_t Encode_rm(T Reg) const {
+      return Reg.Idx() << 16;
+    }
+    uint32_t Encode_rm(uint32_t Reg) const {
+      return Reg << 16;
+    }
+    template<typename T>
+    uint32_t Encode_rs(T Reg) const {
+      return Reg.Idx() << 16;
+    }
+    uint32_t Encode_rs(uint32_t Reg) const {
+      return Reg << 16;
+    }
+    template<typename T>
+    uint32_t Encode_rn(T Reg) const {
+      return Reg.Idx() << 5;
+    }
+    uint32_t Encode_rn(uint32_t Reg) const {
+      return Reg << 5;
+    }
+    template<typename T>
+    uint32_t Encode_rd(T Reg) const {
+      return Reg.Idx();
+    }
+    uint32_t Encode_rd(uint32_t Reg) const {
+      return Reg;
+    }
+    template<typename T>
+    uint32_t Encode_rt(T Reg) const {
+      return Reg.Idx();
+    }
+    template<>
+    uint32_t Encode_rt(Prefetch Reg) const {
+      return FEXCore::ToUnderlying(Reg);
+    }
+    uint32_t Encode_rt(uint32_t Reg) const {
+      return Reg;
+    }
+    template<typename T>
+    uint32_t Encode_pd(T Reg) const {
+      return FEXCore::ToUnderlying(Reg);
+    }
+  };
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SystemOps.inl

@@ -0,0 +1,175 @@
+/* System instruction emitters.
+ *
+ * This is mostly a mashup of various instruction types.
+ * Nothing follows an explicit pattern since they are mostly different.
+ */
+public:
+    // System with result
+    // TODO: SYSL
+    // System Instruction
+    // TODO: AT
+    // TODO: CFP
+    // TODO: CPP
+    void dc(FEXCore::ARMEmitter::DataCacheOperation DCOp, FEXCore::ARMEmitter::Register rt) {
+      constexpr uint32_t Op = 0b1101'0101'0000'1000'0111 << 12;
+      SystemInstruction(Op, 0, FEXCore::ToUnderlying(DCOp), rt);
+    }
+    // TODO: DVP
+    // TODO: IC
+    // TODO: TLBI
+
+    // Exception generation
+    void svc(uint32_t Imm) {
+      ExceptionGeneration(0b000, 0b000, 0b01, Imm);
+    }
+    void hvc(uint32_t Imm) {
+      ExceptionGeneration(0b000, 0b000, 0b10, Imm);
+    }
+    void smc(uint32_t Imm) {
+      ExceptionGeneration(0b000, 0b000, 0b11, Imm);
+    }
+    void brk(uint32_t Imm) {
+      ExceptionGeneration(0b001, 0b000, 0b00, Imm);
+    }
+    void hlt(uint32_t Imm) {
+      ExceptionGeneration(0b010, 0b000, 0b00, Imm);
+    }
+    void tcancel(uint32_t Imm) {
+      ExceptionGeneration(0b011, 0b000, 0b00, Imm);
+    }
+    void dcps1(uint32_t Imm) {
+      ExceptionGeneration(0b101, 0b000, 0b01, Imm);
+    }
+    void dcps2(uint32_t Imm) {
+      ExceptionGeneration(0b101, 0b000, 0b10, Imm);
+    }
+    void dcps3(uint32_t Imm) {
+      ExceptionGeneration(0b101, 0b000, 0b11, Imm);
+    }
+    // System instructions with register argument
+    void wfet(FEXCore::ARMEmitter::Register rt) {
+      SystemInstructionWithReg(0b0000, 0b000, rt);
+    }
+    void wfit(FEXCore::ARMEmitter::Register rt) {
+      SystemInstructionWithReg(0b0000, 0b001, rt);
+    }
+
+    // Hints
+    void nop() {
+      Hint(FEXCore::ARMEmitter::HintRegister::NOP);
+    }
+    void yield() {
+      Hint(FEXCore::ARMEmitter::HintRegister::YIELD);
+    }
+    void wfe() {
+      Hint(FEXCore::ARMEmitter::HintRegister::WFE);
+    }
+    void wfi() {
+      Hint(FEXCore::ARMEmitter::HintRegister::WFI);
+    }
+    void sev() {
+      Hint(FEXCore::ARMEmitter::HintRegister::SEV);
+    }
+    void sevl() {
+      Hint(FEXCore::ARMEmitter::HintRegister::SEVL);
+    }
+    void dgh() {
+      Hint(FEXCore::ARMEmitter::HintRegister::DGH);
+    }
+    void csdb() {
+      Hint(FEXCore::ARMEmitter::HintRegister::CSDB);
+    }
+
+    // Barriers
+    void clrex(uint32_t imm = 15) {
+      LOGMAN_THROW_AA_FMT(imm < 16, "Immediate out of range");
+      Barrier(FEXCore::ARMEmitter::BarrierRegister::CLREX, imm);
+    }
+    void dsb(FEXCore::ARMEmitter::BarrierScope Scope) {
+      Barrier(FEXCore::ARMEmitter::BarrierRegister::DSB, FEXCore::ToUnderlying(Scope));
+    }
+    void dmb(FEXCore::ARMEmitter::BarrierScope Scope) {
+      Barrier(FEXCore::ARMEmitter::BarrierRegister::DMB, FEXCore::ToUnderlying(Scope));
+    }
+    void isb() {
+      Barrier(FEXCore::ARMEmitter::BarrierRegister::ISB, FEXCore::ToUnderlying(FEXCore::ARMEmitter::BarrierScope::SY));
+    }
+    void sb() {
+      Barrier(FEXCore::ARMEmitter::BarrierRegister::SB, 0);
+    }
+    void tcommit() {
+      Barrier(FEXCore::ARMEmitter::BarrierRegister::TCOMMIT, 0);
+    }
+
+    // System register move
+    void msr(FEXCore::ARMEmitter::SystemRegister reg, FEXCore::ARMEmitter::Register rt) {
+      constexpr uint32_t Op = 0b1101'0101'0001 << 20;
+      SystemRegisterMove(Op, rt, reg);
+    }
+
+    void mrs(FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SystemRegister reg) {
+      constexpr uint32_t Op = 0b1101'0101'0011 << 20;
+      SystemRegisterMove(Op, rd, reg);
+    }
+
+private:
+
+    // Exception Generation
+    void ExceptionGeneration(uint32_t opc, uint32_t op2, uint32_t LL, uint32_t Imm) {
+      LOGMAN_THROW_AA_FMT((Imm & 0xFFFF'0000) == 0, "Imm amount too large");
+
+      uint32_t Instr = 0b1101'0100 << 24;
+
+      Instr |= opc << 21;
+      Instr |= Imm << 5;
+      Instr |= op2 << 2;
+      Instr |= LL;
+
+      dc32(Instr);
+    }
+
+    // System instructions with register argument
+    void SystemInstructionWithReg(uint32_t CRm, uint32_t op2, FEXCore::ARMEmitter::Register rt) {
+      uint32_t Instr = 0b1101'0101'0000'0011'0001 << 12;
+
+      Instr |= CRm << 8;
+      Instr |= op2 << 5;
+      Instr |= Encode_rt(rt);
+      dc32(Instr);
+    }
+
+    // Hints
+    void Hint(FEXCore::ARMEmitter::HintRegister Reg) {
+      uint32_t Instr = 0b1101'0101'0000'0011'0010'0000'0001'1111U;
+      Instr |= FEXCore::ToUnderlying(Reg);
+      dc32(Instr);
+    }
+    // Barriers
+    void Barrier(FEXCore::ARMEmitter::BarrierRegister Reg, uint32_t CRm) {
+      uint32_t Instr = 0b1101'0101'0000'0011'0011'0000'0001'1111U;
+      Instr |= CRm << 8;
+      Instr |= FEXCore::ToUnderlying(Reg);
+      dc32(Instr);
+    }
+
+    // System Instruction
+    void SystemInstruction(uint32_t Op, uint32_t L, uint32_t SubOp, FEXCore::ARMEmitter::Register rt) {
+      uint32_t Instr = Op;
+
+      Instr |= L << 21;
+      Instr |= SubOp;
+      Instr |= Encode_rt(rt);
+
+      dc32(Instr);
+    }
+
+    // System register move
+    void SystemRegisterMove(uint32_t Op, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::SystemRegister reg) {
+      uint32_t Instr = Op;
+
+      Instr |= FEXCore::ToUnderlying(reg);
+      Instr |= Encode_rt(rt);
+
+      dc32(Instr);
+    }
+

External/FEXCore/Source/Interface/Core/CPUBackend.cpp

@@ -1,3 +1,4 @@
+#include "FEXCore/Utils/AllocatorHooks.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include <FEXCore/Core/CPUBackend.h>
@@ -57,17 +58,17 @@ auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
   CodeBuffer Buffer;
   Buffer.Size = Size;
   Buffer.Ptr = static_cast<uint8_t *>(
-      FEXCore::Allocator::mmap(nullptr, Buffer.Size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+      FEXCore::Allocator::VirtualAlloc(Buffer.Size, true));
   LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
 
-  if (ThreadState->CTX->Config.GlobalJITNaming()) {
-    ThreadState->CTX->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size);
+  if (static_cast<Context::ContextImpl*>(ThreadState->CTX)->Config.GlobalJITNaming()) {
+    static_cast<Context::ContextImpl*>(ThreadState->CTX)->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size);
   }
   return Buffer;
 }
 
 void CPUBackend::FreeCodeBuffer(CodeBuffer Buffer) {
-  FEXCore::Allocator::munmap(Buffer.Ptr, Buffer.Size);
+  FEXCore::Allocator::VirtualFree(Buffer.Ptr, Buffer.Size);
 }
 
 bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {

External/FEXCore/Source/Interface/Core/CPUID.cpp

@@ -8,18 +8,20 @@ $end_info$
 #include "Common/StringConv.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
-#include "Utils/FileLoading.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CPUID.h>
 #include <FEXCore/Core/HostFeatures.h>
+#include <FEXCore/Utils/CPUInfo.h>
+#include <FEXCore/Utils/FileLoading.h>
+#include <FEXCore/fextl/string.h>
 #include <FEXHeaderUtils/Syscalls.h>
 
 #include "git_version.h"
 
 #include <cstring>
 #ifdef _M_X86_64
-#include <cpuid.h>
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #endif
 
 namespace FEXCore {
@@ -74,21 +76,6 @@ static uint32_t GetCPUID() {
   return CPU;
 }
 
-static uint32_t CalculateNumberOfCPUs() {
-  size_t CPUs = 1;
-
-  while(std::filesystem::exists("/sys/devices/system/cpu/cpu" + std::to_string(CPUs))) {
-    CPUs++;
-  }
-
-  return CPUs;
-}
-
-// TODO: Replace usages with CTX->HostFeatures.EnableAVX
-//       when AVX implementations are further along.
-constexpr uint32_t SUPPORTS_AVX = 0;
-
-// #define CPUID_AMD
 #ifdef CPUID_AMD
 constexpr uint32_t FAMILY_IDENTIFIER =
   0 |          // Stepping
@@ -116,31 +103,30 @@ static uint32_t GetCycleCounterFrequency() {
 }
 
 void CPUIDEmu::SetupHostHybridFlag() {
-  size_t CPUs = CalculateNumberOfCPUs();
+  size_t CPUs = FEXCore::CPUInfo::CalculateNumberOfCPUs();
   PerCPUData.resize(CPUs);
 
   uint64_t MIDR{};
   for (size_t i = 0; i < CPUs; ++i) {
     std::error_code ec{};
-    std::string MIDRPath = "/sys/devices/system/cpu/cpu" + std::to_string(i) + "/regs/identification/midr_el1";
-    if (std::filesystem::exists(MIDRPath, ec)) {
-      std::vector<char> Data{};
-      // Needs to be a fixed size since depending on kernel it will try to read a full page of data and fail
-      // Only read 18 bytes for a 64bit value prefixed with 0x
-      if (FEXCore::FileLoading::LoadFile(Data, MIDRPath, 18)) {
-        uint64_t NewMIDR{};
-        std::string_view MIDRView(&Data.at(0), 18);
-        if (FEXCore::StrConv::Conv(MIDRView, &NewMIDR)) {
-          if (MIDR != 0 && MIDR != NewMIDR) {
-            // CPU mismatch, claim hybrid
-            Hybrid = true;
-          }
+    fextl::string MIDRPath = fextl::fmt::format("/sys/devices/system/cpu/cpu{}/regs/identification/midr_el1", i);
 
-          // Truncate to 32-bits, top 32-bits are all reserved in MIDR
-          PerCPUData[i].ProductName = ProductNames::ARM_UNKNOWN;
-          PerCPUData[i].MIDR = NewMIDR;
-          MIDR = NewMIDR;
+    std::array<char, 18> Data;
+    // Needs to be a fixed size since depending on kernel it will try to read a full page of data and fail
+    // Only read 18 bytes for a 64bit value prefixed with 0x
+    if (FEXCore::FileLoading::LoadFileToBuffer(MIDRPath, Data) == sizeof(Data)) {
+      uint64_t NewMIDR{};
+      std::string_view MIDRView(Data.data(), sizeof(Data));
+      if (FEXCore::StrConv::Conv(MIDRView, &NewMIDR)) {
+        if (MIDR != 0 && MIDR != NewMIDR) {
+          // CPU mismatch, claim hybrid
+          Hybrid = true;
         }
+
+        // Truncate to 32-bits, top 32-bits are all reserved in MIDR
+        PerCPUData[i].ProductName = ProductNames::ARM_UNKNOWN;
+        PerCPUData[i].MIDR = NewMIDR;
+        MIDR = NewMIDR;
       }
     }
   }
@@ -219,8 +205,8 @@ void CPUIDEmu::SetupHostHybridFlag() {
 
   if (Hybrid) {
     // Walk the MIDRs and calculate big little designs
-    std::vector<const CPUMIDR*> BigCores;
-    std::vector<const CPUMIDR*> LittleCores;
+    fextl::vector<const CPUMIDR*> BigCores;
+    fextl::vector<const CPUMIDR*> LittleCores;
 
     // Separate CPU cores out to big or little selected
     for (size_t i = 0; i < CPUs; ++i) {
@@ -356,28 +342,28 @@ void CPUIDEmu::SetupHostHybridFlag() {
 
 #else
 static uint32_t GetCycleCounterFrequency() {
-  uint32_t eax, ebx, ecx, edx;
-  __cpuid(0, eax, ebx, ecx, edx);
-  if (eax >= 0x15) {
-    __cpuid(0x15, eax, ebx, ecx, edx);
+  uint32_t data[4];
+  Xbyak::util::Cpu::getCpuid(0, data);
+  if (data[0] >= 0x15) {
+    Xbyak::util::Cpu::getCpuid(0x15, data);
 
-    if (eax && ebx && ecx) {
-      return ecx * ebx / eax;
+    if (data[0] && data[1] && data[2]) {
+      return data[2] * data[1] / data[0];
     }
   }
   return 0;
 }
 
 void CPUIDEmu::SetupHostHybridFlag() {
-  uint32_t eax, ebx, ecx, edx;
-  __cpuid(0, eax, ebx, ecx, edx);
-  if (eax >= 0x7) {
-    __cpuid(0x7, eax, ebx, ecx, edx);
+  uint32_t data[4];
+  Xbyak::util::Cpu::getCpuid(0, data);
+  if (data[0] >= 0x7) {
+    Xbyak::util::Cpu::getCpuid(0x7, data);
     // Bit 15 of edx claims hybrid CPU
-    Hybrid = (edx & (1U << 15)) != 0;
+    Hybrid = (data[3] & (1U << 15)) != 0;
   }
 
-  size_t CPUs = CalculateNumberOfCPUs();
+  size_t CPUs = FEXCore::CPUInfo::CalculateNumberOfCPUs();
   PerCPUData.resize(CPUs);
   for (size_t i = 0; i < CPUs; ++i) {
     PerCPUData[i].IsBig = true;
@@ -412,6 +398,9 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
   // XXX: Enable once the rest of the SSE4.2 instructions are emulated
   uint32_t SupportsSSE42 = CTX->HostFeatures.SupportsCRC && false ? 1 : 0;
 
+  // Hypervisor bit is normally set but some applications have issues with it.
+  uint32_t Hypervisor = HideHypervisorBit() ? 0 : 1;
+
   Res.eax = FAMILY_IDENTIFIER;
 
   Res.ebx = 0 | // Brand index
@@ -421,7 +410,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
 
   Res.ecx =
     (1 <<  0) | // SSE3
-    (1 <<  1) | // PCLMULQDQ
+    (CTX->HostFeatures.SupportsPMULL_128Bit <<  1) | // PCLMULQDQ
     (1 <<  2) | // DS area supports 64bit layout
     (1 <<  3) | // MWait
     (0 <<  4) | // DS-CPL
@@ -448,10 +437,10 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
     (CTX->HostFeatures.SupportsAES << 25) | // AES
     (0 << 26) | // XSAVE
     (0 << 27) | // OSXSAVE
-    (SUPPORTS_AVX << 28) | // AVX
+    (SupportsAVX() << 28) | // AVX
     (0 << 29) | // F16C
     (CTX->HostFeatures.SupportsRAND << 30) | // RDRAND
-    (1 << 31);  // Hypervisor always returns one
+    (Hypervisor << 31);
 
   Res.edx =
     (1 <<  0) | // FPU
@@ -637,12 +626,12 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) {
       (1 <<  0) | // FS/GS support
       (0 <<  1) | // TSC adjust MSR
       (0 <<  2) | // SGX
-      (1 <<  3) | // BMI1
+      (SupportsAVX() << 3) | // BMI1
       (0 <<  4) | // Intel Hardware Lock Elison
       (0 <<  5) | // AVX2 support
       (1 <<  6) | // FPU data pointer updated only on exception
       (1 <<  7) | // SMEP support
-      (1 <<  8) | // BMI2
+      (SupportsAVX() << 8) | // BMI2
       (0 <<  9) | // Enhanced REP MOVSB/STOSB
       (1 << 10) | // INVPCID for system software control of process-context
       (0 << 11) | // Restricted transactional memory
@@ -657,8 +646,8 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) {
       (0 << 20) | // SMAP Supervisor mode access prevention and CLAC/STAC instructions
       (0 << 21) | // Reserved
       (0 << 22) | // Reserved
-      (0 << 23) | // CLFLUSHOPT instruction
-      (0 << 24) | // CLWB instruction
+      (1 << 23) | // CLFLUSHOPT instruction
+      (CTX->HostFeatures.SupportsCLWB << 24) | // CLWB instruction
       (0 << 25) | // Intel processor trace
       (0 << 26) | // Reserved
       (0 << 27) | // Reserved
@@ -706,7 +695,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) {
       (0 <<  1) | // Reserved
       (0 <<  2) | // AVX512_4VNNIW
       (0 <<  3) | // AVX512_4FMAPS
-      (0 <<  4) | // Fast Short Rep Mov
+      (1 <<  4) | // Fast Short Rep Mov
       (0 <<  5) | // Reserved
       (0 <<  6) | // Reserved
       (0 <<  7) | // Reserved
@@ -743,13 +732,13 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0Dh(uint32_t Leaf) {
   // Leaf 0
   FEXCore::CPUID::FunctionResults Res{};
 
-  uint32_t XFeatureSupportedSizeMax = SUPPORTS_AVX ? 0x0000'0340 : 0x0000'0240; // XFeatureEnabledSizeMax: Legacy Header + FPU/SSE + AVX
+  uint32_t XFeatureSupportedSizeMax = SupportsAVX() ? 0x0000'0340 : 0x0000'0240; // XFeatureEnabledSizeMax: Legacy Header + FPU/SSE + AVX
   if (Leaf == 0) {
     // XFeatureSupportedMask[31:0]
     Res.eax =
       (1 << 0) |            // X87 support
       (1 << 1) |            // 128-bit SSE support
-      (SUPPORTS_AVX << 2) | // 256-bit AVX support
+      (SupportsAVX() << 2) | // 256-bit AVX support
       (0b00 << 3) |         // MPX State
       (0b000 << 5) |        // AVX-512 state
       (0 << 8) |            // "Used for IA32_XSS" ... Used for what?
@@ -783,8 +772,8 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0Dh(uint32_t Leaf) {
     Res.edx = 0;
   }
   else if (Leaf == 2) {
-    Res.eax = SUPPORTS_AVX ? 0x0000'0100 : 0; // YmmSaveStateSize
-    Res.ebx = SUPPORTS_AVX ? 0x0000'0240 : 0; // YmmSaveStateOffset
+    Res.eax = SupportsAVX() ? 0x0000'0100 : 0; // YmmSaveStateSize
+    Res.ebx = SupportsAVX() ? 0x0000'0240 : 0; // YmmSaveStateOffset
 
     // Reserved
     Res.ecx = 0;
@@ -879,6 +868,13 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0000h(uint32_t Leaf) {
 
 // Extended processor and feature bits
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) {
+
+  // RDTSCP is disabled on WIN32/Wine because there is no sane way to query processor ID.
+#ifndef _WIN32
+  constexpr uint32_t SUPPORTS_RDTSCP = 0;
+#else
+  constexpr uint32_t SUPPORTS_RDTSCP = 1;
+#endif
   FEXCore::CPUID::FunctionResults Res{};
 
   Res.eax = FAMILY_IDENTIFIER;
@@ -945,7 +941,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) {
     (1 << 24) | // FXSAVE/FXRSTOR
     (1 << 25) | // FXSAVE/FXRSTOR Optimizations
     (0 << 26) | // 1 gigabit pages
-    (1 << 27) | // RDTSCP
+    (SUPPORTS_RDTSCP << 27) | // RDTSCP
     (0 << 28) | // Reserved
     (1 << 29) | // Long Mode
     (1 << 30) | // 3DNow! Extensions
@@ -976,14 +972,14 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0004h(uint32_t Leaf) {
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0002h(uint32_t Leaf, uint32_t CPU) {
   FEXCore::CPUID::FunctionResults Res{};
   memset(&Res, ' ', sizeof(FEXCore::CPUID::FunctionResults));
-  memcpy(&Res, &ProcessorBrand[0], std::min(16L, DESCRIBE_STR_SIZE));
+  memcpy(&Res, &ProcessorBrand[0], std::min(ssize_t{16L}, DESCRIBE_STR_SIZE));
   return Res;
 }
 
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0003h(uint32_t Leaf, uint32_t CPU) {
   FEXCore::CPUID::FunctionResults Res{};
   memset(&Res, ' ', sizeof(FEXCore::CPUID::FunctionResults));
-  memcpy(&Res, &ProcessorBrand[16], std::max(0L, DESCRIBE_STR_SIZE - 16));
+  memcpy(&Res, &ProcessorBrand[16], std::max(ssize_t{0L}, DESCRIBE_STR_SIZE - 16));
   return Res;
 }
 
@@ -1212,89 +1208,26 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_Reserved(uint32_t Leaf) {
   return Res;
 }
 
-void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
+FEXCore::CPUID::XCRResults CPUIDEmu::XCRFunction_0h() {
+  // This just returns XCR0
+  FEXCore::CPUID::XCRResults Res{
+    .eax = static_cast<uint32_t>(XCR0),
+    .edx = static_cast<uint32_t>(XCR0 >> 32),
+  };
+
+  return Res;
+}
+
+void CPUIDEmu::Init(FEXCore::Context::ContextImpl *ctx) {
   CTX = ctx;
 
-  RegisterFunction(0, &CPUIDEmu::Function_0h);
-  RegisterFunction(1, &CPUIDEmu::Function_01h);
-  RegisterFunction(2, &CPUIDEmu::Function_02h);
-  // 3: Serial Number(previously), now reserved
-#ifndef CPUID_AMD
-  // Deterministic cache parameters for each level
-  RegisterFunction(0x4, &CPUIDEmu::Function_04h);
-#endif
-  // 5: Monitor/mwait
-  // Thermal and power management
-  RegisterFunction(6, &CPUIDEmu::Function_06h);
-  // Extended feature flags
-  RegisterFunction(7, &CPUIDEmu::Function_07h);
-  // 9: Direct Cache Access information
-  // 0x0A: Architectural performance monitoring
-  // 0x0B: Extended topology enumeration
-  // 0x0D: Processor extended state enumeration
-  RegisterFunction(0x0D, &CPUIDEmu::Function_0Dh);
-  // 0x0F: Intel RDT monitoring
-  // 0x10: Intel RDT allocation enumeration
-  // 0x12: Intel SGX capability enumeration
-  // 0x13: Reserved
-  // 0x14: Intel Processor trace
-#ifndef CPUID_AMD
-  // Timestamp counter information
-  // Doesn't exist on AMD hardware
-  RegisterFunction(0x15, &CPUIDEmu::Function_15h);
-#endif
-  // 0x16: Processor frequency information
-  // 0x17: SoC vendor attribute enumeration
-
-  // 0x1A: Hybrid Information Sub-leaf
-#ifndef CPUID_AMD
-  RegisterFunction(0x1A, &CPUIDEmu::Function_1Ah);
-#endif
-  // Hypervisor CPUID information leaf
-  RegisterFunction(0x4000'0000, &CPUIDEmu::Function_4000_0000h);
-  RegisterFunction(0x4000'0001, &CPUIDEmu::Function_4000_0001h);
-
-  // Largest extended function number
-  RegisterFunction(0x8000'0000, &CPUIDEmu::Function_8000_0000h);
-  // Processor vendor
-  RegisterFunction(0x8000'0001, &CPUIDEmu::Function_8000_0001h);
-  // Processor brand string
-  RegisterFunction(0x8000'0002, &CPUIDEmu::Function_8000_0002h);
-  // Processor brand string continued
-  RegisterFunction(0x8000'0003, &CPUIDEmu::Function_8000_0003h);
-  // Processor brand string continued
-  RegisterFunction(0x8000'0004, &CPUIDEmu::Function_8000_0004h);
-  // 0x8000'0005: L1 Cache and TLB identifiers
-#ifdef CPUID_AMD
-  RegisterFunction(0x8000'0005, &CPUIDEmu::Function_8000_0005h);
-#else
-  // This is full reserved on Intel platforms
-  RegisterFunction(0x8000'0005, &CPUIDEmu::Function_Reserved);
-#endif
-  // 0x8000'0006: L2 Cache identifiers
-  RegisterFunction(0x8000'0006, &CPUIDEmu::Function_8000_0006h);
-  // Advanced power management information
-  RegisterFunction(0x8000'0007, &CPUIDEmu::Function_8000_0007h);
-  // Virtual and physical address sizes
-  RegisterFunction(0x8000'0008, &CPUIDEmu::Function_8000_0008h);
-
-  // 0x8000'000A: SVM Revision
-  // TLB 1GB page identifiers
-  RegisterFunction(0x8000'0019, &CPUIDEmu::Function_8000_0019h);
-
-  // 0x8000'001A: Performance optimization identifiers
-  // 0x8000'001B: Instruction based sampling identifiers
-  // 0x8000'001C: Lightweight profiling capabilities
-  // 0x8000'001D: Cache properties
-#ifdef CPUID_AMD
-  // Deterministic cache parameters for each level
-  RegisterFunction(0x8000'001D, &CPUIDEmu::Function_8000_001Dh);
-#endif
-  // 0x8000'001E: Extended APIC ID
-  // 0x8000'001F: AMD Secure Encryption
-
   // Setup some state tracking
   SetupHostHybridFlag();
+
+  // TODO: Enable once AVX is supported.
+  if (false && CTX->HostFeatures.SupportsAVX) {
+    XCR0 |= XCR0_AVX;
+  }
 }
 }
 

External/FEXCore/Source/Interface/Core/CPUID.h

@@ -1,18 +1,21 @@
 #pragma once
 
+#include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/fextl/vector.h>
+
 #include <cstdint>
 #include <unordered_map>
 #include <utility>
-#include <vector>
-
-#include <FEXCore/Core/CPUID.h>
-#include <FEXCore/Config/Config.h>
 
 namespace FEXCore {
 namespace Context {
-  struct Context;
+  class ContextImpl;
 }
 
+// Debugging define to switch what family of CPU we execute as.
+// Might be useful if an application makes an assumption about a CPU.
+// #define CPUID_AMD
 class CPUIDEmu final {
 private:
   constexpr static uint32_t CPUID_VENDOR_INTEL1 = 0x756E6547; // "Genu"
@@ -28,16 +31,27 @@ public:
   // if we report anything differently then applications are likely to break
   constexpr static uint64_t CACHELINE_SIZE = 64;
 
-  void Init(FEXCore::Context::Context *ctx);
+  void Init(FEXCore::Context::ContextImpl *ctx);
 
   FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, uint32_t Leaf) {
-    const auto Handler = FunctionHandlers.find(Function);
-
-    if (Handler == FunctionHandlers.end()) {
-      return Function_Reserved(Leaf);
+    if (Function < Primary.size()) {
+      const auto Handler = Primary[Function];
+      return (this->*Handler)(Leaf);
     }
 
-    return (this->*Handler->second)(Leaf);
+    constexpr uint32_t HypervisorBase = 0x4000'0000;
+    if (Function >= HypervisorBase && Function < (HypervisorBase + Hypervisor.size())) {
+      const auto Handler = Hypervisor[Function - HypervisorBase];
+      return (this->*Handler)(Leaf);
+    }
+
+    constexpr uint32_t ExtendedBase = 0x8000'0000;
+    if (Function >= ExtendedBase && Function < (ExtendedBase + Extended.size())) {
+      const auto Handler = Extended[Function - ExtendedBase];
+      return (this->*Handler)(Leaf);
+    }
+
+    return Function_Reserved(Leaf);
   }
 
   FEXCore::CPUID::FunctionResults RunFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
@@ -49,17 +63,52 @@ public:
       return Function_8000_0004h(Leaf, CPU % PerCPUData.size());
   }
 
-private:
-  FEXCore::Context::Context *CTX;
-  bool Hybrid{};
-  FEX_CONFIG_OPT(Cores, THREADS);
+  FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) {
+    if (Function >= 1) {
+      // XCR function 1 is not yet supported.
+      return {};
+    }
 
-  using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf);
-  void RegisterFunction(uint32_t Function, FunctionHandler Handler) {
-    FunctionHandlers.insert_or_assign(Function, Handler);
+    return XCRFunction_0h();
   }
 
-  std::unordered_map<uint32_t, FunctionHandler> FunctionHandlers;
+private:
+  FEXCore::Context::ContextImpl *CTX;
+  bool Hybrid{};
+  FEX_CONFIG_OPT(Cores, THREADS);
+  FEX_CONFIG_OPT(HideHypervisorBit, HIDEHYPERVISORBIT);
+
+  // XFEATURE_ENABLED_MASK
+  // Mask that configures what features are enabled on the CPU.
+  // Affects XSAVE and XRSTOR when modified.
+  // Bit layout is as follows.
+  // [0]     - x87 enabled
+  // [1]     - SSE enabled
+  // [2]     - YMM enabled (256-bit SSE)
+  // [8:3]   - Reserved. MBZ.
+  // [9]     - MPK
+  // [10]    - Reserved. MBZ.
+  // [11]    - CET_U
+  // [12]    - CET_S
+  // [61:13] - Reserved. MBZ.
+  // [62]    - LWP (Lightweight profiling)
+  // [63]    - Reserved for XCR bit vector expansion. MBZ.
+  // Always enable x87 and SSE by default.
+  constexpr static uint64_t XCR0_X87 = 1ULL << 0;
+  constexpr static uint64_t XCR0_SSE = 1ULL << 1;
+  constexpr static uint64_t XCR0_AVX = 1ULL << 2;
+
+  uint64_t XCR0 {
+    XCR0_X87 |
+    XCR0_SSE
+  };
+
+  uint32_t SupportsAVX() const {
+    return (XCR0 & XCR0_AVX) ? 1 : 0;
+  }
+
+  using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf);
+
   struct CPUData {
     const char *ProductName{};
 #ifdef _M_ARM_64
@@ -67,7 +116,7 @@ private:
 #endif
     bool IsBig{};
   };
-  std::vector<CPUData> PerCPUData{};
+  fextl::vector<CPUData> PerCPUData{};
 
   // Functions
   FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf);
@@ -95,12 +144,163 @@ private:
   FEXCore::CPUID::FunctionResults Function_8000_0006h(uint32_t Leaf);
   FEXCore::CPUID::FunctionResults Function_8000_0007h(uint32_t Leaf);
   FEXCore::CPUID::FunctionResults Function_8000_0008h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0009h(uint32_t Leaf);
   FEXCore::CPUID::FunctionResults Function_8000_0019h(uint32_t Leaf);
   FEXCore::CPUID::FunctionResults Function_8000_001Dh(uint32_t Leaf);
   FEXCore::CPUID::FunctionResults Function_Reserved(uint32_t Leaf);
 
-  void SetupHostHybridFlag();
+  FEXCore::CPUID::XCRResults XCRFunction_0h();
 
+  void SetupHostHybridFlag();
+  static constexpr std::array<FunctionHandler, 27> Primary = {
+    // 0: Highest function parameter and ID
+    &CPUIDEmu::Function_0h,
+    // 1: Processor info
+    &CPUIDEmu::Function_01h,
+    // 2: Cache and TLB info
+    &CPUIDEmu::Function_02h,
+    // 3: Serial Number(previously), now reserved
+    &CPUIDEmu::Function_Reserved,
+#ifndef CPUID_AMD
+    // 4: Deterministic cache parameters for each level
+    &CPUIDEmu::Function_04h,
+#else
+    &CPUIDEmu::Function_Reserved,
+#endif
+    // 5: Monitor/mwait
+    &CPUIDEmu::Function_Reserved,
+    // 6: Thermal and power management
+    &CPUIDEmu::Function_06h,
+    // 7: Extended feature flags
+    &CPUIDEmu::Function_07h,
+    // 0x08: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 9: Direct Cache Access information
+    &CPUIDEmu::Function_Reserved,
+    // 0x0A: Architectural performance monitoring
+    &CPUIDEmu::Function_Reserved,
+    // 0x0B: Extended topology enumeration
+    &CPUIDEmu::Function_Reserved,
+    // 0x0C: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x0D: Processor extended state enumeration
+    &CPUIDEmu::Function_0Dh,
+    // 0x0E: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x0F: Intel RDT monitoring
+    &CPUIDEmu::Function_Reserved,
+    // 0x10: Intel RDT allocation enumeration
+    &CPUIDEmu::Function_Reserved,
+    // 0x12: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x12: Intel SGX capability enumeration
+    &CPUIDEmu::Function_Reserved,
+    // 0x13: Reserved
+    &CPUIDEmu::Function_Reserved,
+    // 0x14: Intel Processor trace
+    &CPUIDEmu::Function_Reserved,
+#ifndef CPUID_AMD
+    // Timestamp counter information
+    // Doesn't exist on AMD hardware
+    &CPUIDEmu::Function_15h,
+#else
+    &CPUIDEmu::Function_Reserved,
+#endif
+    // 0x16: Processor frequency information
+    &CPUIDEmu::Function_Reserved,
+    // 0x17: SoC vendor attribute enumeration
+    &CPUIDEmu::Function_Reserved,
+    // 0x18: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x19: Reserved?
+    &CPUIDEmu::Function_Reserved,
+#ifndef CPUID_AMD
+    // 0x1A: Hybrid Information Sub-leaf
+    &CPUIDEmu::Function_1Ah,
+#else
+    &CPUIDEmu::Function_Reserved,
+#endif
+  };
+
+  static constexpr std::array<FunctionHandler, 2> Hypervisor = {
+    // Hypervisor CPUID information leaf
+    &CPUIDEmu::Function_4000_0000h,
+    // FEX-Emu specific leaf
+    &CPUIDEmu::Function_4000_0001h,
+  };
+
+  static constexpr std::array<FunctionHandler, 32> Extended = {
+    // Largest extended function number
+    &CPUIDEmu::Function_8000_0000h,
+    // Processor vendor
+    &CPUIDEmu::Function_8000_0001h,
+    // Processor brand string
+    &CPUIDEmu::Function_8000_0002h,
+    // Processor brand string continued
+    &CPUIDEmu::Function_8000_0003h,
+    // Processor brand string continued
+    &CPUIDEmu::Function_8000_0004h,
+#ifdef CPUID_AMD
+    // 0x8000'0005: L1 Cache and TLB identifiers
+    &CPUIDEmu::Function_8000_0005h,
+#else
+    &CPUIDEmu::Function_Reserved,
+#endif
+    // 0x8000'0006: L2 Cache identifiers
+    &CPUIDEmu::Function_8000_0006h,
+    // 0x8000'0007: Advanced power management information
+    &CPUIDEmu::Function_8000_0007h,
+    // 0x8000'0008: Virtual and physical address sizes
+    &CPUIDEmu::Function_8000_0008h,
+    // 0x8000'0009: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'000A: SVM Revision
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'000B: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'000C: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'000D: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'000E: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'000F: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0010: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0011: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0012: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0013: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0014: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0015: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0016: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0017: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0018: Reserved?
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'0019: TLB 1GB page identifiers
+    &CPUIDEmu::Function_8000_0019h,
+    // 0x8000'001A: Performance optimization identifiers
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'001B: Instruction based sampling identifiers
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'001C: Lightweight profiling capabilities
+    &CPUIDEmu::Function_Reserved,
+#ifdef CPUID_AMD
+    // 0x8000'001D: Cache properties
+    &CPUIDEmu::Function_8000_001Dh,
+#else
+    &CPUIDEmu::Function_Reserved,
+#endif
+    // 0x8000'001E: Extended APIC ID
+    &CPUIDEmu::Function_Reserved,
+    // 0x8000'001F: AMD Secure Encryption
+    &CPUIDEmu::Function_Reserved,
+  };
 };
 }

External/FEXCore/Source/Interface/Core/Core.cpp

@@ -19,10 +19,12 @@ $end_info$
 #include "Interface/Core/Interpreter/InterpreterCore.h"
 #include "Interface/Core/JIT/JITCore.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 #include "Interface/HLE/Thunks/Thunks.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 #include "Interface/IR/Passes.h"
 #include "Interface/IR/PassManager.h"
+#include "Utils/Allocator/HostAllocator.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CodeLoader.h>
@@ -32,7 +34,6 @@ $end_info$
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/HLE/SourcecodeResolver.h>
 #include <FEXCore/HLE/Linux/ThreadManagement.h>
@@ -42,9 +43,15 @@ $end_info$
 #include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/Event.h>
+#include <FEXCore/Utils/File.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Threads.h>
 #include <FEXCore/Utils/Profiler.h>
+#include <FEXCore/fextl/fmt.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/set.h>
+#include <FEXCore/fextl/sstream.h>
+#include <FEXCore/fextl/vector.h>
 #include <FEXHeaderUtils/Syscalls.h>
 #include <FEXHeaderUtils/TodoDefines.h>
 
@@ -53,33 +60,24 @@ $end_info$
 #include <atomic>
 #include <chrono>
 #include <condition_variable>
-#include <filesystem>
+#include <fcntl.h>
 #include <functional>
-#include <fstream>
-#include <map>
-#include <memory>
 #include <mutex>
 #include <queue>
-#include <set>
 #include <shared_mutex>
 #include <signal.h>
 #include <stdio.h>
-#include <string.h>
-#include <string>
 #include <string_view>
-#include <sys/mman.h>
 #include <sys/stat.h>
-#include <sys/syscall.h>
 #include <type_traits>
 #include <unistd.h>
 #include <unordered_map>
 #include <utility>
-#include <vector>
 #include <xxhash.h>
 
 
 namespace FEXCore::CPU {
-  bool CreateCPUCore(FEXCore::Context::Context *CTX) {
+  bool CreateCPUCore(Context::ContextImpl *CTX) {
     // This should be used for generating things that are shared between threads
     CTX->CPUID.Init(CTX);
     return true;
@@ -147,16 +145,17 @@ std::string_view const& GetGRegName(unsigned Reg) {
 } // namespace FEXCore::Core
 
 namespace FEXCore::Context {
-  Context::Context()
+  ContextImpl::ContextImpl()
   : IRCaptureCache {this} {
 #ifdef BLOCKSTATS
     BlockData = std::make_unique<FEXCore::BlockSamplingData>();
 #endif
     if (Config.CacheObjectCodeCompilation() != FEXCore::Config::ConfigObjectCodeHandler::CONFIG_NONE) {
-      CodeObjectCacheService = std::make_unique<FEXCore::CodeSerialize::CodeObjectSerializeService>(this);
+      CodeObjectCacheService = fextl::make_unique<FEXCore::CodeSerialize::CodeObjectSerializeService>(this);
     }
-    if (!Config.EnableAVX) {
-      HostFeatures.SupportsAVX = false;
+    if (!Config.Is64BitMode()) {
+      // When operating in 32-bit mode, the virtual memory we care about is only the lower 32-bits.
+      Config.VirtualMemSize = 1ULL << 32;
     }
 
     if (Config.BlockJITNaming() ||
@@ -165,9 +164,16 @@ namespace FEXCore::Context {
       // Only initialize symbols file if enabled. Ensures we don't pollute /tmp with empty files.
       Symbols.InitFile();
     }
+
+    // Track atomic TSO emulation configuration.
+    UpdateAtomicTSOEmulationConfig();
   }
 
-  Context::~Context() {
+  ContextImpl::~ContextImpl() {
+    if (ParentThread) {
+      DestroyThread(ParentThread);
+    }
+
     {
       if (CodeObjectCacheService) {
         CodeObjectCacheService->Shutdown();
@@ -186,44 +192,39 @@ namespace FEXCore::Context {
     }
   }
 
-  static FEXCore::Core::CPUState CreateDefaultCPUState() {
-    FEXCore::Core::CPUState NewThreadState{};
+  uint64_t ContextImpl::RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState *Thread, uint64_t HostPC) {
+    const auto Frame = Thread->CurrentFrame;
+    const uint64_t BlockBegin = Frame->State.InlineJITBlockHeader;
+    const CPU::CPUBackend::JITCodeHeader *InlineHeader = reinterpret_cast<const CPU::CPUBackend::JITCodeHeader *>(BlockBegin);
 
-    // Initialize default CPU state
-    NewThreadState.rip = ~0ULL;
-    for (auto& greg : NewThreadState.gregs) {
-      greg = 0;
+    if (InlineHeader) {
+      const CPU::CPUBackend::JITCodeTail *InlineTail = reinterpret_cast<const CPU::CPUBackend::JITCodeTail *>(Frame->State.InlineJITBlockHeader + InlineHeader->OffsetToBlockTail);
+
+      // Check if the host PC is currently within a code block.
+      // If it is then RIP can be reconstructed from the beginning of the code block.
+      // This is currently as close as FEX can get RIP reconstructions.
+      if (HostPC >= reinterpret_cast<uint64_t>(BlockBegin) &&
+          HostPC < reinterpret_cast<uint64_t>(BlockBegin + InlineTail->Size)) {
+        return InlineTail->RIP;
+      }
     }
 
-    for (auto& xmm : NewThreadState.xmm.avx.data) {
-      xmm[0] = 0xDEADBEEFULL;
-      xmm[1] = 0xBAD0DAD1ULL;
-      xmm[2] = 0xDEADCAFEULL;
-      xmm[3] = 0xBAD2CAD3ULL;
-    }
-    memset(NewThreadState.flags, 0, Core::CPUState::NUM_EFLAG_BITS);
-    NewThreadState.flags[1] = 1;
-    NewThreadState.flags[9] = 1;
-    NewThreadState.FCW = 0x37F;
-    NewThreadState.FTW = 0xFFFF;
-    return NewThreadState;
+    // Fallback to what is stored in the RIP currently.
+    return Frame->State.rip;
   }
 
-  FEXCore::Core::InternalThreadState* Context::InitCore(uint64_t InitialRIP, uint64_t StackPointer) {
+  FEXCore::Core::InternalThreadState* ContextImpl::InitCore(uint64_t InitialRIP, uint64_t StackPointer) {
     // Initialize the CPU core signal handlers & DispatcherConfig
     switch (Config.Core) {
 #ifdef INTERPRETER_ENABLED
     case FEXCore::Config::CONFIG_INTERPRETER:
-      FEXCore::CPU::InitializeInterpreterSignalHandlers(this);
       BackendFeatures = FEXCore::CPU::GetInterpreterBackendFeatures();
       break;
 #endif
     case FEXCore::Config::CONFIG_IRJIT:
 #if (_M_X86_64 && JIT_X86_64)
-      FEXCore::CPU::InitializeX86JITSignalHandlers(this);
       BackendFeatures = FEXCore::CPU::GetX86JITBackendFeatures();
 #elif (_M_ARM_64 && JIT_ARM64) || defined(VIXL_SIMULATOR)
-      FEXCore::CPU::InitializeArm64JITSignalHandlers(this);
       BackendFeatures = FEXCore::CPU::GetArm64JITBackendFeatures();
 #else
       ERROR_AND_DIE_FMT("FEXCore has been compiled without a viable JIT core");
@@ -247,24 +248,37 @@ namespace FEXCore::Context {
     ERROR_AND_DIE_FMT("FEXCore has been compiled with an unknown target");
 #endif
 
-    // Initialize common signal handlers
+    // Set up the SignalDelegator config since core is initialized.
+    FEXCore::SignalDelegator::SignalDelegatorConfig SignalConfig {
+      .StaticRegisterAllocation = DispatcherConfig.StaticRegisterAllocation,
+      .SupportsAVX = HostFeatures.SupportsAVX,
 
-    auto PauseHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      return Thread->CTX->Dispatcher->HandleSignalPause(Thread, Signal, info, ucontext);
+      .DispatcherBegin = Dispatcher->Start,
+      .DispatcherEnd = Dispatcher->End,
+
+      .AbsoluteLoopTopAddressFillSRA = Dispatcher->AbsoluteLoopTopAddressFillSRA,
+      .SignalHandlerReturnAddress = Dispatcher->SignalHandlerReturnAddress,
+      .SignalHandlerReturnAddressRT = Dispatcher->SignalHandlerReturnAddressRT,
+
+      .PauseReturnInstruction = Dispatcher->PauseReturnInstruction,
+      .ThreadPauseHandlerAddressSpillSRA = Dispatcher->ThreadPauseHandlerAddressSpillSRA,
+      .ThreadPauseHandlerAddress = Dispatcher->ThreadPauseHandlerAddress,
+
+      // Stop handlers.
+      .ThreadStopHandlerAddressSpillSRA = Dispatcher->ThreadStopHandlerAddressSpillSRA,
+      .ThreadStopHandlerAddress = Dispatcher->ThreadStopHandlerAddress,
+
+      // SRA information.
+      .SRAGPRCount = Dispatcher->GetSRAGPRCount(),
+      .SRAFPRCount = Dispatcher->GetSRAFPRCount(),
     };
 
-    SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, PauseHandler, true);
+    Dispatcher->GetSRAGPRMapping(SignalConfig.SRAGPRMapping);
+    Dispatcher->GetSRAFPRMapping(SignalConfig.SRAFPRMapping);
 
-    auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
-      return Thread->CTX->Dispatcher->HandleGuestSignal(Thread, Signal, info, ucontext, GuestAction, GuestStack);
-    };
+    // Give this configuration to the SignalDelegator.
+    SignalDelegation->SetConfig(SignalConfig);
 
-    for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
-      SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
-    }
-
-    // Initialize GDBServer after the signal handlers are installed
-    // It may install its own handlers that need to be executed AFTER the CPU cores
     if (Config.GdbServer) {
       StartGdbServer();
     }
@@ -272,12 +286,13 @@ namespace FEXCore::Context {
       StopGdbServer();
     }
 
-    ThunkHandler.reset(FEXCore::ThunkHandler::Create());
+#ifndef _WIN32
+    ThunkHandler = FEXCore::ThunkHandler::Create();
+#endif
 
     using namespace FEXCore::Core;
 
-    FEXCore::Core::CPUState NewThreadState = CreateDefaultCPUState();
-    FEXCore::Core::InternalThreadState *Thread = CreateThread(&NewThreadState, 0);
+    FEXCore::Core::InternalThreadState *Thread = CreateThread(nullptr, 0);
 
     // We are the parent thread
     ParentThread = Thread;
@@ -290,30 +305,26 @@ namespace FEXCore::Context {
     return Thread;
   }
 
-  void Context::StartGdbServer() {
+  void ContextImpl::StartGdbServer() {
+#ifndef _WIN32
     if (!DebugServer) {
-      DebugServer = std::make_unique<GdbServer>(this);
+      DebugServer = fextl::make_unique<GdbServer>(this);
       StartPaused = true;
     }
+#endif
   }
 
-  void Context::StopGdbServer() {
+  void ContextImpl::StopGdbServer() {
+#ifndef _WIN32
     DebugServer.reset();
+#endif
   }
 
-  void Context::HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
-    Thread->CTX->Dispatcher->ExecuteJITCallback(Thread->CurrentFrame, RIP);
+  void ContextImpl::HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
+    static_cast<ContextImpl*>(Thread->CTX)->Dispatcher->ExecuteJITCallback(Thread->CurrentFrame, RIP);
   }
 
-  void Context::RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) {
-      SignalDelegation->RegisterHostSignalHandler(Signal, Func, Required);
-  }
-
-  void Context::RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) {
-    SignalDelegation->RegisterFrontendHostSignalHandler(Signal, Func, Required);
-  }
-
-  void Context::WaitForIdle() {
+  void ContextImpl::WaitForIdle() {
     std::unique_lock<std::mutex> lk(IdleWaitMutex);
     IdleWaitCV.wait(lk, [this] {
       return IdleWaitRefCount.load() == 0;
@@ -322,7 +333,7 @@ namespace FEXCore::Context {
     Running = false;
   }
 
-  void Context::WaitForIdleWithTimeout() {
+  void ContextImpl::WaitForIdleWithTimeout() {
     std::unique_lock<std::mutex> lk(IdleWaitMutex);
     bool WaitResult = IdleWaitCV.wait_for(lk, std::chrono::milliseconds(1500),
       [this] {
@@ -340,20 +351,16 @@ namespace FEXCore::Context {
     WaitForIdle();
   }
 
-  void Context::NotifyPause() {
+  void ContextImpl::NotifyPause() {
 
     // Tell all the threads that they should pause
     std::lock_guard<std::mutex> lk(ThreadCreationMutex);
     for (auto &Thread : Threads) {
-      Thread->SignalReason.store(FEXCore::Core::SignalEvent::Pause);
-      if (Thread->RunningEvents.Running.load()) {
-        // Only attempt to stop this thread if it is running
-        FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
-      }
+      SignalDelegation->SignalThread(Thread, FEXCore::Core::SignalEvent::Pause);
     }
   }
 
-  void Context::Pause() {
+  void ContextImpl::Pause() {
     // If we aren't running, WaitForIdle will never compete.
     if (Running) {
       NotifyPause();
@@ -362,7 +369,7 @@ namespace FEXCore::Context {
     }
   }
 
-  void Context::Run() {
+  void ContextImpl::Run() {
     // Spin up all the threads
     std::lock_guard<std::mutex> lk(ThreadCreationMutex);
     for (auto &Thread : Threads) {
@@ -374,7 +381,7 @@ namespace FEXCore::Context {
     }
   }
 
-  void Context::WaitForThreadsToRun() {
+  void ContextImpl::WaitForThreadsToRun() {
     size_t NumThreads{};
     {
       std::lock_guard<std::mutex> lk(ThreadCreationMutex);
@@ -390,7 +397,7 @@ namespace FEXCore::Context {
     Running = true;
   }
 
-  void Context::Step() {
+  void ContextImpl::Step() {
     {
       std::lock_guard<std::mutex> lk(ThreadCreationMutex);
       // Walk the threads and tell them to clear their caches
@@ -410,7 +417,7 @@ namespace FEXCore::Context {
     this->Config.MaxInstPerBlock = PreviousMaxIntPerBlock;
   }
 
-  void Context::Stop(bool IgnoreCurrentThread) {
+  void ContextImpl::Stop(bool IgnoreCurrentThread) {
     pid_t tid = FHU::Syscalls::gettid();
     FEXCore::Core::InternalThreadState* CurrentThread{};
 
@@ -448,21 +455,19 @@ namespace FEXCore::Context {
     }
   }
 
-  void Context::StopThread(FEXCore::Core::InternalThreadState *Thread) {
+  void ContextImpl::StopThread(FEXCore::Core::InternalThreadState *Thread) {
     if (Thread->RunningEvents.Running.exchange(false)) {
-      Thread->SignalReason.store(FEXCore::Core::SignalEvent::Stop);
-      FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
+      SignalDelegation->SignalThread(Thread, FEXCore::Core::SignalEvent::Stop);
     }
   }
 
-  void Context::SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event) {
+  void ContextImpl::SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event) {
     if (Thread->RunningEvents.Running.load()) {
-      Thread->SignalReason.store(Event);
-      FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
+      SignalDelegation->SignalThread(Thread, Event);
     }
   }
 
-  FEXCore::Context::ExitReason Context::RunUntilExit() {
+  FEXCore::Context::ExitReason ContextImpl::RunUntilExit() {
     if(!StartPaused) {
       // We will only have one thread at this point, but just in case run notify everything
       std::lock_guard lk(ThreadCreationMutex);
@@ -483,16 +488,16 @@ namespace FEXCore::Context {
     }
   }
 
-  int Context::GetProgramStatus() const {
+  int ContextImpl::GetProgramStatus() const {
     return ParentThread->StatusCode;
   }
 
-  void Context::InitializeThreadData(FEXCore::Core::InternalThreadState *Thread) {
+  void ContextImpl::InitializeThreadData(FEXCore::Core::InternalThreadState *Thread) {
     Thread->CPUBackend->Initialize();
   }
 
   struct ExecutionThreadHandler {
-    FEXCore::Context::Context *This;
+    ContextImpl *This;
     FEXCore::Core::InternalThreadState *Thread;
   };
 
@@ -503,7 +508,7 @@ namespace FEXCore::Context {
     return nullptr;
   }
 
-  void Context::InitializeThread(FEXCore::Core::InternalThreadState *Thread) {
+  void ContextImpl::InitializeThread(FEXCore::Core::InternalThreadState *Thread) {
     // This will create the execution thread but it won't actually start executing
     ExecutionThreadHandler *Arg = reinterpret_cast<ExecutionThreadHandler*>(FEXCore::Allocator::malloc(sizeof(ExecutionThreadHandler)));
     Arg->This = this;
@@ -525,25 +530,27 @@ namespace FEXCore::Context {
     }
   }
 
-  void Context::InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread) {
+  void ContextImpl::InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread) {
     // Let's do some initial bookkeeping here
     Thread->ThreadManager.TID = FHU::Syscalls::gettid();
     Thread->ThreadManager.PID = ::getpid();
     SignalDelegation->RegisterTLSState(Thread);
-    ThunkHandler->RegisterTLSState(Thread);
+    if (ThunkHandler) {
+      ThunkHandler->RegisterTLSState(Thread);
+    }
   }
 
-  void Context::RunThread(FEXCore::Core::InternalThreadState *Thread) {
+  void ContextImpl::RunThread(FEXCore::Core::InternalThreadState *Thread) {
     // Tell the thread to start executing
     Thread->StartRunning.NotifyAll();
   }
 
-  void Context::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread) {
-    Thread->OpDispatcher = std::make_unique<FEXCore::IR::OpDispatchBuilder>(this);
+  void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread) {
+    Thread->OpDispatcher = fextl::make_unique<FEXCore::IR::OpDispatchBuilder>(this);
     Thread->OpDispatcher->SetMultiblock(Config.Multiblock);
-    Thread->LookupCache = std::make_unique<FEXCore::LookupCache>(this);
-    Thread->FrontendDecoder = std::make_unique<FEXCore::Frontend::Decoder>(this);
-    Thread->PassManager = std::make_unique<FEXCore::IR::PassManager>();
+    Thread->LookupCache = fextl::make_unique<FEXCore::LookupCache>(this);
+    Thread->FrontendDecoder = fextl::make_unique<FEXCore::Frontend::Decoder>(this);
+    Thread->PassManager = fextl::make_unique<FEXCore::IR::PassManager>();
     Thread->PassManager->RegisterExitHandler([this]() {
         Stop(false /* Ignore current thread */);
     });
@@ -590,11 +597,13 @@ namespace FEXCore::Context {
     }
   }
 
-  FEXCore::Core::InternalThreadState* Context::CreateThread(FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) {
+  FEXCore::Core::InternalThreadState* ContextImpl::CreateThread(FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) {
     FEXCore::Core::InternalThreadState *Thread = new FEXCore::Core::InternalThreadState{};
 
     // Copy over the new thread state to the new object
-    memcpy(Thread->CurrentFrame, NewThreadState, sizeof(FEXCore::Core::CPUState));
+    if (NewThreadState) {
+      memcpy(Thread->CurrentFrame, NewThreadState, sizeof(FEXCore::Core::CPUState));
+    }
     Thread->CurrentFrame->Thread = Thread;
 
     // Set up the thread manager state
@@ -603,6 +612,9 @@ namespace FEXCore::Context {
     InitializeCompiler(Thread);
     InitializeThreadData(Thread);
 
+    Thread->CurrentFrame->State.DeferredSignalRefCount.Store(0);
+    Thread->CurrentFrame->State.DeferredSignalFaultAddress = reinterpret_cast<Core::NonAtomicRefCounter<uint64_t>*>(FEXCore::Allocator::VirtualAlloc(4096));
+
     // Insert after the Thread object has been fully initialized
     {
       std::lock_guard lk(ThreadCreationMutex);
@@ -612,7 +624,7 @@ namespace FEXCore::Context {
     return Thread;
   }
 
-  void Context::DestroyThread(FEXCore::Core::InternalThreadState *Thread) {
+  void ContextImpl::DestroyThread(FEXCore::Core::InternalThreadState *Thread) {
     // remove new thread object
     {
       std::lock_guard lk(ThreadCreationMutex);
@@ -628,10 +640,12 @@ namespace FEXCore::Context {
       // To be able to delete a thread from itself, we need to detached the std::thread object
       Thread->ExecutionThread->detach();
     }
+
+    FEXCore::Allocator::VirtualFree(reinterpret_cast<void*>(Thread->CurrentFrame->State.DeferredSignalFaultAddress), 4096);
     delete Thread;
   }
 
-  void Context::CleanupAfterFork(FEXCore::Core::InternalThreadState *LiveThread) {
+  void ContextImpl::CleanupAfterFork(FEXCore::Core::InternalThreadState *LiveThread) {
     // This function is called after fork
     // We need to cleanup some of the thread data that is dead
     for (auto &DeadThread : Threads) {
@@ -670,11 +684,11 @@ namespace FEXCore::Context {
     FEXCore::Threads::Thread::CleanupAfterFork();
   }
 
-  void Context::AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr) {
+  void ContextImpl::AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr) {
     Thread->LookupCache->AddBlockMapping(Address, Ptr);
   }
 
-  void Context::ClearCodeCache(FEXCore::Core::InternalThreadState *Thread) {
+  void ContextImpl::ClearCodeCache(FEXCore::Core::InternalThreadState *Thread) {
     FEXCORE_PROFILE_INSTANT("ClearCodeCache");
 
     {
@@ -690,49 +704,46 @@ namespace FEXCore::Context {
   }
 
   static void IRDumper(FEXCore::Core::InternalThreadState *Thread, IR::IREmitter *IREmitter, uint64_t GuestRIP, IR::RegisterAllocationData* RA) {
-    FILE* f = nullptr;
-    bool CloseAfter = false;
-    const auto DumpIRStr = Thread->CTX->Config.DumpIR();
+    FEXCore::File::File FD;
+    const auto DumpIRStr = static_cast<ContextImpl*>(Thread->CTX)->Config.DumpIR();
 
     // DumpIRStr might be no if not dumping but ShouldDump is set in OpDisp
     if (DumpIRStr =="stderr" || DumpIRStr =="no") {
-      f = stderr;
+      FD = FEXCore::File::File::GetStdERR();
     }
     else if (DumpIRStr =="stdout") {
-      f = stdout;
+      FD = FEXCore::File::File::GetStdOUT();
     }
     else {
-      const auto fileName = fmt::format("{}/{:x}{}", DumpIRStr, GuestRIP, RA ? "-post.ir" : "-pre.ir");
-      f = fopen(fileName.c_str(), "w");
-      CloseAfter = true;
+      const auto fileName = fextl::fmt::format("{}/{:x}{}", DumpIRStr, GuestRIP, RA ? "-post.ir" : "-pre.ir");
+      FD = FEXCore::File::File(fileName.c_str(),
+        FEXCore::File::FileModes::WRITE |
+        FEXCore::File::FileModes::CREATE |
+        FEXCore::File::FileModes::TRUNCATE);
     }
 
-    if (f) {
-      std::stringstream out;
+    if (FD.IsValid()) {
+      fextl::stringstream out;
       auto NewIR = IREmitter->ViewIR();
       FEXCore::IR::Dump(&out, &NewIR, RA);
-      fmt::print(f,"IR-{} 0x{:x}:\n{}\n@@@@@\n", RA ? "post" : "pre", GuestRIP, out.str());
-
-      if (CloseAfter) {
-        fclose(f);
-      }
+      fextl::fmt::print(FD, "IR-{} 0x{:x}:\n{}\n@@@@@\n", RA ? "post" : "pre", GuestRIP, out.str());
     }
   };
 
-  static void ValidateIR(FEXCore::Context::Context *ctx, IR::IREmitter *IREmitter) {
+  static void ValidateIR(ContextImpl *ctx, IR::IREmitter *IREmitter) {
     // Convert to text, Parse, Convert to text again and make sure the texts match
-    std::stringstream out;
+    fextl::stringstream out;
     static auto compaction = IR::CreateIRCompaction(ctx->OpDispatcherAllocator);
     compaction->Run(IREmitter);
     auto NewIR = IREmitter->ViewIR();
     Dump(&out, &NewIR, nullptr);
     out.seekg(0);
     FEXCore::Utils::PooledAllocatorMalloc Allocator;
-    auto reparsed = IR::Parse(Allocator, &out);
+    auto reparsed = IR::Parse(Allocator, out);
     if (reparsed == nullptr) {
       LOGMAN_MSG_A_FMT("Failed to parse IR\n");
     } else {
-      std::stringstream out2;
+      fextl::stringstream out2;
       auto NewIR2 = reparsed->ViewIR();
       Dump(&out2, &NewIR2, nullptr);
       if (out.str() != out2.str()) {
@@ -743,7 +754,7 @@ namespace FEXCore::Context {
     }
   }
 
-  Context::GenerateIRResult Context::GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, bool ExtendedDebugInfo) {
+  ContextImpl::GenerateIRResult ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, bool ExtendedDebugInfo) {
     FEXCORE_PROFILE_SCOPED("GenerateIR");
 
     Thread->OpDispatcher->ReownOrClaimBuffer();
@@ -770,7 +781,7 @@ namespace FEXCore::Context {
 
       Thread->FrontendDecoder->DecodeInstructionsAtEntry(GuestCode, GuestRIP, [Thread](uint64_t BlockEntry, uint64_t Start, uint64_t Length) {
         if (Thread->LookupCache->AddBlockExecutableRange(BlockEntry, Start, Length)) {
-          Thread->CTX->SyscallHandler->MarkGuestExecutableRange(Start, Length);
+          static_cast<ContextImpl*>(Thread->CTX)->SyscallHandler->MarkGuestExecutableRange(Thread, Start, Length);
         }
       });
 
@@ -790,13 +801,6 @@ namespace FEXCore::Context {
         // Reset any block-specific state
         Thread->OpDispatcher->StartNewBlock();
 
-        if (Config.x86dec_SynchronizeRIPOnAllBlocks) {
-          // Ensure the RIP is synchronized to the context on block entry.
-          // In the case of block linking, the RIP may not have synchronized.
-          auto NewRIP = Thread->OpDispatcher->_EntrypointOffset(Block.Entry - GuestRIP, GPRSize);
-          Thread->OpDispatcher->_StoreContext(GPRSize, IR::GPRClass, NewRIP, offsetof(FEXCore::Core::CPUState, rip));
-        }
-
         uint64_t InstsInBlock = Block.NumInstructions;
 
         for (size_t i = 0; i < InstsInBlock; ++i) {
@@ -851,27 +855,33 @@ namespace FEXCore::Context {
             }
           }
           else {
+            if (TableInfo) {
+              LogMan::Msg::EFmt("Invalid or Unknown instruction: {} 0x{:x}", TableInfo->Name ?: "UND", Block.Entry - GuestRIP);
+            }
             // Invalid instruction
             Thread->OpDispatcher->InvalidOp(DecodedInfo);
             Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(Block.Entry - GuestRIP, GPRSize));
           }
 
-          // If we had a dispatch error then leave early
-          if (HadDispatchError) {
-            if (TotalInstructions == 0) {
-              // Couldn't handle any instruction in op dispatcher
-              Thread->OpDispatcher->ResetWorkingList();
-              return { nullptr, nullptr, 0, 0, 0, 0 };
-            }
-            else {
-              const uint8_t GPRSize = GetGPRSize();
+          const bool NeedsBlockEnd = (HadDispatchError && TotalInstructions > 0) ||
+            (Thread->OpDispatcher->NeedsBlockEnder() && i + 1 == InstsInBlock);
 
-              // We had some instructions. Early exit
-              Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(Block.Entry + BlockInstructionsLength - GuestRIP, GPRSize));
-              break;
-            }
+          // If we had a dispatch error then leave early
+          if (HadDispatchError && TotalInstructions == 0) {
+            // Couldn't handle any instruction in op dispatcher
+            Thread->OpDispatcher->ResetWorkingList();
+            return { nullptr, nullptr, 0, 0, 0, 0 };
           }
 
+          if (NeedsBlockEnd) {
+            const uint8_t GPRSize = GetGPRSize();
+
+            // We had some instructions. Early exit
+            Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(Block.Entry + BlockInstructionsLength - GuestRIP, GPRSize));
+            break;
+          }
+
+
           if (Thread->OpDispatcher->FinishOp(DecodedInfo->PC + DecodedInfo->InstSize, i + 1 == InstsInBlock)) {
             break;
           }
@@ -885,14 +895,14 @@ namespace FEXCore::Context {
 
     IR::IREmitter *IREmitter = Thread->OpDispatcher.get();
 
-    auto ShouldDump = Thread->CTX->Config.DumpIR() != "no" || Thread->OpDispatcher->ShouldDump;
+    auto ShouldDump = static_cast<ContextImpl*>(Thread->CTX)->Config.DumpIR() != "no" || Thread->OpDispatcher->ShouldDump;
     // Debug
     {
       if (ShouldDump) {
         IRDumper(Thread, IREmitter, GuestRIP, nullptr);
       }
 
-      if (Thread->CTX->Config.ValidateIRarser) {
+      if (static_cast<ContextImpl*>(Thread->CTX)->Config.ValidateIRarser) {
         ValidateIR(this, IREmitter);
       }
     }
@@ -922,7 +932,7 @@ namespace FEXCore::Context {
     };
   }
 
-  Context::CompileCodeResult Context::CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
+  ContextImpl::CompileCodeResult ContextImpl::CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
     FEXCore::IR::IRListView *IRList {};
     FEXCore::Core::DebugData *DebugData {};
     FEXCore::IR::RegisterAllocationData::UniquePtr RAData {};
@@ -950,7 +960,7 @@ namespace FEXCore::Context {
     }
 
     if (SourcecodeResolver && Config.GDBSymbols()) {
-      auto AOTIRCacheEntry = SyscallHandler->LookupAOTIRCacheEntry(GuestRIP);
+      auto AOTIRCacheEntry = SyscallHandler->LookupAOTIRCacheEntry(Thread, GuestRIP);
       if (AOTIRCacheEntry.Entry && !AOTIRCacheEntry.Entry->ContainsCode) {
         AOTIRCacheEntry.Entry->SourcecodeMap =
             SourcecodeResolver->GenerateMap(AOTIRCacheEntry.Entry->Filename, AOTIRCacheEntry.Entry->FileId);
@@ -959,7 +969,7 @@ namespace FEXCore::Context {
 
     // AOT IR bookkeeping and cache
     {
-      auto [IRCopy, RACopy, DebugDataCopy, _StartAddr, _Length, _GeneratedIR] = IRCaptureCache.PreGenerateIRFetch(GuestRIP, IRList);
+      auto [IRCopy, RACopy, DebugDataCopy, _StartAddr, _Length, _GeneratedIR] = IRCaptureCache.PreGenerateIRFetch(Thread, GuestRIP, IRList);
       if (_GeneratedIR) {
         // Setup pointers to internal structures
         IRList = IRCopy;
@@ -982,9 +992,6 @@ namespace FEXCore::Context {
       StartAddr = _StartAddr;
       Length = _Length;
 
-      // Increment stats
-      Thread->Stats.BlocksCompiled.fetch_add(1);
-
       // These blocks aren't already in the cache
       GeneratedIR = true;
     }
@@ -994,7 +1001,10 @@ namespace FEXCore::Context {
     }
     // Attempt to get the CPU backend to compile this code
     return {
-      .CompiledCode = Thread->CPUBackend->CompileCode(GuestRIP, IRList, DebugData, RAData.get(), GetGdbServerStatus()),
+      // FEX currently throws away the CPUBackend::CompiledCode object other than the entrypoint
+      // In the future with code caching getting wired up, we will pass the rest of the data forward.
+      // TODO: Pass the data forward when code caching is wired up to this.
+      .CompiledCode = Thread->CPUBackend->CompileCode(GuestRIP, IRList, DebugData, RAData.get(), GetGdbServerStatus()).BlockEntry,
       .IRData = IRList,
       .DebugData = DebugData,
       .RAData = std::move(RAData),
@@ -1004,7 +1014,7 @@ namespace FEXCore::Context {
     };
   }
 
-  void Context::CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
+  void ContextImpl::CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
     auto NewBlock = CompileBlock(Frame, GuestRIP);
 
     if (NewBlock == 0) {
@@ -1015,7 +1025,7 @@ namespace FEXCore::Context {
     }
   }
 
-  uintptr_t Context::CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
+  uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
     FEXCORE_PROFILE_SCOPED("CompileBlock");
     auto Thread = Frame->Thread;
 
@@ -1052,7 +1062,7 @@ namespace FEXCore::Context {
       auto FragmentBasePtr = reinterpret_cast<uint8_t *>(CodePtr);
 
       if (DebugData) {
-        auto GuestRIPLookup = SyscallHandler->LookupAOTIRCacheEntry(GuestRIP);
+        auto GuestRIPLookup = SyscallHandler->LookupAOTIRCacheEntry(Thread, GuestRIP);
 
         if (DebugData->Subblocks.size()) {
           for (auto& Subblock: DebugData->Subblocks) {
@@ -1077,7 +1087,7 @@ namespace FEXCore::Context {
     if (CodeObjectCacheService &&
         Config.CacheObjectCodeCompilation == FEXCore::Config::ConfigObjectCodeHandler::CONFIG_READWRITE &&
         DebugData) {
-      CodeObjectCacheService->AsyncAddSerializationJob(std::make_unique<CodeSerialize::AsyncJobHandler::SerializationJobData>(
+      CodeObjectCacheService->AsyncAddSerializationJob(fextl::make_unique<CodeSerialize::AsyncJobHandler::SerializationJobData>(
         CodeSerialize::AsyncJobHandler::SerializationJobData {
           .GuestRIP = GuestRIP,
           .GuestCodeLength = Length,
@@ -1115,18 +1125,19 @@ namespace FEXCore::Context {
     return (uintptr_t)CodePtr;
   }
 
-  void Context::ExecutionThread(FEXCore::Core::InternalThreadState *Thread) {
+  void ContextImpl::ExecutionThread(FEXCore::Core::InternalThreadState *Thread) {
     Core::ThreadData.Thread = Thread;
     Thread->ExitReason = FEXCore::Context::ExitReason::EXIT_WAITING;
 
     InitializeThreadTLSData(Thread);
+    Alloc::OSAllocator::RegisterTLSData(Thread);
 
     ++IdleWaitRefCount;
 
     // Now notify the thread that we are initialized
     Thread->ThreadWaiting.NotifyAll();
 
-    if (Thread != Thread->CTX->ParentThread || StartPaused || Thread->StartPaused) {
+    if (Thread != static_cast<ContextImpl*>(Thread->CTX)->ParentThread || StartPaused || Thread->StartPaused) {
       // Parent thread doesn't need to wait to run
       Thread->StartRunning.Wait();
     }
@@ -1138,7 +1149,7 @@ namespace FEXCore::Context {
 
       Thread->RunningEvents.Running = true;
 
-      Thread->CTX->Dispatcher->ExecuteDispatch(Thread->CurrentFrame);
+      static_cast<ContextImpl*>(Thread->CTX)->Dispatcher->ExecuteDispatch(Thread->CurrentFrame);
 
       Thread->RunningEvents.Running = false;
     }
@@ -1164,10 +1175,11 @@ namespace FEXCore::Context {
     --IdleWaitRefCount;
     IdleWaitCV.notify_all();
 
+    Alloc::OSAllocator::UninstallTLSData(Thread);
     SignalDelegation->UninstallTLSState(Thread);
 
     // If the parent thread is waiting to join, then we can't destroy our thread object
-    if (!Thread->DestroyedByParent && Thread != Thread->CTX->ParentThread) {
+    if (!Thread->DestroyedByParent && Thread != static_cast<ContextImpl*>(Thread->CTX)->ParentThread) {
       Thread->CTX->DestroyThread(Thread);
     }
   }
@@ -1180,40 +1192,45 @@ namespace FEXCore::Context {
 
     for (auto it = lower; it != upper; it++) {
       for (auto Address: it->second) {
-        Context::ThreadRemoveCodeEntry(Thread, Address);
+        ContextImpl::ThreadRemoveCodeEntry(Thread, Address);
       }
       it->second.clear();
     }
   }
 
-  static void InvalidateGuestCodeRangeInternal(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length) {
-    std::lock_guard lk(CTX->ThreadCreationMutex);
+  static void InvalidateGuestCodeRangeInternal(ContextImpl *CTX, uint64_t Start, uint64_t Length) {
+    std::lock_guard lk(static_cast<ContextImpl*>(CTX)->ThreadCreationMutex);
 
-    for (auto &Thread : CTX->Threads) {
+    for (auto &Thread : static_cast<ContextImpl*>(CTX)->Threads) {
       InvalidateGuestThreadCodeRange(Thread, Start, Length);
     }
   }
 
-  void InvalidateGuestCodeRange(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length) {
-    FHU::ScopedSignalMaskWithUniqueLock CodeInvalidationLock(CTX->CodeInvalidationMutex);
+  void ContextImpl::InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length) {
+    // Potential deferred since Thread might not be valid.
+    // Thread object isn't valid very early in frontend's initialization.
+    // To be more optimal the frontend should provide this code with a valid Thread object earlier.
+    ScopedPotentialDeferredSignalWithUniqueLock CodeInvalidationLock(CodeInvalidationMutex, Thread);
 
-    InvalidateGuestCodeRangeInternal(CTX, Start, Length);
+    InvalidateGuestCodeRangeInternal(this, Start, Length);
   }
 
-  void InvalidateGuestCodeRange(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length, std::function<void(uint64_t start, uint64_t Length)> CallAfter) {
-    FHU::ScopedSignalMaskWithUniqueLock CodeInvalidationLock(CTX->CodeInvalidationMutex);
+  void ContextImpl::InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length, std::function<void(uint64_t start, uint64_t Length)> CallAfter) {
+    // Potential deferred since Thread might not be valid.
+    // Thread object isn't valid very early in frontend's initialization.
+    // To be more optimal the frontend should provide this code with a valid Thread object earlier.
+    ScopedPotentialDeferredSignalWithUniqueLock CodeInvalidationLock(CodeInvalidationMutex, Thread);
 
-    InvalidateGuestCodeRangeInternal(CTX, Start, Length);
+    InvalidateGuestCodeRangeInternal(this, Start, Length);
     CallAfter(Start, Length);
   }
 
-  void Context::MarkMemoryShared() {
+  void ContextImpl::MarkMemoryShared() {
     if (!IsMemoryShared) {
       IsMemoryShared = true;
+      UpdateAtomicTSOEmulationConfig();
 
       if (Config.TSOAutoMigration) {
-        LogMan::Msg::IFmt("Migrating to shared memory mode");
-
         std::lock_guard<std::mutex> lkThreads(ThreadCreationMutex);
         LogMan::Throw::AFmt(Threads.size() == 1, "First MarkMemoryShared called must be before creating any threads");
 
@@ -1229,18 +1246,14 @@ namespace FEXCore::Context {
     }
   }
 
-  void MarkMemoryShared(FEXCore::Context::Context *CTX) {
-    CTX->MarkMemoryShared();
-  }
-
-  void Context::ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker) {
-    std::shared_lock lk(Thread->CTX->CodeInvalidationMutex);
+  void ContextImpl::ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker) {
+    std::shared_lock lk(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex);
 
     Thread->LookupCache->AddBlockLink(GuestDestination, HostLink, delinker);
   }
 
-  void Context::ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
-    LogMan::Throw::AFmt(Thread->CTX->CodeInvalidationMutex.try_lock() == false, "CodeInvalidationMutex needs to be unique_locked here");
+  void ContextImpl::ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
+    LogMan::Throw::AFmt(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex.try_lock() == false, "CodeInvalidationMutex needs to be unique_locked here");
 
     std::lock_guard<std::recursive_mutex> lk(Thread->LookupCache->WriteLock);
 
@@ -1248,7 +1261,7 @@ namespace FEXCore::Context {
     Thread->LookupCache->Erase(GuestRIP);
   }
 
-  CustomIRResult Context::AddCustomIREntrypoint(uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator, void *Data) {
+  CustomIRResult ContextImpl::AddCustomIREntrypoint(uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator, void *Data) {
     LOGMAN_THROW_A_FMT(Config.Is64BitMode || !(Entrypoint >> 32), "64-bit Entrypoint in 32-bit mode {:x}", Entrypoint);
 
     std::unique_lock lk(CustomIRMutex);
@@ -1264,66 +1277,23 @@ namespace FEXCore::Context {
     }
   }
 
-  void Context::RemoveCustomIREntrypoint(uintptr_t Entrypoint) {
+  void ContextImpl::RemoveCustomIREntrypoint(uintptr_t Entrypoint) {
     LOGMAN_THROW_A_FMT(Config.Is64BitMode || !(Entrypoint >> 32), "64-bit Entrypoint in 32-bit mode {:x}", Entrypoint);
 
     std::scoped_lock lk(CustomIRMutex);
 
-    InvalidateGuestCodeRange(this, Entrypoint, 1, [this](uint64_t Entrypoint, uint64_t) {
+    InvalidateGuestCodeRange(nullptr, Entrypoint, 1, [this](uint64_t Entrypoint, uint64_t) {
       CustomIRHandlers.erase(Entrypoint);
     });
   }
 
-  // Debug interface
-  void Context::CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
-    uint64_t RIPBackup = Thread->CurrentFrame->State.rip;
-    Thread->CurrentFrame->State.rip = RIP;
-
-    // Erase the RIP from all the storage backings if it exists
-    ThreadRemoveCodeEntry(Thread, RIP);
-
-    // We don't care if compilation passes or not
-    CompileBlock(Thread->CurrentFrame, RIP);
-
-    Thread->CurrentFrame->State.rip = RIPBackup;
-  }
-
-  uint64_t Context::GetThreadCount() const {
-    return Threads.size();
-  }
-
-  FEXCore::Core::RuntimeStats *Context::GetRuntimeStatsForThread(uint64_t Thread) {
-    return &Threads[Thread]->Stats;
-  }
-
-  bool Context::GetDebugDataForRIP(uint64_t RIP, FEXCore::Core::DebugData *Data) {
-    std::lock_guard<std::recursive_mutex> lk(ParentThread->LookupCache->WriteLock);
-    auto it = ParentThread->DebugStore.find(RIP);
-    if (it == ParentThread->DebugStore.end()) {
-      return false;
-    }
-
-    memcpy(Data, it->second.DebugData.get(), sizeof(FEXCore::Core::DebugData));
-    return true;
-  }
-
-  bool Context::FindHostCodeForRIP(uint64_t RIP, uint8_t **Code) {
-    uintptr_t HostCode = ParentThread->LookupCache->FindBlock(RIP);
-    if (!HostCode) {
-      return false;
-    }
-
-    *Code = reinterpret_cast<uint8_t*>(HostCode);
-    return true;
-  }
-
   uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args) {
     uint64_t Result{};
     Result = Handler->HandleSyscall(Frame, Args);
     return Result;
   }
 
-  IR::AOTIRCacheEntry *Context::LoadAOTIRCacheEntry(const std::string &filename) {
+  IR::AOTIRCacheEntry *ContextImpl::LoadAOTIRCacheEntry(const fextl::string &filename) {
     auto rv = IRCaptureCache.LoadAOTIRCacheEntry(filename);
     if (DebugServer) {
       DebugServer->AlertLibrariesChanged();
@@ -1331,19 +1301,20 @@ namespace FEXCore::Context {
     return rv;
   }
 
-  void Context::UnloadAOTIRCacheEntry(IR::AOTIRCacheEntry *Entry) {
+  void ContextImpl::UnloadAOTIRCacheEntry(IR::AOTIRCacheEntry *Entry) {
     IRCaptureCache.UnloadAOTIRCacheEntry(Entry);
     if (DebugServer) {
       DebugServer->AlertLibrariesChanged();
     }
   }
 
-
-  void Context::AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) {
-    ThunkHandler->AppendThunkDefinitions(Definitions);
+  void ContextImpl::AppendThunkDefinitions(fextl::vector<FEXCore::IR::ThunkDefinition> const& Definitions) {
+    if (ThunkHandler) {
+      ThunkHandler->AppendThunkDefinitions(Definitions);
+    }
   }
 
-  void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, std::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) {
+  void ContextImpl::ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) {
     Thread->FrontendDecoder->SetExternalBranches(ExternalBranches);
     Thread->FrontendDecoder->SetSectionMaxAddress(SectionMaxAddress);
   }

External/FEXCore/Source/Interface/Core/Core.h

@@ -5,7 +5,7 @@ namespace FEXCore {
 }
 
 namespace FEXCore::Context {
-  struct Context;
+  class ContextImpl;
 }
 
 namespace FEXCore::CPU {
@@ -17,7 +17,7 @@ namespace FEXCore::CPU {
    *
    * @return true if core was able to be create
    */
-  bool CreateCPUCore(FEXCore::Context::Context *CTX);
+  bool CreateCPUCore(FEXCore::Context::ContextImpl *CTX);
 
-  bool LoadCode(FEXCore::Context::Context *CTX, FEXCore::CodeLoader *Loader);
+  bool LoadCode(FEXCore::Context::ContextImpl *CTX, FEXCore::CodeLoader *Loader);
 }

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp

@@ -1,6 +1,6 @@
+#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/LookupCache.h"
 
-#include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
 #include "Interface/Core/Interpreter/InterpreterClass.h"
 
@@ -11,6 +11,7 @@
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXCore/fextl/memory.h>
 #include <FEXHeaderUtils/Syscalls.h>
 
 #include <array>
@@ -27,32 +28,30 @@
 #include <code-buffer-vixl.h>
 #include <platform-vixl.h>
 
-#include <sys/syscall.h>
 #include <unistd.h>
 
-#define STATE_PTR(STATE_TYPE, FIELD) \
-  MemOperand(STATE, offsetof(FEXCore::Core::STATE_TYPE, FIELD))
-
 namespace FEXCore::CPU {
 
-using namespace vixl;
-using namespace vixl::aarch64;
+constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
 
-constexpr size_t MAX_DISPATCHER_CODE_SIZE = 8192;
-
-Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &config)
+Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config)
   : FEXCore::CPU::Dispatcher(ctx, config), Arm64Emitter(ctx, MAX_DISPATCHER_CODE_SIZE)
 #ifdef VIXL_SIMULATOR
   , Simulator {&Decoder}
 #endif
 {
-
 #ifdef VIXL_SIMULATOR
   // Hardcode a 256-bit vector width if we are running in the simulator.
   Simulator.SetVectorLengthInBits(256);
 #endif
 
-  SetAllowAssembler(true);
+  EmitDispatcher();
+}
+
+void Arm64Dispatcher::EmitDispatcher() {
+#ifdef VIXL_DISASSEMBLER
+  const auto DisasmBegin = GetCursorAddress<const vixl::aarch64::Instruction*>();
+#endif
 
   DispatchPtr = GetCursorAddress<AsmDispatch>();
 
@@ -64,9 +63,9 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   //    Ptr();
   // }
 
-  Literal l_CTX {reinterpret_cast<uintptr_t>(CTX)};
-  Literal l_Sleep {reinterpret_cast<uint64_t>(SleepThread)};
-  Literal l_CompileBlock {GetCompileBlockPtr()};
+  ARMEmitter::ForwardLabel l_CTX;
+  ARMEmitter::ForwardLabel l_Sleep;
+  ARMEmitter::ForwardLabel l_CompileBlock;
 
   // Push all the register we need to save
   PushCalleeSavedRegisters();
@@ -74,12 +73,12 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   // Push our memory base to the correct register
   // Move our thread pointer to the correct register
   // This is passed in to parameter 0 (x0)
-  mov(STATE, x0);
+  mov(STATE, ARMEmitter::XReg::x0);
 
   // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
   // regardless of where we were in the stack
-  add(x0, sp, 0);
-  str(x0, STATE_PTR(CpuStateFrame, ReturningStackLocation));
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, ARMEmitter::Reg::rsp, 0);
+  str(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, ReturningStackLocation));
 
   AbsoluteLoopTopAddressFillSRA = GetCursorAddress<uint64_t>();
 
@@ -89,94 +88,95 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
 
   // We want to ensure that we are 16 byte aligned at the top of this loop
   Align16B();
-  aarch64::Label FullLookup{};
-  aarch64::Label CallBlock{};
-  aarch64::Label LoopTop{};
-  aarch64::Label ExitSpillSRA{};
-  aarch64::Label ThreadPauseHandler{};
+  ARMEmitter::BiDirectionalLabel FullLookup{};
+  ARMEmitter::BiDirectionalLabel CallBlock{};
+  ARMEmitter::BackwardLabel LoopTop{};
 
-  bind(&LoopTop);
-  AbsoluteLoopTopAddress = GetLabelAddress<uint64_t>(&LoopTop);
+  Bind(&LoopTop);
+  AbsoluteLoopTopAddress = GetCursorAddress<uint64_t>();
 
   // Load in our RIP
   // Don't modify x2 since it contains our RIP once the block doesn't exist
-  ldr(x2, STATE_PTR(CpuStateFrame, State.rip));
-  auto RipReg = x2;
+
+  auto RipReg = ARMEmitter::XReg::x2;
+  ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));
 
   // L1 Cache
-  ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
+  ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
 
-  and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
-  add(x0, x0, Operand(x3, Shift::LSL, 4));
-  ldp(x3, x0, MemOperand(x0));
-  cmp(x0, RipReg);
-  b(&FullLookup, Condition::ne);
+  and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, ARMEmitter::Reg::r0, ARMEmitter::Reg::r3, ARMEmitter::ShiftType::LSL , 4);
+  ldp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::XReg::x3, ARMEmitter::XReg::x0, ARMEmitter::Reg::r0, 0);
+  cmp(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, RipReg.R());
+  b(ARMEmitter::Condition::CC_NE, &FullLookup);
 
-  br(x3);
+  br(ARMEmitter::Reg::r3);
 
   // L1C check failed, do a full lookup
-  bind(&FullLookup);
+  Bind(&FullLookup);
 
   // This is the block cache lookup routine
   // It matches what is going on it LookupCache.h::FindBlock
-  ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.L2Pointer));
+  ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.L2Pointer));
 
   // Mask the address by the virtual address size so we can check for aliases
   uint64_t VirtualMemorySize = CTX->Config.VirtualMemSize;
   if (std::popcount(VirtualMemorySize) == 1) {
-    and_(x3, RipReg, VirtualMemorySize - 1);
+    and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg.R(), VirtualMemorySize - 1);
   }
   else {
-    LoadConstant(x3, VirtualMemorySize);
-    and_(x3, RipReg, x3);
+    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, VirtualMemorySize);
+    and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg.R(), ARMEmitter::Reg::r3);
   }
 
-  aarch64::Label NoBlock;
+  ARMEmitter::ForwardLabel NoBlock;
+
   {
     // Offset the address and add to our page pointer
-    lsr(x1, x3, 12);
+    lsr(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::r3, 12);
 
     // Load the pointer from the offset
-    ldr(x0, MemOperand(x0, x1, Shift::LSL, 3));
+    ldr(ARMEmitter::XReg::x0, ARMEmitter::Reg::r0, ARMEmitter::Reg::r1, ARMEmitter::ExtendedType::LSL_64, 3);
 
     // If page pointer is zero then we have no block
-    cbz(x0, &NoBlock);
+    cbz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, &NoBlock);
 
     // Steal the page offset
-    and_(x1, x3, 0x0FFF);
+    and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::r3, 0x0FFF);
 
     // Shift the offset by the size of the block cache entry
-    add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
+    add(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, ARMEmitter::XReg::x1, ARMEmitter::ShiftType::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
 
-    // Load the guest address first to ensure it maps to the address we are currently at
+    // The the full LookupCacheEntry with a single LDP.
+    // Check the guest address first to ensure it maps to the address we are currently at.
     // This fixes aliasing problems
-    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
-    cmp(x1, RipReg);
-    b(&NoBlock, Condition::ne);
+    ldp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::XReg::x3, ARMEmitter::XReg::x1, ARMEmitter::Reg::r0, 0);
 
-    // Now load the actual host block to execute if we can
-    ldr(x3, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
-    cbz(x3, &NoBlock);
+    // If the guest address doesn't match, Compile the block.
+    cmp(ARMEmitter::XReg::x1, RipReg);
+    b(ARMEmitter::Condition::CC_NE, &NoBlock);
+
+    // Check the host address to see if it matches, else compile the block.
+    cbz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, &NoBlock);
 
     // If we've made it here then we have a real compiled block
     {
       // update L1 cache
-      ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
+      ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
 
-      and_(x1, RipReg, LookupCache::L1_ENTRIES_MASK);
-      add(x0, x0, Operand(x1, Shift::LSL, 4));
-      stp(x3, x2, MemOperand(x0));
+      and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
+      add(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, ARMEmitter::XReg::x1, ARMEmitter::ShiftType::LSL, 4);
+      stp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::XReg::x3, ARMEmitter::XReg::x2, ARMEmitter::Reg::r0);
 
       // Jump to the block
-      br(x3);
+      br(ARMEmitter::Reg::r3);
     }
   }
 
   {
-    bind(&ExitSpillSRA);
     ThreadStopHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     ThreadStopHandlerAddress = GetCursorAddress<uint64_t>();
 
@@ -187,126 +187,72 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
     ret();
   }
 
-#ifdef VIXL_SIMULATOR
-  // VIXL simulator can't run syscalls.
-  constexpr bool SignalSafeCompile = false;
-#else
-  constexpr bool SignalSafeCompile = true;
-#endif
   {
     ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // Args:
-      // X0: SETMASK
-      // X1: Pointer to mask value (uint64_t)
-      // X2: Pointer to old mask value (uint64_t)
-      // X3: Size of mask, sizeof(uint64_t)
-      // X8: Syscall
+    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
+    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
 
-      LoadConstant(x0, ~0ULL);
-      stp(x0, x0, MemOperand(sp, -16, PreIndex));
-      LoadConstant(x0, SIG_SETMASK);
-      add(x1, sp, 0);
-      add(x2, sp, 0);
-      LoadConstant(x3, 8);
-      LoadConstant(x8, SYS_rt_sigprocmask);
-      svc(0);
-    }
+    mov(ARMEmitter::XReg::x0, STATE);
+    mov(ARMEmitter::XReg::x1, ARMEmitter::XReg::lr);
 
-    mov(x0, STATE);
-    mov(x1, lr);
-
-    ldr(x2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink));
+    ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink));
 #ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uintptr_t, void *, void *>(x2);
+    GenerateIndirectRuntimeCall<uintptr_t, void *, void *>(ARMEmitter::Reg::r2);
 #else
-    blr(x2);
+    blr(ARMEmitter::Reg::r2);
 #endif
 
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-
-      mov(x4, x0);
-      LoadConstant(x0, SIG_SETMASK);
-      add(x1, sp, 0);
-      LoadConstant(x2, 0);
-      LoadConstant(x3, 8);
-      LoadConstant(x8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Bring stack back
-      add(sp, sp, 16);
-
-      mov(x0, x4);
-    }
-
     if (config.StaticRegisterAllocation)
       FillStaticRegs();
-    br(x0);
+
+    ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    subs(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x1, ARMEmitter::XReg::x1, 1);
+    str(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+
+    // Trigger segfault if any deferred signals are pending
+    ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
+    str(ARMEmitter::XReg::zr, ARMEmitter::XReg::x1, 0);
+
+    br(ARMEmitter::Reg::r0);
   }
 
   // Need to create the block
   {
-    bind(&NoBlock);
+    Bind(&NoBlock);
 
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // Args:
-      // X0: SETMASK
-      // X1: Pointer to mask value (uint64_t)
-      // X2: Pointer to old mask value (uint64_t)
-      // X3: Size of mask, sizeof(uint64_t)
-      // X8: Syscall
+    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
+    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
 
-      LoadConstant(x0, ~0ULL);
-      stp(x0, x2, MemOperand(sp, -16, PreIndex));
-      LoadConstant(x0, SIG_SETMASK);
-      add(x1, sp, 0);
-      add(x2, sp, 0);
-      LoadConstant(x3, 8);
-      LoadConstant(x8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Reload x2 to bring back RIP
-      ldr(x2, MemOperand(sp, 8, Offset));
-    }
-
-    ldr(x0, &l_CTX);
-    mov(x1, STATE);
-    ldr(x3, &l_CompileBlock);
+    ldr(ARMEmitter::XReg::x0, &l_CTX);
+    mov(ARMEmitter::XReg::x1, STATE);
+    ldr(ARMEmitter::XReg::x3, &l_CompileBlock);
 
     // X2 contains our guest RIP
 #ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<void, void *, uint64_t, void *>(x3);
+    GenerateIndirectRuntimeCall<void, void *, uint64_t, void *>(ARMEmitter::Reg::r3);
 #else
-    blr(x3); // { CTX, Frame, RIP}
+    blr(ARMEmitter::Reg::r3); // { CTX, Frame, RIP}
 #endif
 
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-      LoadConstant(x0, SIG_SETMASK);
-      add(x1, sp, 0);
-      LoadConstant(x2, 0);
-      LoadConstant(x3, 8);
-      LoadConstant(x8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Bring stack back
-      add(sp, sp, 16);
-    }
-
     if (config.StaticRegisterAllocation)
       FillStaticRegs();
 
+    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    subs(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
+    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+
+    // Trigger segfault if any deferred signals are pending
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
+    str(ARMEmitter::XReg::zr, TMP1, 0);
+
     b(&LoopTop);
   }
 
@@ -318,13 +264,21 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
     hlt(0);
   }
 
+  {
+    SignalHandlerReturnAddressRT = GetCursorAddress<uint64_t>();
+
+    // Now to get back to our old location we need to do a fault dance
+    // We can't use SIGTRAP here since gdb catches it and never gives it to the application!
+    hlt(0);
+  }
+
   {
     // Guest SIGILL handler
     // Needs to be distinct from the SignalHandlerReturnAddress
-    GuestSignal_SIGILL  = GetCursorAddress<uint64_t>();
+    GuestSignal_SIGILL = GetCursorAddress<uint64_t>();
 
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     hlt(0);
   }
@@ -335,7 +289,7 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
     GuestSignal_SIGTRAP  = GetCursorAddress<uint64_t>();
 
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     brk(0);
   }
@@ -346,34 +300,41 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
     GuestSignal_SIGSEGV = GetCursorAddress<uint64_t>();
 
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     // hlt/udf = SIGILL
     // brk = SIGTRAP
     // ??? = SIGSEGV
     // Force a SIGSEGV by loading zero
-    LoadConstant(x1, 0);
-    ldr(x1, MemOperand(x1));
+    if (CTX->ExitOnHLTEnabled()) {
+      ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, ReturningStackLocation));
+      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::r0, 0);
+      PopCalleeSavedRegisters();
+      ret();
+    }
+    else {
+      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, 0);
+      ldr(ARMEmitter::XReg::x1, ARMEmitter::Reg::r1);
+    }
   }
 
   {
     ThreadPauseHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
-    bind(&ThreadPauseHandler);
     ThreadPauseHandlerAddress = GetCursorAddress<uint64_t>();
     // We are pausing, this means the frontend should be waiting for this thread to idle
     // We will have faulted and jumped to this location at this point
 
     // Call our sleep handler
-    ldr(x0, &l_CTX);
-    mov(x1, STATE);
-    ldr(x2, &l_Sleep);
+    ldr(ARMEmitter::XReg::x0, &l_CTX);
+    mov(ARMEmitter::XReg::x1, STATE);
+    ldr(ARMEmitter::XReg::x2, &l_Sleep);
 #ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<void, void *, void *>(x2);
+    GenerateIndirectRuntimeCall<void, void *, void *>(ARMEmitter::Reg::r2);
 #else
-    blr(x2);
+    blr(ARMEmitter::Reg::r2);
 #endif
 
     PauseReturnInstruction = GetCursorAddress<uint64_t>();
@@ -403,27 +364,27 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
     PushCalleeSavedRegisters();
 
     // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, x0);
+    mov(STATE, ARMEmitter::XReg::x0);
 
     // Make sure to adjust the refcounter so we don't clear the cache now
-    ldr(w2, STATE_PTR(CpuStateFrame, SignalHandlerRefCounter));
-    add(w2, w2, 1);
-    str(w2, STATE_PTR(CpuStateFrame, SignalHandlerRefCounter));
+    ldr(ARMEmitter::WReg::w2, STATE_PTR(CpuStateFrame, SignalHandlerRefCounter));
+    add(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r2, 1);
+    str(ARMEmitter::WReg::w2, STATE_PTR(CpuStateFrame, SignalHandlerRefCounter));
 
     // Now push the callback return trampoline to the guest stack
     // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    LoadConstant(x0, CTX->X86CodeGen.CallbackReturn);
+    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, CTX->X86CodeGen.CallbackReturn);
 
-    ldr(x2, STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]));
-    sub(x2, x2, 16);
-    str(x2, STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]));
+    ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]));
+    sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r2, 16);
+    str(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]));
 
     // Store the trampoline to the guest stack
     // Guest stack is now correctly misaligned after a regular call instruction
-    str(x0, MemOperand(x2));
+    str(ARMEmitter::XReg::x0, ARMEmitter::Reg::r2, 0);
 
     // Store RIP to the context state
-    str(x1, STATE_PTR(CpuStateFrame, State.rip));
+    str(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, State.rip));
 
     // load static regs
     if (config.StaticRegisterAllocation)
@@ -436,14 +397,14 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   {
     LUDIVHandlerAddress = GetCursorAddress<uint64_t>();
 
-    PushDynamicRegsAndLR();
-    SpillStaticRegs();
+    PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
+    SpillStaticRegs(ARMEmitter::Reg::r3);
 
-    ldr(x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUDIV));
+    ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUDIV));
 #ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(x3);
+    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
 #else
-    blr(x3);
+    blr(ARMEmitter::Reg::r3);
 #endif
     FillStaticRegs();
 
@@ -458,14 +419,14 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   {
     LDIVHandlerAddress = GetCursorAddress<uint64_t>();
 
-    PushDynamicRegsAndLR();
-    SpillStaticRegs();
+    PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
+    SpillStaticRegs(ARMEmitter::Reg::r3);
 
-    ldr(x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LDIV));
+    ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LDIV));
 #ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(x3);
+    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
 #else
-    blr(x3);
+    blr(ARMEmitter::Reg::r3);
 #endif
     FillStaticRegs();
 
@@ -480,14 +441,14 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   {
     LUREMHandlerAddress = GetCursorAddress<uint64_t>();
 
-    PushDynamicRegsAndLR();
-    SpillStaticRegs();
+    PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
+    SpillStaticRegs(ARMEmitter::Reg::r3);
 
-    ldr(x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUREM));
+    ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUREM));
 #ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(x3);
+    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
 #else
-    blr(x3);
+    blr(ARMEmitter::Reg::r3);
 #endif
     FillStaticRegs();
 
@@ -502,14 +463,15 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   {
     LREMHandlerAddress = GetCursorAddress<uint64_t>();
 
-    PushDynamicRegsAndLR();
-    SpillStaticRegs();
+    PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
+    SpillStaticRegs(ARMEmitter::Reg::r3);
+
+    ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LREM));
 
-    ldr(x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LREM));
 #ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(x3);
+    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
 #else
-    blr(x3);
+    blr(ARMEmitter::Reg::r3);
 #endif
     FillStaticRegs();
 
@@ -521,129 +483,101 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
     ret();
   }
 
-  place(&l_CTX);
-  place(&l_Sleep);
-  place(&l_CompileBlock);
+  Bind(&l_CTX);
+  dc64(reinterpret_cast<uintptr_t>(CTX));
+  Bind(&l_Sleep);
+  dc64(reinterpret_cast<uint64_t>(SleepThread));
+  Bind(&l_CompileBlock);
+  dc64(GetCompileBlockPtr());
 
-
-  FinalizeCode();
   Start = reinterpret_cast<uint64_t>(DispatchPtr);
   End = GetCursorAddress<uint64_t>();
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
-  GetBuffer()->SetExecutable();
+  ClearICache(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
 
   if (CTX->Config.BlockJITNaming()) {
-    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
+    fextl::string Name = fextl::fmt::format("Dispatch_{}", FHU::Syscalls::gettid());
     CTX->Symbols.Register(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr), Name);
   }
   if (CTX->Config.GlobalJITNaming()) {
     CTX->Symbols.RegisterJITSpace(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
   }
+
+#ifdef VIXL_DISASSEMBLER
+  const auto DisasmEnd = GetCursorAddress<const vixl::aarch64::Instruction*>();
+  Disasm.DisassembleBuffer(DisasmBegin, DisasmEnd);
+#endif
 }
 
 #ifdef VIXL_SIMULATOR
 void Arm64Dispatcher::ExecuteDispatch(FEXCore::Core::CpuStateFrame *Frame) {
   Simulator.WriteXRegister(0, reinterpret_cast<int64_t>(Frame));
-  Simulator.RunFrom(reinterpret_cast<Instruction const*>(DispatchPtr));
+  Simulator.RunFrom(reinterpret_cast<vixl::aarch64::Instruction const*>(DispatchPtr));
 }
 
 void Arm64Dispatcher::ExecuteJITCallback(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP) {
   Simulator.WriteXRegister(0, reinterpret_cast<int64_t>(Frame));
   Simulator.WriteXRegister(1, RIP);
-  Simulator.RunFrom(reinterpret_cast<Instruction const*>(CallbackPtr));
+  Simulator.RunFrom(reinterpret_cast<vixl::aarch64::Instruction const*>(CallbackPtr));
 }
 
 #endif
 
-// Used by GenerateGDBPauseCheck, GenerateInterpreterTrampoline, destination buffer is set before use
-static thread_local vixl::aarch64::Assembler emit((uint8_t*)&emit, 1);
-
 size_t Arm64Dispatcher::GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) {
+  FEXCore::ARMEmitter::Emitter emit{CodeBuffer, MaxGDBPauseCheckSize};
 
-  *emit.GetBuffer() = vixl::CodeBuffer(CodeBuffer, MaxGDBPauseCheckSize);
-
-  vixl::CodeBufferCheckScope scope(&emit, MaxGDBPauseCheckSize, vixl::CodeBufferCheckScope::kDontReserveBufferSpace, vixl::CodeBufferCheckScope::kNoAssert);
-
-  aarch64::Label RunBlock;
+  ARMEmitter::ForwardLabel RunBlock;
 
   // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
   // This happens when single stepping
 
-  static_assert(sizeof(FEXCore::Context::Context::Config.RunningMode) == 4, "This is expected to be size of 4");
-  emit.ldr(x0, STATE_PTR(CpuStateFrame, Thread)); // Get thread
-  emit.ldr(x0, MemOperand(x0, offsetof(FEXCore::Core::InternalThreadState, CTX))); // Get Context
-  emit.ldr(w0, MemOperand(x0, offsetof(FEXCore::Context::Context, Config.RunningMode)));
+  static_assert(sizeof(FEXCore::Context::ContextImpl::Config.RunningMode) == 4, "This is expected to be size of 4");
+  emit.ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Thread));
+  emit.ldr(ARMEmitter::XReg::x0, ARMEmitter::Reg::r0, offsetof(FEXCore::Core::InternalThreadState, CTX)); // Get Context
+  emit.ldr(ARMEmitter::WReg::w0, ARMEmitter::Reg::r0, offsetof(FEXCore::Context::ContextImpl, Config.RunningMode));
 
   // If the value == 0 then we don't need to stop
-  emit.cbz(w0, &RunBlock);
+  emit.cbz(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r0, &RunBlock);
   {
-    Literal l_GuestRIP {GuestRIP};
+    ARMEmitter::ForwardLabel l_GuestRIP;
     // Make sure RIP is syncronized to the context
-    emit.ldr(x0, &l_GuestRIP);
-    emit.str(x0, STATE_PTR(CpuStateFrame, State.rip));
+    emit.ldr(ARMEmitter::XReg::x0, &l_GuestRIP);
+    emit.str(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, State.rip));
 
     // Stop the thread
-    emit.ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.ThreadPauseHandlerSpillSRA));
-    emit.br(x0);
-    emit.place(&l_GuestRIP);
+    emit.ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.ThreadPauseHandlerSpillSRA));
+    emit.br(ARMEmitter::Reg::r0);
+    emit.Bind(&l_GuestRIP);
+    emit.dc64(GuestRIP);
   }
-  emit.bind(&RunBlock);
-  emit.FinalizeCode();
+  emit.Bind(&RunBlock);
 
-  auto UsedBytes = emit.GetBuffer()->GetCursorOffset();
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(CodeBuffer, UsedBytes);
+  auto UsedBytes = emit.GetCursorOffset();
+  emit.ClearICache(CodeBuffer, UsedBytes);
   return UsedBytes;
 }
 
 size_t Arm64Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
   LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "GenerateInterpreterTrampoline dispatcher does not support SRA");
 
-  *emit.GetBuffer() = vixl::CodeBuffer(CodeBuffer, MaxInterpreterTrampolineSize);
+  FEXCore::ARMEmitter::Emitter emit{CodeBuffer, MaxInterpreterTrampolineSize};
+  ARMEmitter::ForwardLabel InlineIRData;
 
-  vixl::CodeBufferCheckScope scope(&emit, MaxInterpreterTrampolineSize, vixl::CodeBufferCheckScope::kDontReserveBufferSpace, vixl::CodeBufferCheckScope::kNoAssert);
+  emit.mov(ARMEmitter::XReg::x0, STATE);
+  emit.adr(ARMEmitter::Reg::r1, &InlineIRData);
 
-  aarch64::Label InlineIRData;
+  emit.ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Interpreter.FragmentExecuter));
+  emit.blr(ARMEmitter::Reg::r3);
 
-  emit.mov(x0, STATE);
-  emit.adr(x1, &InlineIRData);
+  emit.ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.DispatcherLoopTop));
+  emit.br(ARMEmitter::Reg::r0);
 
-  emit.ldr(x3, STATE_PTR(CpuStateFrame, Pointers.Interpreter.FragmentExecuter));
-  emit.blr(x3);
+  emit.Bind(&InlineIRData);
 
-  emit.ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.DispatcherLoopTop));
-  emit.br(x0);
-
-  emit.bind(&InlineIRData);
-
-  emit.FinalizeCode();
-
-  auto UsedBytes = emit.GetBuffer()->GetCursorOffset();
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(CodeBuffer, UsedBytes);
+  auto UsedBytes = emit.GetCursorOffset();
+  emit.ClearICache(CodeBuffer, UsedBytes);
   return UsedBytes;
 }
 
-void Arm64Dispatcher::SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) {
-  for (size_t i = 0; i < SRA64.size(); i++) {
-    if (IgnoreMask & (1U << SRA64[i].GetCode())) {
-      // Skip this one, it's already spilled
-      continue;
-    }
-    Thread->CurrentFrame->State.gregs[i] = ArchHelpers::Context::GetArmReg(ucontext, SRA64[i].GetCode());
-  }
-
-  if (EmitterCTX->HostFeatures.SupportsAVX) {
-    for (size_t i = 0; i < SRAFPR.size(); i++) {
-      auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].GetCode());
-      memcpy(&Thread->CurrentFrame->State.xmm.avx.data[i][0], &FPR, sizeof(__uint128_t));
-    }
-  } else {
-    for (size_t i = 0; i < SRAFPR.size(); i++) {
-      auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].GetCode());
-      memcpy(&Thread->CurrentFrame->State.xmm.sse.data[i][0], &FPR, sizeof(__uint128_t));
-    }
-  }
-}
-
 void Arm64Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) {
   // Setup dispatcher specific pointers that need to be accessed from JIT code
   {
@@ -658,6 +592,7 @@ void Arm64Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thr
     Common.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
     Common.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
     Common.SignalReturnHandler = SignalHandlerReturnAddress;
+    Common.SignalReturnHandlerRT = SignalHandlerReturnAddressRT;
 
     auto &AArch64 = Thread->CurrentFrame->Pointers.AArch64;
     AArch64.LUDIVHandler = LUDIVHandlerAddress;
@@ -667,8 +602,8 @@ void Arm64Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thr
   }
 }
 
-std::unique_ptr<Dispatcher> Dispatcher::CreateArm64(FEXCore::Context::Context *CTX, const DispatcherConfig &Config) {
-  return std::make_unique<Arm64Dispatcher>(CTX, Config);
+fextl::unique_ptr<Dispatcher> Dispatcher::CreateArm64(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
+  return fextl::make_unique<Arm64Dispatcher>(CTX, Config);
 }
 
 }

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.h

@@ -7,19 +7,18 @@
 #include <aarch64/simulator-aarch64.h>
 #endif
 
-namespace FEXCore::Context {
-struct Context;
-}
-
 namespace FEXCore::Core {
 struct InternalThreadState;
 }
 
+#define STATE_PTR(STATE_TYPE, FIELD) \
+  STATE.R(), offsetof(FEXCore::Core::STATE_TYPE, FIELD)
+
 namespace FEXCore::CPU {
 
 class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
   public:
-    Arm64Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &config);
+    Arm64Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config);
     void InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) override;
     size_t GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) override;
     size_t GenerateInterpreterTrampoline(uint8_t *CodeBuffer) override;
@@ -29,8 +28,27 @@ class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
   void ExecuteJITCallback(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP) override;
 #endif
 
-  protected:
-    void SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) override;
+  void EmitDispatcher();
+
+  uint16_t GetSRAGPRCount() const override {
+    return SRA64.size();
+  }
+
+  uint16_t GetSRAFPRCount() const override {
+    return SRAFPR.size();
+  }
+
+  void GetSRAGPRMapping(uint8_t Mapping[16]) const override {
+    for (size_t i = 0; i < SRA64.size(); ++i) {
+      Mapping[i] = SRA64[i].Idx();
+    }
+  }
+
+  void GetSRAFPRMapping(uint8_t Mapping[16]) const override {
+    for (size_t i = 0; i < SRAFPR.size(); ++i) {
+      Mapping[i] = SRAFPR[i].Idx();
+    }
+  }
 
   private:
     // Long division helpers

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -1,13 +1,11 @@
 
 #include "Interface/Context/Context.h"
-#include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/X86HelperGen.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/SignalDelegator.h>
-#include <FEXCore/Core/UContext.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/Event.h>
@@ -22,7 +20,7 @@
 
 namespace FEXCore::CPU {
 
-void Dispatcher::SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame) {
+void Dispatcher::SleepThread(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::CpuStateFrame *Frame) {
   auto Thread = Frame->Thread;
 
   --ctx->IdleWaitRefCount;
@@ -40,802 +38,15 @@ void Dispatcher::SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuS
   ctx->IdleWaitCV.notify_all();
 }
 
-ArchHelpers::Context::ContextBackup* Dispatcher::StoreThreadState(FEXCore::Core::InternalThreadState *Thread, int Signal, void *ucontext) {
-  // We can end up getting a signal at any point in our host state
-  // Jump to a handler that saves all state so we can safely return
-  uint64_t OldSP = ArchHelpers::Context::GetSp(ucontext);
-  uintptr_t NewSP = OldSP;
-
-  size_t StackOffset = sizeof(ArchHelpers::Context::ContextBackup);
-
-  // We need to back up behind the host's red zone
-  // We do this on the guest side as well
-  // (does nothing on arm hosts)
-  NewSP -= ArchHelpers::Context::ContextBackup::RedZoneSize;
-
-  NewSP -= StackOffset;
-  NewSP = AlignDown(NewSP, 16);
-
-  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
-  ArchHelpers::Context::BackupContext(ucontext, Context);
-
-  // Retain the action pointer so we can see it when we return
-  Context->Signal = Signal;
-
-  // Save guest state
-  // We can't guarantee if registers are in context or host GPRs
-  // So we need to save everything
-  memcpy(&Context->GuestState, Thread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
-
-  // Set the new SP
-  ArchHelpers::Context::SetSp(ucontext, NewSP);
-
-  // Signal frames are only used on the interpreter
-  // The JITS require the stack to be setup correctly on rt_sigreturn
-  if (CTX->Config.Core() == FEXCore::Config::CONFIG_INTERPRETER) {
-    SignalFrames.push(NewSP);
-  }
-
-  Context->Flags = 0;
-  Context->FPStateLocation = 0;
-  Context->UContextLocation = 0;
-  Context->SigInfoLocation = 0;
-
-  // Store fault to top status and then reset it
-  Context->FaultToTopAndGeneratedException = Thread->CurrentFrame->SynchronousFaultData.FaultToTopAndGeneratedException;
-  Thread->CurrentFrame->SynchronousFaultData.FaultToTopAndGeneratedException = false;
-
-  return Context;
-}
-
-void Dispatcher::RestoreThreadState(FEXCore::Core::InternalThreadState *Thread, void *ucontext) {
-  uint64_t OldSP{};
-  if (CTX->Config.Core() == FEXCore::Config::CONFIG_IRJIT) {
-    OldSP = ArchHelpers::Context::GetSp(ucontext);
-  }
-  else {
-    LOGMAN_THROW_A_FMT(!SignalFrames.empty(), "Trying to restore a signal frame when we don't have any");
-    OldSP = SignalFrames.top();
-    SignalFrames.pop();
-  }
-
-  const bool IsAVXEnabled = CTX->Config.EnableAVX;
-  uintptr_t NewSP = OldSP;
-  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
-
-  // First thing, reset the guest state
-  memcpy(Thread->CurrentFrame, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
-
-  // Now restore host state
-  ArchHelpers::Context::RestoreContext(ucontext, Context);
-
-  if (Context->UContextLocation) {
-    auto Frame = Thread->CurrentFrame;
-
-    if (Context->Flags &ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_INJIT) {
-      // XXX: Unsupported since it needs state reconstruction
-      // If we are in the JIT then SRA might need to be restored to values from the context
-      // We can't currently support this since it might result in tearing without real state reconstruction
-    }
-
-    if (!(Context->Flags & ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT)) {
-      auto *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(Context->UContextLocation);
-      [[maybe_unused]] auto *guest_siginfo = reinterpret_cast<siginfo_t*>(Context->SigInfoLocation);
-
-      // If the guest modified the RIP then we need to take special precautions here
-      if (Context->OriginalRIP != guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] ||
-          Context->FaultToTopAndGeneratedException) {
-        // Hack! Go back to the top of the dispatcher top
-        // This is only safe inside the JIT rather than anything outside of it
-        ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
-        // Set our state register to point to our guest thread data
-        ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
-
-        Frame->State.rip = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP];
-        // XXX: Full context setting
-        uint32_t eflags = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL];
-        for (size_t i = 0; i < Core::CPUState::NUM_EFLAG_BITS; ++i) {
-          Frame->State.flags[i] = (eflags & (1U << i)) ? 1 : 0;
-        }
-
-        Frame->State.flags[1] = 1;
-        Frame->State.flags[9] = 1;
-
-#define COPY_REG(x) \
-            Frame->State.gregs[X86State::REG_##x] = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x];
-            COPY_REG(R8);
-            COPY_REG(R9);
-            COPY_REG(R10);
-            COPY_REG(R11);
-            COPY_REG(R12);
-            COPY_REG(R13);
-            COPY_REG(R14);
-            COPY_REG(R15);
-            COPY_REG(RDI);
-            COPY_REG(RSI);
-            COPY_REG(RBP);
-            COPY_REG(RBX);
-            COPY_REG(RDX);
-            COPY_REG(RAX);
-            COPY_REG(RCX);
-            COPY_REG(RSP);
-#undef COPY_REG
-        auto *xstate = reinterpret_cast<x86_64::xstate*>(guest_uctx->uc_mcontext.fpregs);
-        auto *fpstate = &xstate->fpstate;
-
-        // Copy float registers
-        memcpy(Frame->State.mm, fpstate->_st, sizeof(Frame->State.mm));
-
-        if (IsAVXEnabled) {
-          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-            memcpy(&Frame->State.xmm.avx.data[i][0], &fpstate->_xmm[i], sizeof(__uint128_t));
-          }
-          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-            memcpy(&Frame->State.xmm.avx.data[i][2], &xstate->ymmh.ymmh_space[i], sizeof(__uint128_t));
-          }
-        } else {
-          memcpy(Frame->State.xmm.sse.data, fpstate->_xmm, sizeof(Frame->State.xmm.sse.data));
-        }
-
-        // FCW store default
-        Frame->State.FCW = fpstate->fcw;
-        Frame->State.FTW = fpstate->ftw;
-
-        // Deconstruct FSW
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] = (fpstate->fsw >> 8) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] = (fpstate->fsw >> 9) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] = (fpstate->fsw >> 10) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] = (fpstate->fsw >> 14) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] = (fpstate->fsw >> 11) & 0b111;
-      }
-    }
-    else {
-      auto *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(Context->UContextLocation);
-      [[maybe_unused]] auto *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(Context->SigInfoLocation);
-      // If the guest modified the RIP then we need to take special precautions here
-      if (Context->OriginalRIP != guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] ||
-          Context->FaultToTopAndGeneratedException) {
-        // Hack! Go back to the top of the dispatcher top
-        // This is only safe inside the JIT rather than anything outside of it
-        ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
-        // Set our state register to point to our guest thread data
-        ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
-
-        // XXX: Full context setting
-        // First 32-bytes of flags is EFLAGS broken out
-        uint32_t eflags = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL];
-        for (size_t i = 0; i < Core::CPUState::NUM_EFLAG_BITS; ++i) {
-          Frame->State.flags[i] = (eflags & (1U << i)) ? 1 : 0;
-        }
-
-        Frame->State.flags[1] = 1;
-        Frame->State.flags[9] = 1;
-
-        Frame->State.rip = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP];
-        Frame->State.cs_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS];
-        Frame->State.ds_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS];
-        Frame->State.es_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES];
-        Frame->State.fs_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS];
-        Frame->State.gs_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS];
-        Frame->State.ss_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS];
-
-        Frame->State.cs_cached = Frame->State.gdt[Frame->State.cs_idx >> 3].base;
-        Frame->State.ds_cached = Frame->State.gdt[Frame->State.ds_idx >> 3].base;
-        Frame->State.es_cached = Frame->State.gdt[Frame->State.es_idx >> 3].base;
-        Frame->State.fs_cached = Frame->State.gdt[Frame->State.fs_idx >> 3].base;
-        Frame->State.gs_cached = Frame->State.gdt[Frame->State.gs_idx >> 3].base;
-        Frame->State.ss_cached = Frame->State.gdt[Frame->State.ss_idx >> 3].base;
-
-#define COPY_REG(x) \
-      Frame->State.gregs[X86State::REG_##x] = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x];
-        COPY_REG(RDI);
-        COPY_REG(RSI);
-        COPY_REG(RBP);
-        COPY_REG(RBX);
-        COPY_REG(RDX);
-        COPY_REG(RAX);
-        COPY_REG(RCX);
-        COPY_REG(RSP);
-#undef COPY_REG
-        auto *xstate = reinterpret_cast<x86::xstate*>(guest_uctx->uc_mcontext.fpregs);
-        auto *fpstate = &xstate->fpstate;
-
-        // Copy float registers
-        for (size_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
-          // 32-bit st register size is only 10 bytes. Not padded to 16byte like x86-64
-          memcpy(&Frame->State.mm[i], &fpstate->_st[i], 10);
-        }
-
-        // Extended XMM state
-        if (IsAVXEnabled) {
-          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-            memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
-          }
-          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-            memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
-          }
-        } else {
-          memcpy(Frame->State.xmm.sse.data, fpstate->_xmm, sizeof(Frame->State.xmm.sse.data));
-        }
-
-        // FCW store default
-        Frame->State.FCW = fpstate->fcw;
-        Frame->State.FTW = fpstate->ftw;
-
-        // Deconstruct FSW
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] = (fpstate->fsw >> 8) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] = (fpstate->fsw >> 9) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] = (fpstate->fsw >> 10) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] = (fpstate->fsw >> 14) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] = (fpstate->fsw >> 11) & 0b111;
-      }
-    }
-  }
-}
-
-static uint32_t ConvertSignalToTrapNo(int Signal, siginfo_t *HostSigInfo) {
-  switch (Signal) {
-    case SIGSEGV:
-      if (HostSigInfo->si_code == SEGV_MAPERR ||
-          HostSigInfo->si_code == SEGV_ACCERR) {
-        // Protection fault
-        return X86State::X86_TRAPNO_PF;
-      }
-      break;
-  }
-
-  // Unknown mapping, fall back to old behaviour and just pass signal
-  return Signal;
-}
-
-static uint32_t ConvertSignalToError(int Signal, siginfo_t *HostSigInfo) {
-  switch (Signal) {
-    case SIGSEGV:
-      if (HostSigInfo->si_code == SEGV_MAPERR ||
-          HostSigInfo->si_code == SEGV_ACCERR) {
-        // Protection fault
-        // Always a user fault for us
-        // XXX: PF_PROT and PF_WRITE
-        return X86State::X86_PF_USER;
-      }
-      break;
-  }
-
-  // Not a page fault issue
-  return 0;
-}
-
-template <typename T>
-static void SetXStateInfo(T* xstate, bool is_avx_enabled) {
-  auto* fpstate = &xstate->fpstate;
-
-  fpstate->sw_reserved.magic1 = x86_64::fpx_sw_bytes::FP_XSTATE_MAGIC;
-  fpstate->sw_reserved.extended_size = is_avx_enabled ? sizeof(T) : 0;
-
-  fpstate->sw_reserved.xfeatures |= x86_64::fpx_sw_bytes::FEATURE_FP |
-                                    x86_64::fpx_sw_bytes::FEATURE_SSE;
-  if (is_avx_enabled) {
-    fpstate->sw_reserved.xfeatures |= x86_64::fpx_sw_bytes::FEATURE_YMM;
-  }
-
-  fpstate->sw_reserved.xstate_size = fpstate->sw_reserved.extended_size;
-
-  if (is_avx_enabled) {
-    xstate->xstate_hdr.xfeatures = 0;
-  }
-}
-
-bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  auto ContextBackup = StoreThreadState(Thread, Signal, ucontext);
-
-  auto Frame = Thread->CurrentFrame;
-
-  // Ref count our faults
-  // We use this to track if it is safe to clear cache
-  ++Thread->CurrentFrame->SignalHandlerRefCounter;
-
-  uint64_t OldPC = ArchHelpers::Context::GetPc(ucontext);
-  // Set the new PC
-  ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
-  // Set our state register to point to our guest thread data
-  ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
-
-  uint64_t OldGuestSP = Frame->State.gregs[X86State::REG_RSP];
-  uint64_t NewGuestSP = OldGuestSP;
-
-  // Pulling from context here
-  const bool Is64BitMode = CTX->Config.Is64BitMode;
-  const bool IsAVXEnabled = CTX->Config.EnableAVX;
-  const uint64_t SignalReturn = CTX->X86CodeGen.SignalReturn;
-
-  // Spill the SRA regardless of signal handler type
-  // We are going to be returning to the top of the dispatcher which will fill again
-  // Otherwise we might load garbage
-  if (config.StaticRegisterAllocation) {
-    if (Thread->CPUBackend->IsAddressInCodeBuffer(OldPC)) {
-      uint32_t IgnoreMask{};
-#ifdef _M_ARM_64
-      if (Frame->InSyscallInfo != 0) {
-        // We are in a syscall, this means we are in a weird register state
-        // We need to spill SRA but only some of it, since some values have already been spilled
-        // Lower 16 bits tells us which registers are already spilled to the context
-        // So we ignore spilling those ones
-        uint16_t NumRegisters = std::popcount(Frame->InSyscallInfo & 0xFFFF);
-        if (NumRegisters >= 4) {
-          // Unhandled case
-          IgnoreMask = 0;
-        }
-        else {
-          IgnoreMask = Frame->InSyscallInfo & 0xFFFF;
-        }
-      }
-      else {
-        // We must spill everything
-        IgnoreMask = 0;
-      }
-#endif
-
-      // We are in jit, SRA must be spilled
-      SpillSRA(Thread, ucontext, IgnoreMask);
-
-      ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_INJIT;
-    } else {
-      if (!IsAddressInDispatcher(OldPC)) {
-        // This is likely to cause issues but in some cases it isn't fatal
-        // This can also happen if we have put a signal on hold, then we just reenabled the signal
-        // So we are in the syscall handler
-        // Only throw a log message in this case
-        if constexpr (false) {
-          // XXX: Messages in the signal handler can cause us to crash
-          LogMan::Msg::EFmt("Signals in dispatcher have unsynchronized context");
-        }
-      }
-    }
-  }
-
-  // altstack is only used if the signal handler was setup with SA_ONSTACK
-  if (GuestAction->sa_flags & SA_ONSTACK) {
-    // Additionally the altstack is only used if the enabled (SS_DISABLE flag is not set)
-    if (!(GuestStack->ss_flags & SS_DISABLE)) {
-      // If our guest is already inside of the alternative stack
-      // Then that means we are hitting recursive signals and we need to walk back the stack correctly
-      uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
-      uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
-      if (OldGuestSP >= AltStackBase &&
-          OldGuestSP <= AltStackEnd) {
-        // We are already in the alt stack, the rest of the code will handle adjusting this
-      }
-      else {
-        NewGuestSP = AltStackEnd;
-      }
-    }
-  }
-
-  if (Is64BitMode) {
-    // Back up past the redzone, which is 128bytes
-    // 32-bit doesn't have a redzone
-    NewGuestSP -= 128;
-  }
-
-  // siginfo_t
-  siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);
-
-  // Backup where we think the RIP currently is
-  ContextBackup->OriginalRIP = Frame->State.rip;
-
-  if (GuestAction->sa_flags & SA_SIGINFO) {
-    // Setup ucontext a bit
-    if (Is64BitMode) {
-      if (IsAVXEnabled) {
-        NewGuestSP -= sizeof(x86_64::xstate);
-        NewGuestSP = AlignDown(NewGuestSP, alignof(x86_64::xstate));
-      } else {
-        NewGuestSP -= sizeof(x86_64::_libc_fpstate);
-        NewGuestSP = AlignDown(NewGuestSP, alignof(x86_64::_libc_fpstate));
-      }
-      uint64_t FPStateLocation = NewGuestSP;
-
-      NewGuestSP -= sizeof(FEXCore::x86_64::ucontext_t);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86_64::ucontext_t));
-      uint64_t UContextLocation = NewGuestSP;
-
-      NewGuestSP -= sizeof(siginfo_t);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(siginfo_t));
-      uint64_t SigInfoLocation = NewGuestSP;
-
-      ContextBackup->FPStateLocation = FPStateLocation;
-      ContextBackup->UContextLocation = UContextLocation;
-      ContextBackup->SigInfoLocation = SigInfoLocation;
-
-      FEXCore::x86_64::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(UContextLocation);
-      siginfo_t *guest_siginfo = reinterpret_cast<siginfo_t*>(SigInfoLocation);
-
-      // We have extended float information
-      guest_uctx->uc_flags = FEXCore::x86_64::UC_FP_XSTATE;
-
-      // Pointer to where the fpreg memory is
-      guest_uctx->uc_mcontext.fpregs = reinterpret_cast<x86_64::_libc_fpstate*>(FPStateLocation);
-      auto *xstate = reinterpret_cast<x86_64::xstate*>(FPStateLocation);
-      SetXStateInfo(xstate, IsAVXEnabled);
-
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] = Frame->State.rip;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL] = 0;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CSGSFS] = 0;
-
-      // aarch64 and x86_64 siginfo_t matches. We can just copy this over
-      // SI_USER could also potentially have random data in it, needs to be bit perfect
-      // For guest faults we don't have a real way to reconstruct state to a real guest RIP
-      *guest_siginfo = *HostSigInfo;
-
-      if (ContextBackup->FaultToTopAndGeneratedException) {
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = Frame->SynchronousFaultData.TrapNo;
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = Frame->SynchronousFaultData.err_code;
-
-        // Overwrite si_code
-        guest_siginfo->si_code = Thread->CurrentFrame->SynchronousFaultData.si_code;
-        Signal = Frame->SynchronousFaultData.Signal;
-      }
-      else {
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
-      }
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_OLDMASK] = 0;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CR2] = 0;
-
-#define COPY_REG(x) \
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
-      COPY_REG(R8);
-      COPY_REG(R9);
-      COPY_REG(R10);
-      COPY_REG(R11);
-      COPY_REG(R12);
-      COPY_REG(R13);
-      COPY_REG(R14);
-      COPY_REG(R15);
-      COPY_REG(RDI);
-      COPY_REG(RSI);
-      COPY_REG(RBP);
-      COPY_REG(RBX);
-      COPY_REG(RDX);
-      COPY_REG(RAX);
-      COPY_REG(RCX);
-      COPY_REG(RSP);
-#undef COPY_REG
-
-      auto* fpstate = &xstate->fpstate;
-
-      // Copy float registers
-      memcpy(fpstate->_st, Frame->State.mm, sizeof(Frame->State.mm));
-
-      if (IsAVXEnabled) {
-        for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-          memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
-        }
-        for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-          memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
-        }
-      } else {
-        memcpy(fpstate->_xmm, Frame->State.xmm.sse.data, sizeof(Frame->State.xmm.sse.data));
-      }
-
-      // FCW store default
-      fpstate->fcw = Frame->State.FCW;
-      fpstate->ftw = Frame->State.FTW;
-
-      // Reconstruct FSW
-      fpstate->fsw =
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
-
-      // Copy over signal stack information
-      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
-      guest_uctx->uc_stack.ss_sp = GuestStack->ss_sp;
-      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
-
-      Frame->State.gregs[X86State::REG_RSI] = SigInfoLocation;
-      Frame->State.gregs[X86State::REG_RDX] = UContextLocation;
-    }
-    else {
-      ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT;
-
-      if (IsAVXEnabled) {
-        NewGuestSP -= sizeof(x86::xstate);
-        NewGuestSP = AlignDown(NewGuestSP, alignof(x86::xstate));
-      } else {
-        NewGuestSP -= sizeof(x86::_libc_fpstate);
-        NewGuestSP = AlignDown(NewGuestSP, alignof(x86::_libc_fpstate));
-      }
-      uint64_t FPStateLocation = NewGuestSP;
-
-      NewGuestSP -= sizeof(FEXCore::x86::ucontext_t);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::ucontext_t));
-      uint64_t UContextLocation = NewGuestSP;
-
-      NewGuestSP -= sizeof(FEXCore::x86::siginfo_t);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::siginfo_t));
-      uint64_t SigInfoLocation = NewGuestSP;
-
-      ContextBackup->FPStateLocation = FPStateLocation;
-      ContextBackup->UContextLocation = UContextLocation;
-      ContextBackup->SigInfoLocation = SigInfoLocation;
-
-      FEXCore::x86::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(UContextLocation);
-      FEXCore::x86::siginfo_t *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(SigInfoLocation);
-
-      // We have extended float information
-      guest_uctx->uc_flags = FEXCore::x86::UC_FP_XSTATE;
-
-      // Pointer to where the fpreg memory is
-      guest_uctx->uc_mcontext.fpregs = static_cast<uint32_t>(FPStateLocation);
-      auto *xstate = reinterpret_cast<x86::xstate*>(FPStateLocation);
-      SetXStateInfo(xstate, IsAVXEnabled);
-
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS] = Frame->State.cs_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS] = Frame->State.ds_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES] = Frame->State.es_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS] = Frame->State.fs_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS] = Frame->State.gs_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS] = Frame->State.ss_idx;
-
-      if (ContextBackup->FaultToTopAndGeneratedException) {
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = Frame->SynchronousFaultData.TrapNo;
-        guest_siginfo->si_code = Frame->SynchronousFaultData.si_code;
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = Frame->SynchronousFaultData.err_code;
-        Signal = Frame->SynchronousFaultData.Signal;
-      }
-      else {
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
-        guest_siginfo->si_code = HostSigInfo->si_code;
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
-      }
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] = Frame->State.rip;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL] = 0;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_UESP] = 0;
-
-#define COPY_REG(x) \
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
-      COPY_REG(RDI);
-      COPY_REG(RSI);
-      COPY_REG(RBP);
-      COPY_REG(RBX);
-      COPY_REG(RDX);
-      COPY_REG(RAX);
-      COPY_REG(RCX);
-      COPY_REG(RSP);
-#undef COPY_REG
-
-      auto *fpstate = &xstate->fpstate;
-
-      // Copy float registers
-      for (size_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
-        // 32-bit st register size is only 10 bytes. Not padded to 16byte like x86-64
-        memcpy(&fpstate->_st[i], &Frame->State.mm[i], 10);
-      }
-
-      // Extended XMM state
-      fpstate->status = FEXCore::x86::fpstate_magic::MAGIC_XFPSTATE;
-      if (IsAVXEnabled) {
-        for (size_t i = 0; i < std::size(Frame->State.xmm.avx.data); i++) {
-          memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
-        }
-        for (size_t i = 0; i < std::size(Frame->State.xmm.avx.data); i++) {
-          memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
-        }
-      } else {
-        memcpy(fpstate->_xmm, Frame->State.xmm.sse.data, sizeof(Frame->State.xmm.sse.data));
-      }
-
-      // FCW store default
-      fpstate->fcw = Frame->State.FCW;
-      fpstate->ftw = Frame->State.FTW;
-      // Reconstruct FSW
-      fpstate->fsw =
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
-
-      // Copy over signal stack information
-      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
-      guest_uctx->uc_stack.ss_sp = static_cast<uint32_t>(reinterpret_cast<uint64_t>(GuestStack->ss_sp));
-      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
-
-      // These three elements are in every siginfo
-      guest_siginfo->si_signo = HostSigInfo->si_signo;
-      guest_siginfo->si_errno = HostSigInfo->si_errno;
-
-      switch (Signal) {
-        case SIGSEGV:
-        case SIGBUS:
-          // Macro expansion to get the si_addr
-          // This is the address trying to be accessed, not the RIP
-          guest_siginfo->_sifields._sigfault.addr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(HostSigInfo->si_addr));
-          break;
-        case SIGFPE:
-        case SIGILL:
-          // Macro expansion to get the si_addr
-          // Can't really give a real result here. Pull from the context for now
-          guest_siginfo->_sifields._sigfault.addr = Frame->State.rip;
-          break;
-        case SIGCHLD:
-          guest_siginfo->_sifields._sigchld.pid = HostSigInfo->si_pid;
-          guest_siginfo->_sifields._sigchld.uid = HostSigInfo->si_uid;
-          guest_siginfo->_sifields._sigchld.status = HostSigInfo->si_status;
-          guest_siginfo->_sifields._sigchld.utime = HostSigInfo->si_utime;
-          guest_siginfo->_sifields._sigchld.stime = HostSigInfo->si_stime;
-          break;
-        case SIGALRM:
-        case SIGVTALRM:
-          guest_siginfo->_sifields._timer.tid = HostSigInfo->si_timerid;
-          guest_siginfo->_sifields._timer.overrun = HostSigInfo->si_overrun;
-          guest_siginfo->_sifields._timer.sigval.sival_int = HostSigInfo->si_int;
-          break;
-        default:
-          LogMan::Msg::EFmt("Unhandled siginfo_t for signal: {}\n", Signal);
-          break;
-      }
-
-      NewGuestSP -= 4;
-      *(uint32_t*)NewGuestSP = UContextLocation;
-      NewGuestSP -= 4;
-      *(uint32_t*)NewGuestSP = SigInfoLocation;
-      NewGuestSP -= 4;
-      *(uint32_t*)NewGuestSP = Signal;
-    }
-
-    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
-  }
-  else {
-    if (!Is64BitMode) {
-      NewGuestSP -= 4;
-      *(uint32_t*)NewGuestSP = Signal;
-    }
-
-    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
-  }
-
-  if (Is64BitMode) {
-    Frame->State.gregs[FEXCore::X86State::REG_RDI] = Signal;
-
-    // Set up the new SP for stack handling
-    NewGuestSP -= 8;
-    *(uint64_t*)NewGuestSP = SignalReturn;
-    Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP;
-  }
-  else {
-    NewGuestSP -= 4;
-    *(uint32_t*)NewGuestSP = SignalReturn;
-    LOGMAN_THROW_AA_FMT(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
-    Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP;
-  }
-
-  // The guest starts its signal frame with a zero initialized FPU
-  // Set that up now. Little bit costly but it's a requirement
-  // This state will be restored on rt_sigreturn
-  memset(Frame->State.xmm.avx.data, 0, sizeof(Frame->State.xmm));
-  memset(Frame->State.mm, 0, sizeof(Frame->State.mm));
-  Frame->State.FCW = 0x37F;
-  Frame->State.FTW = 0xFFFF;
-
-  return true;
-}
-
-bool Dispatcher::HandleSIGILL(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) {
-
-  if (ArchHelpers::Context::GetPc(ucontext) == SignalHandlerReturnAddress) {
-    RestoreThreadState(Thread, ucontext);
-
-    // Ref count our faults
-    // We use this to track if it is safe to clear cache
-    --Thread->CurrentFrame->SignalHandlerRefCounter;
-    return true;
-  }
-
-  if (ArchHelpers::Context::GetPc(ucontext) == PauseReturnInstruction) {
-    RestoreThreadState(Thread, ucontext);
-
-    // Ref count our faults
-    // We use this to track if it is safe to clear cache
-    --Thread->CurrentFrame->SignalHandlerRefCounter;
-    return true;
-  }
-
-  return false;
-}
-
-bool Dispatcher::HandleSignalPause(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) {
-  FEXCore::Core::SignalEvent SignalReason = Thread->SignalReason.load();
-  auto Frame = Thread->CurrentFrame;
-
-  if (SignalReason == FEXCore::Core::SignalEvent::Pause) {
-    // Store our thread state so we can come back to this
-    StoreThreadState(Thread, Signal, ucontext);
-
-    if (config.StaticRegisterAllocation && Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
-      // We are in jit, SRA must be spilled
-      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddressSpillSRA);
-    } else {
-      if (config.StaticRegisterAllocation) {
-        // We are in non-jit, SRA is already spilled
-        LOGMAN_THROW_A_FMT(!IsAddressInDispatcher(ArchHelpers::Context::GetPc(ucontext)),
-                           "Signals in dispatcher have unsynchronized context");
-      }
-      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddress);
-    }
-
-    // Set our state register to point to our guest thread data
-    ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
-
-    // Ref count our faults
-    // We use this to track if it is safe to clear cache
-    ++Thread->CurrentFrame->SignalHandlerRefCounter;
-
-    Thread->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::Stop) {
-    // Our thread is stopping
-    // We don't care about anything at this point
-    // Set the stack to our starting location when we entered the core and get out safely
-    ArchHelpers::Context::SetSp(ucontext, Frame->ReturningStackLocation);
-
-    // Our ref counting doesn't matter anymore
-    Thread->CurrentFrame->SignalHandlerRefCounter = 0;
-
-    // Set the new PC
-    if (config.StaticRegisterAllocation && Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
-      // We are in jit, SRA must be spilled
-      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddressSpillSRA);
-    } else {
-      if (config.StaticRegisterAllocation) {
-        // We are in non-jit, SRA is already spilled
-        LOGMAN_THROW_A_FMT(!IsAddressInDispatcher(ArchHelpers::Context::GetPc(ucontext)),
-                           "Signals in dispatcher have unsynchronized context");
-      }
-      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddress);
-    }
-
-    // We need to be a little bit careful here
-    // If we were already paused (due to GDB) and we are immediately stopping (due to gdb kill)
-    // Then we need to ensure we don't double decrement our idle thread counter
-    if (Thread->RunningEvents.ThreadSleeping) {
-      // If the thread was sleeping then its idle counter was decremented
-      // Reincrement it here to not break logic
-      ++Thread->CTX->IdleWaitRefCount;
-    }
-
-    Thread->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::Return) {
-    RestoreThreadState(Thread, ucontext);
-
-    // Ref count our faults
-    // We use this to track if it is safe to clear cache
-    --Thread->CurrentFrame->SignalHandlerRefCounter;
-
-    Thread->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
-    return true;
-  }
-
-  return false;
-}
-
 uint64_t Dispatcher::GetCompileBlockPtr() {
-  using ClassPtrType = void (FEXCore::Context::Context::*)(FEXCore::Core::CpuStateFrame *, uint64_t);
+  using ClassPtrType = void (FEXCore::Context::ContextImpl::*)(FEXCore::Core::CpuStateFrame *, uint64_t);
   union PtrCast {
     ClassPtrType ClassPtr;
     uintptr_t Data;
   };
 
   PtrCast CompileBlockPtr;
-  CompileBlockPtr.ClassPtr = &FEXCore::Context::Context::CompileBlockJit;
+  CompileBlockPtr.ClassPtr = &FEXCore::Context::ContextImpl::CompileBlockJit;
   return CompileBlockPtr.Data;
 }
 

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -1,14 +1,13 @@
 #pragma once
 
 #include <FEXCore/Core/CPUBackend.h>
-#include "Interface/Core/ArchHelpers/MContext.h"
+#include <FEXCore/fextl/memory.h>
 
 #include <cstdint>
 #include <signal.h>
 #include <stddef.h>
 #include <stack>
 #include <tuple>
-#include <vector>
 
 namespace FEXCore {
 struct GuestSigAction;
@@ -20,7 +19,7 @@ struct InternalThreadState;
 }
 
 namespace FEXCore::Context {
-struct Context;
+class ContextImpl;
 }
 
 namespace FEXCore::CPU {
@@ -44,6 +43,7 @@ public:
   uint64_t ThreadPauseHandlerAddressSpillSRA{};
   uint64_t ExitFunctionLinkerAddress{};
   uint64_t SignalHandlerReturnAddress{};
+  uint64_t SignalHandlerReturnAddressRT{};
   uint64_t GuestSignal_SIGILL{};
   uint64_t GuestSignal_SIGTRAP{};
   uint64_t GuestSignal_SIGSEGV{};
@@ -56,14 +56,6 @@ public:
   uint64_t Start{};
   uint64_t End{};
 
-  bool HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-  bool HandleSIGILL(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext);
-  bool HandleSignalPause(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext);
-
-  bool IsAddressInDispatcher(uint64_t Address) const {
-    return Address >= Start && Address < End;
-  }
-
   virtual void InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) = 0;
 
   // These are across all arches for now
@@ -73,8 +65,8 @@ public:
   virtual size_t GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) = 0;
   virtual size_t GenerateInterpreterTrampoline(uint8_t *CodeBuffer) = 0;
 
-  static std::unique_ptr<Dispatcher> CreateX86(FEXCore::Context::Context *CTX, const DispatcherConfig &Config);
-  static std::unique_ptr<Dispatcher> CreateArm64(FEXCore::Context::Context *CTX, const DispatcherConfig &Config);
+  static fextl::unique_ptr<Dispatcher> CreateX86(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
+  static fextl::unique_ptr<Dispatcher> CreateArm64(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
 
   virtual void ExecuteDispatch(FEXCore::Core::CpuStateFrame *Frame) {
     DispatchPtr(Frame);
@@ -84,22 +76,32 @@ public:
     CallbackPtr(Frame, RIP);
   }
 
+  virtual uint16_t GetSRAGPRCount() const {
+    return 0U;
+  }
+
+  virtual uint16_t GetSRAFPRCount() const {
+    return 0U;
+  }
+
+  virtual void GetSRAGPRMapping(uint8_t Mapping[16]) const {
+  }
+
+  virtual void GetSRAFPRMapping(uint8_t Mapping[16]) const {
+  }
+
+  const DispatcherConfig& GetConfig() const { return config; }
+
 protected:
-  Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &Config)
+  Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &Config)
     : CTX {ctx}
     , config {Config}
     {}
 
-  ArchHelpers::Context::ContextBackup* StoreThreadState(FEXCore::Core::InternalThreadState *Thread, int Signal, void *ucontext);
-  void RestoreThreadState(FEXCore::Core::InternalThreadState *Thread, void *ucontext);
-  std::stack<uint64_t, std::vector<uint64_t>> SignalFrames;
-
-  virtual void SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) {}
-
-  FEXCore::Context::Context *CTX;
+  FEXCore::Context::ContextImpl *CTX;
   DispatcherConfig config;
 
-  static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame);
+  static void SleepThread(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::CpuStateFrame *Frame);
 
   static uint64_t GetCompileBlockPtr();
 

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp

@@ -1,3 +1,4 @@
+#include "FEXCore/Utils/AllocatorHooks.h"
 #include "Interface/Core/LookupCache.h"
 
 #include "Interface/Core/Dispatcher/X86Dispatcher.h"
@@ -11,14 +12,14 @@
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/Allocator.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
 #include <FEXHeaderUtils/Syscalls.h>
 
 #include <cmath>
 #include <memory>
 #include <stddef.h>
 #include <stdint.h>
-#include <sys/mman.h>
-#include <xbyak/xbyak.h>
 
 #define STATE_PTR(STATE_TYPE, FIELD) \
   [STATE + offsetof(FEXCore::Core::STATE_TYPE, FIELD)]
@@ -27,10 +28,10 @@ namespace FEXCore::CPU {
 static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
 #define STATE r14
 
-X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &config)
+X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config)
   : Dispatcher(ctx, config)
   , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE,
-      FEXCore::Allocator::mmap(nullptr, MAX_DISPATCHER_CODE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0),
+      FEXCore::Allocator::VirtualAlloc(MAX_DISPATCHER_CODE_SIZE, true),
       nullptr) {
 
   LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "X86 dispatcher does not support SRA");
@@ -169,36 +170,11 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon
     ret();
   }
 
-  constexpr bool SignalSafeCompile = true;
   // Block creation
   {
     L(NoBlock);
 
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // RDI: SETMASK
-      // RSI: Pointer to mask value (uint64_t)
-      // RDX: Pointer to old mask value (uint64_t)
-      // R10: Size of mask, sizeof(uint64_t)
-      // RAX: Syscall
-
-      // Backup rdx
-      mov(r9, rdx);
-
-      mov(rdi, ~0ULL);
-      sub(rsp, 16);
-      mov(qword [rsp], rdi);
-      mov(qword [rsp + 8], rdi);
-
-      mov(rdi, SIG_SETMASK);
-      mov(rsi, rsp);
-      mov(rdx, rsp);
-      mov(r10, 8);
-      mov(rax, SYS_rt_sigprocmask);
-      syscall();
-
-      mov(rdx, r9);
-    }
+    inc(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
 
     // {rdi, rsi, rdx}
     mov(rdi, reinterpret_cast<uint64_t>(CTX));
@@ -207,24 +183,15 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon
 
     call(rax);
 
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-      // Backup rdx
-      mov(r9, rdx);
+    dec(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
 
-      mov(rdi, SIG_SETMASK);
-      mov(rsi, rsp);
-      mov(rdx, 0); // Don't care about result
-      mov(r10, 8);
-      mov(rax, SYS_rt_sigprocmask);
-      syscall();
+    Label AfterStore;
+    // Skip the deferred fault address if the refcount isn't zero
+    jne(AfterStore);
+    mov(rax, qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress)]);
+    mov(rax, qword [rax]);
 
-      // Bring stack back
-      add(rsp, 16);
-
-      mov(rdx, r9);
-    }
+    L(AfterStore);
 
     // rdx already contains RIP here
     jmp(LoopTop);
@@ -232,31 +199,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon
 
   {
     ExitFunctionLinkerAddress = getCurr<uint64_t>();
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // RDI: SETMASK
-      // RSI: Pointer to mask value (uint64_t)
-      // RDX: Pointer to old mask value (uint64_t)
-      // R10: Size of mask, sizeof(uint64_t)
-      // RAX: Syscall
-
-      // Backup rax
-      mov(r9, rax);
-
-      mov(rdi, ~0ULL);
-      sub(rsp, 16);
-      mov(qword [rsp], rdi);
-      mov(qword [rsp + 8], rdi);
-
-      mov(rdi, SIG_SETMASK);
-      mov(rsi, rsp);
-      mov(rdx, rsp);
-      mov(r10, 8);
-      mov(rax, SYS_rt_sigprocmask);
-      syscall();
-
-      mov(rax, r9);
-    }
+    inc(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
 
     // {rdi, rsi}
     mov(rdi, STATE);
@@ -264,27 +207,17 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon
 
     call(qword STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink));
 
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-      // Backup rax
-      mov(r9, rax);
+    dec(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
 
-      mov(rdi, SIG_SETMASK);
-      mov(rsi, rsp);
-      mov(rdx, 0); // Don't care about result
-      mov(r10, 8);
-      mov(rax, SYS_rt_sigprocmask);
-      syscall();
+    Label AfterStore;
+    // Skip the deferred fault address if the refcount isn't zero
+    jne(AfterStore);
+    mov(rbx, qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress)]);
+    mov(qword [rbx], rbx);
 
-      // Bring stack back
-      add(rsp, 16);
+    L(AfterStore);
 
-      jmp(r9);
-    }
-    else {
-      jmp(rax);
-    }
+    jmp(rax);
   }
 
   {
@@ -344,6 +277,12 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon
     ud2();
   }
 
+  {
+    // RT Signal return handler
+    SignalHandlerReturnAddressRT = getCurr<uint64_t>();
+    ud2();
+  }
+
   {
     // Guest SIGILL handler
     // Needs to be distinct from the SignalHandlerReturnAddress
@@ -401,7 +340,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon
   End = Start + getSize();
 
   if (CTX->Config.BlockJITNaming()) {
-    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
+    fextl::string Name = fextl::fmt::format("Dispatch_{}", FHU::Syscalls::gettid());
     CTX->Symbols.Register(reinterpret_cast<void*>(Start), End-Start, Name);
   }
   if (CTX->Config.GlobalJITNaming()) {
@@ -410,15 +349,13 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon
 
 }
 
-// Used by GenerateGDBPauseCheck, GenerateInterpreterTrampoline
-static thread_local Xbyak::CodeGenerator emit(1, &emit); // actual emit target set with setNewBuffer
-
 size_t X86Dispatcher::GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) {
   using namespace Xbyak;
   using namespace Xbyak::util;
 
+  Xbyak::CodeGenerator emit(1, &emit); // actual emit target set with setNewBuffer
   emit.setNewBuffer(CodeBuffer, MaxGDBPauseCheckSize);
-  
+
   Label RunBlock;
 
   // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
@@ -427,7 +364,7 @@ size_t X86Dispatcher::GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestR
   emit.mov(rax, reinterpret_cast<uint64_t>(CTX));
 
   // If the value == 0 then we don't need to stop
-  emit.cmp(dword [rax + (offsetof(FEXCore::Context::Context, Config.RunningMode))], 0);
+  emit.cmp(dword [rax + (offsetof(FEXCore::Context::ContextImpl, Config.RunningMode))], 0);
   emit.je(RunBlock);
   {
     // Make sure RIP is syncronized to the context
@@ -451,10 +388,11 @@ size_t X86Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
   using namespace Xbyak;
   using namespace Xbyak::util;
 
+  Xbyak::CodeGenerator emit(1, &emit); // actual emit target set with setNewBuffer
   emit.setNewBuffer(CodeBuffer, MaxInterpreterTrampolineSize);
 
   Label InlineIRData;
-  
+
   emit.mov(rdi, STATE);
   emit.lea(rsi, ptr[rip + InlineIRData]);
   emit.call(qword STATE_PTR(CpuStateFrame, Pointers.Interpreter.FragmentExecuter));
@@ -469,7 +407,7 @@ size_t X86Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
 }
 
 X86Dispatcher::~X86Dispatcher() {
-  FEXCore::Allocator::munmap(top_, MAX_DISPATCHER_CODE_SIZE);
+  FEXCore::Allocator::VirtualFree(top_, MAX_DISPATCHER_CODE_SIZE);
 }
 
 void X86Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) {
@@ -486,14 +424,15 @@ void X86Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Threa
     Common.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
     Common.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
     Common.SignalReturnHandler = SignalHandlerReturnAddress;
+    Common.SignalReturnHandlerRT = SignalHandlerReturnAddressRT;
 
     auto &Interpreter = Thread->CurrentFrame->Pointers.Interpreter;
     (uintptr_t&)Interpreter.CallbackReturn = IntCallbackReturnAddress;
   }
 }
 
-std::unique_ptr<Dispatcher> Dispatcher::CreateX86(FEXCore::Context::Context *CTX, const DispatcherConfig &Config) {
-  return std::make_unique<X86Dispatcher>(CTX, Config);
+fextl::unique_ptr<Dispatcher> Dispatcher::CreateX86(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
+  return fextl::make_unique<X86Dispatcher>(CTX, Config);
 }
 
 }

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.h

@@ -1,13 +1,24 @@
 #pragma once
 
+#include <FEXCore/fextl/list.h>
+#include <FEXCore/fextl/unordered_map.h>
+#include <FEXCore/fextl/unordered_set.h>
+
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #define XBYAK64
-#include <xbyak/xbyak.h>
+#define XBYAK_CUSTOM_ALLOC
+#define XBYAK_CUSTOM_MALLOC FEXCore::Allocator::malloc
+#define XBYAK_CUSTOM_FREE FEXCore::Allocator::free
+#define XBYAK_CUSTOM_SETS
+#define XBYAK_STD_UNORDERED_SET fextl::unordered_set
+#define XBYAK_STD_UNORDERED_MAP fextl::unordered_map
+#define XBYAK_STD_UNORDERED_MULTIMAP fextl::unordered_multimap
+#define XBYAK_STD_LIST fextl::list
+#define XBYAK_NO_EXCEPTION
 
-namespace FEXCore::Context {
-  struct Context;
-}
+#include <xbyak/xbyak.h>
+#include <xbyak/xbyak_util.h>
 
 namespace FEXCore::Core {
   struct InternalThreadState;
@@ -17,7 +28,7 @@ namespace FEXCore::CPU {
 
 class X86Dispatcher final : public Dispatcher, public Xbyak::CodeGenerator {
   public:
-    X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &config);
+    X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config);
     void InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) override;
     size_t GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) override;
     size_t GenerateInterpreterTrampoline(uint8_t *CodeBuffer) override;

External/FEXCore/Source/Interface/Core/Frontend.cpp

@@ -7,6 +7,7 @@ $end_info$
 
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Frontend.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <array>
 #include <assert.h>
@@ -14,15 +15,13 @@ $end_info$
 #include <cstring>
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/Utils/Telemetry.h>
+#include <FEXCore/fextl/set.h>
 #include <FEXHeaderUtils/TypeDefines.h>
-#include <set>
-#include <sys/mman.h>
 
 namespace FEXCore::Frontend {
 #include "Interface/Core/VSyscall/VSyscall.inc"
@@ -32,26 +31,6 @@ using namespace FEXCore::X86Tables;
 static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool HasREX, bool HasXMM, bool HasMM, uint8_t InvalidOffset = 16) {
   using GPRArray = std::array<uint32_t, 16>;
 
-  static constexpr GPRArray GPRIndexes = {
-    // Classical ordering?
-    FEXCore::X86State::REG_RAX,
-    FEXCore::X86State::REG_RCX,
-    FEXCore::X86State::REG_RDX,
-    FEXCore::X86State::REG_RBX,
-    FEXCore::X86State::REG_RSP,
-    FEXCore::X86State::REG_RBP,
-    FEXCore::X86State::REG_RSI,
-    FEXCore::X86State::REG_RDI,
-    FEXCore::X86State::REG_R8,
-    FEXCore::X86State::REG_R9,
-    FEXCore::X86State::REG_R10,
-    FEXCore::X86State::REG_R11,
-    FEXCore::X86State::REG_R12,
-    FEXCore::X86State::REG_R13,
-    FEXCore::X86State::REG_R14,
-    FEXCore::X86State::REG_R15,
-  };
-
   static constexpr GPRArray GPR8BitHighIndexes = {
     // Classical ordering?
     FEXCore::X86State::REG_RAX,
@@ -72,112 +51,34 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_R15,
   };
 
-  static constexpr GPRArray XMMIndexes = {
-    FEXCore::X86State::REG_XMM_0,
-    FEXCore::X86State::REG_XMM_1,
-    FEXCore::X86State::REG_XMM_2,
-    FEXCore::X86State::REG_XMM_3,
-    FEXCore::X86State::REG_XMM_4,
-    FEXCore::X86State::REG_XMM_5,
-    FEXCore::X86State::REG_XMM_6,
-    FEXCore::X86State::REG_XMM_7,
-    FEXCore::X86State::REG_XMM_8,
-    FEXCore::X86State::REG_XMM_9,
-    FEXCore::X86State::REG_XMM_10,
-    FEXCore::X86State::REG_XMM_11,
-    FEXCore::X86State::REG_XMM_12,
-    FEXCore::X86State::REG_XMM_13,
-    FEXCore::X86State::REG_XMM_14,
-    FEXCore::X86State::REG_XMM_15,
-  };
-
-  static constexpr GPRArray MMIndexes = {
-    FEXCore::X86State::REG_MM_0,
-    FEXCore::X86State::REG_MM_1,
-    FEXCore::X86State::REG_MM_2,
-    FEXCore::X86State::REG_MM_3,
-    FEXCore::X86State::REG_MM_4,
-    FEXCore::X86State::REG_MM_5,
-    FEXCore::X86State::REG_MM_6,
-    FEXCore::X86State::REG_MM_7,
-    FEXCore::X86State::REG_INVALID,
-    FEXCore::X86State::REG_INVALID,
-    FEXCore::X86State::REG_INVALID,
-    FEXCore::X86State::REG_INVALID,
-    FEXCore::X86State::REG_INVALID,
-    FEXCore::X86State::REG_INVALID,
-    FEXCore::X86State::REG_INVALID,
-    FEXCore::X86State::REG_INVALID
-  };
-
-  const GPRArray *GPRs = &GPRIndexes;
-  if (HasXMM) {
-    GPRs = &XMMIndexes;
-  }
-  else if (HasMM) {
-    GPRs = &MMIndexes;
-  }
-  else if (HighBits && !HasREX) {
-    GPRs = &GPR8BitHighIndexes;
-  }
-
   uint8_t Offset = (REX << 3) | bits;
 
   if (Offset == InvalidOffset) {
     return FEXCore::X86State::REG_INVALID;
   }
-  return (*GPRs)[(REX << 3) | bits];
+
+  if (HasXMM) {
+    return FEXCore::X86State::REG_XMM_0 + Offset;
+  }
+  else if (HasMM) {
+    return FEXCore::X86State::REG_MM_0 + Offset;
+  }
+  else if (!(HighBits && !HasREX)) {
+    return FEXCore::X86State::REG_RAX + Offset;
+  }
+
+  return GPR8BitHighIndexes[Offset];
 }
 
 static uint32_t MapVEXToReg(uint8_t vvvv, bool HasXMM) {
-  using GPRArray = std::array<uint32_t, 16>;
-
-  static constexpr GPRArray GPRIndexes = {
-    FEXCore::X86State::REG_RAX,
-    FEXCore::X86State::REG_RCX,
-    FEXCore::X86State::REG_RDX,
-    FEXCore::X86State::REG_RBX,
-    FEXCore::X86State::REG_RSP,
-    FEXCore::X86State::REG_RBP,
-    FEXCore::X86State::REG_RSI,
-    FEXCore::X86State::REG_RDI,
-    FEXCore::X86State::REG_R8,
-    FEXCore::X86State::REG_R9,
-    FEXCore::X86State::REG_R10,
-    FEXCore::X86State::REG_R11,
-    FEXCore::X86State::REG_R12,
-    FEXCore::X86State::REG_R13,
-    FEXCore::X86State::REG_R14,
-    FEXCore::X86State::REG_R15,
-  };
-
-  static constexpr GPRArray XMMIndexes = {
-    FEXCore::X86State::REG_XMM_0,
-    FEXCore::X86State::REG_XMM_1,
-    FEXCore::X86State::REG_XMM_2,
-    FEXCore::X86State::REG_XMM_3,
-    FEXCore::X86State::REG_XMM_4,
-    FEXCore::X86State::REG_XMM_5,
-    FEXCore::X86State::REG_XMM_6,
-    FEXCore::X86State::REG_XMM_7,
-    FEXCore::X86State::REG_XMM_8,
-    FEXCore::X86State::REG_XMM_9,
-    FEXCore::X86State::REG_XMM_10,
-    FEXCore::X86State::REG_XMM_11,
-    FEXCore::X86State::REG_XMM_12,
-    FEXCore::X86State::REG_XMM_13,
-    FEXCore::X86State::REG_XMM_14,
-    FEXCore::X86State::REG_XMM_15,
-  };
-
   if (HasXMM) {
-    return XMMIndexes[vvvv];
+    return FEXCore::X86State::REG_XMM_0 + vvvv;
   } else {
-    return GPRIndexes[vvvv];
+    return FEXCore::X86State::REG_RAX + vvvv;
   }
 }
 
-Decoder::Decoder(FEXCore::Context::Context *ctx)
+Decoder::Decoder(FEXCore::Context::ContextImpl *ctx)
   : CTX {ctx}
   , OSABI { ctx->SyscallHandler ? ctx->SyscallHandler->GetOSABI() : FEXCore::HLE::SyscallOSABI::OS_UNKNOWN }
   , PoolObject {ctx->FrontendAllocator, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize} {
@@ -206,7 +107,7 @@ uint64_t Decoder::ReadData(uint8_t Size) {
   uint64_t Res = 0;
   std::memcpy(&Res, &InstStream[InstructionSize], Size);
 
-#ifndef NDEBUG
+#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
   for(size_t i = 0; i < Size; ++i) {
     ReadByte();
   }
@@ -384,12 +285,6 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
   DecodeInst->OP = Op;
   DecodeInst->TableInfo = Info;
 
-  // XXX: Once we support 32bit x86 then this will be necessary to support
-  if (Info->Type == FEXCore::X86Tables::TYPE_LEGACY_PREFIX) {
-    LogMan::Msg::DFmt("Legacy Prefix");
-    return false;
-  }
-
   if (Info->Type == FEXCore::X86Tables::TYPE_UNKNOWN) {
     LogMan::Msg::DFmt("Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
     return false;
@@ -408,27 +303,35 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
                                        (Options.w && CTX->Config.Is64BitMode);
   const bool HasNarrowingDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST) != 0;
 
-  bool HasXMMSrc = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_GPR) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_SRC);
-  bool HasXMMDst = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_GPR) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_DST);
-  bool HasMMSrc = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_GPR) &&
-    HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_SRC);
-  bool HasMMDst = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_GPR) &&
-    HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_DST);
+  const bool HasXMMFlags = (Info->Flags & InstFlags::FLAGS_XMM_FLAGS) != 0;
+  bool HasXMMSrc = HasXMMFlags &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_SRC_GPR) &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_SRC);
+  bool HasXMMDst = HasXMMFlags &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_DST_GPR) &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_DST);
+  bool HasMMSrc = HasXMMFlags &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_SRC_GPR) &&
+    HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_SRC);
+  bool HasMMDst = HasXMMFlags &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_DST_GPR) &&
+    HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_DST);
 
   // Is ModRM present via explicit instruction encoded or REX?
   const bool HasMODRM = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM);
 
   const bool HasREX = !!(DecodeInst->Flags & DecodeFlags::FLAG_REX_PREFIX);
-  const bool HasHighXMM = HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_HIGH_XMM_REG);
   const bool Has16BitAddressing = !CTX->Config.Is64BitMode &&
     DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
 
+  // This is used for ModRM register modification
+  // For both modrm.reg and modrm.rm(when mod == 0b11) when value is >= 0b100
+  // then it changes from expected registers to the high 8bits of the lower registers
+  // Bit annoying to support
+  // In the case of no modrm (REX in byte situation) then it is unaffected
+  bool Is8BitSrc{};
+  bool Is8BitDest{};
+
   // If we require ModRM and haven't decoded it yet, do it now
   // Some instructions have to read modrm upfront, others do it later
   if (HasMODRM && !DecodeInst->DecodedModRM) {
@@ -445,14 +348,24 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
     if (DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_8BIT) {
       DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_8BIT);
       DestSize = 1;
+      Is8BitDest = true;
     }
     else if (DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_16BIT) {
       DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_16BIT);
       DestSize = 2;
     }
     else if (DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_128BIT) {
-      DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_128BIT);
-      DestSize = 16;
+      if (Options.L) {
+        DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_256BIT);
+        DestSize = 32;
+      } else {
+        DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_128BIT);
+        DestSize = 16;
+      }
+    }
+    else if (DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_256BIT) {
+      DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_256BIT);
+      DestSize = 32;
     }
     else if (HasNarrowingDisplacement &&
       (DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_DEF ||
@@ -478,12 +391,20 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
     // Decode sources
     if (SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_8BIT) {
       DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_8BIT);
+      Is8BitSrc = true;
     }
     else if (SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_16BIT) {
       DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_16BIT);
     }
     else if (SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_128BIT) {
-      DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_128BIT);
+      if (Options.L) {
+        DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_256BIT);
+      } else {
+        DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_128BIT);
+      }
+    }
+    else if (SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_256BIT) {
+      DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_256BIT);
     }
     else if (HasNarrowingDisplacement &&
       (SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_DEF ||
@@ -504,14 +425,6 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
     }
   }
 
-  // This is used for ModRM register modification
-  // For both modrm.reg and modrm.rm(when mod == 0b11) when value is >= 0b100
-  // then it changes from expected registers to the high 8bits of the lower registers
-  // Bit annoying to support
-  // In the case of no modrm (REX in byte situation) then it is unaffected
-  const bool Is8BitSrc = (DecodeFlags::GetSizeSrcFlags(DecodeInst->Flags) == DecodeFlags::SIZE_8BIT);
-  const bool Is8BitDest = (DecodeFlags::GetSizeDstFlags(DecodeInst->Flags) == DecodeFlags::SIZE_8BIT);
-
   auto *CurrentDest = &DecodeInst->Dest;
 
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ||
@@ -522,8 +435,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
     CurrentDest->Data.GPR.GPR = HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ? FEXCore::X86State::REG_RAX : FEXCore::X86State::REG_RDX;
     CurrentDest = &DecodeInst->Src[0];
   }
-
-  if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) {
+  else if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) {
     LOGMAN_THROW_AA_FMT(!HasMODRM, "This instruction shouldn't have ModRM!");
 
     // If the REX is in the byte that means the lower nibble of the OP contains the destination GPR
@@ -531,7 +443,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
     // ADDITIONALLY:
     // If there is a REX prefix then that allows extended GPR usage
     CurrentDest->Type = DecodedOperand::OpType::GPR;
-    DecodeInst->Dest.Data.GPR.HighBits = (Is8BitDest && !HasREX && (Op & 0b111) >= 0b100) || HasHighXMM;
+    DecodeInst->Dest.Data.GPR.HighBits = (Is8BitDest && !HasREX && (Op & 0b111) >= 0b100);
     CurrentDest->Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, Op & 0b111, Is8BitDest, HasREX, false, false);
 
     if (CurrentDest->Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
@@ -559,7 +471,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
 
     // Decode the GPR source first
     GPR.Type = DecodedOperand::OpType::GPR;
-    GPR.Data.GPR.HighBits = (GPR8Bit && ModRM.reg >= 0b100 && !HasREX) || HasHighXMM;
+    GPR.Data.GPR.HighBits = (GPR8Bit && ModRM.reg >= 0b100 && !HasREX);
     GPR.Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_R ? 1 : 0, ModRM.reg, GPR8Bit, HasREX, HasXMMGPR, HasMMGPR);
 
     if (GPR.Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
@@ -569,7 +481,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
     // ModRM.Mod != 0b11 == Register-direct addressing
     if (ModRM.mod == 0b11) {
       NonGPR.Type = DecodedOperand::OpType::GPR;
-      NonGPR.Data.GPR.HighBits = (NonGPR8Bit && ModRM.rm >= 0b100 && !HasREX) || HasHighXMM;
+      NonGPR.Data.GPR.HighBits = (NonGPR8Bit && ModRM.rm >= 0b100 && !HasREX);
       NonGPR.Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, NonGPR8Bit, HasREX, HasXMMNonGPR, HasMMNonGPR);
       if (NonGPR.Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
         return false;
@@ -590,7 +502,12 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
   if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_VEX_1ST_SRC) != 0) {
     DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
     DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
-    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMSrc);
+
+    // If we have XMM flags at all, then SRC 1 cannot be a GPR. The only case where
+    // this is possible is with BMI1 and BMI2 instructions (which are all GPR-based
+    // and don't use XMM flags)
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMFlags);
+
     ++CurrentSrc;
   }
 
@@ -668,12 +585,6 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
   DecodeInst->OP = Op;
   DecodeInst->TableInfo = Info;
 
-  // XXX: Once we support 32bit x86 then this will be necessary to support
-  if (Info->Type == FEXCore::X86Tables::TYPE_LEGACY_PREFIX) {
-    LogMan::Msg::DFmt("Legacy Prefix");
-    return false;
-  }
-
   if (Info->Type == FEXCore::X86Tables::TYPE_UNKNOWN) {
     LogMan::Msg::DFmt("Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
     return false;
@@ -687,7 +598,11 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
   LOGMAN_THROW_AA_FMT(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX,
                      "REX PREFIX should have been decoded before this!");
 
-  if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 &&
+  // A normal instruction is the most likely.
+  if (Info->Type == FEXCore::X86Tables::TYPE_INST) [[likely]] {
+    return NormalOp(Info, Op);
+  }
+  else if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 &&
       Info->Type <= FEXCore::X86Tables::TYPE_GROUP_11) {
     uint8_t ModRMByte = ReadByte();
     DecodeInst->ModRM = ModRMByte;
@@ -777,6 +692,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
     if (Op == 0xC5) { // Two byte VEX
       pp = Byte1 & 0b11;
       options.vvvv = 15 - ((Byte1 & 0b01111000) >> 3);
+      options.L = (Byte1 & 0b100) != 0;
     }
     else { // 0xC4 = Three byte VEX
       const uint8_t Byte2 = ReadByte();
@@ -784,6 +700,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
       map_select = Byte1 & 0b11111;
       options.vvvv = 15 - ((Byte2 & 0b01111000) >> 3);
       options.w = (Byte2 & 0b10000000) != 0;
+      options.L = (Byte2 & 0b100) != 0;
       if ((Byte1 & 0b01000000) == 0) {
         LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "VEX.X shouldn't be 0 in 32-bit mode!");
         DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_X;
@@ -833,7 +750,8 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
     return NormalOp(&EVEXTableOps[EVEXOp], EVEXOp);
   }
 
-  return NormalOp(Info, Op);
+  LOGMAN_MSG_A_FMT("Invalid instruction decoding type");
+  FEX_UNREACHABLE;
 }
 
 bool Decoder::DecodeInstruction(uint64_t PC) {
@@ -852,105 +770,106 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
     case 0x0F: {// Escape Op
       uint8_t EscapeOp = ReadByte();
       switch (EscapeOp) {
-      case 0x0F: [[unlikely]] { // 3DNow!
-        // 3DNow! Instruction Encoding: 0F 0F [ModRM] [SIB] [Displacement] [Opcode]
-        // Decode ModRM
-        uint8_t ModRMByte = ReadByte();
-        DecodeInst->ModRM = ModRMByte;
-        DecodeInst->DecodedModRM = true;
+        case 0x0F: [[unlikely]] { // 3DNow!
+          // 3DNow! Instruction Encoding: 0F 0F [ModRM] [SIB] [Displacement] [Opcode]
+          // Decode ModRM
+          uint8_t ModRMByte = ReadByte();
+          DecodeInst->ModRM = ModRMByte;
+          DecodeInst->DecodedModRM = true;
 
-        FEXCore::X86Tables::ModRMDecoded ModRM;
-        ModRM.Hex = DecodeInst->ModRM;
+          FEXCore::X86Tables::ModRMDecoded ModRM;
+          ModRM.Hex = DecodeInst->ModRM;
 
-        const bool Has16BitAddressing = !CTX->Config.Is64BitMode &&
-          DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
+          const bool Has16BitAddressing = !CTX->Config.Is64BitMode &&
+            DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
 
-        // All 3DNow! instructions have the second argument as the rm handler
-        // We need to decode it upfront to get the displacement out of the way
-        if (ModRM.mod != 0b11) {
-          auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
-          (this->*Disp)(&DecodeInst->Src[0], ModRM);
+          // All 3DNow! instructions have the second argument as the rm handler
+          // We need to decode it upfront to get the displacement out of the way
+          if (ModRM.mod != 0b11) {
+            auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
+            (this->*Disp)(&DecodeInst->Src[0], ModRM);
+          }
+
+          // Take a peek at the op just past the displacement
+          uint8_t LocalOp = ReadByte();
+          return NormalOpHeader(&FEXCore::X86Tables::DDDNowOps[LocalOp], LocalOp);
+        break;
         }
+        case 0x38: { // F38 Table!
+          constexpr uint16_t PF_38_NONE = 0;
+          constexpr uint16_t PF_38_66   = (1U << 0);
+          constexpr uint16_t PF_38_F2   = (1U << 1);
+          constexpr uint16_t PF_38_F3   = (1U << 2);
 
-        // Take a peek at the op just past the displacement
-        uint8_t LocalOp = ReadByte();
-        return NormalOpHeader(&FEXCore::X86Tables::DDDNowOps[LocalOp], LocalOp);
-      break;
-      }
-      case 0x38: { // F38 Table!
-        constexpr uint16_t PF_38_NONE = 0;
-        constexpr uint16_t PF_38_66   = (1U << 0);
-        constexpr uint16_t PF_38_F2   = (1U << 1);
-        constexpr uint16_t PF_38_F3   = (1U << 2);
+          uint16_t Prefix = PF_38_NONE;
+          if (DecodeInst->Flags & DecodeFlags::FLAG_OPERAND_SIZE) {
+            Prefix |= PF_38_66;
+          }
+          if (DecodeInst->Flags & DecodeFlags::FLAG_REPNE_PREFIX) {
+            Prefix |= PF_38_F2;
+          }
+          if (DecodeInst->Flags & DecodeFlags::FLAG_REP_PREFIX) {
+            Prefix |= PF_38_F3;
+          }
 
-        uint16_t Prefix = PF_38_NONE;
-        if (DecodeInst->Flags & DecodeFlags::FLAG_OPERAND_SIZE) {
-          Prefix |= PF_38_66;
-        }
-        if (DecodeInst->Flags & DecodeFlags::FLAG_REPNE_PREFIX) {
-          Prefix |= PF_38_F2;
-        }
-        if (DecodeInst->Flags & DecodeFlags::FLAG_REP_PREFIX) {
-          Prefix |= PF_38_F3;
+          uint16_t LocalOp = (Prefix << 8) | ReadByte();
+          return NormalOpHeader(&FEXCore::X86Tables::H0F38TableOps[LocalOp], LocalOp);
+        break;
         }
+        case 0x3A: { // F3A Table!
+          constexpr uint16_t PF_3A_NONE = 0;
+          constexpr uint16_t PF_3A_66   = (1 << 0);
+          constexpr uint16_t PF_3A_REX  = (1 << 1);
 
-        uint16_t LocalOp = (Prefix << 8) | ReadByte();
-        return NormalOpHeader(&FEXCore::X86Tables::H0F38TableOps[LocalOp], LocalOp);
-      break;
-      }
-      case 0x3A: { // F3A Table!
-        constexpr uint16_t PF_3A_NONE = 0;
-        constexpr uint16_t PF_3A_66   = (1 << 0);
-        constexpr uint16_t PF_3A_REX  = (1 << 1);
+          uint16_t Prefix = PF_3A_NONE;
+          if (DecodeInst->LastEscapePrefix == 0x66) // Operand Size
+            Prefix = PF_3A_66;
 
-        uint16_t Prefix = PF_3A_NONE;
-        if (DecodeInst->LastEscapePrefix == 0x66) // Operand Size
-          Prefix = PF_3A_66;
+          if (DecodeInst->Flags & DecodeFlags::FLAG_REX_WIDENING)
+            Prefix |= PF_3A_REX;
 
-        if (DecodeInst->Flags & DecodeFlags::FLAG_REX_WIDENING)
-          Prefix |= PF_3A_REX;
+          uint16_t LocalOp = (Prefix << 8) | ReadByte();
+          return NormalOpHeader(&FEXCore::X86Tables::H0F3ATableOps[LocalOp], LocalOp);
+        break;
+        }
+        default: [[likely]] { // Two byte table!
+          // x86-64 abuses three legacy prefixes to extend the table encodings
+          // 0x66 - Operand Size prefix
+          // 0xF2 - REPNE prefix
+          // 0xF3 - REP prefix
+          // If any of these three prefixes are used then it falls down the subtable
+          // Additionally: If you hit repeat of differnt prefixes then only the LAST one before this one works for subtable selection
 
-        uint16_t LocalOp = (Prefix << 8) | ReadByte();
-        return NormalOpHeader(&FEXCore::X86Tables::H0F3ATableOps[LocalOp], LocalOp);
-      break;
-      }
-      default: // Two byte table!
-        // x86-64 abuses three legacy prefixes to extend the table encodings
-        // 0x66 - Operand Size prefix
-        // 0xF2 - REPNE prefix
-        // 0xF3 - REP prefix
-        // If any of these three prefixes are used then it falls down the subtable
-        // Additionally: If you hit repeat of differnt prefixes then only the LAST one before this one works for subtable selection
+          bool NoOverlay = (FEXCore::X86Tables::SecondBaseOps[EscapeOp].Flags & InstFlags::FLAGS_NO_OVERLAY) != 0;
+          bool NoOverlay66 = (FEXCore::X86Tables::SecondBaseOps[EscapeOp].Flags & InstFlags::FLAGS_NO_OVERLAY66) != 0;
 
-        bool NoOverlay = (FEXCore::X86Tables::SecondBaseOps[EscapeOp].Flags & InstFlags::FLAGS_NO_OVERLAY) != 0;
-        bool NoOverlay66 = (FEXCore::X86Tables::SecondBaseOps[EscapeOp].Flags & InstFlags::FLAGS_NO_OVERLAY66) != 0;
-
-        if (NoOverlay) { // This section of the table ignores prefix extention
-          return NormalOpHeader(&FEXCore::X86Tables::SecondBaseOps[EscapeOp], EscapeOp);
+          if (NoOverlay) { // This section of the table ignores prefix extention
+            return NormalOpHeader(&FEXCore::X86Tables::SecondBaseOps[EscapeOp], EscapeOp);
+          }
+          else if (DecodeInst->LastEscapePrefix == 0xF3) { // REP
+            // Remove prefix so it doesn't effect calculations.
+            // This is only an escape prefix rather tan modifier now
+            DecodeInst->Flags &= ~DecodeFlags::FLAG_REP_PREFIX;
+            return NormalOpHeader(&FEXCore::X86Tables::RepModOps[EscapeOp], EscapeOp);
+          }
+          else if (DecodeInst->LastEscapePrefix == 0xF2) { // REPNE
+            // Remove prefix so it doesn't effect calculations.
+            // This is only an escape prefix rather tan modifier now
+            DecodeInst->Flags &= ~DecodeFlags::FLAG_REPNE_PREFIX;
+            return NormalOpHeader(&FEXCore::X86Tables::RepNEModOps[EscapeOp], EscapeOp);
+          }
+          else if (DecodeInst->LastEscapePrefix == 0x66 && !NoOverlay66) { // Operand Size
+            // Remove prefix so it doesn't effect calculations.
+            // This is only an escape prefix rather tan modifier now
+            DecodeInst->Flags &= ~DecodeFlags::FLAG_OPERAND_SIZE;
+            DecodeFlags::PopOpAddrIf(&DecodeInst->Flags, DecodeFlags::FLAG_OPERAND_SIZE_LAST);
+            return NormalOpHeader(&FEXCore::X86Tables::OpSizeModOps[EscapeOp], EscapeOp);
+          }
+          else {
+            return NormalOpHeader(&FEXCore::X86Tables::SecondBaseOps[EscapeOp], EscapeOp);
+          }
+        break;
         }
-        else if (DecodeInst->LastEscapePrefix == 0xF3) { // REP
-          // Remove prefix so it doesn't effect calculations.
-          // This is only an escape prefix rather tan modifier now
-          DecodeInst->Flags &= ~DecodeFlags::FLAG_REP_PREFIX;
-          return NormalOpHeader(&FEXCore::X86Tables::RepModOps[EscapeOp], EscapeOp);
-        }
-        else if (DecodeInst->LastEscapePrefix == 0xF2) { // REPNE
-          // Remove prefix so it doesn't effect calculations.
-          // This is only an escape prefix rather tan modifier now
-          DecodeInst->Flags &= ~DecodeFlags::FLAG_REPNE_PREFIX;
-          return NormalOpHeader(&FEXCore::X86Tables::RepNEModOps[EscapeOp], EscapeOp);
-        }
-        else if (DecodeInst->LastEscapePrefix == 0x66 && !NoOverlay66) { // Operand Size
-          // Remove prefix so it doesn't effect calculations.
-          // This is only an escape prefix rather tan modifier now
-          DecodeInst->Flags &= ~DecodeFlags::FLAG_OPERAND_SIZE;
-          DecodeFlags::PopOpAddrIf(&DecodeInst->Flags, DecodeFlags::FLAG_OPERAND_SIZE_LAST);
-          return NormalOpHeader(&FEXCore::X86Tables::OpSizeModOps[EscapeOp], EscapeOp);
-        }
-        else {
-          return NormalOpHeader(&FEXCore::X86Tables::SecondBaseOps[EscapeOp], EscapeOp);
-        }
-      break;
       }
     break;
     }
@@ -1003,7 +922,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
     case 0x65: // GS prefix
       DecodeInst->Flags |= DecodeFlags::FLAG_GS_PREFIX;
     break;
-    default: { // Default base table
+    default: [[likely]] { // Default base table
       auto Info = &FEXCore::X86Tables::BaseOps[Op];
 
       if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) {
@@ -1113,6 +1032,35 @@ void Decoder::BranchTargetInMultiblockRange() {
   }
 }
 
+bool Decoder::BranchTargetCanContinue(bool FinalInstruction) const {
+  if (FinalInstruction) {
+    return false;
+  }
+
+  uint64_t TargetRIP = 0;
+  const uint8_t GPRSize = CTX->GetGPRSize();
+
+  if (DecodeInst->OP == 0xE8) { // Call - immediate target
+    const uint64_t NextRIP = DecodeInst->PC + DecodeInst->InstSize;
+    LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+    TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
+
+    if (GPRSize == 4) {
+      // If we are running a 32bit guest then wrap around addresses that go above 32bit
+      TargetRIP &= 0xFFFFFFFFU;
+    }
+
+    if (TargetRIP == NextRIP) {
+      // Optimize the case that the instruction is jumping just after itself.
+      // This is a GOT calculation which we can optimize out.
+      // Optimization occurs inside of the OpDispatcher implementation
+      return true;
+    }
+  }
+
+  return false;
+}
+
 const uint8_t *Decoder::AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP) {
   constexpr uint64_t VSyscall_Base = 0xFFFF'FFFF'FF60'0000ULL;
   constexpr uint64_t VSyscall_End = VSyscall_Base + 0x1000;
@@ -1165,7 +1113,7 @@ void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC,
 
   uint64_t CurrentCodePage = PC & FHU::FEX_PAGE_MASK;
 
-  std::set<uint64_t> CodePages = { CurrentCodePage };
+  fextl::set<uint64_t> CodePages = { CurrentCodePage };
 
   AddContainedCodePage(PC, CurrentCodePage, FHU::FEX_PAGE_SIZE);
 
@@ -1193,24 +1141,19 @@ void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC,
       auto OpMinPage = OpMinAddress & FHU::FEX_PAGE_MASK;
       auto OpMaxPage = OpMaxAddress & FHU::FEX_PAGE_MASK;
 
-
       if (OpMinPage != CurrentCodePage) {
         CurrentCodePage = OpMinPage;
-        if (CodePages.insert(CurrentCodePage).second) {
-          AddContainedCodePage(PC, CurrentCodePage, FHU::FEX_PAGE_SIZE);
-        }
+        CodePages.insert(CurrentCodePage);
       }
 
       if (OpMaxPage != CurrentCodePage) {
         CurrentCodePage = OpMaxPage;
-        if (CodePages.insert(CurrentCodePage).second) {
-          AddContainedCodePage(PC, CurrentCodePage, FHU::FEX_PAGE_SIZE);
-        }
+        CodePages.insert(CurrentCodePage);
       }
 
       bool ErrorDuringDecoding = !DecodeInstruction(RIPToDecode + PCOffset);
 
-      if (ErrorDuringDecoding) {
+      if (ErrorDuringDecoding) [[unlikely]] {
         LogMan::Msg::DFmt("Couldn't Decode something at 0x{:x}, Started at 0x{:x}", RIPToDecode + PCOffset, PC);
         // Put an invalid instruction in the stream so the core can raise SIGILL if hit
         CurrentBlockDecoding.HasInvalidInstruction = true;
@@ -1237,23 +1180,21 @@ void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC,
         CanContinue = true;
       }
 
+      bool FinalInstruction = DecodedSize >= CTX->Config.MaxInstPerBlock ||
+          DecodedSize >= DefaultDecodedBufferSize ||
+          TotalInstructions >= CTX->Config.MaxInstPerBlock;
+
       if (DecodeInst->TableInfo->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SETS_RIP) {
         // If we have multiblock enabled
         // If the branch target is within our multiblock range then we can keep going on
         // We don't want to short circuit this since we want to calculate our ranges still
         BranchTargetInMultiblockRange();
+
+        // Bypass branches if we can continue through them in some cases.
+        CanContinue |= BranchTargetCanContinue(FinalInstruction);
       }
 
-      if (!CanContinue) {
-        break;
-      }
-
-      if (DecodedSize >= CTX->Config.MaxInstPerBlock ||
-          DecodedSize >= DefaultDecodedBufferSize) {
-        break;
-      }
-
-      if (TotalInstructions >= CTX->Config.MaxInstPerBlock) {
+      if (FinalInstruction || !CanContinue) {
         break;
       }
 
@@ -1269,6 +1210,9 @@ void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC,
     CurrentBlockDecoding.DecodedInstructions = &DecodedBuffer[BlockStartOffset];
   }
 
+  for (auto CodePage : CodePages) {
+    AddContainedCodePage(PC, CodePage, FHU::FEX_PAGE_SIZE);
+  }
 
   // sort for better branching
   std::sort(Blocks.begin(), Blocks.end(), [](const FEXCore::Frontend::Decoder::DecodedBlocks& a, const FEXCore::Frontend::Decoder::DecodedBlocks& b) {

External/FEXCore/Source/Interface/Core/Frontend.h

@@ -1,17 +1,18 @@
 #pragma once
 
-#include <FEXCore/Debug/X86Tables.h>
+#include "Interface/Core/X86Tables/X86Tables.h"
+
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/Telemetry.h>
+#include <FEXCore/fextl/set.h>
+#include <FEXCore/fextl/vector.h>
 
 #include <array>
 #include <cstdint>
-#include <set>
 #include <stddef.h>
-#include <vector>
 
 namespace FEXCore::Context {
-struct Context;
+class ContextImpl;
 }
 
 namespace FEXCore::Frontend {
@@ -25,11 +26,11 @@ public:
     bool HasInvalidInstruction{};
   };
 
-  Decoder(FEXCore::Context::Context *ctx);
+  Decoder(FEXCore::Context::ContextImpl *ctx);
   ~Decoder();
   void DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC, std::function<void(uint64_t BlockEntry, uint64_t Start, uint64_t Length)> AddContainedCodePage);
 
-  std::vector<DecodedBlocks> const *GetDecodedBlocks() const {
+  fextl::vector<DecodedBlocks> const *GetDecodedBlocks() const {
     return &Blocks;
   }
 
@@ -37,7 +38,7 @@ public:
   uint64_t DecodedMaxAddress {~0ULL};
 
   void SetSectionMaxAddress(uint64_t v) { SectionMaxAddress = v; }
-  void SetExternalBranches(std::set<uint64_t> *v) { ExternalBranches = v; }
+  void SetExternalBranches(fextl::set<uint64_t> *v) { ExternalBranches = v; }
 
   void DelayedDisownBuffer() {
     PoolObject.DelayedDisownBuffer();
@@ -49,14 +50,16 @@ private:
   struct DecodedHeader {
     uint8_t vvvv; // Encoded operand in a VEX prefix.
     bool w;       // VEX.W bit.
+    bool L;       // VEX.L bit (if set then 256 bit operation, if unset then scalar or 128-bit operation)
   };
 
-  FEXCore::Context::Context *CTX;
+  FEXCore::Context::ContextImpl *CTX;
   const FEXCore::HLE::SyscallOSABI OSABI{};
 
   bool DecodeInstruction(uint64_t PC);
 
   void BranchTargetInMultiblockRange();
+  bool BranchTargetCanContinue(bool FinalInstruction) const;
 
   uint8_t ReadByte();
   uint8_t PeekByte(uint8_t Offset) const;
@@ -87,10 +90,10 @@ private:
   uint64_t SymbolMinAddress {~0ULL};
   uint64_t SectionMaxAddress {~0ULL};
 
-  std::vector<DecodedBlocks> Blocks;
-  std::set<uint64_t> BlocksToDecode;
-  std::set<uint64_t> HasBlocks;
-  std::set<uint64_t> *ExternalBranches {nullptr};
+  fextl::vector<DecodedBlocks> Blocks;
+  fextl::set<uint64_t> BlocksToDecode;
+  fextl::set<uint64_t> HasBlocks;
+  fextl::set<uint64_t> *ExternalBranches {nullptr};
 
   // ModRM rm decoding
   using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);

External/FEXCore/Source/Interface/Core/GdbServer.cpp

@@ -8,11 +8,8 @@ $end_info$
 #include <cstdlib>
 #include <cstdio>
 #include <iomanip>
-#include <sstream>
-#include <string>
 #include <memory>
 #include <optional>
-#include <vector>
 #include "Common/SoftFloat.h"
 #include "Common/StringUtils.h"
 #include "Interface/Context/Context.h"
@@ -27,39 +24,45 @@ $end_info$
 #include <FEXCore/HLE/Linux/ThreadManagement.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/FileLoading.h>
 #include <FEXCore/Utils/NetStream.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Threads.h>
+#include <FEXCore/fextl/fmt.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/sstream.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/vector.h>
 
 #include <atomic>
 #include <cstring>
+#ifndef _WIN32
 #include <elf.h>
+#include <netdb.h>
+#include <sys/socket.h>
+#endif
 #include <errno.h>
 #include <fcntl.h>
-#include <fstream>
 #include <fmt/format.h>
-#include <netdb.h>
 #include <signal.h>
 #include <stddef.h>
 #include <string_view>
-#include <sys/socket.h>
 #include <sys/stat.h>
 #include <unistd.h>
 #include <utility>
-#include <vector>
 
 #include "GdbServer.h"
 
 namespace FEXCore
 {
-
+#ifndef _WIN32
 void GdbServer::Break(int signal) {
   std::lock_guard lk(sendMutex);
   if (!CommsStream) {
     return;
   }
 
-  const auto str = fmt::format("S{:02x}", signal);
+  const fextl::string str = fextl::fmt::format("S{:02x}", signal);
   SendPacket(*CommsStream, str);
 }
 
@@ -68,11 +71,11 @@ void GdbServer::WaitForThreadWakeup() {
   ThreadBreakEvent.Wait();
 }
 
-GdbServer::GdbServer(FEXCore::Context::Context *ctx) : CTX(ctx) {
+GdbServer::GdbServer(FEXCore::Context::ContextImpl *ctx) : CTX(ctx) {
   // Pass all signals by default
   std::fill(PassSignals.begin(), PassSignals.end(), true);
 
-  Context::SetExitHandler(ctx, [this](uint64_t ThreadId, FEXCore::Context::ExitReason ExitReason) {
+  ctx->SetExitHandler([this](uint64_t ThreadId, FEXCore::Context::ExitReason ExitReason) {
     if (ExitReason == FEXCore::Context::ExitReason::EXIT_DEBUG) {
       this->Break(SIGTRAP);
     }
@@ -101,7 +104,7 @@ GdbServer::GdbServer(FEXCore::Context::Context *ctx) : CTX(ctx) {
   StartThread();
 }
 
-static int calculateChecksum(const std::string &packet) {
+static int calculateChecksum(const fextl::string &packet) {
   unsigned char checksum = 0;
   for (const char &c : packet) {
     checksum += c;
@@ -109,8 +112,8 @@ static int calculateChecksum(const std::string &packet) {
   return checksum;
 }
 
-static std::string hexstring(std::istringstream &ss, int delm) {
-  std::string ret;
+static fextl::string hexstring(fextl::istringstream &ss, int delm) {
+  fextl::string ret;
 
   char hexString[3] = {0, 0, 0};
   while (ss.peek() != delm) {
@@ -125,8 +128,8 @@ static std::string hexstring(std::istringstream &ss, int delm) {
   return ret;
 }
 
-static std::string encodeHex(const unsigned char *data, size_t length) {
-  std::ostringstream ss;
+static fextl::string encodeHex(const unsigned char *data, size_t length) {
+  fextl::ostringstream ss;
 
   for (size_t i=0; i < length; i++) {
     ss << std::setfill('0') << std::setw(2) << std::hex << int(data[i]);
@@ -134,26 +137,19 @@ static std::string encodeHex(const unsigned char *data, size_t length) {
   return ss.str();
 }
 
-static std::string getThreadName(uint32_t ThreadID) {
-  const auto ThreadFile = fmt::format("/proc/{}/task/{}/comm", getpid(), ThreadID);
-  std::fstream fs(ThreadFile, std::fstream::in | std::fstream::binary);
-
-  if (fs.is_open()) {
-    std::string ThreadName;
-    fs >> ThreadName;
-    fs.close();
-    return ThreadName;
-  }
-
-  return "<No Name>";
+static fextl::string getThreadName(uint32_t ThreadID) {
+  const auto ThreadFile = fextl::fmt::format("/proc/{}/task/{}/comm", getpid(), ThreadID);
+  fextl::string ThreadName {"<No Name>"};
+  FEXCore::FileLoading::LoadFile(ThreadName, ThreadFile);
+  return ThreadName;
 }
 
 // Packet parser
 // Takes a serial stream and reads a single packet
 // Un-escapes chars, checks the checksum and request a retransmit if it fails.
 // Once the checksum is validated, it acknowledges and returns the packet in a string
-std::string GdbServer::ReadPacket(std::iostream &stream) {
-  std::string packet{};
+fextl::string GdbServer::ReadPacket(std::iostream &stream) {
+  fextl::string packet{};
 
   // The GDB "Remote Serial Protocal" was originally 7bit clean for use on serial ports.
   // Binary data is useally hex encoded. However some later extentions just put
@@ -172,7 +168,7 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
           LogMan::Msg::EFmt("Dropping unexpected data: \"{}\"", packet);
 
         // clear any existing data, must have been a mistake.
-        packet = std::string();
+        packet = fextl::string();
         break;
       case '}': // escape char
       {
@@ -203,8 +199,8 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
   return "";
 }
 
-static std::string escapePacket(const std::string& packet) {
-  std::ostringstream ss;
+static fextl::string escapePacket(const fextl::string& packet) {
+  fextl::ostringstream ss;
 
   for(const auto &c : packet) {
     switch (c) {
@@ -225,9 +221,9 @@ static std::string escapePacket(const std::string& packet) {
   return ss.str();
 }
 
-void GdbServer::SendPacket(std::ostream &stream, const std::string& packet) {
+void GdbServer::SendPacket(std::ostream &stream, const fextl::string& packet) {
   const auto escaped = escapePacket(packet);
-  const auto str = fmt::format("${}#{:02x}", escaped, calculateChecksum(escaped));
+  const auto str = fextl::fmt::format("${}#{:02x}", escaped, calculateChecksum(escaped));
 
   stream << str << std::flush;
 }
@@ -263,7 +259,7 @@ struct FEX_PACKED GDBContextDefinition {
   uint32_t mxcsr;
 };
 
-std::string GdbServer::readRegs() {
+fextl::string GdbServer::readRegs() {
   GDBContextDefinition GDB{};
   FEXCore::Core::CPUState state{};
 
@@ -311,11 +307,11 @@ std::string GdbServer::readRegs() {
   return encodeHex((unsigned char *)&GDB, sizeof(GDBContextDefinition));
 }
 
-GdbServer::HandledPacketType GdbServer::readReg(const std::string& packet) {
-	size_t addr;
-	auto ss = std::istringstream(packet);
-	ss.get(); // Drop first letter
-	ss >> std::hex >> addr;
+GdbServer::HandledPacketType GdbServer::readReg(const fextl::string& packet) {
+  size_t addr;
+  auto ss = fextl::istringstream(packet);
+  ss.get(); // Drop first letter
+  ss >> std::hex >> addr;
 
   FEXCore::Core::CPUState state{};
 
@@ -395,8 +391,8 @@ GdbServer::HandledPacketType GdbServer::readReg(const std::string& packet) {
   return {"E00", HandledPacketType::TYPE_ACK};
 }
 
-std::string buildTargetXML() {
-  std::ostringstream xml;
+fextl::string buildTargetXML() {
+  fextl::ostringstream xml;
 
   xml << "<?xml version='1.0'?>\n";
   xml << "<!DOCTYPE target SYSTEM 'gdb-target.dtd'>\n";
@@ -448,7 +444,7 @@ std::string buildTargetXML() {
 
       // x87 stack
       for (int i=0; i < 8; i++) {
-          reg("st" + std::to_string(i), "i387_ext", 80);
+        reg(fextl::fmt::format("st{}", i), "i387_ext", 80);
       }
 
       // x87 control
@@ -484,7 +480,7 @@ std::string buildTargetXML() {
 
       // SSE regs
       for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-          reg("xmm" + std::to_string(i), "vec128", 128);
+          reg(fextl::fmt::format("xmm{}", i), "vec128", 128);
       }
 
       reg("mxcsr", "int", 32);
@@ -520,8 +516,8 @@ std::string buildTargetXML() {
   return xml.str();
 }
 
-std::string buildOSData() {
-  std::ostringstream xml;
+fextl::string buildOSData() {
+  fextl::ostringstream xml;
 
   xml << "<?xml version='1.0'?>\n";
 
@@ -541,24 +537,27 @@ void GdbServer::buildLibraryMap() {
     return;
   }
 
-  std::ostringstream xml;
+  fextl::ostringstream xml;
 
-  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
-  std::string Line;
+  fextl::string MapsFile;
+  FEXCore::FileLoading::LoadFile(MapsFile, "/proc/self/maps");
+  fextl::istringstream MapsStream(MapsFile);
+
+  fextl::string Line;
 
   struct FileData {
     uint64_t Begin;
   };
 
-  std::map<std::string, std::vector<FileData>> SegmentMaps;
+  fextl::map<fextl::string, fextl::vector<FileData>> SegmentMaps;
 
   // 7ff5dd6d2000-7ff5dd6d3000 rw-p 0000a000 103:0b 1881447                   /usr/lib/x86_64-linux-gnu/libnss_compat.so.2
-  std::string const &RuntimeExecutable = Filename();
-  while (std::getline(fs, Line)) {
-    auto ss = std::istringstream(Line);
-    std::string Tmp;
-    std::string Begin;
-    std::string Name;
+  fextl::string const &RuntimeExecutable = Filename();
+  while (std::getline(MapsStream, Line)) {
+    auto ss = fextl::istringstream(Line);
+    fextl::string Tmp;
+    fextl::string Begin;
+    fextl::string Name;
     std::getline(ss, Begin, '-');
     std::getline(ss, Tmp, ' '); // End
     std::getline(ss, Tmp, ' '); // Perm
@@ -609,18 +608,18 @@ void GdbServer::buildLibraryMap() {
   LibraryMapChanged = false;
 }
 
-GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
-  std::string object;
-  std::string rw;
-  std::string annex;
+GdbServer::HandledPacketType GdbServer::handleXfer(const fextl::string &packet) {
+  fextl::string object;
+  fextl::string rw;
+  fextl::string annex;
   int annex_pid;
   int offset;
   int length;
 
   // Parse Xfer message
   {
-    auto ss = std::istringstream(packet);
-    std::string expectXfer;
+    auto ss = fextl::istringstream(packet);
+    fextl::string expectXfer;
     char expectComma;
 
     std::getline(ss, expectXfer, ':');
@@ -631,7 +630,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
       annex_pid = getpid();
     }
     else {
-      auto ss_pid = std::istringstream(annex);
+      auto ss_pid = fextl::istringstream(annex);
       ss_pid >> std::hex >> annex_pid;
     }
     ss >> std::hex >> offset;
@@ -644,7 +643,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
   }
 
   // Lambda to correctly encode any reply
-  auto encode = [&](std::string data) -> std::string {
+  auto encode = [&](fextl::string data) -> fextl::string {
     if (offset == data.size())
       return "l";
     if (offset >= data.size())
@@ -674,7 +673,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
       auto Threads = CTX->GetThreads();
 
       ThreadString.clear();
-      std::ostringstream ss;
+      fextl::ostringstream ss;
       ss << "<?xml version=\"1.0\"?>\n";
       ss << "<threads>\n";
       for (auto &Thread : *Threads) {
@@ -710,7 +709,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
     auto CodeLoader = CTX->SyscallHandler->GetCodeLoader();
     uint64_t auxv_ptr, auxv_size;
     CodeLoader->GetAuxv(auxv_ptr, auxv_size);
-    std::string data;
+    fextl::string data;
     if (CTX->Config.Is64BitMode) {
       data.resize(auxv_size);
       memcpy(data.data(), reinterpret_cast<void*>(auxv_ptr), data.size());
@@ -736,11 +735,14 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
 
 static size_t CheckMemMapping(uint64_t Address, size_t Size) {
   uint64_t AddressEnd = Address + Size;
-  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
-  std::string Line;
+  fextl::string MapsFile;
+  FEXCore::FileLoading::LoadFile(MapsFile, "/proc/self/maps");
+  fextl::istringstream MapsStream(MapsFile);
 
-  while (std::getline(fs, Line)) {
-    if (fs.eof()) break;
+  fextl::string Line;
+
+  while (std::getline(MapsStream, Line)) {
+    if (MapsStream.eof()) break;
     uint64_t Begin, End;
     char r,w,x,p;
     if (sscanf(Line.c_str(), "%lx-%lx %c%c%c%c", &Begin, &End, &r, &w, &x, &p) == 6) {
@@ -761,17 +763,17 @@ static size_t CheckMemMapping(uint64_t Address, size_t Size) {
 GdbServer::HandledPacketType GdbServer::handleProgramOffsets() {
   auto CodeLoader = CTX->SyscallHandler->GetCodeLoader();
   uint64_t BaseOffset = CodeLoader->GetBaseOffset();
-  auto str = fmt::format("Text={:x};Data={:x};Bss={:x}", BaseOffset, BaseOffset, BaseOffset);
+  fextl::string str = fextl::fmt::format("Text={:x};Data={:x};Bss={:x}", BaseOffset, BaseOffset, BaseOffset);
   return {std::move(str), HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleMemory(const std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleMemory(const fextl::string &packet) {
   bool write;
   size_t addr;
   size_t length;
-  std::string data;
+  fextl::string data;
 
-  auto ss = std::istringstream(packet);
+  auto ss = fextl::istringstream(packet);
   write = ss.get() == 'M';
   ss >> std::hex >> addr;
   ss.get(); // discard comma
@@ -806,22 +808,22 @@ GdbServer::HandledPacketType GdbServer::handleMemory(const std::string &packet)
 }
 
 
-GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleQuery(const fextl::string &packet) {
   const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
-  const auto MatchStr = [](const std::string &Str, const char *str) -> bool { return Str.rfind(str, 0) == 0; };
+  const auto MatchStr = [](const fextl::string &Str, const char *str) -> bool { return Str.rfind(str, 0) == 0; };
 
-  const auto split = [](const std::string &Str, char deliminator) -> std::vector<std::string> {
-    std::vector<std::string> Elements;
-    std::istringstream Input(Str);
-    for (std::string line;
+  const auto split = [](const fextl::string &Str, char deliminator) -> fextl::vector<fextl::string> {
+    fextl::vector<fextl::string> Elements;
+    fextl::istringstream Input(Str);
+    for (fextl::string line;
          std::getline(Input, line);
          Elements.emplace_back(line));
     return Elements;
   };
 
   if (match("QNonStop:")) {
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("QNonStop:").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("QNonStop:").size());
     ss.get(); // discard colon
     ss >> NonStopMode;
     return {"OK", HandledPacketType::TYPE_ACK};
@@ -832,7 +834,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
 
     // For feature documentation
     // https://sourceware.org/gdb/current/onlinedocs/gdb/General-Query-Packets.html#qSupported
-    std::string SupportedFeatures{};
+    fextl::string SupportedFeatures{};
 
     // Required features
     SupportedFeatures += "PacketSize=32768;";
@@ -901,7 +903,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
   if (match("qfThreadInfo")) {
     auto Threads = CTX->GetThreads();
 
-    std::ostringstream ss;
+    fextl::ostringstream ss;
     ss << "m";
     for (size_t i = 0; i < Threads->size(); ++i) {
       auto Thread = Threads->at(i);
@@ -916,8 +918,8 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
     return {"l", HandledPacketType::TYPE_ACK};
   }
   if (match("qThreadExtraInfo")) {
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("qThreadExtraInfo").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("qThreadExtraInfo").size());
     ss.get(); // discard comma
     uint32_t ThreadID;
     ss >> std::hex >> ThreadID;
@@ -926,7 +928,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
   }
   if (match("qC")) {
     // Returns the current Thread ID
-    std::ostringstream ss;
+    fextl::ostringstream ss;
     ss << "m" <<  std::hex << CTX->ParentThread->ThreadManager.TID;
     return {ss.str(), HandledPacketType::TYPE_ACK};
   }
@@ -935,10 +937,10 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
     return {"OK", HandledPacketType::TYPE_ACK};
   }
   if (match("qSymbol")) {
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("qSymbol").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("qSymbol").size());
     ss.get(); // discard colon
-    std::string Symbol_Val, Symbol_name;
+    fextl::string Symbol_Val, Symbol_name;
     std::getline(ss, Symbol_Val, ':');
     std::getline(ss, Symbol_name, ':');
 
@@ -955,13 +957,13 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
     std::fill(PassSignals.begin(), PassSignals.end(), false);
 
     // eg: QPassSignals:e;10;14;17;1a;1b;1c;21;24;25;2c;4c;97;
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("QPassSignals").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("QPassSignals").size());
     ss.get(); // discard colon
 
     // We now have a semi-colon deliminated list of signals to pass to the guest process
-    for (std::string tmp; std::getline(ss, tmp, ';'); ) {
-      uint32_t Signal = std::stoi(tmp, nullptr, 16);
+    for (fextl::string tmp; std::getline(ss, tmp, ';'); ) {
+      uint32_t Signal = std::stoi(tmp.c_str(), nullptr, 16);
       if (Signal < SignalDelegator::MAX_SIGNALS) {
         PassSignals[Signal] = true;
       }
@@ -984,7 +986,7 @@ GdbServer::HandledPacketType GdbServer::ThreadAction(char action, uint32_t tid)
     case 's': {
       CTX->Step();
       SendPacketPair({"OK", HandledPacketType::TYPE_ACK});
-      auto str = fmt::format("T05thread:{:02x};", getpid());
+      fextl::string str = fextl::fmt::format("T05thread:{:02x};", getpid());
       if (LibraryMapChanged) {
         // If libraries have changed then let gdb know
         str += "library:1;";
@@ -1002,26 +1004,26 @@ GdbServer::HandledPacketType GdbServer::ThreadAction(char action, uint32_t tid)
   }
 }
 
-GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
-  const auto match = [&](const std::string& str) -> std::optional<std::istringstream> {
+GdbServer::HandledPacketType GdbServer::handleV(const fextl::string& packet) {
+  const auto match = [&](const fextl::string& str) -> std::optional<fextl::istringstream> {
     if (packet.rfind(str, 0) == 0) {
-      auto ss = std::istringstream(packet);
+      auto ss = fextl::istringstream(packet);
       ss.seekg(str.size());
       return ss;
     }
     return std::nullopt;
   };
 
-  const auto F       = [](int result) { return fmt::format("F{:x}", result); };
-  const auto F_error = [] { return fmt::format("F-1,{:x}", errno); };
-  const auto F_data  = [](int result, const std::string& data) {
+  const auto F       = [](int result) -> fextl::string { return fextl::fmt::format("F{:x}", result); };
+  const auto F_error = []() -> fextl::string { return fextl::fmt::format("F-1,{:x}", errno); };
+  const auto F_data  = [](int result, const fextl::string& data) -> fextl::string {
     // Binary encoded data is raw appended to the end
-    return fmt::format("F{:#x};", result) + data;
+    return fextl::fmt::format("F{:#x};", result) + data;
   };
 
-  std::optional<std::istringstream> ss;
+  std::optional<fextl::istringstream> ss;
   if((ss = match("vFile:open:"))) {
-    std::string filename;
+    fextl::string filename;
     int flags;
     int mode;
 
@@ -1053,7 +1055,7 @@ GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
     ss->get(); // discard comma
     *ss >> std::hex >> offset;
 
-    std::string data(count, '\0');
+    fextl::string data(count, '\0');
     if (lseek(fd, offset, SEEK_SET) < 0) {
       return {F_error(), HandledPacketType::TYPE_ACK};
     }
@@ -1093,14 +1095,14 @@ GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
   return {"", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleThreadOp(const fextl::string &packet) {
   const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
 
   if (match("Hc")) {
     // Sets thread to this ID for stepping
     // This is deprecated and vCont should be used instead
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("Hc").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("Hc").size());
     ss >> std::hex >> CurrentDebuggingThread;
 
     CTX->Pause();
@@ -1109,7 +1111,7 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet
 
   if (match("Hg")) {
     // Sets thread for "other" operations
-    auto ss = std::istringstream(packet);
+    auto ss = fextl::istringstream(packet);
     ss.seekg(std::string_view("Hg").size());
     ss >> std::hex >> CurrentDebuggingThread;
 
@@ -1121,8 +1123,8 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet
   return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
-GdbServer::HandledPacketType GdbServer::handleBreakpoint(const std::string &packet) {
-  auto ss = std::istringstream(packet);
+GdbServer::HandledPacketType GdbServer::handleBreakpoint(const fextl::string &packet) {
+  auto ss = fextl::istringstream(packet);
 
   // Don't do anything with set breakpoints yet
   [[maybe_unused]] bool Set{};
@@ -1138,13 +1140,13 @@ GdbServer::HandledPacketType GdbServer::handleBreakpoint(const std::string &pack
   return {"OK", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::ProcessPacket(const std::string &packet) {
+GdbServer::HandledPacketType GdbServer::ProcessPacket(const fextl::string &packet) {
   switch (packet[0]) {
     case '?': {
       // Indicates the reason that the thread has stopped
       // Behaviour changes if the target is in non-stop mode
       // Binja doesn't support S response here
-      auto str = fmt::format("T00thread:{:x};", getpid());
+      fextl::string str = fextl::fmt::format("T00thread:{:x};", getpid());
       return {std::move(str), HandledPacketType::TYPE_ACK};
     }
     case 'c':
@@ -1225,7 +1227,7 @@ void GdbServer::GdbServerLoop() {
     while ((c = CommsStream->get()) >= 0 ) {
         switch (c) {
         case '$': {
-            std::string packet = ReadPacket(*CommsStream);
+            auto packet = ReadPacket(*CommsStream);
             response = ProcessPacket(packet);
             SendPacketPair(response);
             if (response.TypeResponse == HandledPacketType::TYPE_UNKNOWN) {
@@ -1245,7 +1247,7 @@ void GdbServer::GdbServerLoop() {
             break;
         case '\x03': { // ASCII EOT
             CTX->Pause();
-            auto str = fmt::format("T02thread:{:02x};", getpid());
+            fextl::string str = fextl::fmt::format("T02thread:{:02x};", getpid());
             if (LibraryMapChanged) {
               // If libraries have changed then let gdb know
               str += "library:1;";
@@ -1279,7 +1281,8 @@ void GdbServer::StartThread() {
 }
 
 void GdbServer::OpenListenSocket() {
-  // open socket
+  // getaddrinfo allocates memory that can't be removed.
+  FEXCore::Allocator::YesIKnowImNotSupposedToUseTheGlibcAllocator glibc;
   struct addrinfo hints, *res;
 
   memset(&hints, 0, sizeof(hints));
@@ -1308,9 +1311,11 @@ void GdbServer::OpenListenSocket() {
   }
 
   listen(ListenSocket, 1);
+
+  freeaddrinfo(res);
 }
 
-std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
+fextl::unique_ptr<std::iostream> GdbServer::OpenSocket() {
   // Block until a connection arrives
   struct sockaddr_storage their_addr{};
   socklen_t addr_size{};
@@ -1318,7 +1323,8 @@ std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
   LogMan::Msg::IFmt("GdbServer, waiting for connection on localhost:8086");
   int new_fd = accept(ListenSocket, (struct sockaddr *)&their_addr, &addr_size);
 
-  return std::make_unique<FEXCore::Utils::NetStream>(new_fd);
+  return fextl::make_unique<FEXCore::Utils::NetStream>(new_fd);
 }
 
+#endif
 } // namespace FEXCore

External/FEXCore/Source/Interface/Core/GdbServer.h

@@ -8,23 +8,24 @@ $end_info$
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/Threads.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
 
 #include <atomic>
 #include <istream>
 #include <memory>
 #include <mutex>
 #include <stdint.h>
-#include <string>
 
 namespace FEXCore {
 
 namespace Context {
-  struct Context;
+  class ContextImpl;
 }
 
 class GdbServer {
 public:
-    GdbServer(FEXCore::Context::Context *ctx);
+    GdbServer(FEXCore::Context::ContextImpl *ctx);
 
     // Public for threading
     void GdbServerLoop();
@@ -37,10 +38,10 @@ private:
     void Break(int signal);
 
     void OpenListenSocket();
-    std::unique_ptr<std::iostream> OpenSocket();
+    fextl::unique_ptr<std::iostream> OpenSocket();
     void StartThread();
-    std::string ReadPacket(std::iostream &stream);
-    void SendPacket(std::ostream &stream, const std::string& packet);
+    fextl::string ReadPacket(std::iostream &stream);
+    void SendPacket(std::ostream &stream, const fextl::string& packet);
 
     void SendACK(std::ostream &stream, bool NACK);
 
@@ -48,7 +49,7 @@ private:
     void WaitForThreadWakeup();
 
     struct HandledPacketType {
-      std::string Response{};
+      fextl::string Response{};
       enum ResponseType {
         TYPE_NONE,
         TYPE_UNKNOWN,
@@ -61,32 +62,32 @@ private:
     };
 
     void SendPacketPair(const HandledPacketType& packetPair);
-    HandledPacketType ProcessPacket(const std::string &packet);
-    HandledPacketType handleQuery(const std::string &packet);
-    HandledPacketType handleXfer(const std::string &packet);
-    HandledPacketType handleMemory(const std::string &packet);
-    HandledPacketType handleV(const std::string& packet);
-    HandledPacketType handleThreadOp(const std::string &packet);
-    HandledPacketType handleBreakpoint(const std::string &packet);
+    HandledPacketType ProcessPacket(const fextl::string &packet);
+    HandledPacketType handleQuery(const fextl::string &packet);
+    HandledPacketType handleXfer(const fextl::string &packet);
+    HandledPacketType handleMemory(const fextl::string &packet);
+    HandledPacketType handleV(const fextl::string& packet);
+    HandledPacketType handleThreadOp(const fextl::string &packet);
+    HandledPacketType handleBreakpoint(const fextl::string &packet);
     HandledPacketType handleProgramOffsets();
 
     HandledPacketType ThreadAction(char action, uint32_t tid);
 
-    std::string readRegs();
-    HandledPacketType readReg(const std::string& packet);
+    fextl::string readRegs();
+    HandledPacketType readReg(const fextl::string& packet);
 
-    FEXCore::Context::Context *CTX;
-    std::unique_ptr<FEXCore::Threads::Thread> gdbServerThread;
-    std::unique_ptr<std::iostream> CommsStream;
+    FEXCore::Context::ContextImpl *CTX;
+    fextl::unique_ptr<FEXCore::Threads::Thread> gdbServerThread;
+    fextl::unique_ptr<std::iostream> CommsStream;
     std::mutex sendMutex;
     bool SettingNoAckMode{false};
     bool NoAckMode{false};
     bool NonStopMode{false};
-    std::string ThreadString{};
-    std::string OSDataString{};
+    fextl::string ThreadString{};
+    fextl::string OSDataString{};
     void buildLibraryMap();
     std::atomic<bool> LibraryMapChanged = true;
-    std::string LibraryMapString{};
+    fextl::string LibraryMapString{};
 
     // Used to keep track of which signals to pass to the guest
     std::array<bool, SignalDelegator::MAX_SIGNALS + 1> PassSignals{};

External/FEXCore/Source/Interface/Core/HostFeatures.cpp

@@ -9,7 +9,7 @@
 #endif
 
 #ifdef _M_X86_64
-#include <xbyak/xbyak_util.h>
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #endif
 
 namespace FEXCore {
@@ -17,12 +17,12 @@ namespace FEXCore {
 // Data Zero Prohibited flag
 // 0b0 = ZVA/GVA/GZVA permitted
 // 0b1 = ZVA/GVA/GZVA prohibited
-constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
+[[maybe_unused]] constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
 // Log2 of the blocksize in 32-bit words
-constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
+[[maybe_unused]] constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
 
 #ifdef _M_ARM_64
-static uint32_t GetDCZID() {
+[[maybe_unused]] static uint32_t GetDCZID() {
   uint64_t Result{};
   __asm("mrs %[Res], DCZID_EL0"
       : [Res] "=r" (Result));
@@ -54,7 +54,12 @@ HostFeatures::HostFeatures() {
 #ifdef VIXL_SIMULATOR
   auto Features = vixl::CPUFeatures::All();
 #else
+#ifndef _WIN32
   auto Features = vixl::CPUFeatures::InferFromOS();
+#else
+  // Need to use ID registers in WINE.
+  auto Features = vixl::CPUFeatures::InferFromIDRegisters();
+#endif
 #endif
   SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
   SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
@@ -65,6 +70,7 @@ HostFeatures::HostFeatures() {
   SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
   SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
   SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
+  SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
 
   Supports3DNow = true;
   SupportsSSE4A = true;
@@ -78,6 +84,7 @@ HostFeatures::HostFeatures() {
   SupportsSHA = true;
   SupportsBMI1 = true;
   SupportsBMI2 = true;
+  SupportsCLWB = true;
 
   if (!SupportsAtomics) {
     WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
@@ -127,15 +134,18 @@ HostFeatures::HostFeatures() {
   SupportsSHA = Features.has(Xbyak::util::Cpu::tSHA);
   SupportsBMI1 = Features.has(Xbyak::util::Cpu::tBMI1);
   SupportsBMI2 = Features.has(Xbyak::util::Cpu::tBMI2);
+  SupportsBMI2 = Features.has(Xbyak::util::Cpu::tCLWB);
+  SupportsPMULL_128Bit = Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
 
   // xbyak doesn't know how to check for CLZero
-  uint32_t eax, ebx, ecx, edx;
   // First ensure we support a new enough extended CPUID function range
-  __cpuid(0x8000'0000, eax, ebx, ecx, edx);
-  if (eax >= 0x8000'0008U) {
+
+  uint32_t data[4];
+  Xbyak::util::Cpu::getCpuid(0x8000'0000, data);
+  if (data[0] >= 0x8000'0008U) {
     // CLZero defined in 8000_00008_EBX[bit 0]
-    __cpuid(0x8000'0008, eax, ebx, ecx, edx);
-    SupportsCLZERO = ebx & 1;
+    Xbyak::util::Cpu::getCpuid(0x8000'0008, data);
+    SupportsCLZERO = data[1] & 1;
   }
 
   SupportsFlushInputsToZero = true;
@@ -156,5 +166,11 @@ HostFeatures::HostFeatures() {
     SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
   }
 #endif
+
+  // Disable AVX if the configuration explicitly has disabled it.
+  FEX_CONFIG_OPT(EnableAVX, ENABLEAVX);
+  if (!EnableAVX) {
+    SupportsAVX = false;
+  }
 }
 }

External/FEXCore/Source/Interface/Core/Interpreter/BranchOps.cpp

@@ -17,20 +17,8 @@ $end_info$
 #include <unistd.h>
 
 namespace FEXCore::CPU {
-[[noreturn]]
-static void SignalReturn(FEXCore::Core::InternalThreadState *Thread) {
-  Thread->CTX->SignalThread(Thread, FEXCore::Core::SignalEvent::Return);
-
-  LOGMAN_MSG_A_FMT("unreachable");
-  FEX_UNREACHABLE;
-}
-
 #define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 
-DEF_OP(SignalReturn) {
-  SignalReturn(Data->State);
-}
-
 DEF_OP(CallbackReturn) {
   Data->State->CurrentFrame->Pointers.Interpreter.CallbackReturn(Data->State, Data->StackEntry);
 }
@@ -91,7 +79,7 @@ DEF_OP(Syscall) {
     Args.Argument[j] = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[j]);
   }
 
-  uint64_t Res = FEXCore::Context::HandleSyscall(Data->State->CTX->SyscallHandler, Data->State->CurrentFrame, &Args);
+  uint64_t Res = FEXCore::Context::HandleSyscall(static_cast<Context::ContextImpl*>(Data->State->CTX)->SyscallHandler, Data->State->CurrentFrame, &Args);
   GD = Res;
 }
 
@@ -126,7 +114,7 @@ DEF_OP(InlineSyscall) {
 DEF_OP(Thunk) {
   auto Op = IROp->C<IR::IROp_Thunk>();
 
-  auto thunkFn = Data->State->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
+  auto thunkFn = static_cast<Context::ContextImpl*>(Data->State->CTX)->ThunkHandler->LookupThunk(Op->ThunkNameHash);
   thunkFn(*GetSrc<void**>(Data->SSAData, Op->ArgPtr));
 }
 
@@ -142,7 +130,7 @@ DEF_OP(ValidateCode) {
 }
 
 DEF_OP(ThreadRemoveCodeEntry) {
-  Data->State->CTX->ThreadRemoveCodeEntryFromJit(Data->State->CurrentFrame, Data->CurrentEntry);
+  static_cast<Context::ContextImpl*>(Data->State->CTX)->ThreadRemoveCodeEntryFromJit(Data->State->CurrentFrame, Data->CurrentEntry);
 }
 
 DEF_OP(CPUID) {
@@ -151,10 +139,19 @@ DEF_OP(CPUID) {
   const uint64_t Arg = *GetSrc<uint64_t*>(Data->SSAData, Op->Function);
   const uint64_t Leaf = *GetSrc<uint64_t*>(Data->SSAData, Op->Leaf);
 
-  auto Results = Data->State->CTX->CPUID.RunFunction(Arg, Leaf);
+  auto Results = Data->State->CTX->RunCPUIDFunction(Arg, Leaf);
   memcpy(DstPtr, &Results, sizeof(uint32_t) * 4);
 }
 
+DEF_OP(XGETBV) {
+  auto Op = IROp->C<IR::IROp_XGetBV>();
+  uint32_t *DstPtr = GetDest<uint32_t*>(Data->SSAData, Node);
+  const uint32_t Function = *GetSrc<uint32_t*>(Data->SSAData, Op->Function);
+
+  auto Results = Data->State->CTX->RunXCRFunction(Function);
+  memcpy(DstPtr, &Results, sizeof(uint32_t) * 2);
+}
+
 #undef DEF_OP
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/ConversionOps.cpp

@@ -62,6 +62,23 @@ DEF_OP(VCastFromGPR) {
   memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Src), Op->Header.ElementSize);
 }
 
+DEF_OP(VDupFromGPR) {
+  const auto Op = IROp->C<IR::IROp_VDupFromGPR>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = IROp->ElementSize;
+  const auto NumElements = OpSize / IROp->ElementSize;
+
+  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE]{};
+
+  const auto *Src = GetSrc<void*>(Data->SSAData, Op->Src);
+  for (size_t i = 0; i < NumElements; i++) {
+    memcpy(Tmp + (i * ElementSize), Src, ElementSize);
+  }
+
+  memcpy(GDP, Tmp, sizeof(Tmp));
+}
+
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
 
@@ -195,7 +212,7 @@ DEF_OP(Vector_FToF) {
       // Sometimes is used to convert from a 128bit vector register
       // in to a 64bit vector register with different sized elements
       // eg: %ssa5 i32v2 = Vector_FToF %ssa4 i128, #0x8
-      uint8_t Elements = (OpSize << 1) / Op->SrcElementSize;
+      uint8_t Elements = OpSize == 8 ? 2 : OpSize / Op->SrcElementSize;
       DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(float, double, Func, 0, 0)
       break;
     }

External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp

@@ -8,7 +8,7 @@ $end_info$
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 #include "Interface/Core/Interpreter/InterpreterDefines.h"
 
-#include "F80Ops.h"
+#include "Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h"
 
 #include <cstdint>
 
@@ -417,7 +417,6 @@ DEF_OP(F64SCALE) {
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
-
 #undef DEF_OP
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h

@@ -4,12 +4,9 @@
 
 #include <FEXCore/IR/IR.h>
 
+#include "Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h"
+
 namespace FEXCore::CPU {
-template<IR::IROps Op>
-struct OpHandlers {
-
-};
-
 template<>
 struct OpHandlers<IR::OP_F80CVTTO> {
   static X80SoftFloat handle4(float src) {
@@ -395,5 +392,4 @@ struct OpHandlers<IR::OP_F80LOADFCW> {
   }
 };
 
-
-}
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h

@@ -0,0 +1,75 @@
+#pragma once
+
+#include <cstdint>
+
+namespace FEXCore::IR {
+enum IROps : uint8_t;
+}
+
+namespace FEXCore::CPU {
+
+// Base template for fallback handling.
+//
+// Registering and hooking up fallback is currently like so:
+//
+// 1. Go to InterpreterFallbacks.cpp and create a template specialization of
+//    the GetFallbackInfo member function.
+//
+//    This member function should reasonably define what the fallback you're
+//    going to create will take as parameters and return as a result. For example:
+//
+//    template<>
+//    FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(double), Core::FallbackHandlerIndex Index) {
+//      return {FABI_F80_F64, (void*)fn, Index};
+//    }
+//
+//    Defines info about a fallback that takes a double as an argument and
+//    returns a X80SoftFloat instance.
+//
+//    You will also want to define a new FallbackHandlerIndex enum member and use it
+//    to set up the new info handler into the Info array in FillFallbackIndexPointers.
+//
+// 1.1. (potentially optional). Define a new ABI element in the FallbackAPI enum.
+//      This ABI enum value will be used to tell the JITs how to handle the fallback
+//      properly. These enum values specify the return type followed by its argument types.
+//
+//      So, FABI_I64_F80_F80, for example indicates that the function will behave like a
+//      function as if were defined as:
+//
+//      uint64_t fn(X80SoftFloat, X80SoftFloat)
+//
+// 1.2. (potentially optional). If you needed to define a new enum ABI type like in 1.1, then
+//      you need to add the handling for it in the JITs, which can be found in the respective
+//      JIT's JIT.cpp file in a function called Op_Unhandled
+//
+//      You need to add a new case to the ABI switch statement using the new ABI type
+//      and do the necessary moving of data from register-allocated JIT parameters
+//      into that platform's registers that respects the calling convention. After this is
+//      done, most of the necessary background boilerplate is finished.
+//
+// 2. Now, make a specialization of this class with a member function named 'handle()'
+//    that takes the same parameters as the ones described in the fallback info function
+//    specialization.
+//
+//    For example, if you have the fallback info from the example in step 1, it would be:
+//
+//    template <>
+//    struct OpHandlers<IR::CoolNewIROpcode> {
+//      static X80SoftFloat handle(double src) {
+//        return ...;
+//      }
+//    };
+//
+// 3. Fill out the behavior of the OpHandler specialization to perform what you would like
+//    the fallback to do.
+//
+// 4. Add an implementation of the IR op to the Interpreter that passes through to the
+//    OpHandler implementation.
+//
+// 5. Done.
+//
+template <IR::IROps Op>
+struct OpHandlers {
+};
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp

@@ -1,6 +1,8 @@
-#include "FEXCore/Core/CoreState.h"
+#include <FEXCore/Core/CoreState.h>
+
 #include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/F80Ops.h"
+#include "Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h"
+#include "Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h"
 
 #include <cstddef>
 #include <cstdint>
@@ -87,6 +89,16 @@ FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat, X80SoftFloat), FEXC
   return {FABI_F80_F80_F80, (void*)fn, HandlerIndex};
 }
 
+template<>
+FallbackInfo GetFallbackInfo(uint32_t(*fn)(uint64_t, uint64_t, __uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_I32_I64_I64_I128_I128_I16, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(uint32_t(*fn)(__uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_I32_I128_I128_I16, (void*)fn, HandlerIndex};
+}
+
 void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) {
   Info[Core::OPINDEX_F80LOADFCW] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle, Core::OPINDEX_F80LOADFCW).fn);
   Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4).fn);
@@ -144,9 +156,12 @@ void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) {
   Info[Core::OPINDEX_F64FPREM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM1>::handle, Core::OPINDEX_F64FPREM1).fn);
   Info[Core::OPINDEX_F64SCALE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64SCALE>::handle, Core::OPINDEX_F64SCALE).fn);
 
+  // SSE4.2 string instructions
+  Info[Core::OPINDEX_VPCMPESTRX] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX).fn);
+  Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX).fn);
 }
 
-bool InterpreterOps::GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info) {
+bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info) {
   uint8_t OpSize = IROp->Size;
   switch(IROp->Op) {
     case IR::OP_F80LOADFCW: {
@@ -302,6 +317,14 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Inf
     COMMON_F64_OP(FPREM)
     COMMON_F64_OP(SCALE)
 
+    // SSE4.2 Fallbacks
+    case IR::OP_VPCMPESTRX:
+      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX);
+      return true;
+    case IR::OP_VPCMPISTRX:
+      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX);
+      return true;
+
     default:
       break;
   }

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h

@@ -0,0 +1,408 @@
+#pragma once
+
+#include <algorithm>
+#include <cstddef>
+#include <cstdint>
+#include <cstdlib>
+#include <cstring>
+
+#include <FEXCore/IR/IR.h>
+
+#include "Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h"
+
+namespace FEXCore::CPU {
+
+template<>
+struct OpHandlers<IR::OP_VPCMPESTRX> {
+  enum class AggregationOp {
+    EqualAny     = 0b00,
+    Ranges       = 0b01,
+    EqualEach    = 0b10,
+    EqualOrdered = 0b11,
+  };
+
+  enum class SourceData {
+    U8,
+    U16,
+    S8,
+    S16,
+  };
+
+  enum class Polarity {
+    Positive,
+    Negative,
+    PositiveMasked,
+    NegativeMasked,
+  };
+
+  static uint32_t handle(uint64_t RAX, uint64_t RDX, __uint128_t lhs, __uint128_t rhs, uint16_t control) {
+    // Subtract by 1 in order to make validity limits 0-based
+    const auto valid_lhs = GetExplicitLength(RAX, control) - 1;
+    const auto valid_rhs = GetExplicitLength(RDX, control) - 1;
+
+    return MainBody(lhs, valid_lhs, rhs, valid_rhs, control);
+  }
+
+  // Main PCMPXSTRX algorithm body. Allows for reuse with both implicit and explicit length variants.
+  static uint32_t MainBody(const __uint128_t& lhs, int valid_lhs, const __uint128_t& rhs, int valid_rhs, uint16_t control) {
+    const uint32_t aggregation = PerformAggregation(lhs, valid_lhs, rhs, valid_rhs, control);
+    const uint32_t upper_limit = (16U >> (control & 1)) - 1;
+
+    // Bits are arranged as:
+    // Bit #:   3    2    1    0
+    //         [OF | CF | SF | ZF]
+    uint32_t flags = 0;
+    flags |= (valid_rhs < upper_limit) ? 0b01 : 0b00;
+    flags |= (valid_lhs < upper_limit) ? 0b10 : 0b00;
+
+    const uint32_t result = HandlePolarity(aggregation, control, upper_limit, valid_rhs);
+    if (result != 0) {
+      flags |= 0b0100;
+    }
+    if ((result & 1) != 0) {
+      flags |= 0b1000;
+    }
+
+    // We tack the flags on top of the result to avoid needing to handle
+    // multiple return values in the JITs.
+    return result | (flags << 16);
+  }
+
+  static int32_t GetExplicitLength(uint64_t reg, uint16_t control) {
+    // Bit 8 controls whether or not the reg value is 64-bit or 32-bit.
+    int64_t value = 0;
+    if (((control >> 8) & 1) != 0) {
+      value = static_cast<int64_t>(reg);
+    } else {
+      // We need a sign extend in this case.
+      value = static_cast<int32_t>(reg);
+    }
+
+    // If control[0] is set, then we're dealing with words instead of bytes
+    const int64_t limit = (control & 1) != 0 ? 8 : 16;
+
+    // Length needs to saturate to 16 (if bytes) or 8 (if words)
+    // when the length value is greater than 16 (if bytes)/8 (if words)
+    // or if the length value is less than -16 (if bytes)/-8 (if words).
+    if (value < -limit || value > limit) {
+      return limit;
+    }
+
+    return std::abs(static_cast<int>(value));
+  }
+
+  static int32_t GetElement(const __uint128_t& vec, int32_t index, uint16_t control) {
+    const auto* vec_ptr = reinterpret_cast<const uint8_t*>(&vec);
+
+    // Control bits [1:0] define the data type being dealt with.
+    switch (static_cast<SourceData>(control & 0b11)) {
+    case SourceData::U8:
+      return static_cast<int32_t>(vec_ptr[index]);
+    case SourceData::U16: {
+      uint16_t value{};
+      std::memcpy(&value, vec_ptr + (sizeof(uint16_t) * static_cast<size_t>(index)), sizeof(value));
+      return value;
+    }
+    case SourceData::S8:
+      return static_cast<int8_t>(vec_ptr[index]);
+    case SourceData::S16:
+    default: {
+      int16_t value{};
+      std::memcpy(&value, vec_ptr + (sizeof(int16_t) * static_cast<size_t>(index)), sizeof(value));
+      return value;
+    }
+    }
+  }
+
+  static uint32_t PerformAggregation(const __uint128_t& lhs, int32_t valid_lhs,
+                                     const __uint128_t& rhs, int32_t valid_rhs,
+                                     uint16_t control) {
+    switch (static_cast<AggregationOp>((control >> 2) & 0b11)) {
+    case AggregationOp::EqualAny:
+      return HandleEqualAny(lhs, valid_lhs, rhs, valid_rhs, control);
+    case AggregationOp::Ranges:
+      return HandleRanges(lhs, valid_lhs, rhs, valid_rhs, control);
+    case AggregationOp::EqualEach:
+      return HandleEqualEach(lhs, valid_lhs, rhs, valid_rhs, control);
+    case AggregationOp::EqualOrdered:
+    default:
+      return HandleEqualOrdered(lhs, valid_lhs, rhs, valid_rhs, control);
+    }
+  }
+
+  static uint32_t HandlePolarity(uint32_t value, uint16_t control, int upper_limit, int valid_rhs) {
+    switch (static_cast<Polarity>((control >> 4) & 0b11)) {
+      case Polarity::Negative:
+        return value ^ ((2U << upper_limit) - 1);
+      case Polarity::NegativeMasked:
+        return value ^ ((1U << (valid_rhs + 1)) - 1);
+      case Polarity::Positive:
+      case Polarity::PositiveMasked:
+      default:
+        // Both positive masking and positive polarity are documented
+        // as both being equivalent to "IntRes2 = IntRes1", where IntRes1
+        // is our 'value' parameter, so we don't need to do anything in
+        // these cases except return the same value.
+        return value;
+    }
+  }
+
+  // Finds characters from an overall character set.
+  //
+  // Scans through RHS trying to find any characters contained in LHS.
+  // Think of this as a sort of vectorized version of strspn (kind of).
+  //
+  // e.g. Assume operating on two character vectors as unsigned words
+  //
+  //         0  1  2  3  4  5  6  7
+  // LHS -> [a, b, c, d, e, f, g, n]
+  // RHS -> [z, k, v, c, d, o, p, n]
+  //
+  // With both explicit lengths for each string being 8 (the max length for words),
+  // this would result in an intermediate result like:
+  //
+  //            0b1001'1000
+  //              │  │ │
+  // 'n' match ───┘  │ │
+  //                 │ │
+  // 'd' match ──────┘ │
+  //                   │
+  // 'c' match ────────┘
+  //
+  static uint32_t HandleEqualAny(const __uint128_t& lhs, int32_t valid_lhs,
+                                 const __uint128_t& rhs, int32_t valid_rhs,
+                                 uint16_t control) {
+    uint32_t result = 0;
+
+    for (int j = valid_rhs; j >= 0; j--) {
+      result <<= 1;
+
+      const int rhs_value = GetElement(rhs, j, control);
+      for (int i = valid_lhs; i >= 0; i--) {
+        const int lhs_value = GetElement(lhs, i, control);
+        result |= static_cast<uint32_t>(rhs_value == lhs_value);
+      }
+    }
+
+    return result;
+  }
+
+  // Determines if a character falls within a limited range
+  //
+  // Scans through rhs using a range denoted by two elements
+  // in lhs and determines if the respective character in rhs
+  // falls within its range.
+  //
+  // i.e.
+  //      lhs_upper_bound >= rhs_value && lhs_lower_bound <= rhs_value
+  //
+  // e.g. Assume operating on two character vectors as unsigned words
+  //
+  //         0  1  2  3  4  5  6  7
+  // LHS -> [a, z, A, Z, 0, 0, 0, 0]
+  // RHS -> [z, k, ., C, M, ;, \, ']
+  //
+  // With LHS's length being 4 and RHS's lenth being 8,
+  // this would result in an intermediate result like:
+  //
+  //                          0b0001'1011
+  //                               │ │ ││
+  // 'z' >= 'M' && 'a' <= 'M' ─────┘ │ ││
+  //                                 │ ││
+  // 'z' >= 'C' && 'a' <= 'C' ───────┘ ││
+  //                                   ││
+  // 'Z' >= 'k' && 'A' <= 'k' ─────────┘│
+  //                                    │
+  // 'Z' >= 'z' && 'A' <= 'z' ──────────┘
+  //
+  static uint32_t HandleRanges(const __uint128_t& lhs, int32_t valid_lhs,
+                               const __uint128_t& rhs, int32_t valid_rhs,
+                               uint16_t control) {
+    uint32_t result = 0;
+
+    for (int j = valid_rhs; j >= 0; j--) {
+      result <<= 1;
+
+      const int element = GetElement(rhs, j, control);
+      for (int i = (valid_lhs - 1) | 1; i >= 0; i -= 2) {
+        const int upper_bound = GetElement(lhs, i - 0, control);
+        const int lower_bound = GetElement(lhs, i - 1, control);
+
+        const bool ge = upper_bound >= element;
+        const bool le = lower_bound <= element;
+
+        result |= static_cast<uint32_t>(ge && le);
+      }
+    }
+
+    return result;
+  }
+
+  // Determines if each character is equal to one another (string compare)
+  //
+  // Essentially the PCMPXSTRX variant of memcmp/strcmp. Sets the bit of the
+  // resulting mask if both elements are equal to one another. Otherwise
+  // sets it to false.
+  //
+  // e.g. Assume operating on two character vectors as unsigned words
+  //
+  //         0  1  2  3  4  5  6  7
+  // LHS -> [a, b, c, d, e, f, g, n]
+  // RHS -> [a, b, c, d, e, f, e, x]
+  //
+  // With both explicit lengths for each string being 8 (the max length for words),
+  // this would result in an intermediate result like:
+  //
+  //            0b0011'1111
+  //                ││ ││││
+  // 'f' == 'f' ────┘│ ││││
+  //                 │ ││││
+  // 'e' == 'e' ─────┘ ││││
+  //                   ││││
+  // 'd' == 'd' ───────┘│││
+  //                    │││
+  // 'c' == 'c' ────────┘││
+  //                     ││
+  // 'b' == 'b' ─────────┘│
+  //                      │
+  // 'a' == 'a' ──────────┘
+  //
+  static uint32_t HandleEqualEach(const __uint128_t& lhs, int32_t valid_lhs,
+                                  const __uint128_t& rhs, int32_t valid_rhs,
+                                  uint16_t control) {
+    const auto upper_limit = (16 >> (control & 1)) - 1;
+    const auto max_valid = std::max(valid_lhs, valid_rhs);
+    const auto min_valid = std::min(valid_lhs, valid_rhs);
+
+    // All values past the end of string must be forced to true.
+    // (See 4.1.6 Valid/Invalid Override of Comparisons in the Intel Software Development Manual)
+    // So we can calculate this part of the mask ahead of time and set all those to-be bits to true
+    // and then progressively shift them into place over the course of execution.
+    uint32_t result = (1U << (upper_limit - max_valid)) - 1;
+    result <<= (max_valid - min_valid);
+
+    for (int i = min_valid; i >= 0; i--) {
+      const int lhs_element = GetElement(lhs, i, control);
+      const int rhs_element = GetElement(rhs, i, control);
+
+      result <<= 1;
+      result |= static_cast<uint32_t>(lhs_element == rhs_element);
+    }
+
+    return result;
+  }
+
+  // Determines if a substring exists within an overall string
+  //
+  // Somewhat equivalent to the behavior of strstr.
+  //
+  // Sets the corresponding index in the result where a substring is found.
+  //
+  // e.g. Assume operating on two character vectors as unsigned words
+  //
+  //         0  1  2  3  4  5  6  7
+  // LHS -> [b, a, x, z, y, v, o, m]
+  // RHS -> [b, a, d, b, a, n, k, s]
+  //
+  // With the length of LHS being 2 and the length of RHS being 8, we have a composition like:
+  //
+  //      Substring to look for
+  //       ┌──┴──┐
+  // LHS -> [b, a, x, z, y, v, o, m]
+  // RHS -> [b, a, d, b, a, n, k, s]
+  //       └───────────┬────────────┘
+  //         Entire string to search
+  //
+  // And we end up with a result like:
+  //
+  //            0b0000'1001
+  //                   │  │
+  // At index 3 ───────┘  │
+  //                      │
+  // At index 0 ──────────┘
+  //
+  static uint32_t HandleEqualOrdered(const __uint128_t& lhs, int32_t valid_lhs,
+                                     const __uint128_t& rhs, int32_t valid_rhs,
+                                     uint16_t control) {
+    const auto upper_limit = (16 >> (control & 1)) - 1;
+
+    // Edge case!
+    // If we have *no* valid characters in our inner string, then
+    // we need to return the intermediate result as
+    // 0xFF (if operating on words) or 0xFFFF (if operating on bytes)
+    if (valid_lhs == -1) {
+      return (2U << upper_limit) - 1;
+    }
+
+    uint32_t result = 0;
+    const int initial = valid_rhs == upper_limit ? valid_rhs
+                                                 : valid_rhs - valid_lhs;
+    for (int j = initial; j >= 0; j--) {
+      result <<= 1;
+
+      uint32_t value = 1;
+      const int start = std::min(valid_rhs - j, valid_lhs);
+      for (int i = start; i >= 0; i--) {
+        const int lhs_value = GetElement(lhs, i + 0, control);
+        const int rhs_value = GetElement(rhs, i + j, control);
+
+        value &= static_cast<uint32_t>(lhs_value == rhs_value);
+      }
+
+      result |= value;
+    }
+
+    return result;
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_VPCMPISTRX> {
+  // Essentially the same in terms of behavior with VPCMPESTRX instructions,
+  // with the only difference being that the length of the string is encoded
+  // as part of the data vectors passed in.
+  //
+  // i.e. Length is determined by the presence of a NUL (all-zero) character
+  //      within the data.
+  //
+  //      If no NUL character exists, then the length of the strings are assumed
+  //      to be the max length possible for the given character size specified
+  //      in the control flags (16 characters for 8-bit, and 8 characters for 16-bit).
+  //
+  static uint32_t handle(__uint128_t lhs, __uint128_t rhs, uint16_t control) {
+    // Subtract by 1 in order to make validity limits 0-based
+    const auto valid_lhs = GetImplicitLength(lhs, control) - 1;
+    const auto valid_rhs = GetImplicitLength(rhs, control) - 1;
+
+    return OpHandlers<IR::OP_VPCMPESTRX>::MainBody(lhs, valid_lhs, rhs, valid_rhs, control);
+  }
+
+  static int32_t GetImplicitLength(const __uint128_t& data, uint16_t control) {
+    const auto* data_u8 = reinterpret_cast<const uint8_t*>(&data);
+    const auto is_using_words = (control & 1) != 0;
+
+    int32_t length = 0;
+
+    if (is_using_words) {
+      const auto get_word = [data_u8](int32_t index) {
+        const auto* src = data_u8 + (index * sizeof(uint16_t));
+
+        uint16_t element{};
+        std::memcpy(&element, src, sizeof(uint16_t));
+        return element;
+      };
+
+      while (length < 8 && get_word(length) != 0) {
+        length++;
+      }
+    } else {
+      while (length < 16 && data_u8[length] != 0) {
+        length++;
+      }
+    }
+
+    return length;
+  }
+};
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h

@@ -6,27 +6,24 @@
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/vector.h>
 
 namespace FEXCore::CPU {
 class Dispatcher;
 class X86DispatchGenerator;
 class Arm64DispatchGenerator;
 
-#define DESTMAP_AS_MAP 0
-#if DESTMAP_AS_MAP
-using DestMapType = std::unordered_map<uint32_t, uint32_t>;
-#else
-using DestMapType = std::vector<uint32_t>;
-#endif
+using DestMapType = fextl::vector<uint32_t>;
 
 class InterpreterCore final : public CPUBackend {
 public:
   explicit InterpreterCore(Dispatcher *Dispatch,
                            FEXCore::Core::InternalThreadState *Thread);
 
-  [[nodiscard]] std::string GetName() override { return "Interpreter"; }
+  [[nodiscard]] fextl::string GetName() override { return "Interpreter"; }
 
-  [[nodiscard]] void *CompileCode(uint64_t Entry,
+  [[nodiscard]] CPUBackend::CompiledCode CompileCode(uint64_t Entry,
                                   FEXCore::IR::IRListView const *IR,
                                   FEXCore::Core::DebugData *DebugData,
                                   FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) override;
@@ -35,8 +32,8 @@ public:
 
   [[nodiscard]] bool NeedsOpDispatch() override { return true; }
 
-  static void InitializeSignalHandlers(FEXCore::Context::Context *CTX);
-  
+  static void InitializeSignalHandlers(FEXCore::Context::ContextImpl *CTX);
+
   void ClearCache() override;
 
 private:

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -1,17 +1,14 @@
 #include "Interface/Context/Context.h"
 
-#include "Interface/Core/ArchHelpers/Arm64.h"
-#include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/Interpreter/InterpreterClass.h"
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
+#include <FEXCore/fextl/memory.h>
 
-#include <memory>
 #include <signal.h>
 #include <stdint.h>
 #include <utility>
@@ -49,27 +46,21 @@ InterpreterCore::InterpreterCore(Dispatcher *Dispatcher, FEXCore::Core::Internal
   ClearCache();
 }
 
-void InterpreterCore::InitializeSignalHandlers(FEXCore::Context::Context *CTX) {
-
-#ifdef _M_ARM_64
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(true, Signal, info, ucontext);
-  }, true);
-#endif
-}
-
-void *InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) {
+CPUBackend::CompiledCode InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) {
 
   const auto IRSize = AlignUp(IR->GetInlineSize(), 16);
   const auto MaxSize = IRSize + Dispatcher::MaxInterpreterTrampolineSize + GDBEnabled * Dispatcher::MaxGDBPauseCheckSize;
 
   if ((BufferUsed + MaxSize) > CurrentCodeBuffer->Size) {
-    ThreadState->CTX->ClearCodeCache(ThreadState);
+    static_cast<Context::ContextImpl*>(ThreadState->CTX)->ClearCodeCache(ThreadState);
   }
 
-  const auto BufferStart = CurrentCodeBuffer->Ptr + BufferUsed;
+  CPUBackend::CompiledCode CodeData{};
 
-  auto DestBuffer = BufferStart;
+  const auto BufferStartOffset = BufferUsed;
+  CodeData.BlockBegin = CodeData.BlockEntry = CurrentCodeBuffer->Ptr + BufferStartOffset;
+
+  auto DestBuffer = CodeData.BlockBegin;
 
   if (GDBEnabled) {
     const auto GDBSize = Dispatch->GenerateGDBPauseCheck(DestBuffer, Entry);
@@ -86,7 +77,9 @@ void *InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR:
   DestBuffer += IRSize;
   BufferUsed += IRSize;
 
-  return BufferStart;
+  CodeData.Size = BufferUsed - BufferStartOffset;
+
+  return CodeData;
 }
 
 void InterpreterCore::ClearCache() {
@@ -95,12 +88,8 @@ void InterpreterCore::ClearCache() {
   BufferUsed = 0;
 }
 
-std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  return std::make_unique<InterpreterCore>(ctx->Dispatcher.get(), Thread);
-}
-
-void InitializeInterpreterSignalHandlers(FEXCore::Context::Context *CTX) {
-  InterpreterCore::InitializeSignalHandlers(CTX);
+fextl::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  return fextl::make_unique<InterpreterCore>(ctx->Dispatcher.get(), Thread);
 }
 
 CPUBackendFeatures GetInterpreterBackendFeatures() {

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.h

@@ -1,9 +1,10 @@
 #pragma once
 
-#include <memory>
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/fextl/memory.h>
 
 namespace FEXCore::Context {
-struct Context;
+class ContextImpl;
 }
 
 namespace FEXCore::Core {
@@ -14,9 +15,9 @@ namespace FEXCore::CPU {
 class CPUBackend;
 struct DispatcherConfig;
 
-[[nodiscard]] std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx,
+[[nodiscard]] fextl::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::ContextImpl *ctx,
                                                                 FEXCore::Core::InternalThreadState *Thread);
-void InitializeInterpreterSignalHandlers(FEXCore::Context::Context *CTX);
+void InitializeInterpreterSignalHandlers(FEXCore::Context::ContextImpl *CTX);
 CPUBackendFeatures GetInterpreterBackendFeatures();
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp

@@ -2,11 +2,6 @@
 #include "Interface/Core/CPUID.h"
 #include "InterpreterDefines.h"
 #include "InterpreterOps.h"
-#include "F80Ops.h"
-
-#ifdef _M_ARM_64
-#include "Interface/Core/ArchHelpers/Arm64.h"
-#endif
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/CoreState.h>
@@ -113,7 +108,6 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(ATOMICFETCHNEG,         AtomicFetchNeg);
 
   // Branch ops
-  REGISTER_OP(SIGNALRETURN,           SignalReturn);
   REGISTER_OP(CALLBACKRETURN,         CallbackReturn);
   REGISTER_OP(EXITFUNCTION,           ExitFunction);
   REGISTER_OP(JUMP,                   Jump);
@@ -124,10 +118,12 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(VALIDATECODE,           ValidateCode);
   REGISTER_OP(THREADREMOVECODEENTRY,        ThreadRemoveCodeEntry);
   REGISTER_OP(CPUID,                  CPUID);
+  REGISTER_OP(XGETBV,                 XGETBV);
 
   // Conversion ops
   REGISTER_OP(VINSGPR,                VInsGPR);
   REGISTER_OP(VCASTFROMGPR,           VCastFromGPR);
+  REGISTER_OP(VDUPFROMGPR,            VDupFromGPR);
   REGISTER_OP(FLOAT_FROMGPR_S,        Float_FromGPR_S);
   REGISTER_OP(FLOAT_FTOF,             Float_FToF);
   REGISTER_OP(VECTOR_STOF,            Vector_SToF);
@@ -154,9 +150,12 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(STOREMEM,               StoreMem);
   REGISTER_OP(LOADMEMTSO,             LoadMem);
   REGISTER_OP(STOREMEMTSO,            StoreMem);
-  REGISTER_OP(VLOADMEMELEMENT,        VLoadMemElement);
-  REGISTER_OP(VSTOREMEMELEMENT,       VStoreMemElement);
+  REGISTER_OP(VLOADVECTORMASKED,      VLoadVectorMasked);
+  REGISTER_OP(VSTOREVECTORMASKED,     VStoreVectorMasked);
+  REGISTER_OP(MEMSET,                 MemSet);
+  REGISTER_OP(MEMCPY,                 MemCpy);
   REGISTER_OP(CACHELINECLEAR,         CacheLineClear);
+  REGISTER_OP(CACHELINECLEAN,         CacheLineClean);
   REGISTER_OP(CACHELINEZERO,          CacheLineZero);
 
   // Misc ops
@@ -223,6 +222,8 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(VZIP2,                  VZip);
   REGISTER_OP(VUNZIP,                 VUnZip);
   REGISTER_OP(VUNZIP2,                VUnZip);
+  REGISTER_OP(VTRN,                   VTrn);
+  REGISTER_OP(VTRN2,                  VTrn);
   REGISTER_OP(VBSL,                   VBSL);
   REGISTER_OP(VCMPEQ,                 VCMPEQ);
   REGISTER_OP(VCMPEQZ,                VCMPEQZ);
@@ -245,8 +246,6 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(VINSELEMENT,            VInsElement);
   REGISTER_OP(VDUPELEMENT,            VDupElement);
   REGISTER_OP(VEXTR,                  VExtr);
-  REGISTER_OP(VSLI,                   VSLI);
-  REGISTER_OP(VSRI,                   VSRI);
   REGISTER_OP(VUSHRI,                 VUShrI);
   REGISTER_OP(VSSHRI,                 VSShrI);
   REGISTER_OP(VSHLI,                  VShlI);
@@ -269,6 +268,8 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(VUABDL,                 VUABDL);
   REGISTER_OP(VTBL1,                  VTBL1);
   REGISTER_OP(VREV64,                 VRev64);
+  REGISTER_OP(VPCMPESTRX,             VPCMPESTRX);
+  REGISTER_OP(VPCMPISTRX,             VPCMPISTRX);
 
   // Encryption ops
   REGISTER_OP(VAESIMC,                AESImc);
@@ -333,7 +334,6 @@ void InterpreterOps::InterpretIR(FEXCore::Core::CpuStateFrame *Frame, FEXCore::I
 
   const uintptr_t ListSize = CurrentIR->GetSSACount();
 
-  static_assert(sizeof(FEXCore::IR::IROp_Header) == 4);
   static_assert(sizeof(FEXCore::IR::OrderedNode) == 16);
 
   auto BlockEnd = CurrentIR->GetBlocks().end();

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -36,6 +36,8 @@ namespace FEXCore::CPU {
     FABI_I64_F80_F80,
     FABI_F80_F80,
     FABI_F80_F80_F80,
+    FABI_I32_I64_I64_I128_I128_I16,
+    FABI_I32_I128_I128_I16,
   };
 
   struct FallbackInfo {
@@ -49,7 +51,7 @@ namespace FEXCore::CPU {
     public:
       static void InterpretIR(FEXCore::Core::CpuStateFrame *Frame, FEXCore::IR::IRListView const *IR);
       static void FillFallbackIndexPointers(uint64_t *Info);
-      static bool GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info);
+      static bool GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info);
 
       struct IROpData {
         FEXCore::Core::InternalThreadState *State{};
@@ -142,7 +144,6 @@ namespace FEXCore::CPU {
   DEF_OP(AtomicFetchNeg);
 
   ///< Branch ops
-  DEF_OP(SignalReturn);
   DEF_OP(CallbackReturn);
   DEF_OP(ExitFunction);
   DEF_OP(Jump);
@@ -153,10 +154,12 @@ namespace FEXCore::CPU {
   DEF_OP(ValidateCode);
   DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
+  DEF_OP(XGETBV);
 
   ///< Conversion ops
   DEF_OP(VInsGPR);
   DEF_OP(VCastFromGPR);
+  DEF_OP(VDupFromGPR);
   DEF_OP(Float_FromGPR_S);
   DEF_OP(Float_FToF);
   DEF_OP(Vector_SToF);
@@ -181,9 +184,12 @@ namespace FEXCore::CPU {
   DEF_OP(StoreFlag);
   DEF_OP(LoadMem);
   DEF_OP(StoreMem);
-  DEF_OP(VLoadMemElement);
-  DEF_OP(VStoreMemElement);
+  DEF_OP(VLoadVectorMasked);
+  DEF_OP(VStoreVectorMasked);
+  DEF_OP(MemSet);
+  DEF_OP(MemCpy);
   DEF_OP(CacheLineClear);
+  DEF_OP(CacheLineClean);
   DEF_OP(CacheLineZero);
 
   ///< Misc ops
@@ -243,6 +249,7 @@ namespace FEXCore::CPU {
   DEF_OP(VSMax);
   DEF_OP(VZip);
   DEF_OP(VUnZip);
+  DEF_OP(VTrn);
   DEF_OP(VBSL);
   DEF_OP(VCMPEQ);
   DEF_OP(VCMPEQZ);
@@ -265,8 +272,6 @@ namespace FEXCore::CPU {
   DEF_OP(VInsElement);
   DEF_OP(VDupElement);
   DEF_OP(VExtr);
-  DEF_OP(VSLI);
-  DEF_OP(VSRI);
   DEF_OP(VUShrI);
   DEF_OP(VSShrI);
   DEF_OP(VShlI);
@@ -289,6 +294,8 @@ namespace FEXCore::CPU {
   DEF_OP(VUABDL);
   DEF_OP(VTBL1);
   DEF_OP(VRev64);
+  DEF_OP(VPCMPESTRX);
+  DEF_OP(VPCMPISTRX);
 
   ///< Encryption ops
   DEF_OP(AESImc);

External/FEXCore/Source/Interface/Core/Interpreter/MemoryOps.cpp

@@ -23,6 +23,22 @@ static inline void CacheLineFlush(char *Addr) {
 #endif
 }
 
+static inline void CacheLineClean(char *Addr) {
+#ifdef _M_X86_64
+  __asm volatile (
+    "clwb (%[Addr]);"
+    :: [Addr] "r" (Addr)
+    : "memory");
+#elif _M_ARM_64
+  __asm volatile (
+    "dc cvac, %[Addr]"
+    :: [Addr] "r" (Addr)
+    : "memory");
+#else
+    LOGMAN_THROW_A_FMT("Unsupported architecture with cacheline clean");
+#endif
+}
+
 #define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(LoadContext) {
   const auto Op = IROp->C<IR::IROp_LoadContext>();
@@ -69,11 +85,47 @@ DEF_OP(StoreContext) {
 }
 
 DEF_OP(LoadRegister) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
+  const auto Op = IROp->C<IR::IROp_LoadRegister>();
+  const auto OpSize = IROp->Size;
+
+  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
+  const auto Src = ContextPtr + Op->Offset;
+
+  #define LOAD_CTX(x, y) \
+    case x: { \
+      y const *MemData = reinterpret_cast<y const*>(Src); \
+      GD = *MemData; \
+      break; \
+    }
+
+  switch (OpSize) {
+    LOAD_CTX(1, uint8_t)
+    LOAD_CTX(2, uint16_t)
+    LOAD_CTX(4, uint32_t)
+    LOAD_CTX(8, uint64_t)
+    case 16:
+    case 32: {
+      void const *MemData = reinterpret_cast<void const*>(Src);
+      memcpy(GDP, MemData, OpSize);
+      break;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
+      break;
+  }
+  #undef LOAD_CTX
 }
 
 DEF_OP(StoreRegister) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
+  const auto Op = IROp->C<IR::IROp_StoreRegister>();
+  const auto OpSize = IROp->Size;
+
+  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
+  const auto Dst = ContextPtr + Op->Offset;
+
+  void *MemData = reinterpret_cast<void*>(Dst);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Value);
+  memcpy(MemData, Src, OpSize);
 }
 
 DEF_OP(LoadContextIndexed) {
@@ -236,34 +288,364 @@ DEF_OP(StoreMem) {
   }
 }
 
-DEF_OP(VLoadMemElement) {
-  auto Op = IROp->C<IR::IROp_VLoadMemElement>();
-  void const *MemData = *GetSrc<void const**>(Data->SSAData, Op->Value);
+DEF_OP(VLoadVectorMasked) {
+  const auto Op = IROp->C<IR::IROp_VLoadVectorMasked>();
+  const auto OpSize = IROp->Size;
 
-  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Addr), 16);
-  memcpy(reinterpret_cast<void*>(reinterpret_cast<uintptr_t>(GDP) + (Op->Header.ElementSize * Op->Index)),
-    MemData, Op->Header.ElementSize);
+  const auto ElementSize = IROp->ElementSize;
+  const auto NumElements = OpSize / ElementSize;
+
+  const auto *MemData = *GetSrc<uint8_t const**>(Data->SSAData, Op->Addr);
+  const auto *Mask = GetSrc<uint8_t const*>(Data->SSAData, Op->Mask);
+
+  const auto SetElements = [NumElements]<typename T>(void* Dst, const T* MaskValues, const T* MemoryData) {
+    const auto SignBit = 1ULL << ((sizeof(T) * 8) - 1);
+    for (size_t i = 0; i < NumElements; i++) {
+      if ((MaskValues[i] & SignBit) != 0) {
+        std::memcpy(static_cast<uint8_t*>(Dst) + (i * sizeof(T)), MemoryData + i, sizeof(T));
+      }
+    }
+  };
+
+  if (!Op->Offset.IsInvalid()) {
+    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
+
+    switch(Op->OffsetType.Val) {
+      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
+      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
+      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
+    }
+  }
+
+  memset(GDP, 0, Core::CPUState::XMM_AVX_REG_SIZE);
+  switch (ElementSize) {
+    case 1: {
+      SetElements(GDP, Mask, MemData);
+      return;
+    }
+    case 2: {
+      SetElements(GDP,
+                  reinterpret_cast<const uint16_t*>(Mask),
+                  reinterpret_cast<const uint16_t*>(MemData));
+      return;
+    }
+    case 4: {
+      SetElements(GDP,
+                  reinterpret_cast<const uint32_t*>(Mask),
+                  reinterpret_cast<const uint32_t*>(MemData));
+      return;
+    }
+    case 8: {
+      SetElements(GDP,
+                  reinterpret_cast<const uint64_t*>(Mask),
+                  reinterpret_cast<const uint64_t*>(MemData));
+      return;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VLoadVectorMasked element size: {}", ElementSize);
+      return;
+  }
 }
 
-DEF_OP(VStoreMemElement) {
-  #define STORE_DATA(x, y) \
-    case x: { \
-      y *MemData = *GetSrc<y**>(Data->SSAData, Op->Value); \
-      memcpy(MemData, &GetSrc<y*>(Data->SSAData, Op->Addr)[Op->Index], sizeof(y)); \
-      break; \
+DEF_OP(VStoreVectorMasked) {
+  const auto Op = IROp->C<IR::IROp_VStoreVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = IROp->ElementSize;
+  const auto NumElements = OpSize / ElementSize;
+
+  auto *Dst = *GetSrc<uint8_t**>(Data->SSAData, Op->Addr);
+  const auto *RegData = GetSrc<uint8_t const*>(Data->SSAData, Op->Data);
+  const auto *Mask = GetSrc<uint8_t const*>(Data->SSAData, Op->Mask);
+
+  const auto SetElements = [NumElements]<typename T>(void* Dst, const T* MaskValues, const T* DataVals) {
+    const auto SignBit = 1ULL << ((sizeof(T) * 8) - 1);
+    for (size_t i = 0; i < NumElements; i++) {
+      if ((MaskValues[i] & SignBit) != 0) {
+        std::memcpy(static_cast<uint8_t*>(Dst) + (i * sizeof(T)), DataVals + i, sizeof(T));
+      }
     }
+  };
 
-  auto Op = IROp->C<IR::IROp_VStoreMemElement>();
-  uint8_t OpSize = IROp->Size;
+  if (!Op->Offset.IsInvalid()) {
+    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
 
-  switch (OpSize) {
-    STORE_DATA(1, uint8_t)
-    STORE_DATA(2, uint16_t)
-    STORE_DATA(4, uint32_t)
-    STORE_DATA(8, uint64_t)
-    default: LOGMAN_MSG_A_FMT("Unhandled StoreMem size"); break;
+    switch(Op->OffsetType.Val) {
+      case IR::MEM_OFFSET_SXTX.Val: Dst +=  Offset; break;
+      case IR::MEM_OFFSET_UXTW.Val: Dst += (uint32_t)Offset; break;
+      case IR::MEM_OFFSET_SXTW.Val: Dst += (int32_t)Offset; break;
+    }
+  }
+
+  switch (ElementSize) {
+    case 1: {
+      SetElements(Dst, Mask, RegData);
+      return;
+    }
+    case 2: {
+      SetElements(Dst,
+                  reinterpret_cast<const uint16_t*>(Mask),
+                  reinterpret_cast<const uint16_t*>(RegData));
+      return;
+    }
+    case 4: {
+      SetElements(Dst,
+                  reinterpret_cast<const uint32_t*>(Mask),
+                  reinterpret_cast<const uint32_t*>(RegData));
+      return;
+    }
+    case 8: {
+      SetElements(Dst,
+                  reinterpret_cast<const uint64_t*>(Mask),
+                  reinterpret_cast<const uint64_t*>(RegData));
+      return;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VStoreVectorMasked element size: {}", ElementSize);
+      return;
+  }
+}
+
+DEF_OP(MemSet) {
+  const auto Op = IROp->C<IR::IROp_MemSet>();
+  const int32_t Size = Op->Size;
+
+  char *MemData = *GetSrc<char **>(Data->SSAData, Op->Addr);
+  uint64_t MemPrefix{};
+  if (!Op->Prefix.IsInvalid()) {
+    MemPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->Prefix);
+  }
+
+  const auto Value = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
+  const auto Length = *GetSrc<uint64_t*>(Data->SSAData, Op->Length);
+  const auto Direction = *GetSrc<uint8_t*>(Data->SSAData, Op->Direction);
+
+  auto MemSetElements = [](auto* Memory, uint64_t Value, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      Memory[i] = Value;
+    }
+  };
+
+  auto MemSetElementsInverse = [](auto* Memory, uint64_t Value, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      Memory[-i] = Value;
+    }
+  };
+
+  if (Direction == 0) { // Forward
+    if (Op->IsAtomic) {
+      switch (Size) {
+        case 1:
+          MemSetElements(reinterpret_cast<std::atomic<uint8_t>*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 2:
+          MemSetElements(reinterpret_cast<std::atomic<uint16_t>*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 4:
+          MemSetElements(reinterpret_cast<std::atomic<uint32_t>*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 8:
+          MemSetElements(reinterpret_cast<std::atomic<uint64_t>*>(MemData + MemPrefix), Value, Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    else {
+      switch (Size) {
+        case 1:
+          MemSetElements(reinterpret_cast<uint8_t*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 2:
+          MemSetElements(reinterpret_cast<uint16_t*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 4:
+          MemSetElements(reinterpret_cast<uint32_t*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 8:
+          MemSetElements(reinterpret_cast<uint64_t*>(MemData + MemPrefix), Value, Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    GD = reinterpret_cast<uint64_t>(MemData + (Length * Size));
+  }
+  else { // Backward
+    if (Op->IsAtomic) {
+      switch (Size) {
+        case 1:
+          MemSetElementsInverse(reinterpret_cast<std::atomic<uint8_t>*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 2:
+          MemSetElementsInverse(reinterpret_cast<std::atomic<uint16_t>*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 4:
+          MemSetElementsInverse(reinterpret_cast<std::atomic<uint32_t>*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 8:
+          MemSetElementsInverse(reinterpret_cast<std::atomic<uint64_t>*>(MemData + MemPrefix), Value, Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    else {
+      switch (Size) {
+        case 1:
+          MemSetElementsInverse(reinterpret_cast<uint8_t*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 2:
+          MemSetElementsInverse(reinterpret_cast<uint16_t*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 4:
+          MemSetElementsInverse(reinterpret_cast<uint32_t*>(MemData + MemPrefix), Value, Length);
+          break;
+        case 8:
+          MemSetElementsInverse(reinterpret_cast<uint64_t*>(MemData + MemPrefix), Value, Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    GD = reinterpret_cast<uint64_t>(MemData - (Length * Size));
+  }
+}
+
+DEF_OP(MemCpy) {
+  const auto Op = IROp->C<IR::IROp_MemCpy>();
+  const int32_t Size = Op->Size;
+
+  uint64_t *DstPtr = GetDest<uint64_t*>(Data->SSAData, Node);
+
+  char *MemDataDest = *GetSrc<char **>(Data->SSAData, Op->AddrDest);
+  char *MemDataSrc = *GetSrc<char **>(Data->SSAData, Op->AddrSrc);
+
+  uint64_t DestPrefix{};
+  uint64_t SrcPrefix{};
+  if (!Op->PrefixDest.IsInvalid()) {
+    DestPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->PrefixDest);
+
+  }
+  if (!Op->PrefixSrc.IsInvalid()) {
+    SrcPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->PrefixSrc);
+  }
+
+  const auto Length = *GetSrc<uint64_t*>(Data->SSAData, Op->Length);
+  const auto Direction = *GetSrc<uint8_t*>(Data->SSAData, Op->Direction);
+
+  auto MemSetElementsAtomic = [](auto* MemDst, auto* MemSrc, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      MemDst[i].store(MemSrc[i].load());
+    }
+  };
+
+  auto MemSetElementsAtomicInverse = [](auto* MemDst, auto* MemSrc, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      MemDst[-i].store(MemSrc[-i].load());
+    }
+  };
+
+  auto MemSetElements = [](auto* MemDst, auto* MemSrc, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      MemDst[i] = MemSrc[i];
+    }
+  };
+
+  auto MemSetElementsInverse = [](auto* MemDst, auto* MemSrc, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      MemDst[-i] = MemSrc[-i];
+    }
+  };
+
+  if (Direction == 0) { // Forward
+    if (Op->IsAtomic) {
+      switch (Size) {
+        case 1:
+          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint8_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint8_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 2:
+          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint16_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint16_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 4:
+          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint32_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint32_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 8:
+          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint64_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint64_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    else {
+      switch (Size) {
+        case 1:
+          MemSetElements(reinterpret_cast<uint8_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint8_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 2:
+          MemSetElements(reinterpret_cast<uint16_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint16_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 4:
+          MemSetElements(reinterpret_cast<uint32_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint32_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 8:
+          MemSetElements(reinterpret_cast<uint64_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint64_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    DstPtr[0] = reinterpret_cast<uint64_t>(MemDataDest + (Length * Size));
+    DstPtr[1] = reinterpret_cast<uint64_t>(MemDataSrc + (Length * Size));
+  }
+  else { // Backward
+    if (Op->IsAtomic) {
+      switch (Size) {
+        case 1:
+          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint8_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint8_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 2:
+          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint16_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint16_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 4:
+          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint32_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint32_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 8:
+          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint64_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint64_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    else {
+      switch (Size) {
+        case 1:
+          MemSetElementsInverse(reinterpret_cast<uint8_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint8_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 2:
+          MemSetElementsInverse(reinterpret_cast<uint16_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint16_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 4:
+          MemSetElementsInverse(reinterpret_cast<uint32_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint32_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 8:
+          MemSetElementsInverse(reinterpret_cast<uint64_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint64_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    DstPtr[0] = reinterpret_cast<uint64_t>(MemDataDest - (Length * Size));
+    DstPtr[1] = reinterpret_cast<uint64_t>(MemDataSrc - (Length * Size));
   }
-  #undef STORE_DATA
 }
 
 DEF_OP(CacheLineClear) {
@@ -275,6 +657,15 @@ DEF_OP(CacheLineClear) {
   CacheLineFlush(MemData);
 }
 
+DEF_OP(CacheLineClean) {
+  auto Op = IROp->C<IR::IROp_CacheLineClean>();
+
+  char *MemData = *GetSrc<char **>(Data->SSAData, Op->Addr);
+
+  // 64-byte cache line clear
+  CacheLineClean(MemData);
+}
+
 DEF_OP(CacheLineZero) {
   auto Op = IROp->C<IR::IROp_CacheLineZero>();
 

External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp

@@ -8,9 +8,12 @@ $end_info$
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 #include "Interface/Core/Interpreter/InterpreterDefines.h"
 
+#include "Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h"
+
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Utils/BitUtils.h>
 
+#include <array>
 #include <bit>
 #include <cstdint>
 #include <limits>
@@ -358,23 +361,26 @@ DEF_OP(VAddP) {
 }
 
 DEF_OP(VAddV) {
-  auto Op = IROp->C<IR::IROp_VAddV>();
-  const uint8_t OpSize = IROp->Size;
+  const auto Op = IROp->C<IR::IROp_VAddV>();
+  const auto OpSize = IROp->Size;
 
   void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
-  uint8_t Tmp[16];
+  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE];
 
-  const uint8_t Elements = OpSize / Op->Header.ElementSize;
+  const uint8_t ElementSize = Op->Header.ElementSize;
+  const uint8_t Elements = OpSize / ElementSize;
 
   const auto Func = [](auto current, auto a) { return current + a; };
-  switch (Op->Header.ElementSize) {
+  switch (ElementSize) {
     DO_VECTOR_REDUCE_1SRC_OP(1, int8_t, Func, 0)
     DO_VECTOR_REDUCE_1SRC_OP(2, int16_t, Func, 0)
     DO_VECTOR_REDUCE_1SRC_OP(4, int32_t, Func, 0)
     DO_VECTOR_REDUCE_1SRC_OP(8, int64_t, Func, 0)
-    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
+      return;
   }
-  memcpy(GDP, Tmp, Op->Header.ElementSize);
+  memcpy(GDP, Tmp, ElementSize);
 }
 
 DEF_OP(VUMinV) {
@@ -898,6 +904,67 @@ DEF_OP(VZip) {
   memcpy(GDP, Tmp, OpSize);
 }
 
+DEF_OP(VTrn) {
+  const auto Op = IROp->C<IR::IROp_VTrn>();
+  const uint8_t OpSize = IROp->Size;
+
+  void *Src1 = GetSrc<void*>(Data->SSAData, Op->VectorLower);
+  void *Src2 = GetSrc<void*>(Data->SSAData, Op->VectorUpper);
+  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE]{};
+  const uint8_t ElementSize = Op->Header.ElementSize;
+  uint8_t Elements = OpSize / ElementSize;
+  const uint8_t BaseOffset = IROp->Op == IR::OP_VTRN2 ? 1 : 0;
+  Elements >>= 1;
+
+  switch (ElementSize) {
+    case 1: {
+      auto *Dst_d  = reinterpret_cast<uint8_t*>(Tmp);
+      auto *Src1_d = reinterpret_cast<uint8_t*>(Src1);
+      auto *Src2_d = reinterpret_cast<uint8_t*>(Src2);
+      for (unsigned i = 0; i < Elements; ++i) {
+        Dst_d[i*2] = Src1_d[i*2 + BaseOffset];
+        Dst_d[i*2+1] = Src2_d[i*2 + BaseOffset];
+      }
+      break;
+    }
+    case 2: {
+      auto *Dst_d  = reinterpret_cast<uint16_t*>(Tmp);
+      auto *Src1_d = reinterpret_cast<uint16_t*>(Src1);
+      auto *Src2_d = reinterpret_cast<uint16_t*>(Src2);
+      for (unsigned i = 0; i < Elements; ++i) {
+        Dst_d[i*2] = Src1_d[i*2 + BaseOffset];
+        Dst_d[i*2+1] = Src2_d[i*2 + BaseOffset];
+      }
+      break;
+    }
+    case 4: {
+      auto *Dst_d  = reinterpret_cast<uint32_t*>(Tmp);
+      auto *Src1_d = reinterpret_cast<uint32_t*>(Src1);
+      auto *Src2_d = reinterpret_cast<uint32_t*>(Src2);
+      for (unsigned i = 0; i < Elements; ++i) {
+        Dst_d[i*2] = Src1_d[i*2 + BaseOffset];
+        Dst_d[i*2+1] = Src2_d[i*2 + BaseOffset];
+      }
+      break;
+    }
+    case 8: {
+      auto *Dst_d  = reinterpret_cast<uint64_t*>(Tmp);
+      auto *Src1_d = reinterpret_cast<uint64_t*>(Src1);
+      auto *Src2_d = reinterpret_cast<uint64_t*>(Src2);
+      for (unsigned i = 0; i < Elements; ++i) {
+        Dst_d[i*2] = Src1_d[i*2 + BaseOffset];
+        Dst_d[i*2+1] = Src2_d[i*2 + BaseOffset];
+      }
+      break;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
+      break;
+  }
+
+  memcpy(GDP, Tmp, OpSize);
+}
+
 DEF_OP(VUnZip) {
   const auto Op = IROp->C<IR::IROp_VUnZip>();
   const uint8_t OpSize = IROp->Size;
@@ -960,7 +1027,9 @@ DEF_OP(VUnZip) {
 }
 
 DEF_OP(VBSL) {
-  auto Op = IROp->C<IR::IROp_VBSL>();
+  const auto Op = IROp->C<IR::IROp_VBSL>();
+  const auto OpSize = IROp->Size;
+
   const auto Src1 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorMask);
   const auto Src2 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorTrue);
   const auto Src3 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorFalse);
@@ -970,7 +1039,8 @@ DEF_OP(VBSL) {
     .Upper = (Src2.Upper & Src1.Upper) | (Src3.Upper & ~Src1.Upper),
   };
 
-  memcpy(GDP, &Tmp, sizeof(Tmp));
+  memset(GDP, 0, sizeof(InterpVector256));
+  memcpy(GDP, &Tmp, OpSize);
 }
 
 DEF_OP(VCMPEQ) {
@@ -1545,6 +1615,12 @@ DEF_OP(VInsElement) {
       Dst_d[Op->DestIdx] = Src2_d[Op->SrcIdx];
       break;
     }
+    case 16: {
+      auto *Dst_d  = reinterpret_cast<__uint128_t*>(Tmp);
+      auto *Src2_d = reinterpret_cast<__uint128_t*>(Src2);
+      Dst_d[Op->DestIdx] = Src2_d[Op->SrcIdx];
+      break;
+    }
     default:
       LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
       break;
@@ -1619,41 +1695,53 @@ DEF_OP(VDupElement) {
 }
 
 DEF_OP(VExtr) {
-  auto Op = IROp->C<IR::IROp_VExtr>();
-  const uint8_t OpSize = IROp->Size;
+  const auto Op = IROp->C<IR::IROp_VExtr>();
+  const auto OpSize = IROp->Size;
+  const auto OpSizeBits = OpSize * 8;
 
-  const auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorLower);
-  const auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorUpper);
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = Op->Header.ElementSize;
+  const auto Index = Op->Index;
 
-  uint64_t Offset = Op->Index * Op->Header.ElementSize * 8;
-  __uint128_t Dst{};
-  if (Offset >= (OpSize * 8)) {
-    Offset -= OpSize * 8;
-    Dst = Src1 >> Offset;
+  if (Is256Bit) {
+    const auto ByteIndex = Index * ElementSize;
+    const auto IsUpperVectorZero = ByteIndex >= OpSize;
+    const auto SanitizedByteIndex = IsUpperVectorZero ? ByteIndex - OpSize
+                                                      : ByteIndex;
+
+    const auto Vectors = IsUpperVectorZero
+      ?
+        std::array<InterpVector256, 2>{
+          *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorLower),
+          InterpVector256{},
+        }
+      :
+        std::array<InterpVector256, 2>{
+          *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorUpper),
+          *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorLower),
+        };
+
+    const auto* VectorsPtr = reinterpret_cast<const uint8_t*>(Vectors.data());
+    const auto* SrcPtr = VectorsPtr + SanitizedByteIndex;
+    const auto CopyAmount = std::max(0, int(sizeof(Vectors) - SanitizedByteIndex));
+
+    memcpy(GDP, SrcPtr, CopyAmount);
+  } else {
+    uint64_t Offset = Index * ElementSize * 8;
+
+    const auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorLower);
+    const auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorUpper);
+
+    __uint128_t Dst{};
+    if (Offset >= OpSizeBits) {
+      Offset -= OpSizeBits;
+      Dst = Src1 >> Offset;
+    } else {
+      Dst = (Src1 << (OpSizeBits - Offset)) | (Src2 >> Offset);
+    }
+
+    memcpy(GDP, &Dst, OpSize);
   }
-  else {
-    Dst = (Src1 << (OpSize * 8 - Offset)) | (Src2 >> Offset);
-  }
-
-  memcpy(GDP, &Dst, OpSize);
-}
-
-DEF_OP(VSLI) {
-  auto Op = IROp->C<IR::IROp_VSLI>();
-  const __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector);
-  const __uint128_t Src2 = Op->ByteShift * 8;
-
-  const __uint128_t Dst = Op->ByteShift >= sizeof(__uint128_t) ? 0 : Src1 << Src2;
-  memcpy(GDP, &Dst, 16);
-}
-
-DEF_OP(VSRI) {
-  auto Op = IROp->C<IR::IROp_VSRI>();
-  const __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector);
-  const __uint128_t Src2 = Op->ByteShift * 8;
-
-  const __uint128_t Dst = Op->ByteShift >= sizeof(__uint128_t) ? 0 : Src1 >> Src2;
-  memcpy(GDP, &Dst, 16);
 }
 
 DEF_OP(VUShrI) {
@@ -2190,6 +2278,37 @@ DEF_OP(VRev64) {
   memcpy(GDP, Tmp, OpSize);
 }
 
+DEF_OP(VPCMPESTRX) {
+  const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
+  const auto Is64Bit = Op->GPRSize == 8;
+
+  const auto RAX = *GetSrc<uint64_t*>(Data->SSAData, Op->RAX);
+  const auto RDX = *GetSrc<uint64_t*>(Data->SSAData, Op->RDX);
+  const auto LHS = *GetSrc<__uint128_t*>(Data->SSAData, Op->LHS);
+  const auto RHS = *GetSrc<__uint128_t*>(Data->SSAData, Op->RHS);
+
+  // We can be cheeky and encode the size at bit 8 to save a parameter
+  const auto Control = Op->Control | (uint16_t(Is64Bit) << 8);
+
+  const auto Result = OpHandlers<IR::OP_VPCMPESTRX>::handle(RAX, RDX, LHS, RHS, Control);
+
+  memset(GDP, 0, sizeof(uint64_t));
+  memcpy(GDP, &Result, sizeof(Result));
+}
+
+DEF_OP(VPCMPISTRX) {
+  const auto Op = IROp->C<IR::IROp_VPCMPISTRX>();
+
+  const auto LHS = *GetSrc<__uint128_t*>(Data->SSAData, Op->LHS);
+  const auto RHS = *GetSrc<__uint128_t*>(Data->SSAData, Op->RHS);
+  const auto Control = Op->Control;
+
+  const auto Result = OpHandlers<IR::OP_VPCMPISTRX>::handle(LHS, RHS, Control);
+
+  memset(GDP, 0, sizeof(uint64_t));
+  memcpy(GDP, &Result, sizeof(Result));
+}
+
 #undef DEF_OP
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp

@@ -9,7 +9,7 @@ $end_info$
 #include "Interface/HLE/Thunks/Thunks.h"
 
 namespace FEXCore::CPU {
-    
+
 uint64_t Arm64JITCore::GetNamedSymbolLiteral(FEXCore::CPU::RelocNamedSymbolLiteral::NamedSymbol Op) {
   switch (Op) {
     case FEXCore::CPU::RelocNamedSymbolLiteral::NamedSymbol::SYMBOL_LITERAL_EXITFUNCTION_LINKER:
@@ -22,18 +22,18 @@ uint64_t Arm64JITCore::GetNamedSymbolLiteral(FEXCore::CPU::RelocNamedSymbolLiter
   return ~0ULL;
 }
 
-void Arm64JITCore::InsertNamedThunkRelocation(vixl::aarch64::Register Reg, const IR::SHA256Sum &Sum) {
+void Arm64JITCore::InsertNamedThunkRelocation(ARMEmitter::Register Reg, const IR::SHA256Sum &Sum) {
   Relocation MoveABI{};
   MoveABI.NamedThunkMove.Header.Type = FEXCore::CPU::RelocationTypes::RELOC_NAMED_THUNK_MOVE;
   // Offset is the offset from the entrypoint of the block
   auto CurrentCursor = GetCursorAddress<uint8_t *>();
-  MoveABI.NamedThunkMove.Offset = CurrentCursor - GuestEntry;
+  MoveABI.NamedThunkMove.Offset = CurrentCursor - CodeData.BlockBegin;
   MoveABI.NamedThunkMove.Symbol = Sum;
-  MoveABI.NamedThunkMove.RegisterIndex = Reg.GetCode();
+  MoveABI.NamedThunkMove.RegisterIndex = Reg.Idx();
 
   uint64_t Pointer = reinterpret_cast<uint64_t>(EmitterCTX->ThunkHandler->LookupThunk(Sum));
 
-  LoadConstant(Reg, Pointer, EmitterCTX->Config.CacheObjectCodeCompilation());
+  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Pointer, EmitterCTX->Config.CacheObjectCodeCompilation());
   Relocations.emplace_back(MoveABI);
 }
 
@@ -41,7 +41,7 @@ Arm64JITCore::NamedSymbolLiteralPair Arm64JITCore::InsertNamedSymbolLiteral(FEXC
   uint64_t Pointer = GetNamedSymbolLiteral(Op);
 
   Arm64JITCore::NamedSymbolLiteralPair Lit {
-    .Lit = Literal(Pointer),
+    .Lit = Pointer,
     .MoveABI = {
       .NamedSymbolLiteral = {
         .Header = {
@@ -58,22 +58,23 @@ Arm64JITCore::NamedSymbolLiteralPair Arm64JITCore::InsertNamedSymbolLiteral(FEXC
 void Arm64JITCore::PlaceNamedSymbolLiteral(NamedSymbolLiteralPair &Lit) {
   // Offset is the offset from the entrypoint of the block
   auto CurrentCursor = GetCursorAddress<uint8_t *>();
-  Lit.MoveABI.NamedSymbolLiteral.Offset = CurrentCursor - GuestEntry;
+  Lit.MoveABI.NamedSymbolLiteral.Offset = CurrentCursor - CodeData.BlockBegin;
 
-  place(&Lit.Lit);
+  Bind(&Lit.Loc);
+  dc64(Lit.Lit);
   Relocations.emplace_back(Lit.MoveABI);
 }
 
-void Arm64JITCore::InsertGuestRIPMove(vixl::aarch64::Register Reg, uint64_t Constant) {
+void Arm64JITCore::InsertGuestRIPMove(ARMEmitter::Register Reg, uint64_t Constant) {
   Relocation MoveABI{};
   MoveABI.GuestRIPMove.Header.Type = FEXCore::CPU::RelocationTypes::RELOC_GUEST_RIP_MOVE;
   // Offset is the offset from the entrypoint of the block
   auto CurrentCursor = GetCursorAddress<uint8_t *>();
-  MoveABI.GuestRIPMove.Offset = CurrentCursor - GuestEntry;
+  MoveABI.GuestRIPMove.Offset = CurrentCursor - CodeData.BlockBegin;
   MoveABI.GuestRIPMove.GuestRIP = Constant;
-  MoveABI.GuestRIPMove.RegisterIndex = Reg.GetCode();
+  MoveABI.GuestRIPMove.RegisterIndex = Reg.Idx();
 
-  LoadConstant(Reg, Constant, EmitterCTX->Config.CacheObjectCodeCompilation());
+  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Constant, EmitterCTX->Config.CacheObjectCodeCompilation());
   Relocations.emplace_back(MoveABI);
 }
 
@@ -87,11 +88,10 @@ bool Arm64JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uin
       case FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: {
         uint64_t Pointer = GetNamedSymbolLiteral(Reloc->NamedSymbolLiteral.Symbol);
         // Relocation occurs at the cursorEntry + offset relative to that cursor
-        GetBuffer()->SetCursorOffset(CursorEntry + Reloc->NamedSymbolLiteral.Offset);
+        SetCursorOffset(CursorEntry + Reloc->NamedSymbolLiteral.Offset);
 
         // Generate a literal so we can place it
-        Literal<uint64_t> Lit(Pointer);
-        place(&Lit);
+        dc64(Pointer);
 
         DataIndex += sizeof(Reloc->NamedSymbolLiteral);
         break;
@@ -103,8 +103,8 @@ bool Arm64JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uin
         }
 
         // Relocation occurs at the cursorEntry + offset relative to that cursor.
-        GetBuffer()->SetCursorOffset(CursorEntry + Reloc->NamedThunkMove.Offset);
-        LoadConstant(vixl::aarch64::XRegister(Reloc->NamedThunkMove.RegisterIndex), Pointer, true);
+        SetCursorOffset(CursorEntry + Reloc->NamedThunkMove.Offset);
+        LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc->NamedThunkMove.RegisterIndex), Pointer, true);
         DataIndex += sizeof(Reloc->NamedThunkMove);
         break;
       }
@@ -117,8 +117,8 @@ bool Arm64JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uin
         }
 
         // Relocation occurs at the cursorEntry + offset relative to that cursor.
-        GetBuffer()->SetCursorOffset(CursorEntry + Reloc->GuestRIPMove.Offset);
-        LoadConstant(vixl::aarch64::XRegister(Reloc->GuestRIPMove.RegisterIndex), Pointer, true);
+        SetCursorOffset(CursorEntry + Reloc->GuestRIPMove.Offset);
+        LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc->GuestRIPMove.RegisterIndex), Pointer, true);
         DataIndex += sizeof(Reloc->GuestRIPMove);
         break;
       }

External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp

@@ -6,6 +6,7 @@ $end_info$
 
 #include "Interface/Context/Context.h"
 #include "FEXCore/IR/IR.h"
+#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/LookupCache.h"
 
 #include "Interface/Core/JIT/Arm64/JITClass.h"
@@ -17,38 +18,25 @@ $end_info$
 #include <Interface/HLE/Thunks/Thunks.h>
 
 namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-
-DEF_OP(SignalReturn) {
-  // First we must reset the stack
-  ResetStack();
-
-  // Now branch to our signal return helper
-  // This can't be a direct branch since the code needs to live at a constant location
-  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SignalReturnHandler)));
-  br(x0);
-}
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 
 DEF_OP(CallbackReturn) {
-
   // spill back to CTX
-  SpillStaticRegs();
+  SpillStaticRegs(TMP1);
 
   // First we must reset the stack
   ResetStack();
 
   // We can now lower the ref counter again
 
-  ldr(w2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SignalHandlerRefCounter)));
-  sub(w2, w2, 1);
-  str(w2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SignalHandlerRefCounter)));
+  ldr(ARMEmitter::WReg::w2, STATE, offsetof(FEXCore::Core::CpuStateFrame, SignalHandlerRefCounter));
+  sub(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r2, 1);
+  str(ARMEmitter::WReg::w2, STATE, offsetof(FEXCore::Core::CpuStateFrame, SignalHandlerRefCounter));
 
   // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
-  add(x2, x2, 8);
-  str(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
+  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP]));
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r2, 8);
+  str(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP]));
 
   PopCalleeSavedRegisters();
 
@@ -59,39 +47,41 @@ DEF_OP(CallbackReturn) {
 DEF_OP(ExitFunction) {
   auto Op = IROp->C<IR::IROp_ExitFunction>();
 
-  Label FullLookup;
-
   ResetStack();
 
-  aarch64::Register RipReg;
   uint64_t NewRIP;
 
   if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
-    Literal l_BranchHost{ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker};
-    Literal l_BranchGuest{NewRIP};
+    ARMEmitter::ForwardLabel l_BranchHost;
+    ARMEmitter::ForwardLabel l_BranchGuest;
 
-    ldr(x0, &l_BranchHost);
-    blr(x0);
+    ldr(ARMEmitter::XReg::x0, &l_BranchHost);
+    blr(ARMEmitter::Reg::r0);
+
+    Bind(&l_BranchHost);
+    dc64(ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker);
+    Bind(&l_BranchGuest);
+    dc64(NewRIP);
 
-    place(&l_BranchHost);
-    place(&l_BranchGuest);
   } else {
-    RipReg = GetReg<RA_64>(Op->NewRIP.ID());
+
+    ARMEmitter::ForwardLabel FullLookup;
+    auto RipReg = GetReg(Op->NewRIP.ID());
 
     // L1 Cache
-    ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.L1Pointer)));
+    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.L1Pointer));
 
-    and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
-    add(x0, x0, Operand(x3, Shift::LSL, 4));
+    and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg, LookupCache::L1_ENTRIES_MASK);
+    add(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, ARMEmitter::XReg::x3, ARMEmitter::ShiftType::LSL, 4);
 
-    ldp(x1, x0, MemOperand(x0));
-    cmp(x0, RipReg);
-    b(&FullLookup, Condition::ne);
-    br(x1);
+    ldp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::XReg::x1, ARMEmitter::XReg::x0, ARMEmitter::Reg::r0, 0);
+    cmp(ARMEmitter::XReg::x0, RipReg.X());
+    b(ARMEmitter::Condition::CC_NE, &FullLookup);
+    br(ARMEmitter::Reg::r1);
 
-    bind(&FullLookup);
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop)));
-    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
+    Bind(&FullLookup);
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop));
+    str(RipReg.X(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip));
     br(TMP1);
   }
 }
@@ -103,66 +93,65 @@ DEF_OP(Jump) {
   PendingTargetLabel = &JumpTargets.try_emplace(Target).first->second;
 }
 
-#define GRCMP(Node) (Op->CompareSize == 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))
-#define GRFCMP(Node) (Op->CompareSize == 4 ? GetDst(Node).S() : GetDst(Node).D())
-
-static Condition MapBranchCC(IR::CondClassType Cond) {
+static ARMEmitter::Condition MapBranchCC(IR::CondClassType Cond) {
   switch (Cond.Val) {
-  case FEXCore::IR::COND_EQ: return Condition::eq;
-  case FEXCore::IR::COND_NEQ: return Condition::ne;
-  case FEXCore::IR::COND_SGE: return Condition::ge;
-  case FEXCore::IR::COND_SLT: return Condition::lt;
-  case FEXCore::IR::COND_SGT: return Condition::gt;
-  case FEXCore::IR::COND_SLE: return Condition::le;
-  case FEXCore::IR::COND_UGE: return Condition::cs;
-  case FEXCore::IR::COND_ULT: return Condition::cc;
-  case FEXCore::IR::COND_UGT: return Condition::hi;
-  case FEXCore::IR::COND_ULE: return Condition::ls;
-  case FEXCore::IR::COND_FLU: return Condition::lt;
-  case FEXCore::IR::COND_FGE: return Condition::ge;
-  case FEXCore::IR::COND_FLEU:return Condition::le;
-  case FEXCore::IR::COND_FGT: return Condition::gt;
-  case FEXCore::IR::COND_FU:  return Condition::vs;
-  case FEXCore::IR::COND_FNU: return Condition::vc;
+  case FEXCore::IR::COND_EQ:  return ARMEmitter::Condition::CC_EQ;
+  case FEXCore::IR::COND_NEQ: return ARMEmitter::Condition::CC_NE;
+  case FEXCore::IR::COND_SGE: return ARMEmitter::Condition::CC_GE;
+  case FEXCore::IR::COND_SLT: return ARMEmitter::Condition::CC_LT;
+  case FEXCore::IR::COND_SGT: return ARMEmitter::Condition::CC_GT;
+  case FEXCore::IR::COND_SLE: return ARMEmitter::Condition::CC_LE;
+  case FEXCore::IR::COND_UGE: return ARMEmitter::Condition::CC_CS;
+  case FEXCore::IR::COND_ULT: return ARMEmitter::Condition::CC_CC;
+  case FEXCore::IR::COND_UGT: return ARMEmitter::Condition::CC_HI;
+  case FEXCore::IR::COND_ULE: return ARMEmitter::Condition::CC_LS;
+  case FEXCore::IR::COND_FLU: return ARMEmitter::Condition::CC_LT;
+  case FEXCore::IR::COND_FGE: return ARMEmitter::Condition::CC_GE;
+  case FEXCore::IR::COND_FLEU:return ARMEmitter::Condition::CC_LE;
+  case FEXCore::IR::COND_FGT: return ARMEmitter::Condition::CC_GT;
+  case FEXCore::IR::COND_FU:  return ARMEmitter::Condition::CC_VS;
+  case FEXCore::IR::COND_FNU: return ARMEmitter::Condition::CC_VC;
   case FEXCore::IR::COND_VS:
   case FEXCore::IR::COND_VC:
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
   LOGMAN_MSG_A_FMT("Unsupported compare type");
-  return Condition::nv;
+  return ARMEmitter::Condition::CC_NV;
   }
 }
 
-
 DEF_OP(CondJump) {
   auto Op = IROp->C<IR::IROp_CondJump>();
 
-  Label *TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
+  auto TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
 
   uint64_t Const;
   const bool isConst = IsInlineConstant(Op->Cmp2, &Const);
 
+  const auto Size = Op->CompareSize == 4 ? ARMEmitter::Size::i32Bit : ARMEmitter::Size::i64Bit;
+  const auto SubSize = ARMEmitter::ToVectorSizePair(Op->CompareSize == 4 ? ARMEmitter::SubRegSize::i32Bit : ARMEmitter::SubRegSize::i64Bit);
+
   if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_EQ) {
     LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
-    cbz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
+    cbz(Size, GetReg(Op->Cmp1.ID()), TrueTargetLabel);
   } else if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_NEQ) {
     LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
-    cbnz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
+    cbnz(Size, GetReg(Op->Cmp1.ID()), TrueTargetLabel);
   } else {
     if (IsGPR(Op->Cmp1.ID())) {
       if (isConst) {
-        cmp(GRCMP(Op->Cmp1.ID()), Const);
+        cmp(Size, GetReg(Op->Cmp1.ID()), Const);
       } else {
-        cmp(GRCMP(Op->Cmp1.ID()), GRCMP(Op->Cmp2.ID()));
+        cmp(Size, GetReg(Op->Cmp1.ID()), GetReg(Op->Cmp2.ID()));
       }
     } else if (IsFPR(Op->Cmp1.ID())) {
-      fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
+      fcmp(SubSize.Scalar, GetVReg(Op->Cmp1.ID()), GetVReg(Op->Cmp2.ID()));
     } else {
       LOGMAN_MSG_A_FMT("CondJump: Expected GPR or FPR");
     }
 
-    b(TrueTargetLabel, MapBranchCC(Op->Cond));
+    b(MapBranchCC(Op->Cond), TrueTargetLabel);
   }
 
   PendingTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
@@ -176,50 +165,62 @@ DEF_OP(Syscall) {
   // X2: Pointer to SyscallArguments
 
   FEXCore::IR::SyscallFlags Flags = Op->Flags;
-  PushDynamicRegsAndLR();
+  PushDynamicRegsAndLR(TMP1);
 
-  if ((Flags & FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) != FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) {
-    SpillStaticRegs();
-  }
-  else {
+  uint32_t GPRSpillMask = ~0U;
+  uint32_t FPRSpillMask = ~0U;
+  if ((Flags & FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) == FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) {
     // Need to spill all caller saved registers still
-    SpillStaticRegs(true, CALLER_GPR_MASK, CALLER_FPR_MASK);
+    GPRSpillMask = CALLER_GPR_MASK;
+    FPRSpillMask = CALLER_FPR_MASK;
   }
 
+  SpillStaticRegs(TMP1, true, GPRSpillMask, FPRSpillMask);
+
+  // Now that we are spilled, store in the state that we are in a syscall
+  // Still without overwriting registers that matter
+  // 16bit LoadConstant to be a single instruction
+  // This gives the signal handler a value to check to see if we are in a syscall at all
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GPRSpillMask & 0xFFFF);
+  str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
+
   uint64_t SPOffset = AlignUp(FEXCore::HLE::SyscallArguments::MAX_ARGS * 8, 16);
-  sub(sp, sp, SPOffset);
+  sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, SPOffset);
   for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++i) {
     if (Op->Header.Args[i].IsInvalid()) continue;
-    str(GetReg<RA_64>(Op->Header.Args[i].ID()), MemOperand(sp, i * 8));
+    str(GetReg(Op->Header.Args[i].ID()).X(), ARMEmitter::Reg::rsp, i * 8);
   }
 
-  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerObj)));
-  ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerFunc)));
-  mov(x1, STATE);
-  mov(x2, sp);
+  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerObj));
+  ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerFunc));
+  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, STATE.R());
+
+  // SP supporting move
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::rsp, 0);
 #ifdef VIXL_SIMULATOR
-  GenerateIndirectRuntimeCall<uint64_t, void*, void*, void*>(x3);
+  GenerateIndirectRuntimeCall<uint64_t, void*, void*, void*>(ARMEmitter::Reg::r3);
 #else
-  blr(x3);
+  blr(ARMEmitter::Reg::r3);
 #endif
 
-  add(sp, sp, SPOffset);
-
-  if ((Flags & FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) != FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY &&
-      (Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
-    FillStaticRegs();
-  }
-  else {
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    FillStaticRegs(true, CALLER_GPR_MASK, CALLER_FPR_MASK);
-  }
-
-  PopDynamicRegsAndLR();
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, SPOffset);
 
   if ((Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
-    // Move result to its destination register
-    mov(GetReg<RA_64>(Node), x0);
+    // Result is now in x0
+    // Fix the stack and any values that were stepped on
+    FillStaticRegs(true, GPRSpillMask, FPRSpillMask);
+
+    // Now the registers we've spilled are back in their original host registers
+    // We can safely claim we are no longer in a syscall
+    str(ARMEmitter::XReg::zr, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
+
+    PopDynamicRegsAndLR();
+
+    if ((Flags & FEXCore::IR::SyscallFlags::NORETURNEDRESULT) != FEXCore::IR::SyscallFlags::NORETURNEDRESULT) {
+      // Move result to its destination register.
+      // Only if `NORETURNEDRESULT` wasn't set, otherwise we might overwrite the CPUState refilled with `FillStaticRegs`
+      mov(ARMEmitter::Size::i64Bit, GetReg(Node), ARMEmitter::Reg::r0);
+    }
   }
 }
 
@@ -236,8 +237,8 @@ DEF_OP(InlineSyscall) {
   // X6: Arg6 - Doesn't exist in x86-64 land. RA INTERSECT
 
   // One argument is removed from the SyscallArguments::MAX_ARGS since the first argument was syscall number
-  const static std::array<vixl::aarch64::Register, FEXCore::HLE::SyscallArguments::MAX_ARGS-1> RegArgs = {{
-    x0, x1, x2, x3, x4, x5
+  const static std::array<ARMEmitter::XRegister, FEXCore::HLE::SyscallArguments::MAX_ARGS-1> RegArgs = {{
+    ARMEmitter::XReg::x0, ARMEmitter::XReg::x1, ARMEmitter::XReg::x2, ARMEmitter::XReg::x3, ARMEmitter::XReg::x4, ARMEmitter::XReg::x5
   }};
 
   bool Intersects{};
@@ -246,90 +247,51 @@ DEF_OP(InlineSyscall) {
   for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
     if (Op->Header.Args[i].IsInvalid()) break;
 
-    auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
-    if (Reg.GetCode() == x8.GetCode() ||
-        Reg.GetCode() == x4.GetCode() ||
-        Reg.GetCode() == x5.GetCode()) {
+    auto Reg = GetReg(Op->Header.Args[i].ID());
+    if (Reg == ARMEmitter::Reg::r8 ||
+        Reg == ARMEmitter::Reg::r4 ||
+        Reg == ARMEmitter::Reg::r5) {
 
-      SpillMask |= (1U << Reg.GetCode());
+      SpillMask |= (1U << Reg.Idx());
       Intersects = true;
     }
   }
-  // XXX: For some reason spilling only the x4, x5, and x8 registers was causing issues
-  // Come back to this once investigation reveals why it fails the gvisor ioctl test
-  // For now override to all GPRs
-  SpillMask = ~0U;
 
   // Ordering is incredibly important here
   // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
   // Only spill the registers that intersect with our usage
-  SpillStaticRegs(false, SpillMask);
+  SpillStaticRegs(TMP1, false, SpillMask);
 
   // Now that we are spilled, store in the state that we are in a syscall
   // Still without overwriting registers that matter
   // 16bit LoadConstant to be a single instruction
   // We must always spill at least one register (x8) so this value always has a bit set
   // This gives the signal handler a value to check to see if we are in a syscall at all
-  LoadConstant(x0, SpillMask & 0xFFFF);
-  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, SpillMask & 0xFFFF);
+  str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
 
   // Now that we have claimed to be a syscall we can set up the arguments
+  const auto EmitSize = CTX->Config.Is64BitMode() ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+  const auto EmitSubSize = CTX->Config.Is64BitMode() ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i32Bit;
   if (Intersects) {
     for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
       if (Op->Header.Args[i].IsInvalid()) break;
 
-      if (CTX->Config.Is64BitMode()) {
-        auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
-        // In the case of intersection with x4, x5, or x8 then these are currently SRA
-        // for registers RAX, RBX, and RSI. Which have just been spilled
-        // Just load back from the context. Could be slightly smarter but this is fairly uncommon
-        if (Reg.GetCode() == x8.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
-        }
-        else if (Reg.GetCode() == x4.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
-        }
-        else if (Reg.GetCode() == x5.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
-        }
+      auto Reg = GetReg(Op->Header.Args[i].ID());
+      // In the case of intersection with x4, x5, or x8 then these are currently SRA
+      // for registers RAX, RBX, and RSI. Which have just been spilled
+      // Just load back from the context. Could be slightly smarter but this is fairly uncommon
+      if (Reg == ARMEmitter::Reg::r8) {
+        ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI]));
       }
-    }
-
-    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
-      if (Op->Header.Args[i].IsInvalid()) break;
-
-      if (CTX->Config.Is64BitMode()) {
-        auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
-        // In the case of intersection with x4, x5, or x8 then these are currently SRA
-        // for registers RAX, RBX, and RSI. Which have just been spilled
-        // Just load back from the context. Could be slightly smarter but this is fairly uncommon
-        if (Reg.GetCode() == x8.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
-        }
-        else if (Reg.GetCode() == x4.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
-        }
-        else if (Reg.GetCode() == x5.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
-        }
-        else {
-          mov(RegArgs[i], Reg);
-        }
+      else if (Reg == ARMEmitter::Reg::r4) {
+        ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX]));
+      }
+      else if (Reg == ARMEmitter::Reg::r5) {
+        ldr(EmitSubSize, RegArgs[i].R(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX]));
       }
       else {
-        auto Reg = GetReg<RA_32>(Op->Header.Args[i].ID());
-        if (Reg.GetCode() == w8.GetCode()) {
-          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
-        }
-        else if (Reg.GetCode() == w4.GetCode()) {
-          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
-        }
-        else if (Reg.GetCode() == w5.GetCode()) {
-          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
-        }
-        else {
-          uxtw(RegArgs[i].W(), Reg);
-        }
+        mov(EmitSize, RegArgs[i].R(), Reg);
       }
     }
   }
@@ -337,16 +299,11 @@ DEF_OP(InlineSyscall) {
     for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
       if (Op->Header.Args[i].IsInvalid()) break;
 
-      if (CTX->Config.Is64BitMode()) {
-        mov(RegArgs[i], GetReg<RA_64>(Op->Header.Args[i].ID()));
-      }
-      else {
-        uxtw(RegArgs[i], GetReg<RA_64>(Op->Header.Args[i].ID()));
-      }
+      mov(EmitSize, RegArgs[i].R(), GetReg(Op->Header.Args[i].ID()));
     }
   }
 
-  LoadConstant(x8, Op->HostSyscallNumber);
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r8, Op->HostSyscallNumber);
   svc(0);
   // On updated signal mask we can receive a signal RIGHT HERE
 
@@ -357,16 +314,11 @@ DEF_OP(InlineSyscall) {
 
     // Now the registers we've spilled are back in their original host registers
     // We can safely claim we are no longer in a syscall
-    str(xzr, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+    str(ARMEmitter::XReg::zr, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
 
     // Result is now in x0
     // Move result to its destination register
-    if (CTX->Config.Is64BitMode()) {
-      mov(GetReg<RA_64>(Node), x0);
-    }
-    else {
-      uxtw(GetReg<RA_64>(Node), x0);
-    }
+    mov(EmitSize, GetReg(Node), ARMEmitter::Reg::r0);
   }
 }
 
@@ -376,18 +328,18 @@ DEF_OP(Thunk) {
   // X0: CTX
   // X1: Args (from guest stack)
 
-  SpillStaticRegs(); // spill to ctx before ra64 spill
+  SpillStaticRegs(TMP1); // spill to ctx before ra64 spill
 
-  PushDynamicRegsAndLR();
+  PushDynamicRegsAndLR(TMP1);
 
-  mov(x0, GetReg<RA_64>(Op->ArgPtr.ID()));
+  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GetReg(Op->ArgPtr.ID()));
 
-  auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
-  LoadConstant(x2, (uintptr_t)thunkFn);
+  auto thunkFn = static_cast<Context::ContextImpl*>(ThreadState->CTX)->ThunkHandler->LookupThunk(Op->ThunkNameHash);
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, (uintptr_t)thunkFn);
 #ifdef VIXL_SIMULATOR
-  GenerateIndirectRuntimeCall<void, void*, void*>(x2);
+  GenerateIndirectRuntimeCall<void, void*, void*>(ARMEmitter::Reg::r2);
 #else
-  blr(x2);
+  blr(ARMEmitter::Reg::r2);
 #endif
 
   PopDynamicRegsAndLR();
@@ -401,43 +353,45 @@ DEF_OP(ValidateCode) {
   int len = Op->CodeLength;
   int idx = 0;
 
-  LoadConstant(GetReg<RA_64>(Node), 0);
-  LoadConstant(x0, Entry + Op->Offset);
-  LoadConstant(x1, 1);
+  LoadConstant(ARMEmitter::Size::i64Bit, GetReg(Node), 0);
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, Entry + Op->Offset);
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, 1);
+
+  const auto Dst = GetReg(Node);
 
   while (len >= 8)
   {
-    ldr(x2, MemOperand(x0, idx));
-    LoadConstant(x3, *(const uint32_t *)(OldCode + idx));
-    cmp(x2, x3);
-    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
+    ldr(ARMEmitter::XReg::x2, ARMEmitter::Reg::r0, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, *(const uint32_t *)(OldCode + idx));
+    cmp(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r3);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::r1, ARMEmitter::Condition::CC_EQ);
     len -= 8;
     idx += 8;
   }
   while (len >= 4)
   {
-    ldr(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(const uint32_t *)(OldCode + idx));
-    cmp(w2, w3);
-    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
+    ldr(ARMEmitter::WReg::w2, ARMEmitter::Reg::r0, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, *(const uint32_t *)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r3);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::r1, ARMEmitter::Condition::CC_EQ);
     len -= 4;
     idx += 4;
   }
   while (len >= 2)
   {
-    ldrh(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(const uint16_t *)(OldCode + idx));
-    cmp(w2, w3);
-    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
+    ldrh(ARMEmitter::Reg::r2, ARMEmitter::Reg::r0, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, *(const uint16_t *)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r3);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::r1, ARMEmitter::Condition::CC_EQ);
     len -= 2;
     idx += 2;
   }
   while (len >= 1)
   {
-    ldrb(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(const uint8_t *)(OldCode + idx));
-    cmp(w2, w3);
-    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
+    ldrb(ARMEmitter::Reg::r2, ARMEmitter::Reg::r0, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, *(const uint8_t *)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r3);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::r1, ARMEmitter::Condition::CC_EQ);
     len -= 1;
     idx += 1;
   }
@@ -448,17 +402,17 @@ DEF_OP(ThreadRemoveCodeEntry) {
   // X0: Thread
   // X1: RIP
 
-  PushDynamicRegsAndLR();
+  PushDynamicRegsAndLR(TMP1);
+  SpillStaticRegs(TMP1);
 
-  mov(x0, STATE);
-  LoadConstant(x1, Entry);
+  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, STATE.R());
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, Entry);
 
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT)));
-  SpillStaticRegs();
+  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT));
 #ifdef VIXL_SIMULATOR
-  GenerateIndirectRuntimeCall<void, void*, void*>(x2);
+  GenerateIndirectRuntimeCall<void, void*, void*>(ARMEmitter::Reg::r2);
 #else
-  blr(x2);
+  blr(ARMEmitter::Reg::r2);
 #endif
   FillStaticRegs();
 
@@ -469,47 +423,61 @@ DEF_OP(ThreadRemoveCodeEntry) {
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
 
-  PushDynamicRegsAndLR();
-  SpillStaticRegs();
+  PushDynamicRegsAndLR(TMP1);
+  SpillStaticRegs(TMP1);
 
   // x0 = CPUID Handler
   // x1 = CPUID Function
   // x2 = CPUID Leaf
-  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)));
-  ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDFunction)));
-  mov(x1, GetReg<RA_64>(Op->Function.ID()));
-  mov(x2, GetReg<RA_64>(Op->Leaf.ID()));
+  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj));
+  ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDFunction));
+  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, GetReg(Op->Function.ID()));
+  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, GetReg(Op->Leaf.ID()));
 #ifdef VIXL_SIMULATOR
-  GenerateIndirectRuntimeCall<__uint128_t, void*, uint64_t, uint64_t>(x3);
+  GenerateIndirectRuntimeCall<__uint128_t, void*, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
 #else
-  blr(x3);
+  blr(ARMEmitter::Reg::r3);
 #endif
 
   FillStaticRegs();
+
   PopDynamicRegsAndLR();
 
   // Results are in x0, x1
   // Results want to be in a i64v2 vector
-  auto Dst = GetSrcPair<RA_64>(Node);
-  mov(Dst.first,  x0);
-  mov(Dst.second, x1);
+  auto Dst = GetRegPair(Node);
+  mov(ARMEmitter::Size::i64Bit, Dst.first,  ARMEmitter::Reg::r0);
+  mov(ARMEmitter::Size::i64Bit, Dst.second, ARMEmitter::Reg::r1);
+}
+
+DEF_OP(XGETBV) {
+  auto Op = IROp->C<IR::IROp_XGetBV>();
+
+  PushDynamicRegsAndLR(TMP1);
+  SpillStaticRegs(TMP1);
+
+  // x0 = CPUID Handler
+  // x1 = XCR Function
+  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj));
+  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.XCRFunction));
+  mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, GetReg(Op->Function.ID()));
+#ifdef VIXL_SIMULATOR
+  GenerateIndirectRuntimeCall<uint64_t, void*, uint32_t>(ARMEmitter::Reg::r2);
+#else
+  blr(ARMEmitter::Reg::r2);
+#endif
+
+  FillStaticRegs();
+
+  PopDynamicRegsAndLR();
+
+  // Results are in x0
+  // Results want to be in a i32v2 vector
+  auto Dst = GetRegPair(Node);
+  mov(ARMEmitter::Size::i32Bit, Dst.first,  ARMEmitter::Reg::r0);
+  lsr(ARMEmitter::Size::i64Bit, Dst.second, ARMEmitter::Reg::r0, 32);
 }
 
 #undef DEF_OP
-void Arm64JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(SIGNALRETURN,      SignalReturn);
-  REGISTER_OP(CALLBACKRETURN,    CallbackReturn);
-  REGISTER_OP(EXITFUNCTION,      ExitFunction);
-  REGISTER_OP(JUMP,              Jump);
-  REGISTER_OP(CONDJUMP,          CondJump);
-  REGISTER_OP(SYSCALL,           Syscall);
-  REGISTER_OP(INLINESYSCALL,     InlineSyscall);
-  REGISTER_OP(THUNK,             Thunk);
-  REGISTER_OP(VALIDATECODE,      ValidateCode);
-  REGISTER_OP(THREADREMOVECODEENTRY,   ThreadRemoveCodeEntry);
-  REGISTER_OP(CPUID,             CPUID);
-#undef REGISTER_OP
-}
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp

@@ -4,13 +4,11 @@ tags: backend|arm64
 $end_info$
 */
 
+#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
-
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 DEF_OP(VInsGPR) {
   const auto Op = IROp->C<IR::IROp_VInsGPR>();
   const auto OpSize = IROp->Size;
@@ -19,8 +17,16 @@ DEF_OP(VInsGPR) {
   const auto ElementSize = Op->Header.ElementSize;
   const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
 
-  const auto Dst = GetDst(Node);
-  const auto DestVector = GetSrc(Op->DestVector.ID());
+  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2 || ElementSize == 1, "Unexpected {} size", __func__);
+  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit : ARMEmitter::SubRegSize::i8Bit;
+  const auto ElementsPer128Bit = 16 / ElementSize;
+
+  const auto Dst = GetVReg(Node);
+  const auto DestVector = GetVReg(Op->DestVector.ID());
+  const auto Src = GetReg(Op->Src.ID());
 
   if (HostSupportsSVE && Is256Bit) {
     const auto ElementSizeBits = ElementSize * 8;
@@ -47,125 +53,111 @@ DEF_OP(VInsGPR) {
 
     if (InUpperLane) {
       // Move the upper lane down for the insertion.
-      const auto CompactPred = p0;
-      not_(CompactPred.VnB(), PRED_TMP_32B.Zeroing(), PRED_TMP_16B.VnB());
-      compact(VTMP1.Z().VnD(), CompactPred, DestVector.Z().VnD());
+      const auto CompactPred = ARMEmitter::PReg::p0;
+      not_(CompactPred, PRED_TMP_32B.Zeroing(), PRED_TMP_16B);
+      compact(ARMEmitter::SubRegSize::i64Bit, VTMP1.Z(), CompactPred, DestVector.Z());
     }
 
     // Put data in place for destructive SPLICE below.
-    mov(Dst.Z().VnD(), DestVector.Z().VnD());
+    mov(Dst.Z(), DestVector.Z());
 
     // Inserts the GPR value into the given V register.
     // Also automatically adjusts the index in the case of using the
     // moved upper lane.
-    const auto Insert = [&](const aarch64::VRegister& reg, int index) {
-      switch (ElementSize) {
-        case 1:
-          if (InUpperLane) {
-            index -= 16;
-          }
-          ins(reg.V16B(), index, GetReg<RA_32>(Op->Src.ID()));
-          break;
-        case 2:
-          if (InUpperLane) {
-            index -= 8;
-          }
-          ins(reg.V8H(), index, GetReg<RA_32>(Op->Src.ID()));
-          break;
-        case 4:
-          if (InUpperLane) {
-            index -= 4;
-          }
-          ins(reg.V4S(), index, GetReg<RA_32>(Op->Src.ID()));
-          break;
-        case 8:
-          if (InUpperLane) {
-            index -= 2;
-          }
-          ins(reg.V2D(), index, GetReg<RA_64>(Op->Src.ID()));
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
-          break;
+    const auto Insert = [&](const FEXCore::ARMEmitter::VRegister& reg, int index) {
+      if (InUpperLane) {
+        index -= ElementsPer128Bit;
       }
+      ins(SubEmitSize, reg, index, Src);
     };
 
     if (InUpperLane) {
       Insert(VTMP1, DestIdx);
-      splice(Dst.Z().VnD(), PRED_TMP_16B, Dst.Z().VnD(), VTMP1.Z().VnD());
+      splice<ARMEmitter::OpType::Destructive>(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), PRED_TMP_16B, Dst.Z(), VTMP1.Z());
     } else {
       Insert(Dst, DestIdx);
-      splice(Dst.Z().VnD(), PRED_TMP_16B, Dst.Z().VnD(), DestVector.Z().VnD());
+      splice<ARMEmitter::OpType::Destructive>(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), PRED_TMP_16B, Dst.Z(), DestVector.Z());
     }
   } else {
-    mov(Dst, DestVector);
-
-    switch (ElementSize) {
-      case 1: {
-        ins(Dst.V16B(), DestIdx, GetReg<RA_32>(Op->Src.ID()));
-        break;
-      }
-      case 2: {
-        ins(Dst.V8H(), DestIdx, GetReg<RA_32>(Op->Src.ID()));
-        break;
-      }
-      case 4: {
-        ins(Dst.V4S(), DestIdx, GetReg<RA_32>(Op->Src.ID()));
-        break;
-      }
-      case 8: {
-        ins(Dst.V2D(), DestIdx, GetReg<RA_64>(Op->Src.ID()));
-        break;
-      }
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
-        break;
-    }
+    mov(Dst.Q(), DestVector.Q());
+    ins(SubEmitSize, Dst, DestIdx, Src);
   }
 }
 
 DEF_OP(VCastFromGPR) {
   auto Op = IROp->C<IR::IROp_VCastFromGPR>();
+  auto Dst = GetVReg(Node);
+  auto Src = GetReg(Op->Src.ID());
+
   switch (Op->Header.ElementSize) {
     case 1:
-      uxtb(TMP1.W(), GetReg<RA_32>(Op->Src.ID()));
-      fmov(GetDst(Node).S(), TMP1.W());
+      uxtb(ARMEmitter::Size::i32Bit, TMP1, Src);
+      fmov(ARMEmitter::Size::i32Bit, Dst.S(), TMP1);
       break;
     case 2:
-      uxth(TMP1.W(), GetReg<RA_32>(Op->Src.ID()));
-      fmov(GetDst(Node).S(), TMP1.W());
+      uxth(ARMEmitter::Size::i32Bit, TMP1, Src);
+      fmov(ARMEmitter::Size::i32Bit, Dst.S(), TMP1);
       break;
     case 4:
-      fmov(GetDst(Node).S(), GetReg<RA_32>(Op->Src.ID()).W());
+      fmov(ARMEmitter::Size::i32Bit, Dst.S(), Src);
       break;
     case 8:
-      fmov(GetDst(Node).D(), GetReg<RA_64>(Op->Src.ID()).X());
+      fmov(ARMEmitter::Size::i64Bit, Dst.D(), Src);
       break;
     default: LOGMAN_MSG_A_FMT("Unknown castGPR element size: {}", Op->Header.ElementSize);
   }
 }
 
+DEF_OP(VDupFromGPR) {
+  const auto Op = IROp->C<IR::IROp_VDupFromGPR>();
+  const auto OpSize = IROp->Size;
+
+  const auto Dst = GetVReg(Node);
+  const auto Src = GetReg(Op->Src.ID());
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = IROp->ElementSize;
+
+  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2 || ElementSize == 1,
+                      "Unexpected {} element size: {}", __func__, ElementSize);
+
+  const auto SubEmitSize =
+    ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit : ARMEmitter::SubRegSize::i8Bit;
+
+  if (HostSupportsSVE && Is256Bit) {
+    dup(SubEmitSize, Dst.Z(), Src);
+  } else {
+    dup(SubEmitSize, Dst.Q(), Src);
+  }
+}
+
 DEF_OP(Float_FromGPR_S) {
   const auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
 
   const uint16_t ElementSize = Op->Header.ElementSize;
   const uint16_t Conv = (ElementSize << 8) | Op->SrcElementSize;
 
+  auto Dst = GetVReg(Node);
+  auto Src = GetReg(Op->Src.ID());
+
   switch (Conv) {
     case 0x0404: { // Float <- int32_t
-      scvtf(GetDst(Node).S(), GetReg<RA_32>(Op->Src.ID()));
+      scvtf(ARMEmitter::Size::i32Bit, Dst.S(), Src);
       break;
     }
     case 0x0408: { // Float <- int64_t
-      scvtf(GetDst(Node).S(), GetReg<RA_64>(Op->Src.ID()));
+      scvtf(ARMEmitter::Size::i64Bit, Dst.S(), Src);
       break;
     }
     case 0x0804: { // Double <- int32_t
-      scvtf(GetDst(Node).D(), GetReg<RA_32>(Op->Src.ID()));
+      scvtf(ARMEmitter::Size::i32Bit, Dst.D(), Src);
       break;
     }
     case 0x0808: { // Double <- int64_t
-      scvtf(GetDst(Node).D(), GetReg<RA_64>(Op->Src.ID()));
+      scvtf(ARMEmitter::Size::i64Bit, Dst.D(), Src);
       break;
     }
     default:
@@ -178,13 +170,17 @@ DEF_OP(Float_FromGPR_S) {
 DEF_OP(Float_FToF) {
   auto Op = IROp->C<IR::IROp_Float_FToF>();
   const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+
+  auto Dst = GetVReg(Node);
+  auto Src = GetVReg(Op->Scalar.ID());
+
   switch (Conv) {
     case 0x0804: { // Double <- Float
-      fcvt(GetDst(Node).D(), GetSrc(Op->Scalar.ID()).S());
+      fcvt(Dst.D(), Src.S());
       break;
     }
     case 0x0408: { // Float <- Double
-      fcvt(GetDst(Node).S(), GetSrc(Op->Scalar.ID()).D());
+      fcvt(Dst.S(), Src.D());
       break;
     }
     default: LOGMAN_MSG_A_FMT("Unknown FCVT sizes: 0x{:x}", Conv);
@@ -198,41 +194,18 @@ DEF_OP(Vector_SToF) {
   const auto ElementSize = Op->Header.ElementSize;
   const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
 
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
+  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
+  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i16Bit;
 
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
   if (HostSupportsSVE && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
-    switch (ElementSize) {
-      case 2:
-        scvtf(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-        break;
-      case 4:
-        scvtf(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-        break;
-      case 8:
-        scvtf(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", ElementSize);
-        break;
-    }
+    const auto Mask = PRED_TMP_32B;
+    scvtf(Dst.Z(), SubEmitSize, Mask.Merging(), Vector.Z(), SubEmitSize);
   } else {
-    switch (ElementSize) {
-      case 2:
-        scvtf(Dst.V8H(), Vector.V8H());
-        break;
-      case 4:
-        scvtf(Dst.V4S(), Vector.V4S());
-        break;
-      case 8:
-        scvtf(Dst.V2D(), Vector.V2D());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", ElementSize);
-        break;
-    }
+    scvtf(SubEmitSize, Dst.Q(), Vector.Q());
   }
 }
 
@@ -243,41 +216,18 @@ DEF_OP(Vector_FToZS) {
   const auto ElementSize = Op->Header.ElementSize;
   const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
 
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
+  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
+  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i16Bit;
 
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
   if (HostSupportsSVE && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
-    switch (ElementSize) {
-      case 2:
-        fcvtzs(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-        break;
-      case 4:
-        fcvtzs(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-        break;
-      case 8:
-        fcvtzs(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", ElementSize);
-        break;
-    }
+    const auto Mask = PRED_TMP_32B;
+    fcvtzs(Dst.Z(), SubEmitSize, Mask.Merging(), Vector.Z(), SubEmitSize);
   } else {
-    switch (ElementSize) {
-      case 2:
-        fcvtzs(Dst.V8H(), Vector.V8H());
-        break;
-      case 4:
-        fcvtzs(Dst.V4S(), Vector.V4S());
-        break;
-      case 8:
-        fcvtzs(Dst.V2D(), Vector.V2D());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", ElementSize);
-        break;
-    }
+    fcvtzs(SubEmitSize, Dst.Q(), Vector.Q());
   }
 }
 
@@ -288,47 +238,23 @@ DEF_OP(Vector_FToS) {
   const auto ElementSize = Op->Header.ElementSize;
   const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
 
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
+  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
+  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i16Bit;
+
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
 
   if (HostSupportsSVE && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
-    switch (ElementSize) {
-      case 2:
-        frinti(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-        fcvtzs(Dst.Z().VnH(), Mask, Dst.Z().VnH());
-        break;
-      case 4:
-        frinti(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-        fcvtzs(Dst.Z().VnS(), Mask, Dst.Z().VnS());
-        break;
-      case 8:
-        frinti(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-        fcvtzs(Dst.Z().VnD(), Mask, Dst.Z().VnD());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", ElementSize);
-        break;
-    }
+    const auto Mask = PRED_TMP_32B;
+    frinti(SubEmitSize, Dst.Z(), Mask.Merging(), Vector.Z());
+    fcvtzs(Dst.Z(), SubEmitSize, Mask.Merging(), Dst.Z(), SubEmitSize);
   } else {
-    switch (ElementSize) {
-      case 2:
-        frinti(Dst.V8H(), Vector.V8H());
-        fcvtzs(Dst.V8H(), Dst.V8H());
-        break;
-      case 4:
-        frinti(Dst.V4S(), Vector.V4S());
-        fcvtzs(Dst.V4S(), Dst.V4S());
-        break;
-      case 8:
-        frinti(Dst.V2D(), Vector.V2D());
-        fcvtzs(Dst.V2D(), Dst.V2D());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", ElementSize);
-        break;
-    }
+    const auto Dst = GetVReg(Node);
+    const auto Vector = GetVReg(Op->Vector.ID());
+    frinti(SubEmitSize, Dst.Q(), Vector.Q());
+    fcvtzs(SubEmitSize, Dst.Q(), Dst.Q());
   }
 }
 
@@ -340,8 +266,13 @@ DEF_OP(Vector_FToF) {
   const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
   const auto Conv = (ElementSize << 8) | Op->SrcElementSize;
 
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
+  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
+  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i16Bit;
+
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
 
   if (HostSupportsSVE && Is256Bit) {
     // Curiously, FCVTLT and FCVTNT have no bottom variants,
@@ -361,23 +292,23 @@ DEF_OP(Vector_FToF) {
 
     switch (Conv) {
       case 0x0402: { // Float <- Half
-        zip1(Dst.Z().VnH(), Vector.Z().VnH(), Vector.Z().VnH());
-        fcvtlt(Dst.Z().VnS(), Mask, Dst.Z().VnH());
+        zip1(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Vector.Z(), Vector.Z());
+        fcvtlt(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Dst.Z());
         break;
       }
       case 0x0804: { // Double <- Float
-        zip1(Dst.Z().VnS(), Vector.Z().VnS(), Vector.Z().VnS());
-        fcvtlt(Dst.Z().VnD(), Mask, Dst.Z().VnS());
+        zip1(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Vector.Z(), Vector.Z());
+        fcvtlt(FEXCore::ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Dst.Z());
         break;
       }
       case 0x0204: { // Half <- Float
-        fcvtnt(Dst.Z().VnH(), Mask, Vector.Z().VnS());
-        uzp2(Dst.Z().VnH(), Dst.Z().VnH(), Dst.Z().VnH());
+        fcvtnt(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Mask, Vector.Z());
+        uzp2(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Dst.Z(), Dst.Z());
         break;
       }
       case 0x0408: { // Float <- Double
-        fcvtnt(Dst.Z().VnS(), Mask, Vector.Z().VnD());
-        uzp2(Dst.Z().VnS(), Dst.Z().VnS(), Dst.Z().VnS());
+        fcvtnt(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Vector.Z());
+        uzp2(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Dst.Z(), Dst.Z());
         break;
       }
       default:
@@ -386,20 +317,14 @@ DEF_OP(Vector_FToF) {
     }
   } else {
     switch (Conv) {
-      case 0x0402: { // Float <- Half
-        fcvtl(Dst.V4S(), Vector.V4H());
-        break;
-      }
+      case 0x0402: // Float <- Half
       case 0x0804: { // Double <- Float
-        fcvtl(Dst.V2D(), Vector.V2S());
-        break;
-      }
-      case 0x0204: { // Half <- Float
-        fcvtn(Dst.V4H(), Vector.V4S());
+        fcvtl(SubEmitSize, Dst.D(), Vector.D());
         break;
       }
+      case 0x0204: // Half <- Float
       case 0x0408: { // Float <- Double
-        fcvtn(Dst.V2S(), Vector.V2D());
+        fcvtn(SubEmitSize, Dst.D(), Vector.D());
         break;
       }
       default:
@@ -415,172 +340,56 @@ DEF_OP(Vector_FToI) {
 
   const auto ElementSize = Op->Header.ElementSize;
   const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
 
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
+  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i16Bit;
+
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
 
   if (HostSupportsSVE && Is256Bit) {
     const auto Mask = PRED_TMP_32B.Merging();
-    
+
     switch (Op->Round) {
       case FEXCore::IR::Round_Nearest.Val:
-        switch (ElementSize) {
-          case 2:
-            frintn(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frintn(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frintn(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
+        frintn(SubEmitSize, Dst.Z(), Mask, Vector.Z());
         break;
-
       case FEXCore::IR::Round_Negative_Infinity.Val:
-        switch (ElementSize) {
-          case 2:
-            frintm(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frintm(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frintm(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
+        frintm(SubEmitSize, Dst.Z(), Mask, Vector.Z());
         break;
-
       case FEXCore::IR::Round_Positive_Infinity.Val:
-        switch (ElementSize) {
-          case 2:
-            frintp(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frintp(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frintp(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
+        frintp(SubEmitSize, Dst.Z(), Mask, Vector.Z());
         break;
-
       case FEXCore::IR::Round_Towards_Zero.Val:
-        switch (ElementSize) {
-          case 2:
-            frintz(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frintz(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frintz(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
+        frintz(SubEmitSize, Dst.Z(), Mask, Vector.Z());
         break;
-
       case FEXCore::IR::Round_Host.Val:
-        switch (ElementSize) {
-          case 2:
-            frinti(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frinti(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frinti(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
+        frinti(SubEmitSize, Dst.Z(), Mask, Vector.Z());
         break;
     }
   } else {
     switch (Op->Round) {
       case FEXCore::IR::Round_Nearest.Val:
-        switch (ElementSize) {
-          case 2:
-            frintn(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frintn(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frintn(Dst.V2D(), Vector.V2D());
-            break;
-        }
+        frinti(SubEmitSize, Dst.Q(), Vector.Q());
         break;
-
       case FEXCore::IR::Round_Negative_Infinity.Val:
-        switch (ElementSize) {
-          case 2:
-            frintm(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frintm(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frintm(Dst.V2D(), Vector.V2D());
-            break;
-        }
+        frintm(SubEmitSize, Dst.Q(), Vector.Q());
         break;
-
       case FEXCore::IR::Round_Positive_Infinity.Val:
-        switch (ElementSize) {
-          case 2:
-            frintp(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frintp(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frintp(Dst.V2D(), Vector.V2D());
-            break;
-        }
+        frintp(SubEmitSize, Dst.Q(), Vector.Q());
         break;
-
       case FEXCore::IR::Round_Towards_Zero.Val:
-        switch (ElementSize) {
-          case 2:
-            frintz(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frintz(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frintz(Dst.V2D(), Vector.V2D());
-            break;
-        }
+        frintz(SubEmitSize, Dst.Q(), Vector.Q());
         break;
-
       case FEXCore::IR::Round_Host.Val:
-        switch (ElementSize) {
-          case 2:
-            frinti(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frinti(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frinti(Dst.V2D(), Vector.V2D());
-            break;
-        }
+        frinti(SubEmitSize, Dst.Q(), Vector.Q());
         break;
     }
   }
 }
 
 #undef DEF_OP
-void Arm64JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(VINSGPR,         VInsGPR);
-  REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
-  REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
-  REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
-  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
-#undef REGISTER_OP
-}
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp

@@ -4,125 +4,170 @@ tags: backend|arm64
 $end_info$
 */
 
+#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
-  aesimc(GetDst(Node).V16B(), GetSrc(Op->Vector.ID()).V16B());
+  aesimc(GetVReg(Node), GetVReg(Op->Vector.ID()));
 }
 
 DEF_OP(AESEnc) {
-	auto Op = IROp->C<IR::IROp_VAESEnc>();
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->State.ID()).V16B());
-  aese(VTMP1.V16B(), VTMP2.V16B());
-  aesmc(VTMP1.V16B(), VTMP1.V16B());
-  eor(GetDst(Node).V16B(), VTMP1.V16B(), GetSrc(Op->Key.ID()).V16B());
+  const auto Op = IROp->C<IR::IROp_VAESEnc>();
+  const auto OpSize = IROp->Size;
+
+  const auto Dst = GetVReg(Node);
+  const auto Key = GetVReg(Op->Key.ID());
+  const auto State = GetVReg(Op->State.ID());
+
+  LOGMAN_THROW_AA_FMT(OpSize == Core::CPUState::XMM_SSE_REG_SIZE,
+                      "Currently only supports 128-bit operations.");
+
+  eor(VTMP2.Q(), VTMP2.Q(), VTMP2.Q());
+  mov(VTMP1.Q(), State.Q());
+  aese(VTMP1, VTMP2);
+  aesmc(VTMP1, VTMP1);
+  eor(Dst.Q(), VTMP1.Q(), Key.Q());
 }
 
 DEF_OP(AESEncLast) {
-	auto Op = IROp->C<IR::IROp_VAESEncLast>();
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->State.ID()).V16B());
-  aese(VTMP1.V16B(), VTMP2.V16B());
-  eor(GetDst(Node).V16B(), VTMP1.V16B(), GetSrc(Op->Key.ID()).V16B());
+  const auto Op = IROp->C<IR::IROp_VAESEncLast>();
+  const auto OpSize = IROp->Size;
+
+  const auto Dst = GetVReg(Node);
+  const auto Key = GetVReg(Op->Key.ID());
+  const auto State = GetVReg(Op->State.ID());
+
+  LOGMAN_THROW_AA_FMT(OpSize == Core::CPUState::XMM_SSE_REG_SIZE,
+                      "Currently only supports 128-bit operations.");
+
+  eor(VTMP2.Q(), VTMP2.Q(), VTMP2.Q());
+  mov(VTMP1.Q(), State.Q());
+  aese(VTMP1, VTMP2);
+  eor(Dst.Q(), VTMP1.Q(), Key.Q());
 }
 
 DEF_OP(AESDec) {
-	auto Op = IROp->C<IR::IROp_VAESDec>();
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->State.ID()).V16B());
-  aesd(VTMP1.V16B(), VTMP2.V16B());
-  aesimc(VTMP1.V16B(), VTMP1.V16B());
-  eor(GetDst(Node).V16B(), VTMP1.V16B(), GetSrc(Op->Key.ID()).V16B());
+  const auto Op = IROp->C<IR::IROp_VAESDec>();
+  const auto OpSize = IROp->Size;
+
+  const auto Dst = GetVReg(Node);
+  const auto Key = GetVReg(Op->Key.ID());
+  const auto State = GetVReg(Op->State.ID());
+
+  LOGMAN_THROW_AA_FMT(OpSize == Core::CPUState::XMM_SSE_REG_SIZE,
+                      "Currently only supports 128-bit operations.");
+
+  eor(VTMP2.Q(), VTMP2.Q(), VTMP2.Q());
+  mov(VTMP1.Q(), State.Q());
+  aesd(VTMP1, VTMP2);
+  aesimc(VTMP1, VTMP1);
+  eor(Dst.Q(), VTMP1.Q(), Key.Q());
 }
 
 DEF_OP(AESDecLast) {
-	auto Op = IROp->C<IR::IROp_VAESDecLast>();
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->State.ID()).V16B());
-  aesd(VTMP1.V16B(), VTMP2.V16B());
-  eor(GetDst(Node).V16B(), VTMP1.V16B(), GetSrc(Op->Key.ID()).V16B());
+  const auto Op = IROp->C<IR::IROp_VAESDecLast>();
+  const auto OpSize = IROp->Size;
+
+  const auto Dst = GetVReg(Node);
+  const auto Key = GetVReg(Op->Key.ID());
+  const auto State = GetVReg(Op->State.ID());
+
+  LOGMAN_THROW_AA_FMT(OpSize == Core::CPUState::XMM_SSE_REG_SIZE,
+                      "Currently only supports 128-bit operations.");
+
+  eor(VTMP2.Q(), VTMP2.Q(), VTMP2.Q());
+  mov(VTMP1.Q(), State.Q());
+  aesd(VTMP1, VTMP2);
+  eor(Dst.Q(), VTMP1.Q(), Key.Q());
 }
 
 DEF_OP(AESKeyGenAssist) {
-	auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
+  auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
 
-  aarch64::Literal ConstantLiteral (0x0C030609'0306090CULL, 0x040B0E01'0B0E0104ULL);
-  aarch64::Label PastConstant;
+  ARMEmitter::ForwardLabel Constant;
+  ARMEmitter::ForwardLabel PastConstant;
 
   // Do a "regular" AESE step
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->Src.ID()).V16B());
-  aese(VTMP1.V16B(), VTMP2.V16B());
+  eor(VTMP2.Q(), VTMP2.Q(), VTMP2.Q());
+  mov(VTMP1.Q(), GetVReg(Op->Src.ID()).Q());
+  aese(VTMP1, VTMP2);
 
   // Do a table shuffle to undo ShiftRows
-  ldr(VTMP3, &ConstantLiteral);
+  ldr(VTMP3.Q(), &Constant);
 
   // Now EOR in the RCON
   if (Op->RCON) {
-    tbl(VTMP1.V16B(), VTMP1.V16B(), VTMP3.V16B());
+    tbl(VTMP1.Q(), VTMP1.Q(), VTMP3.Q());
 
-    LoadConstant(TMP1.W(), Op->RCON);
-    ins(VTMP2.V4S(), 1, TMP1.W());
-    ins(VTMP2.V4S(), 3, TMP1.W());
-    eor(GetDst(Node).V16B(), VTMP1.V16B(), VTMP2.V16B());
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP1, static_cast<uint64_t>(Op->RCON) << 32);
+    dup(ARMEmitter::SubRegSize::i64Bit, VTMP2.Q(), TMP1);
+    eor(GetVReg(Node).Q(), VTMP1.Q(), VTMP2.Q());
   }
   else {
-    tbl(GetDst(Node).V16B(), VTMP1.V16B(), VTMP3.V16B());
+    tbl(GetVReg(Node).Q(), VTMP1.Q(), VTMP3.Q());
   }
 
   b(&PastConstant);
-  place(&ConstantLiteral);
-  bind(&PastConstant);
+  Bind(&Constant);
+  dc64(0x040B0E01'0B0E0104ULL);
+  dc64(0x0C030609'0306090CULL);
+  Bind(&PastConstant);
 }
 
 DEF_OP(CRC32) {
   auto Op = IROp->C<IR::IROp_CRC32>();
+
+  const auto Dst = GetReg(Node);
+  const auto Src1 = GetReg(Op->Src1.ID());
+  const auto Src2 = GetReg(Op->Src2.ID());
+
   switch (Op->SrcSize) {
     case 1:
-      crc32cb(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      crc32cb(Dst.W(), Src1.W(), Src2.W());
       break;
     case 2:
-      crc32ch(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      crc32ch(Dst.W(), Src1.W(), Src2.W());
       break;
     case 4:
-      crc32cw(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      crc32cw(Dst.W(), Src1.W(), Src2.W());
       break;
     case 8:
-      crc32cx(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_64>(Op->Src2.ID()));
+      crc32cx(Dst.X(), Src1.X(), Src2.X());
       break;
     default: LOGMAN_MSG_A_FMT("Unknown CRC32 size: {}", Op->SrcSize);
   }
 }
 
 DEF_OP(PCLMUL) {
-  auto Op = IROp->C<IR::IROp_PCLMUL>();
+  const auto Op = IROp->C<IR::IROp_PCLMUL>();
+  const auto OpSize = IROp->Size;
 
-  auto Dst  = GetDst(Node).Q();
-  auto Src1 = GetSrc(Op->Src1.ID()).V2D();
-  auto Src2 = GetSrc(Op->Src2.ID()).V2D();
+  const auto Dst  = GetVReg(Node);
+  const auto Src1 = GetVReg(Op->Src1.ID());
+  const auto Src2 = GetVReg(Op->Src2.ID());
+
+  LOGMAN_THROW_AA_FMT(OpSize == Core::CPUState::XMM_SSE_REG_SIZE,
+                      "Currently only supports 128-bit operations.");
 
   switch (Op->Selector) {
   case 0b00000000:
-    pmull(Dst, Src1, Src2);
+    pmull(ARMEmitter::SubRegSize::i128Bit, Dst.D(), Src1.D(), Src2.D());
     break;
   case 0b00000001:
-    mov(VTMP1.V1D(), Src1, 1);
-    pmull(Dst, VTMP1.V2D(), Src2);
+    dup(ARMEmitter::SubRegSize::i64Bit, VTMP1.Q(), Src1.Q(), 1);
+    pmull(ARMEmitter::SubRegSize::i128Bit, Dst.D(), VTMP1.D(), Src2.D());
     break;
   case 0b00010000:
-    mov(VTMP1.V1D(), Src2, 1);
-    pmull(Dst, VTMP1.V2D(), Src1);
+    dup(ARMEmitter::SubRegSize::i64Bit, VTMP1.Q(), Src2.Q(), 1);
+    pmull(ARMEmitter::SubRegSize::i128Bit, Dst.D(), VTMP1.D(), Src1.D());
     break;
   case 0b00010001:
-    pmull2(Dst, Src1, Src2);
+    pmull2(ARMEmitter::SubRegSize::i128Bit, Dst.Q(), Src1.Q(), Src2.Q());
     break;
   default:
     LOGMAN_MSG_A_FMT("Unknown PCLMUL selector: {}", Op->Selector);
@@ -131,16 +176,4 @@ DEF_OP(PCLMUL) {
 }
 
 #undef DEF_OP
-void Arm64JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(VAESIMC,           AESImc);
-  REGISTER_OP(VAESENC,           AESEnc);
-  REGISTER_OP(VAESENCLAST,       AESEncLast);
-  REGISTER_OP(VAESDEC,           AESDec);
-  REGISTER_OP(VAESDECLAST,       AESDecLast);
-  REGISTER_OP(VAESKEYGENASSIST,  AESKeyGenAssist);
-  REGISTER_OP(CRC32,             CRC32);
-  REGISTER_OP(PCLMUL,            PCLMUL);
-#undef REGISTER_OP
-}
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/FlagOps.cpp

@@ -7,20 +7,12 @@ $end_info$
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
-
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
-  ubfx(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Value.ID()), Op->Flag, 1);
+  ubfx(ARMEmitter::Size::i64Bit, GetReg(Node), GetReg(Op->Value.ID()), Op->Flag, 1);
 }
 
 #undef DEF_OP
-void Arm64JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(GETHOSTFLAG, GetHostFlag);
-#undef REGISTER_OP
-}
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -6,40 +6,40 @@ $end_info$
 
 #pragma once
 
-#include <FEXCore/IR/RegisterAllocationData.h>
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #include <aarch64/assembler-aarch64.h>
 #include <aarch64/disasm-aarch64.h>
 
+#include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
+#include <FEXCore/IR/RegisterAllocationData.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/vector.h>
 
 #include <array>
 #include <cstdint>
-#include <map>
 #include <utility>
-#include <vector>
 
 namespace FEXCore::Core {
   struct InternalThreadState;
 }
 
 namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-
 class Arm64JITCore final : public CPUBackend, public Arm64Emitter  {
 public:
-  explicit Arm64JITCore(FEXCore::Context::Context *ctx,
+  explicit Arm64JITCore(FEXCore::Context::ContextImpl *ctx,
                         FEXCore::Core::InternalThreadState *Thread);
   ~Arm64JITCore() override;
 
-  [[nodiscard]] std::string GetName() override { return "JIT"; }
+  [[nodiscard]] fextl::string GetName() override { return "JIT"; }
 
-  [[nodiscard]] void *CompileCode(uint64_t Entry,
+  [[nodiscard]] CPUBackend::CompiledCode CompileCode(uint64_t Entry,
                                   FEXCore::IR::IRListView const *IR,
                                   FEXCore::Core::DebugData *DebugData,
                                   FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) override;
@@ -50,70 +50,71 @@ public:
 
   void ClearCache() override;
 
-  static void InitializeSignalHandlers(FEXCore::Context::Context *CTX);
-
   void ClearRelocations() override { Relocations.clear(); }
 
 private:
   FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
   const bool HostSupportsSVE{};
 
-  Label *PendingTargetLabel;
-  FEXCore::Context::Context *CTX;
+  ARMEmitter::BiDirectionalLabel *PendingTargetLabel;
+  FEXCore::Context::ContextImpl *CTX;
   FEXCore::IR::IRListView const *IR;
   uint64_t Entry;
+  CPUBackend::CompiledCode CodeData{};
 
-  std::map<IR::NodeID, aarch64::Label> JumpTargets;
+  fextl::map<IR::NodeID, ARMEmitter::BiDirectionalLabel> JumpTargets;
 
-  /**
-   * @name Register Allocation
-   * @{ */
-  constexpr static uint32_t NumGPRs = RA64.size();
-  constexpr static uint32_t NumFPRs = RAFPR.size();
-  constexpr static uint32_t NumGPRPairs = RA64Pair.size();
-  constexpr static uint32_t NumCalleeGPRs = 10;
-  constexpr static uint32_t NumCalleeGPRPairs = 5;
-  constexpr static uint32_t RegisterCount = NumGPRs + NumFPRs + NumGPRPairs;
-  constexpr static uint32_t RegisterClasses = 6;
+  [[nodiscard]] FEXCore::ARMEmitter::Register GetReg(IR::NodeID Node) const {
+    const auto Reg = GetPhys(Node);
 
-  constexpr static uint64_t GPRBase = (0ULL << 32);
-  constexpr static uint64_t FPRBase = (1ULL << 32);
-  constexpr static uint64_t GPRPairBase = (2ULL << 32);
+    LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class);
 
-  /**  @} */
+    if (Reg.Class == IR::GPRFixedClass.Val) {
+      return SRA64[Reg.Reg];
+    } else if (Reg.Class == IR::GPRClass.Val) {
+      return RA64[Reg.Reg];
+    }
 
-  constexpr static uint8_t RA_32 = 0;
-  constexpr static uint8_t RA_64 = 1;
-  constexpr static uint8_t RA_FPR = 2;
+    FEX_UNREACHABLE;
+  }
 
-  template<uint8_t RAType>
-  [[nodiscard]] aarch64::Register GetReg(IR::NodeID Node) const;
+  [[nodiscard]] FEXCore::ARMEmitter::VRegister GetVReg(IR::NodeID Node) const {
+    const auto Reg = GetPhys(Node);
 
-  template<>
-  [[nodiscard]] aarch64::Register GetReg<RA_32>(IR::NodeID Node) const;
-  template<>
-  [[nodiscard]] aarch64::Register GetReg<RA_64>(IR::NodeID Node) const;
+    LOGMAN_THROW_AA_FMT(Reg.Class == IR::FPRFixedClass.Val || Reg.Class == IR::FPRClass.Val, "Unexpected Class: {}", Reg.Class);
 
-  template<uint8_t RAType>
-  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair(IR::NodeID Node) const;
+    if (Reg.Class == IR::FPRFixedClass.Val) {
+      return SRAFPR[Reg.Reg];
+    } else if (Reg.Class == IR::FPRClass.Val) {
+      return RAFPR[Reg.Reg];
+    }
 
-  template<>
-  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(IR::NodeID Node) const;
-  template<>
-  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(IR::NodeID Node) const;
+    FEX_UNREACHABLE;
+  }
 
-  [[nodiscard]] aarch64::VRegister GetSrc(IR::NodeID Node) const;
-  [[nodiscard]] aarch64::VRegister GetDst(IR::NodeID Node) const;
+  [[nodiscard]] std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register> GetRegPair(IR::NodeID Node) const {
+    const auto Reg = GetPhys(Node);
+
+    LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRPairClass.Val, "Unexpected Class: {}", Reg.Class);
+
+    return RA64Pair[Reg.Reg];
+  }
 
   [[nodiscard]] FEXCore::IR::RegisterClassType GetRegClass(IR::NodeID Node) const;
 
-  [[nodiscard]] IR::PhysicalRegister GetPhys(IR::NodeID Node) const;
+  [[nodiscard]] IR::PhysicalRegister GetPhys(IR::NodeID Node) const {
+    auto PhyReg = RAData->GetNodeRegister(Node);
+
+    LOGMAN_THROW_A_FMT(!PhyReg.IsInvalid(), "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
+
+    return PhyReg;
+  }
 
   [[nodiscard]] bool IsFPR(IR::NodeID Node) const;
   [[nodiscard]] bool IsGPR(IR::NodeID Node) const;
 
-  [[nodiscard]] MemOperand GenerateMemOperand(uint8_t AccessSize,
-                                              aarch64::Register Base,
+  [[nodiscard]] FEXCore::ARMEmitter::ExtendedMemOperand GenerateMemOperand(uint8_t AccessSize,
+                                              FEXCore::ARMEmitter::Register Base,
                                               IR::OrderedNodeWrapper Offset,
                                               IR::MemOffsetType OffsetType,
                                               uint8_t OffsetScale);
@@ -123,8 +124,8 @@ private:
   //
   //       TMP1 is safe to use again once this memory operand is used with its
   //       equivalent loads or stores that this was called for.
-  [[nodiscard]] SVEMemOperand GenerateSVEMemOperand(uint8_t AccessSize,
-                                                    aarch64::Register Base,
+  [[nodiscard]] FEXCore::ARMEmitter::SVEMemOperand GenerateSVEMemOperand(uint8_t AccessSize,
+                                                    FEXCore::ARMEmitter::Register Base,
                                                     IR::OrderedNodeWrapper Offset,
                                                     IR::MemOffsetType OffsetType,
                                                     uint8_t OffsetScale);
@@ -162,7 +163,8 @@ private:
      * @brief A literal pair relocation object for named symbol literals
      */
     struct NamedSymbolLiteralPair {
-      Literal<uint64_t> Lit;
+      ARMEmitter::ForwardLabel Loc;
+      uint64_t Lit;
       Relocation MoveABI{};
     };
 
@@ -172,7 +174,7 @@ private:
      * @param Reg - The GPR to move the thunk handler in to
      * @param Sum - The hash of the thunk
      */
-    void InsertNamedThunkRelocation(vixl::aarch64::Register Reg, const IR::SHA256Sum &Sum);
+    void InsertNamedThunkRelocation(ARMEmitter::Register Reg, const IR::SHA256Sum &Sum);
 
     /**
      * @brief Inserts a guest GPR move relocation
@@ -180,7 +182,7 @@ private:
      * @param Reg - The GPR to move the guest RIP in to
      * @param Constant - The guest RIP that will be relocated
      */
-    void InsertGuestRIPMove(vixl::aarch64::Register Reg, uint64_t Constant);
+    void InsertGuestRIPMove(ARMEmitter::Register Reg, uint64_t Constant);
 
     /**
      * @brief Inserts a named symbol as a literal in memory
@@ -200,7 +202,7 @@ private:
      */
     void PlaceNamedSymbolLiteral(NamedSymbolLiteralPair &Lit);
 
-    std::vector<FEXCore::CPU::Relocation> Relocations;
+    fextl::vector<FEXCore::CPU::Relocation> Relocations;
 
     ///< Relocation code loading
     bool ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint64_t CursorEntry, size_t NumRelocations, const char* EntryRelocations);
@@ -208,24 +210,17 @@ private:
   /**  @} */
 
   uint32_t SpillSlots{};
-  /**
-  * @brief Current guest RIP entrypoint
-  */
-  uint8_t *GuestEntry{};
+  using OpType = void (Arm64JITCore::*)(IR::IROp_Header const *IROp, IR::NodeID Node);
 
-  using OpHandler = void (Arm64JITCore::*)(IR::IROp_Header *IROp, IR::NodeID Node);
-  std::array<OpHandler, IR::IROps::OP_LAST + 1> OpHandlers {};
-  void RegisterALUHandlers();
-  void RegisterAtomicHandlers();
-  void RegisterBranchHandlers();
-  void RegisterConversionHandlers();
-  void RegisterFlagHandlers();
-  void RegisterMemoryHandlers();
-  void RegisterMiscHandlers();
-  void RegisterMoveHandlers();
-  void RegisterVectorHandlers();
-  void RegisterEncryptionHandlers();
-#define DEF_OP(x) void Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
+  // Runtime selection;
+  // Load and store register style.
+  OpType RT_LoadRegister;
+  OpType RT_StoreRegister;
+  // Load and store TSO memory style
+  OpType RT_LoadMemTSO;
+  OpType RT_StoreMemTSO;
+
+#define DEF_OP(x) void Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 
   ///< Unhandled handler
   DEF_OP(Unhandled);
@@ -302,7 +297,6 @@ private:
   DEF_OP(AtomicFetchNeg);
 
   ///< Branch ops
-  DEF_OP(SignalReturn);
   DEF_OP(CallbackReturn);
   DEF_OP(ExitFunction);
   DEF_OP(Jump);
@@ -313,10 +307,12 @@ private:
   DEF_OP(ValidateCode);
   DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
+  DEF_OP(XGETBV);
 
   ///< Conversion ops
   DEF_OP(VInsGPR);
   DEF_OP(VCastFromGPR);
+  DEF_OP(VDupFromGPR);
   DEF_OP(Float_FromGPR_S);
   DEF_OP(Float_FToF);
   DEF_OP(Vector_SToF);
@@ -333,6 +329,8 @@ private:
   DEF_OP(StoreContext);
   DEF_OP(LoadRegister);
   DEF_OP(StoreRegister);
+  DEF_OP(LoadRegisterSRA);
+  DEF_OP(StoreRegisterSRA);
   DEF_OP(LoadContextIndexed);
   DEF_OP(StoreContextIndexed);
   DEF_OP(SpillRegister);
@@ -343,11 +341,14 @@ private:
   DEF_OP(StoreMem);
   DEF_OP(LoadMemTSO);
   DEF_OP(StoreMemTSO);
+  DEF_OP(VLoadVectorMasked);
+  DEF_OP(VStoreVectorMasked);
+  DEF_OP(MemSet);
+  DEF_OP(MemCpy);
   DEF_OP(ParanoidLoadMemTSO);
   DEF_OP(ParanoidStoreMemTSO);
-  DEF_OP(VLoadMemElement);
-  DEF_OP(VStoreMemElement);
   DEF_OP(CacheLineClear);
+  DEF_OP(CacheLineClean);
   DEF_OP(CacheLineZero);
 
   ///< Misc ops
@@ -408,6 +409,8 @@ private:
   DEF_OP(VZip2);
   DEF_OP(VUnZip);
   DEF_OP(VUnZip2);
+  DEF_OP(VTrn);
+  DEF_OP(VTrn2);
   DEF_OP(VBSL);
   DEF_OP(VCMPEQ);
   DEF_OP(VCMPEQZ);
@@ -430,8 +433,6 @@ private:
   DEF_OP(VInsElement);
   DEF_OP(VDupElement);
   DEF_OP(VExtr);
-  DEF_OP(VSLI);
-  DEF_OP(VSRI);
   DEF_OP(VUShrI);
   DEF_OP(VSShrI);
   DEF_OP(VShlI);

External/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp

@@ -4,32 +4,36 @@ tags: backend|arm64
 $end_info$
 */
 
+#ifndef _WIN32
 #include <syscall.h>
+#endif
+
+#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "FEXCore/Debug/InternalThreadState.h"
 
+#include <FEXCore/Core/SignalDelegator.h>
+
 namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 
 DEF_OP(GuestOpcode) {
   auto Op = IROp->C<IR::IROp_GuestOpcode>();
   // metadata
-  DebugData->GuestOpcodes.push_back({Op->GuestEntryOffset, GetCursorAddress<uint8_t*>() - GuestEntry});
+  DebugData->GuestOpcodes.push_back({Op->GuestEntryOffset, GetCursorAddress<uint8_t*>() - CodeData.BlockBegin});
 }
 
 DEF_OP(Fence) {
   auto Op = IROp->C<IR::IROp_Fence>();
   switch (Op->Fence) {
     case IR::Fence_Load.Val:
-      dmb(FullSystem, BarrierReads);
+      dmb(FEXCore::ARMEmitter::BarrierScope::LD);
       break;
     case IR::Fence_LoadStore.Val:
-      dmb(FullSystem, BarrierAll);
+      dmb(FEXCore::ARMEmitter::BarrierScope::SY);
       break;
     case IR::Fence_Store.Val:
-      dmb(FullSystem, BarrierWrites);
+      dmb(FEXCore::ARMEmitter::BarrierScope::ST);
       break;
     default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
   }
@@ -41,121 +45,124 @@ DEF_OP(Break) {
   // First we must reset the stack
   ResetStack();
 
-  LoadConstant(w1, 1);
-  strb(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.FaultToTopAndGeneratedException)));
-  LoadConstant(w1, Op->Reason.Signal);
-  strb(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.Signal)));
-  LoadConstant(w1, Op->Reason.TrapNumber);
-  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.TrapNo)));
-  LoadConstant(w1, Op->Reason.si_code);
-  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.si_code)));
-  LoadConstant(x1, Op->Reason.ErrorRegister);
-  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.err_code)));
+  Core::CpuStateFrame::SynchronousFaultDataStruct State = {
+    .FaultToTopAndGeneratedException = 1,
+    .Signal = Op->Reason.Signal,
+    .TrapNo = Op->Reason.TrapNumber,
+    .si_code = Op->Reason.si_code,
+    .err_code = Op->Reason.ErrorRegister,
+  };
+
+  uint64_t Constant{};
+  memcpy(&Constant, &State, sizeof(State));
+
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, Constant);
+  str(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData));
 
   switch (Op->Reason.Signal) {
-  case SIGILL:
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL)));
+  case Core::FAULT_SIGILL:
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL));
     br(TMP1);
     break;
-  case SIGTRAP:
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)));
+  case Core::FAULT_SIGTRAP:
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP));
     br(TMP1);
     break;
-  case SIGSEGV:
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV)));
+  case Core::FAULT_SIGSEGV:
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV));
     br(TMP1);
     break;
   default:
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)));
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP));
     br(TMP1);
     break;
   }
 }
 
 DEF_OP(GetRoundingMode) {
-  auto Dst = GetReg<RA_64>(Node);
-  mrs(Dst, FPCR);
-  lsr(Dst, Dst,  22);
+  auto Dst = GetReg(Node);
+  mrs(Dst, ARMEmitter::SystemRegister::FPCR);
+  lsr(ARMEmitter::Size::i64Bit, Dst, Dst, 22);
 
   // FTZ is already in the correct location
   // Rounding mode is different
-  and_(TMP1, Dst, 0b11);
+  and_(ARMEmitter::Size::i64Bit, TMP1, Dst, 0b11);
 
-  cmp(TMP1, 1);
-  LoadConstant(TMP3, IR::ROUND_MODE_POSITIVE_INFINITY);
-  csel(TMP2, TMP3, xzr, vixl::aarch64::Condition::eq);
+  cmp(ARMEmitter::Size::i64Bit, TMP1, 1);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP3, IR::ROUND_MODE_POSITIVE_INFINITY);
+  csel(ARMEmitter::Size::i64Bit, TMP2, TMP3, ARMEmitter::Reg::zr, ARMEmitter::Condition::CC_EQ);
 
-  cmp(TMP1, 2);
-  LoadConstant(TMP3, IR::ROUND_MODE_NEGATIVE_INFINITY);
-  csel(TMP2, TMP3, TMP2, vixl::aarch64::Condition::eq);
+  cmp(ARMEmitter::Size::i64Bit, TMP1, 2);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP3, IR::ROUND_MODE_NEGATIVE_INFINITY);
+  csel(ARMEmitter::Size::i64Bit, TMP2, TMP3, TMP2, ARMEmitter::Condition::CC_EQ);
 
-  cmp(TMP1, 3);
-  LoadConstant(TMP3, IR::ROUND_MODE_TOWARDS_ZERO);
-  csel(TMP2, TMP3, TMP2, vixl::aarch64::Condition::eq);
+  cmp(ARMEmitter::Size::i64Bit, TMP1, 3);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP3, IR::ROUND_MODE_TOWARDS_ZERO);
+  csel(ARMEmitter::Size::i64Bit, TMP2, TMP3, TMP2, ARMEmitter::Condition::CC_EQ);
 
-  orr(Dst, Dst, TMP2);
+  orr(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2.R());
 
-  bfi(Dst, TMP2, 0, 2);
+  bfi(ARMEmitter::Size::i64Bit, Dst, TMP2, 0, 2);
 }
 
 DEF_OP(SetRoundingMode) {
   auto Op = IROp->C<IR::IROp_SetRoundingMode>();
-  auto Src = GetReg<RA_64>(Op->RoundMode.ID());
+  auto Src = GetReg(Op->RoundMode.ID());
 
   // Setup the rounding flags correctly
-  and_(TMP1, Src, 0b11);
+  and_(ARMEmitter::Size::i64Bit, TMP1, Src, 0b11);
 
-  cmp(TMP1, IR::ROUND_MODE_POSITIVE_INFINITY);
-  LoadConstant(TMP3, 1);
-  csel(TMP2, TMP3, xzr, vixl::aarch64::Condition::eq);
+  cmp(ARMEmitter::Size::i64Bit, TMP1, IR::ROUND_MODE_POSITIVE_INFINITY);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP3, 1);
+  csel(ARMEmitter::Size::i64Bit, TMP2, TMP3, ARMEmitter::Reg::zr, ARMEmitter::Condition::CC_EQ);
 
-  cmp(TMP1, IR::ROUND_MODE_NEGATIVE_INFINITY);
-  LoadConstant(TMP3, 2);
-  csel(TMP2, TMP3, TMP2, vixl::aarch64::Condition::eq);
+  cmp(ARMEmitter::Size::i64Bit, TMP1, IR::ROUND_MODE_NEGATIVE_INFINITY);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP3, 2);
+  csel(ARMEmitter::Size::i64Bit, TMP2, TMP3, TMP2, ARMEmitter::Condition::CC_EQ);
 
-  cmp(TMP1, IR::ROUND_MODE_TOWARDS_ZERO);
-  LoadConstant(TMP3, 3);
-  csel(TMP2, TMP3, TMP2, vixl::aarch64::Condition::eq);
+  cmp(ARMEmitter::Size::i64Bit, TMP1, IR::ROUND_MODE_TOWARDS_ZERO);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP3, 3);
+  csel(ARMEmitter::Size::i64Bit, TMP2, TMP3, TMP2, ARMEmitter::Condition::CC_EQ);
 
-  mrs(TMP1, FPCR);
+  mrs(TMP1, ARMEmitter::SystemRegister::FPCR);
 
   // vixl simulator doesn't support anything beyond ties-to-even rounding
 #ifndef VIXL_SIMULATOR
   // Insert the rounding flags
-  bfi(TMP1, TMP2, 22, 2);
+  bfi(ARMEmitter::Size::i64Bit, TMP1, TMP2, 22, 2);
 #endif
 
   // Insert the FTZ flag
-  lsr(TMP2, Src, 2);
-  bfi(TMP1, TMP2, 24, 1);
+  lsr(ARMEmitter::Size::i64Bit, TMP2, Src, 2);
+  bfi(ARMEmitter::Size::i64Bit, TMP1, TMP2, 24, 1);
 
   // Now save the new FPCR
-  msr(FPCR, TMP1);
+  msr(ARMEmitter::SystemRegister::FPCR, TMP1);
 }
 
 DEF_OP(Print) {
   auto Op = IROp->C<IR::IROp_Print>();
 
-  PushDynamicRegsAndLR();
-  SpillStaticRegs();
+  PushDynamicRegsAndLR(TMP1);
+  SpillStaticRegs(TMP1);
 
   if (IsGPR(Op->Value.ID())) {
-    mov(x0, GetReg<RA_64>(Op->Value.ID()));
-    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintValue)));
+    mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GetReg(Op->Value.ID()));
+    ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintValue));
   }
   else {
-    fmov(x0, GetSrc(Op->Value.ID()).V1D());
-    // Bug in vixl that source vector needs to b V1D rather than V2D?
-    fmov(x1, GetSrc(Op->Value.ID()).V1D(), 1);
-    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintVectorValue)));
+    fmov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GetVReg(Op->Value.ID()), false);
+    fmov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, GetVReg(Op->Value.ID()), true);
+    ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintVectorValue));
   }
 
-  blr(x3);
+  blr(ARMEmitter::Reg::r3);
 
   FillStaticRegs();
   PopDynamicRegsAndLR();
 }
 
+#ifndef _WIN32
 DEF_OP(ProcessorID) {
   // We always need to spill x8 since we can't know if it is live at this SSA location
   uint32_t SpillMask = 1U << 8;
@@ -163,34 +170,34 @@ DEF_OP(ProcessorID) {
   // Ordering is incredibly important here
   // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
   // Only spill the registers that intersect with our usage
-  SpillStaticRegs(false, SpillMask);
+  SpillStaticRegs(TMP1, false, SpillMask);
 
   // Now that we are spilled, store in the state that we are in a syscall
   // Still without overwriting registers that matter
   // 16bit LoadConstant to be a single instruction
   // We must always spill at least one register (x8) so this value always has a bit set
   // This gives the signal handler a value to check to see if we are in a syscall at all
-  LoadConstant(x0, SpillMask & 0xFFFF);
-  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, SpillMask & 0xFFFF);
+  str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
 
   // Allocate some temporary space for storing the uint32_t CPU and Node IDs
-  sub(sp, sp, 16);
+  sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 16);
 
   // Load the getcpu syscall number
-  LoadConstant(x8, SYS_getcpu);
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r8, SYS_getcpu);
 
   // CPU pointer in x0
-  add(x0, sp, 0);
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, ARMEmitter::Reg::rsp, 0);
   // Node in x1
-  add(x1, sp, 4);
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::rsp, 4);
 
   svc(0);
   // On updated signal mask we can receive a signal RIGHT HERE
 
   // Load the values returned by the kernel
-  ldp(w0, w1, MemOperand(sp));
+  ldp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::WReg::w0, ARMEmitter::WReg::w1, ARMEmitter::Reg::rsp);
   // Deallocate stack space
-  sub(sp, sp, 16);
+  sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 16);
 
   // Now that we are done in the syscall we need to carefully peel back the state
   // First unspill the registers from before
@@ -198,60 +205,42 @@ DEF_OP(ProcessorID) {
 
   // Now the registers we've spilled are back in their original host registers
   // We can safely claim we are no longer in a syscall
-  str(xzr, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
-
+  str(ARMEmitter::XReg::zr, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
 
   // Now store the result in the destination in the expected format
   // uint32_t Res = (node << 12) | cpu;
   // CPU is in w0
   // Node is in w1
-  orr(GetReg<RA_64>(Node), x0, Operand(x1, LSL, 12));
+  orr(ARMEmitter::Size::i64Bit, GetReg(Node), ARMEmitter::Reg::r0, ARMEmitter::Reg::r1, ARMEmitter::ShiftType::LSL, 12);
 }
+#else
+DEF_OP(ProcessorID) {
+  ERROR_AND_DIE_FMT("Unsupported");
+}
+#endif
 
 DEF_OP(RDRAND) {
   auto Op = IROp->C<IR::IROp_RDRAND>();
 
   // Results are in x0, x1
   // Results want to be in a i64v2 vector
-  auto Dst = GetSrcPair<RA_64>(Node);
+  auto Dst = GetRegPair(Node);
 
   if (Op->GetReseeded) {
-    mrs(Dst.first, RNDRRS);
+    mrs(Dst.first, ARMEmitter::SystemRegister::RNDRRS);
   }
   else {
-    mrs(Dst.first, RNDR);
+    mrs(Dst.first, ARMEmitter::SystemRegister::RNDR);
   }
 
   // If the rng number is valid then NZCV is 0b0000, otherwise NZCV is 0b0100
-  cset(Dst.second, Condition::ne);
+  cset(ARMEmitter::Size::i64Bit, Dst.second, ARMEmitter::Condition::CC_NE);
 }
 
 DEF_OP(Yield) {
-  hint(SystemHint::YIELD);
+  yield();
 }
 
 #undef DEF_OP
-void Arm64JITCore::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(DUMMY,      NoOp);
-  REGISTER_OP(IRHEADER,   NoOp);
-  REGISTER_OP(CODEBLOCK,  NoOp);
-  REGISTER_OP(BEGINBLOCK, NoOp);
-  REGISTER_OP(ENDBLOCK,   NoOp);
-  REGISTER_OP(GUESTOPCODE, GuestOpcode);
-  REGISTER_OP(FENCE,      Fence);
-  REGISTER_OP(BREAK,      Break);
-  REGISTER_OP(PHI,        NoOp);
-  REGISTER_OP(PHIVALUE,   NoOp);
-  REGISTER_OP(PRINT,      Print);
-  REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
-  REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
-  REGISTER_OP(INVALIDATEFLAGS,   NoOp);
-  REGISTER_OP(PROCESSORID,   ProcessorID);
-  REGISTER_OP(RDRAND, RDRAND);
-  REGISTER_OP(YIELD, Yield);
-
-#undef REGISTER_OP
-}
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp

@@ -7,73 +7,40 @@ $end_info$
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
-
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 DEF_OP(ExtractElementPair) {
   auto Op = IROp->C<IR::IROp_ExtractElementPair>();
-  switch (Op->Header.Size) {
-    case 4: {
-      auto Src = GetSrcPair<RA_32>(Op->Pair.ID());
-      std::array<aarch64::Register, 2> Regs = {Src.first, Src.second};
-      mov (GetReg<RA_32>(Node), Regs[Op->Element]);
-      break;
-    }
-    case 8: {
-      auto Src = GetSrcPair<RA_64>(Op->Pair.ID());
-      std::array<aarch64::Register, 2> Regs = {Src.first, Src.second};
-      mov (GetReg<RA_64>(Node), Regs[Op->Element]);
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
-  }
+  LOGMAN_THROW_AA_FMT(Op->Header.Size == 4 || Op->Header.Size == 8, "Invalid size");
+  const auto EmitSize = Op->Header.Size == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  const auto Src = GetRegPair(Op->Pair.ID());
+  const std::array<ARMEmitter::Register, 2> Regs = {Src.first, Src.second};
+  mov(EmitSize, GetReg(Node), Regs[Op->Element]);
 }
 
 DEF_OP(CreateElementPair) {
   auto Op = IROp->C<IR::IROp_CreateElementPair>();
-  std::pair<aarch64::Register, aarch64::Register> Dst;
-  aarch64::Register RegFirst;
-  aarch64::Register RegSecond;
-  aarch64::Register RegTmp;
+  LOGMAN_THROW_AA_FMT(IROp->ElementSize == 4 || IROp->ElementSize == 8, "Invalid size");
+  std::pair<ARMEmitter::Register, ARMEmitter::Register> Dst = GetRegPair(Node);
+  ARMEmitter::Register RegFirst = GetReg(Op->Lower.ID());
+  ARMEmitter::Register RegSecond = GetReg(Op->Upper.ID());
+  ARMEmitter::Register RegTmp = TMP1.R();
 
-  switch (IROp->ElementSize) {
-    case 4: {
-      Dst = GetSrcPair<RA_32>(Node);
-      RegFirst = GetReg<RA_32>(Op->Lower.ID());
-      RegSecond = GetReg<RA_32>(Op->Upper.ID());
-      RegTmp = w0;
-      break;
-    }
-    case 8: {
-      Dst = GetSrcPair<RA_64>(Node);
-      RegFirst = GetReg<RA_64>(Op->Lower.ID());
-      RegSecond = GetReg<RA_64>(Op->Upper.ID());
-      RegTmp = x0;
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
-  }
+  const auto EmitSize = IROp->ElementSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
 
-  if (Dst.first.GetCode() != RegSecond.GetCode()) {
-    mov(Dst.first, RegFirst);
-    mov(Dst.second, RegSecond);
-  } else if (Dst.second.GetCode() != RegFirst.GetCode()) {
-    mov(Dst.second, RegSecond);
-    mov(Dst.first, RegFirst);
+  if (Dst.first.Idx() != RegSecond.Idx()) {
+    mov(EmitSize, Dst.first, RegFirst);
+    mov(EmitSize, Dst.second, RegSecond);
+  } else if (Dst.second.Idx() != RegFirst.Idx()) {
+    mov(EmitSize, Dst.second, RegSecond);
+    mov(EmitSize, Dst.first, RegFirst);
   } else {
-    mov(RegTmp, RegFirst);
-    mov(Dst.second, RegSecond);
-    mov(Dst.first, RegTmp);
+    mov(EmitSize, RegTmp, RegFirst);
+    mov(EmitSize, Dst.second, RegSecond);
+    mov(EmitSize, Dst.first, RegTmp);
   }
 }
 
 #undef DEF_OP
-void Arm64JITCore::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
-  REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
-#undef REGISTER_OP
-}
 }
 

External/FEXCore/Source/Interface/Core/JIT/JITCore.h

@@ -1,9 +1,10 @@
 #pragma once
 
-#include <memory>
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/fextl/memory.h>
 
 namespace FEXCore::Context {
-struct Context;
+class ContextImpl;
 }
 
 namespace FEXCore::Core {
@@ -13,14 +14,12 @@ struct InternalThreadState;
 namespace FEXCore::CPU {
 class CPUBackend;
 
-[[nodiscard]] std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::Context *ctx,
+[[nodiscard]] fextl::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::ContextImpl *ctx,
                                                            FEXCore::Core::InternalThreadState *Thread);
-void InitializeX86JITSignalHandlers(FEXCore::Context::Context *CTX);
 CPUBackendFeatures GetX86JITBackendFeatures();
 
-[[nodiscard]] std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::Context *ctx,
+[[nodiscard]] fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl *ctx,
                                                              FEXCore::Core::InternalThreadState *Thread);
-void InitializeArm64JITSignalHandlers(FEXCore::Context::Context *CTX);
 CPUBackendFeatures GetArm64JITBackendFeatures();
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp

@@ -5,6 +5,7 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
@@ -12,7 +13,6 @@ $end_info$
 #include <array>
 #include <stdint.h>
 #include <utility>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/AtomicOps.cpp

@@ -5,6 +5,7 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
@@ -12,7 +13,6 @@ $end_info$
 #include <array>
 #include <stdint.h>
 #include <utility>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp

@@ -7,6 +7,7 @@ $end_info$
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/HLE/Thunks/Thunks.h"
@@ -25,20 +26,10 @@ $end_info$
 #include <stdint.h>
 #include <unordered_map>
 #include <utility>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 
-DEF_OP(SignalReturn) {
-  // Adjust the stack first for a regular return
-  if (SpillSlots) {
-    add(rsp, SpillSlots * MaxSpillSlotSize); // + 8 to consume return address
-  }
-
-  jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SignalReturnHandler)]);
-}
-
 DEF_OP(CallbackReturn) {
   // Adjust the stack first for a regular return
   if (SpillSlots) {
@@ -155,6 +146,7 @@ DEF_OP(Syscall) {
   auto Op = IROp->C<IR::IROp_Syscall>();
   // XXX: This is very terrible, but I don't care for right now
 
+  FEXCore::IR::SyscallFlags Flags = Op->Flags;
   auto NumPush = RA64.size();
 
   for (auto &Reg : RA64)
@@ -195,7 +187,11 @@ DEF_OP(Syscall) {
   for (uint32_t i = RA64.size(); i > 0; --i)
     pop(RA64[i - 1]);
 
-  mov (GetDst<RA_64>(Node), rax);
+  if ((Flags & FEXCore::IR::SyscallFlags::NORETURNEDRESULT) != FEXCore::IR::SyscallFlags::NORETURNEDRESULT) {
+    // Move result to its destination register.
+    // Only if `NORETURNEDRESULT` wasn't set, otherwise we might overwrite the CPUState refilled with `FillStaticRegs`
+    mov (GetDst<RA_64>(Node), rax);
+  }
 }
 
 DEF_OP(Thunk) {
@@ -211,7 +207,7 @@ DEF_OP(Thunk) {
 
   mov(rdi, GetSrc<RA_64>(Op->ArgPtr.ID()));
 
-  auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
+  auto thunkFn = static_cast<Context::ContextImpl*>(ThreadState->CTX)->ThunkHandler->LookupThunk(Op->ThunkNameHash);
 
   mov(rax, reinterpret_cast<uintptr_t>(thunkFn));
   call(rax);
@@ -311,10 +307,45 @@ DEF_OP(CPUID) {
   mov(Dst.second, rdx);
 }
 
+DEF_OP(XGETBV) {
+  auto Op = IROp->C<IR::IROp_XGetBV>();
+
+  for (auto &Reg : RA64)
+    push(Reg);
+
+  // CPUID ABI
+  // this: rdi
+  // Function: rsi
+  //
+  // Result: RAX, RDX. 4xi32
+
+  // rsi can be in the source registers, so copy argument to edx first
+  mov (esi, GetSrc<RA_32>(Op->Function.ID()));
+  mov (rdi, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)]);
+
+  auto NumPush = RA64.size();
+
+  if (NumPush & 1)
+    sub(rsp, 8); // Align
+
+  // {rdi, rsi, rdx}
+  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.XCRFunction)]);
+
+  if (NumPush & 1)
+    add(rsp, 8); // Align
+
+  for (uint32_t i = RA64.size(); i > 0; --i)
+    pop(RA64[i - 1]);
+
+  auto Dst = GetSrcPair<RA_64>(Node);
+  mov(Dst.first.cvt32(), eax);
+  mov(Dst.second, rax);
+  shr(Dst.second, 32);
+}
+
 #undef DEF_OP
 void X86JITCore::RegisterBranchHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
-  REGISTER_OP(SIGNALRETURN,      SignalReturn);
   REGISTER_OP(CALLBACKRETURN,    CallbackReturn);
   REGISTER_OP(EXITFUNCTION,      ExitFunction);
   REGISTER_OP(JUMP,              Jump);
@@ -324,6 +355,7 @@ void X86JITCore::RegisterBranchHandlers() {
   REGISTER_OP(VALIDATECODE,      ValidateCode);
   REGISTER_OP(THREADREMOVECODEENTRY,   ThreadRemoveCodeEntry);
   REGISTER_OP(CPUID,             CPUID);
+  REGISTER_OP(XGETBV,            XGETBV);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp

@@ -5,13 +5,12 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <array>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 
@@ -111,6 +110,53 @@ DEF_OP(VCastFromGPR) {
   }
 }
 
+DEF_OP(VDupFromGPR) {
+  const auto Op = IROp->C<IR::IROp_VDupFromGPR>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = IROp->ElementSize;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetDst(Node);
+  const auto Src = GetSrc<RA_64>(Op->Src.ID()).cvt64();
+
+  vmovq(Dst, Src);
+
+  switch (ElementSize) {
+    case 1:
+      if (Is256Bit) {
+        vpbroadcastb(ToYMM(Dst), Dst);
+      } else {
+        vpbroadcastb(Dst, Dst);
+      }
+      break;
+    case 2:
+      if (Is256Bit) {
+        vpbroadcastw(ToYMM(Dst), Dst);
+      } else {
+        vpbroadcastw(Dst, Dst);
+      }
+      break;
+    case 4:
+      if (Is256Bit) {
+        vpbroadcastd(ToYMM(Dst), Dst);
+      } else {
+        vpbroadcastd(Dst, Dst);
+      }
+      break;
+    case 8:
+      if (Is256Bit) {
+        vpbroadcastq(ToYMM(Dst), Dst);
+      } else {
+        vpbroadcastq(Dst, Dst);
+      }
+      break;
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled element size: {}", ElementSize);
+      return;
+  }
+}
+
 DEF_OP(Float_FromGPR_S) {
   const auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
 
@@ -186,8 +232,8 @@ DEF_OP(Vector_SToF) {
       pextrq(rcx, Vector, 0);
       cvtsi2sd(Dst, rcx);
       cvtsi2sd(xmm15, rax);
-      vmovlhps(Dst, Dst, xmm15);
       if (Is256Bit) {
+        movlhps(Dst, xmm15);
         vextracti128(xmm15, ToYMM(Vector), 1);
 
         pextrq(rax, xmm15, 1);
@@ -197,6 +243,8 @@ DEF_OP(Vector_SToF) {
         movlhps(xmm15, xmm14);
 
         vinserti128(ToYMM(Dst), ToYMM(Dst), xmm15, 1);
+      } else {
+        vmovlhps(Dst, Dst, xmm15);
       }
       break;
     default:
@@ -355,6 +403,7 @@ void X86JITCore::RegisterConversionHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(VINSGPR,         VInsGPR);
   REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
+  REGISTER_OP(VDUPFROMGPR,     VDupFromGPR);
   REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
   REGISTER_OP(FLOAT_FTOF,      Float_FToF);
   REGISTER_OP(VECTOR_STOF,     Vector_SToF);

External/FEXCore/Source/Interface/Core/JIT/x86_64/EncryptionOps.cpp

@@ -5,12 +5,11 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/IR/IR.h>
 
 #include <array>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
@@ -21,23 +20,67 @@ DEF_OP(AESImc) {
 }
 
 DEF_OP(AESEnc) {
-  auto Op = IROp->C<IR::IROp_VAESEnc>();
-  vaesenc(GetDst(Node), GetSrc(Op->State.ID()), GetSrc(Op->Key.ID()));
+  const auto Op = IROp->C<IR::IROp_VAESEnc>();
+  const auto OpSize = IROp->Size;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetDst(Node);
+  const auto Key = GetSrc(Op->Key.ID());
+  const auto State = GetSrc(Op->State.ID());
+
+  if (Is256Bit) {
+    vaesenc(ToYMM(Dst), ToYMM(State), ToYMM(Key));
+  } else {
+    vaesenc(Dst, State, Key);
+  }
 }
 
 DEF_OP(AESEncLast) {
-  auto Op = IROp->C<IR::IROp_VAESEncLast>();
-  vaesenclast(GetDst(Node), GetSrc(Op->State.ID()), GetSrc(Op->Key.ID()));
+  const auto Op = IROp->C<IR::IROp_VAESEncLast>();
+  const auto OpSize = IROp->Size;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetDst(Node);
+  const auto Key = GetSrc(Op->Key.ID());
+  const auto State = GetSrc(Op->State.ID());
+
+  if (Is256Bit) {
+    vaesenclast(ToYMM(Dst), ToYMM(State), ToYMM(Key));
+  } else {
+    vaesenclast(Dst, State, Key);
+  }
 }
 
 DEF_OP(AESDec) {
-  auto Op = IROp->C<IR::IROp_VAESDec>();
-  vaesdec(GetDst(Node), GetSrc(Op->State.ID()), GetSrc(Op->Key.ID()));
+  const auto Op = IROp->C<IR::IROp_VAESDec>();
+  const auto OpSize = IROp->Size;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetDst(Node);
+  const auto Key = GetSrc(Op->Key.ID());
+  const auto State = GetSrc(Op->State.ID());
+
+  if (Is256Bit) {
+    vaesdec(ToYMM(Dst), ToYMM(State), ToYMM(Key));
+  } else {
+    vaesdec(Dst, State, Key);
+  }
 }
 
 DEF_OP(AESDecLast) {
-  auto Op = IROp->C<IR::IROp_VAESDecLast>();
-  vaesdeclast(GetDst(Node), GetSrc(Op->State.ID()), GetSrc(Op->Key.ID()));
+  const auto Op = IROp->C<IR::IROp_VAESDecLast>();
+  const auto OpSize = IROp->Size;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetDst(Node);
+  const auto Key = GetSrc(Op->Key.ID());
+  const auto State = GetSrc(Op->State.ID());
+
+  if (Is256Bit) {
+    vaesdeclast(ToYMM(Dst), ToYMM(State), ToYMM(Key));
+  } else {
+    vaesdeclast(Dst, State, Key);
+  }
 }
 
 DEF_OP(AESKeyGenAssist) {
@@ -76,18 +119,24 @@ DEF_OP(CRC32) {
 }
 
 DEF_OP(PCLMUL) {
-  auto Op = IROp->C<IR::IROp_PCLMUL>();
+  const auto Op = IROp->C<IR::IROp_PCLMUL>();
+  const auto OpSize = IROp->Size;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
 
-  auto Dst = GetDst(Node);
-  auto Src1 = GetSrc(Op->Src1.ID());
-  auto Src2 = GetSrc(Op->Src2.ID());
+  const auto Dst = GetDst(Node);
+  const auto Src1 = GetSrc(Op->Src1.ID());
+  const auto Src2 = GetSrc(Op->Src2.ID());
 
   switch (Op->Selector) {
   case 0b00000000:
   case 0b00000001:
   case 0b00010000:
   case 0b00010001:
-    vpclmulqdq(Dst, Src1, Src2, Op->Selector);
+    if (Is256Bit) {
+      vpclmulqdq(ToYMM(Dst), ToYMM(Src1), ToYMM(Src2), Op->Selector);
+    } else {
+      vpclmulqdq(Dst, Src1, Src2, Op->Selector);
+    }
     break;
   default:
     LOGMAN_MSG_A_FMT("Unknown PCLMUL selector: {}", Op->Selector);

External/FEXCore/Source/Interface/Core/JIT/x86_64/FlagOps.cpp

@@ -5,12 +5,12 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 
 #include <FEXCore/IR/IR.h>
 
 #include <array>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp

@@ -19,7 +19,6 @@ $end_info$
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
@@ -28,6 +27,7 @@ $end_info$
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
+#include <FEXCore/fextl/sstream.h>
 
 #include <algorithm>
 #include <array>
@@ -35,12 +35,9 @@ $end_info$
 #include <stddef.h>
 #include <stdint.h>
 #include <signal.h>
-#include <sys/mman.h>
 #include <tuple>
 #include <unordered_map>
 #include <utility>
-#include <vector>
-#include <xbyak/xbyak.h>
 
 // #define DEBUG_RA 1
 // #define DEBUG_CYCLES
@@ -147,7 +144,12 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
       case FABI_F80_I32: {
         PushRegs();
 
-        mov(edi, GetSrc<RA_32>(IROp->Args[0].ID()));
+        if (Info.ABI == FABI_F80_I16) {
+          movsx(rdi, GetSrc<RA_32>(IROp->Args[0].ID()).cvt16());
+        }
+        else {
+          mov(edi, GetSrc<RA_32>(IROp->Args[0].ID()));
+        }
         call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
 
         PopRegs();
@@ -223,7 +225,7 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
 
         PopRegs();
 
-        movzx(GetDst<RA_64>(Node), ax);
+        movsx(GetDst<RA_64>(Node), ax);
       }
       break;
       case FABI_I32_F80:{
@@ -302,6 +304,66 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
       }
       break;
 
+      case FABI_I32_I64_I64_I128_I128_I16: {
+        PushRegs();
+
+        const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
+        const auto Is64Bit = Op->GPRSize == 8;
+
+        const auto LHS = GetSrc(Op->LHS.ID());
+        const auto RHS = GetSrc(Op->RHS.ID());
+        const auto SrcRAX = GetSrc<RA_64>(Op->RAX.ID());
+        const auto SrcRDX = GetSrc<RA_64>(Op->RDX.ID());
+
+        // Encode the size check into the 8th bit to save a parameter
+        const auto Control = Op->Control | (uint16_t(Is64Bit) << 8);
+
+        mov(rdi, SrcRAX);
+        mov(rsi, SrcRDX);
+
+        movq(rdx, LHS);
+        pextrq(rcx, LHS, 1);
+
+        movq(r8, RHS);
+        pextrq(r9, RHS, 1);
+
+        sub(rsp, 16);
+        mov(dword [rsp], Control);
+
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
+
+        add(rsp, 16);
+        PopRegs();
+
+        mov(GetDst<RA_32>(Node), rax);
+        break;
+      }
+
+      case FABI_I32_I128_I128_I16: {
+        PushRegs();
+
+        const auto Op = IROp->C<IR::IROp_VPCMPISTRX>();
+
+        const auto LHS = GetSrc(Op->LHS.ID());
+        const auto RHS = GetSrc(Op->RHS.ID());
+        const auto Control = Op->Control;
+
+        movq(rdi, LHS);
+        pextrq(rsi, LHS, 1);
+
+        movq(rdx, RHS);
+        pextrq(rcx, RHS, 1);
+
+        mov(r8, Control);
+
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
+
+        PopRegs();
+
+        mov(GetDst<RA_32>(Node), rax);
+        break;
+      }
+
       case FABI_UNKNOWN:
       default:
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
@@ -325,7 +387,7 @@ static uint64_t X86JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame,
   }
 
   auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
-  Context::Context::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [record, LinkerAddress]{
+  Context::ContextImpl::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [record, LinkerAddress]{
     // undo the link
     record[0] = LinkerAddress;
   });
@@ -337,14 +399,14 @@ static uint64_t X86JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame,
 void X86JITCore::Op_NoOp(IR::IROp_Header *IROp, IR::NodeID Node) {
 }
 
-X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
+X86JITCore::X86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread)
   : CPUBackend(Thread, INITIAL_CODE_SIZE, MAX_CODE_SIZE)
   , CodeGenerator(0, this, nullptr) // this is not used here
   , CTX {ctx} {
 
   RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");
 
-  RAPass->AllocateRegisterSet(RegisterCount, RegisterClasses);
+  RAPass->AllocateRegisterSet(RegisterClasses);
   RAPass->AddRegisters(FEXCore::IR::GPRClass, NumGPRs);
   RAPass->AddRegisters(FEXCore::IR::FPRClass, NumXMMs);
   RAPass->AddRegisters(FEXCore::IR::GPRPairClass, NumGPRPairs);
@@ -374,7 +436,7 @@ X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalTh
 
     Common.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
     Common.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
-    Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::Context::ThreadRemoveCodeEntryFromJit);
+    Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadRemoveCodeEntryFromJit);
     Common.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
 
     {
@@ -382,9 +444,14 @@ X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalTh
       Common.CPUIDFunction = PMF.GetConvertedPointer();
     }
 
+    {
+      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunXCRFunction);
+      Common.XCRFunction = PMF.GetConvertedPointer();
+    }
+
     Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
     Common.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
-    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::Context::ThreadExitFunctionLink<X86JITCore_ExitFunctionLink>);
+    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadExitFunctionLink<X86JITCore_ExitFunctionLink>);
 
     // Fill in the fallback handlers
     InterpreterOps::FillFallbackIndexPointers(Common.FallbackHandlerPointers);
@@ -394,12 +461,6 @@ X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalTh
   ClearCache();
 }
 
-void X86JITCore::InitializeSignalHandlers(FEXCore::Context::Context *CTX) {
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    return Thread->CTX->Dispatcher->HandleSIGILL(Thread, Signal, info, ucontext);
-  }, true);
-}
-
 X86JITCore::~X86JITCore() {
 
 }
@@ -582,7 +643,7 @@ std::tuple<X86JITCore::SetCC, X86JITCore::CMovCC, X86JITCore::JCC> X86JITCore::G
   return { &CodeGenerator::sete , &CodeGenerator::cmove , &CodeGenerator::je  };
 }
 
-void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) {
+CPUBackend::CompiledCode X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) {
 
   FEXCORE_PROFILE_SCOPED("x86::CompileCode");
   JumpTargets.clear();
@@ -598,12 +659,27 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
     CTX->ClearCodeCache(ThreadState);
   }
 
-	GuestEntry = getCurr<uint8_t*>();
+  CodeData.BlockBegin = getCurr<uint8_t*>();
+
+  // Put the code header at the start of the data block.
+  Label JITCodeHeaderLabel{};
+  L(JITCodeHeaderLabel);
+
+  JITCodeHeader *CodeHeader = getCurr<JITCodeHeader *>();
+  setSize(getSize() + sizeof(JITCodeHeader));
+
+  CodeData.BlockEntry = getCurr<uint8_t*>();
+
+  // Get the address of the JITCodeHeader and store in to the core state.
+  // Only two instructions, so very low overhead.
+  lea(TMP1, ptr [rip + JITCodeHeaderLabel]);
+  mov(qword [STATE + offsetof(FEXCore::Core::CPUState, InlineJITBlockHeader)], TMP1);
+
   CursorEntry = getSize();
   this->IR = IR;
 
   if (GDBEnabled) {
-    auto GDBSize = CTX->Dispatcher->GenerateGDBPauseCheck(GuestEntry, Entry);
+    auto GDBSize = CTX->Dispatcher->GenerateGDBPauseCheck(CodeData.BlockBegin, Entry);
     setSize(getSize() + GDBSize);
   }
 
@@ -686,7 +762,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
       if (IROp->Op != IR::OP_BEGINBLOCK &&
           IROp->Op != IR::OP_CONDJUMP &&
           IROp->Op != IR::OP_JUMP) {
-        std::stringstream Inst;
+        fextl::stringstream Inst;
         auto Name = FEXCore::IR::GetName(IROp->Op);
 
         if (IROp->HasDest) {
@@ -726,7 +802,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
 
     if (DebugData) {
       DebugData->Subblocks.push_back({
-        static_cast<uint32_t>(BlockStartHostCode - GuestEntry),
+        static_cast<uint32_t>(BlockStartHostCode - CodeData.BlockBegin),
         static_cast<uint32_t>(getCurr<uint8_t *>() - BlockStartHostCode)
       });
     }
@@ -739,29 +815,41 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
   }
   PendingTargetLabel = nullptr;
 
-  void *GuestExit = getCurr<void*>();
+  // Add the JitCodeTail
+  auto JITBlockTailLocation = getCurr<uint8_t *>();
+  auto JITBlockTail = getCurr<JITCodeTail*>();
+  setSize(getSize() + sizeof(JITCodeTail));
+
+  // Put the block's RIP entry in the tail.
+  // This will be used for RIP reconstruction in the future.
+  // TODO: This needs to be a data RIP relocation once code caching works.
+  //   Current relocation code doesn't support this feature yet.
+  JITBlockTail->RIP = Entry;
+
+  CodeHeader->OffsetToBlockTail = JITBlockTailLocation - CodeData.BlockBegin;
+
+  CodeData.Size = getCurr<uint8_t*>() - CodeData.BlockBegin;
+
+  JITBlockTail->Size = CodeData.Size;
+
   this->IR = nullptr;
 
   ready();
 
   if (DebugData) {
-    DebugData->HostCodeSize = reinterpret_cast<uintptr_t>(GuestExit) - reinterpret_cast<uintptr_t>(GuestEntry);
+    DebugData->HostCodeSize = CodeData.Size;
     DebugData->Relocations = &Relocations;
   }
 
-  return GuestEntry;
+  return CodeData;
 }
 
-std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  return std::make_unique<X86JITCore>(ctx, Thread);
+fextl::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  return fextl::make_unique<X86JITCore>(ctx, Thread);
 }
 
 CPUBackendFeatures GetX86JITBackendFeatures() {
   return CPUBackendFeatures { };
 }
 
-void InitializeX86JITSignalHandlers(FEXCore::Context::Context *CTX) {
-  X86JITCore::InitializeSignalHandlers(CTX);
-}
-
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h

@@ -9,18 +9,20 @@ $end_info$
 #include <FEXCore/IR/RegisterAllocationData.h>
 #include "Interface/Core/BlockSamplingData.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include "Interface/Core/ObjectCache/Relocations.h"
 
-#define XBYAK64
-#include <xbyak/xbyak.h>
-#include <xbyak/xbyak_util.h>
-
 using namespace Xbyak;
 
+#include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/MathUtils.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/unordered_map.h>
+#include <FEXCore/fextl/vector.h>
+
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 #include <tuple>
@@ -51,13 +53,13 @@ const std::array<Xbyak::Xmm, 11> RAXMM_x = {  xmm1, xmm2, xmm3, xmm4, xmm5, xmm6
 
 class X86JITCore final : public CPUBackend, public Xbyak::CodeGenerator {
 public:
-  explicit X86JITCore(FEXCore::Context::Context *ctx,
+  explicit X86JITCore(FEXCore::Context::ContextImpl *ctx,
                       FEXCore::Core::InternalThreadState *Thread);
   ~X86JITCore() override;
 
-  [[nodiscard]] std::string GetName() override { return "JIT"; }
+  [[nodiscard]] fextl::string GetName() override { return "JIT"; }
 
-  [[nodiscard]] void *CompileCode(uint64_t Entry,
+  [[nodiscard]] CPUBackend::CompiledCode CompileCode(uint64_t Entry,
                                   FEXCore::IR::IRListView const *IR,
                                   FEXCore::Core::DebugData *DebugData,
                                   FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) override;
@@ -68,8 +70,6 @@ public:
 
   void ClearCache() override;
 
-  static void InitializeSignalHandlers(FEXCore::Context::Context *CTX);
-
   void ClearRelocations() override { Relocations.clear(); }
 
 private:
@@ -123,7 +123,7 @@ private:
 
     void PlaceNamedSymbolLiteral(NamedSymbolLiteralPair &Lit);
 
-    std::vector<FEXCore::CPU::Relocation> Relocations;
+    fextl::vector<FEXCore::CPU::Relocation> Relocations;
 
     ///< Relocation code loading
     bool ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint64_t CursorEntry, size_t NumRelocations, const char* EntryRelocations);
@@ -135,11 +135,12 @@ private:
   /**  @} */
 
   Label* PendingTargetLabel{};
-  FEXCore::Context::Context *CTX;
+  FEXCore::Context::ContextImpl *CTX;
   FEXCore::IR::IRListView const *IR;
   uint64_t Entry;
+  CPUBackend::CompiledCode CodeData{};
 
-  std::unordered_map<IR::NodeID, Label> JumpTargets;
+  fextl::unordered_map<IR::NodeID, Label> JumpTargets;
   Xbyak::util::Cpu Features{};
 
   bool MemoryDebug = false;
@@ -150,7 +151,6 @@ private:
   constexpr static uint32_t NumGPRs = RA64.size(); // 4 is the minimum required for GPR ops
   constexpr static uint32_t NumXMMs = RAXMM.size();
   constexpr static uint32_t NumGPRPairs = RA64Pair.size();
-  constexpr static uint32_t RegisterCount = NumGPRs + NumXMMs + NumGPRPairs;
   constexpr static uint32_t RegisterClasses = 6;
 
   constexpr static uint64_t GPRBase = (0ULL << 32);
@@ -205,10 +205,6 @@ private:
   void EmitDetectionString();
 
   uint32_t SpillSlots{};
-  /**
-  * @brief Current guest RIP entrypoint
-  */
-  uint8_t *GuestEntry{};
 
   using SetCC = void (X86JITCore::*)(const Operand& op);
   using CMovCC = void (X86JITCore::*)(const Reg& reg, const Operand& op);
@@ -308,7 +304,6 @@ private:
   DEF_OP(AtomicFetchNeg);
 
   ///< Branch ops
-  DEF_OP(SignalReturn);
   DEF_OP(CallbackReturn);
   DEF_OP(ExitFunction);
   DEF_OP(Jump);
@@ -318,10 +313,12 @@ private:
   DEF_OP(ValidateCode);
   DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
+  DEF_OP(XGETBV);
 
   ///< Conversion ops
   DEF_OP(VInsGPR);
   DEF_OP(VCastFromGPR);
+  DEF_OP(VDupFromGPR);
   DEF_OP(Float_FromGPR_S);
   DEF_OP(Float_FToF);
   DEF_OP(Vector_UToF);
@@ -337,6 +334,8 @@ private:
   ///< Memory ops
   DEF_OP(LoadContext);
   DEF_OP(StoreContext);
+  DEF_OP(LoadRegister);
+  DEF_OP(StoreRegister);
   DEF_OP(LoadContextIndexed);
   DEF_OP(StoreContextIndexed);
   DEF_OP(SpillRegister);
@@ -345,9 +344,12 @@ private:
   DEF_OP(StoreFlag);
   DEF_OP(LoadMem);
   DEF_OP(StoreMem);
-  DEF_OP(VLoadMemElement);
-  DEF_OP(VStoreMemElement);
+  DEF_OP(VLoadVectorMasked);
+  DEF_OP(VStoreVectorMasked);
+  DEF_OP(MemSet);
+  DEF_OP(MemCpy);
   DEF_OP(CacheLineClear);
+  DEF_OP(CacheLineClean);
   DEF_OP(CacheLineZero);
 
   ///< Misc ops
@@ -408,6 +410,8 @@ private:
   DEF_OP(VZip2);
   DEF_OP(VUnZip);
   DEF_OP(VUnZip2);
+  DEF_OP(VTrn);
+  DEF_OP(VTrn2);
   DEF_OP(VBSL);
   DEF_OP(VCMPEQ);
   DEF_OP(VCMPEQZ);
@@ -430,8 +434,6 @@ private:
   DEF_OP(VInsElement);
   DEF_OP(VDupElement);
   DEF_OP(VExtr);
-  DEF_OP(VSLI);
-  DEF_OP(VSRI);
   DEF_OP(VUShrI);
   DEF_OP(VSShrI);
   DEF_OP(VShlI);

External/FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp

@@ -6,7 +6,7 @@ $end_info$
 
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
@@ -14,7 +14,6 @@ $end_info$
 #include <array>
 #include <stddef.h>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 
@@ -82,11 +81,7 @@ DEF_OP(LoadContext) {
       break;
     }
     case 32: {
-      if (Op->Offset % 32 == 0) {
-        vmovaps(ToYMM(Dst), yword [STATE + Op->Offset]);
-      } else {
-        vmovups(ToYMM(Dst), yword [STATE + Op->Offset]);
-      }
+      vmovups(ToYMM(Dst), yword [STATE + Op->Offset]);
       break;
     }
     default:
@@ -156,11 +151,7 @@ DEF_OP(StoreContext) {
       break;
     }
     case 32: {
-      if (Op->Offset % 32 == 0) {
-        vmovaps(yword [STATE + Op->Offset], ToYMM(Value));
-      } else {
-        vmovups(yword [STATE + Op->Offset], ToYMM(Value));
-      }
+      vmovups(yword [STATE + Op->Offset], ToYMM(Value));
       break;
     }
     default:
@@ -170,6 +161,120 @@ DEF_OP(StoreContext) {
   }
 }
 
+DEF_OP(LoadRegister) {
+  const auto Op = IROp->C<IR::IROp_LoadRegister>();
+  const auto OpSize = IROp->Size;
+
+  if (Op->Class == IR::GPRClass) {
+    switch (OpSize) {
+    case 1: {
+      movzx(GetSrc<RA_32>(Node), byte [STATE + Op->Offset]);
+      break;
+    }
+    case 2: {
+      movzx(GetSrc<RA_32>(Node), word [STATE + Op->Offset]);
+      break;
+    }
+    case 4: {
+      mov(GetSrc<RA_32>(Node), dword [STATE + Op->Offset]);
+      break;
+    }
+    case 8: {
+      mov(GetSrc<RA_64>(Node), qword [STATE + Op->Offset]);
+      break;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled LoadRegister size: {}", OpSize);
+      break;
+    }
+  }
+  else {
+    const auto Dst = GetSrc(Node);
+
+    switch (OpSize) {
+    case 1: {
+      movzx(rax, byte [STATE + Op->Offset]);
+      vmovq(Dst, rax);
+      break;
+    }
+    case 2: {
+      movzx(rax, word [STATE + Op->Offset]);
+      vmovq(Dst, rax);
+      break;
+    }
+    case 4: {
+      vmovd(Dst, dword [STATE + Op->Offset]);
+      break;
+    }
+    case 8: {
+      vmovq(Dst, qword [STATE + Op->Offset]);
+      break;
+    }
+    case 16: {
+      if (Op->Offset % 16 == 0) {
+        vmovaps(Dst, xword [STATE + Op->Offset]);
+      } else {
+        vmovups(Dst, xword [STATE + Op->Offset]);
+      }
+      break;
+    }
+    case 32: {
+      vmovups(ToYMM(Dst), yword [STATE + Op->Offset]);
+      break;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled LoadRegister size: {}", OpSize);
+      break;
+    }
+  }
+}
+
+DEF_OP(StoreRegister) {
+  const auto Op = IROp->C<IR::IROp_StoreRegister>();
+  const auto OpSize = IROp->Size;
+
+  if (Op->Class == IR::GPRClass) {
+    const auto regOffs = Op->Offset & 7;
+
+    switch (OpSize) {
+      case 4:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
+        mov(dword [STATE + Op->Offset], GetSrc<RA_32>(Op->Value.ID()));
+        break;
+
+      case 8:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
+        mov(qword [STATE + Op->Offset], GetSrc<RA_64>(Op->Value.ID()));
+        break;
+
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled StoreRegister GPR size: {}", OpSize);
+        break;
+    }
+  } else if (Op->Class == IR::FPRClass) {
+    const auto Value = GetSrc(Op->Value.ID());
+    switch (OpSize) {
+      case 16: {
+        if (Op->Offset % 16 == 0) {
+          vmovaps(xword [STATE + Op->Offset], Value);
+        } else {
+          vmovups(xword [STATE + Op->Offset], Value);
+        }
+        break;
+      }
+      case 32: {
+        vmovups(yword [STATE + Op->Offset], ToYMM(Value));
+        break;
+      }
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
+        break;
+    }
+  } else {
+    LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class);
+  }
+}
+
 DEF_OP(LoadContextIndexed) {
   const auto Op = IROp->C<IR::IROp_LoadContextIndexed>();
   const auto OpSize = IROp->Size;
@@ -269,11 +374,7 @@ DEF_OP(LoadContextIndexed) {
         }
         break;
       case 32:
-        if (Op->BaseOffset % 32 == 0) {
-          vmovaps(ToYMM(Dst), yword [STATE + rax]);
-        } else {
-          vmovups(ToYMM(Dst), yword [STATE + rax]);
-        }
+        vmovups(ToYMM(Dst), yword [STATE + rax]);
         break;
       default:
         LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", OpSize);
@@ -369,11 +470,7 @@ DEF_OP(StoreContextIndexed) {
         }
         break;
       case 32:
-        if (Op->BaseOffset % 32 == 0) {
-          vmovaps(yword [STATE + rax], ToYMM(Value));
-        } else {
-          vmovups(yword [STATE + rax], ToYMM(Value));
-        }
+        vmovups(yword [STATE + rax], ToYMM(Value));
         break;
       default:
         LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", OpSize);
@@ -432,7 +529,7 @@ DEF_OP(SpillRegister) {
         break;
       }
       case 32: {
-        vmovaps(yword [rsp + SlotOffset], ToYMM(Src));
+        vmovups(yword [rsp + SlotOffset], ToYMM(Src));
         break;
       }
       default:
@@ -488,7 +585,7 @@ DEF_OP(FillRegister) {
         break;
       }
       case 32: {
-        vmovaps(ToYMM(Dst), yword [rsp + SlotOffset]);
+        vmovups(ToYMM(Dst), yword [rsp + SlotOffset]);
         break;
       }
       default:
@@ -668,12 +765,300 @@ DEF_OP(StoreMem) {
   }
 }
 
-DEF_OP(VLoadMemElement) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
+DEF_OP(VLoadVectorMasked) {
+  const auto Op = IROp->C<IR::IROp_VLoadVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = IROp->ElementSize;
+
+  const auto Dst = GetDst(Node);
+  const auto Mask = GetSrc(Op->Mask.ID());
+
+  const Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
+  const auto MemPtr = GenerateModRM(MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+
+  switch (ElementSize) {
+    case 4: {
+      if (Is256Bit) {
+        vmaskmovps(ToYMM(Dst), ToYMM(Mask), yword [MemPtr]);
+      } else {
+        vmaskmovps(Dst, Mask, xword [MemPtr]);
+      }
+      return;
+    }
+    case 8: {
+      if (Is256Bit) {
+        vmaskmovpd(ToYMM(Dst), ToYMM(Mask), yword [MemPtr]);
+      } else {
+        vmaskmovpd(Dst, Mask, xword [MemPtr]);
+      }
+      return;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VLoadVectorMasked element size: {}", ElementSize);
+      return;
+  }
+}
+DEF_OP(VStoreVectorMasked) {
+  const auto Op = IROp->C<IR::IROp_VStoreVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = IROp->ElementSize;
+
+  const auto Data = GetDst(Op->Data.ID());
+  const auto Mask = GetSrc(Op->Mask.ID());
+
+  const Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
+  const auto MemPtr = GenerateModRM(MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+
+  switch (ElementSize) {
+    case 4: {
+      if (Is256Bit) {
+        vmaskmovps(yword [MemPtr], ToYMM(Mask), ToYMM(Data));
+      } else {
+        vmaskmovps(xword [MemPtr], Mask, Data);
+      }
+      return;
+    }
+    case 8: {
+      if (Is256Bit) {
+        vmaskmovpd(yword [MemPtr], ToYMM(Mask), ToYMM(Data));
+      } else {
+        vmaskmovpd(xword [MemPtr], Mask, Data);
+      }
+      return;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VStoreVectorMasked element size: {}", ElementSize);
+      return;
+  }
 }
 
-DEF_OP(VStoreMemElement) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
+DEF_OP(MemSet) {
+  const auto Op = IROp->C<IR::IROp_MemSet>();
+
+  const int32_t Size = Op->Size;
+  const auto MemReg = GetSrc<RA_64>(Op->Addr.ID());
+  const auto Value = GetSrc<RA_64>(Op->Value.ID());
+  const auto Length = GetSrc<RA_64>(Op->Length.ID());
+  const auto Direction = GetSrc<RA_64>(Op->Direction.ID());
+  const auto Dst = GetSrc<RA_64>(Node);
+
+  // If Direction == 0 then:
+  //   MemReg is incremented (by size)
+  // else:
+  //   MemReg is decremented (by size)
+  //
+  // Counter is decremented regardless.
+
+  // TMP1 = rax
+  // TMP2 = rcx
+  // TMP4 = rdi
+  // That leaves us with TMP3 and TMP5
+  mov(rax, Value);
+  mov(rcx, Length);
+  mov(rdi, MemReg);
+
+  if (!Op->Prefix.IsInvalid()) {
+    add(rdi, GetSrc<RA_64>(Op->Prefix.ID()));
+  }
+
+  {
+    mov(TMP3, Length);
+    auto CalculateDest = [&]() {
+      mov(Dst, MemReg);
+      switch (Size) {
+        case 1:
+          break;
+        case 2:
+          shl(TMP3, 1);
+          break;
+        case 4:
+          shl(TMP3, 2);
+          break;
+        case 8:
+          shl(TMP3, 3);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    };
+
+    Label AfterDir;
+    Label BackwardDir;
+
+    cmp(Direction, 0);
+    jne(BackwardDir);
+    // Incrementing DF flag.
+    cld();
+    CalculateDest();
+    add(Dst, TMP3);
+    jmp(AfterDir);
+
+    L(BackwardDir);
+    // Decrementing DF flag.
+    std();
+    CalculateDest();
+    sub(Dst, TMP3);
+
+    L(AfterDir);
+  }
+
+  switch (Size) {
+    case 1:
+      rep(); stosb();
+      break;
+    case 2:
+      rep(); stosw();
+      break;
+    case 4:
+      rep(); stosd();
+      break;
+    case 8:
+      rep(); stosq();
+      break;
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+      break;
+  }
+  // Ensure we set DF back to zero. Required by the ABI.
+  cld();
+}
+
+DEF_OP(MemCpy) {
+  const auto Op = IROp->C<IR::IROp_MemCpy>();
+
+  const int32_t Size = Op->Size;
+  const auto MemRegDest = GetSrc<RA_64>(Op->AddrDest.ID());
+  const auto MemRegSrc = GetSrc<RA_64>(Op->AddrSrc.ID());
+
+  const auto Length = GetSrc<RA_64>(Op->Length.ID());
+  const auto Direction = GetSrc<RA_64>(Op->Direction.ID());
+
+  // If Direction == 0 then:
+  //   MemRegDest is incremented (by size)
+  //   MemRegSrc is incremented (by size)
+  // else:
+  //   MemRegDest is decremented (by size)
+  //   MemRegSrc is decremented (by size)
+  //
+  // Counter is decremented regardless.
+
+  // TMP1 = Length
+  // TMP2 = Dest
+  // TMP3 = Src
+  // TMP4 = Temp value
+  mov(TMP1, Length);
+  mov(TMP2, MemRegDest);
+  mov(TMP3, MemRegSrc);
+  if (!Op->PrefixDest.IsInvalid()) {
+    add(TMP2, GetSrc<RA_64>(Op->PrefixDest.ID()));
+  }
+  if (!Op->PrefixSrc.IsInvalid()) {
+    add(TMP3, GetSrc<RA_64>(Op->PrefixSrc.ID()));
+  }
+
+  auto Dst = GetSrcPair<RA_64>(Node);
+  Label Done;
+  Label BackwardImpl;
+  cmp(Direction, 0);
+  jne(BackwardImpl);
+
+  // Emit forward direction memcpy then backward direction memcpy.
+  for (int32_t Direction :  { 1, -1 }) {
+    Label DoneInternal;
+    Label AgainInternal;
+
+    L(AgainInternal);
+    cmp(TMP1, 0);
+    je(DoneInternal);
+
+    {
+      switch (Size) {
+        case 1:
+          movzx(TMP4, byte [TMP3]);
+          mov(byte [TMP2], TMP4.cvt8());
+          break;
+        case 2:
+          movzx(TMP4, word [TMP3]);
+          mov(word [TMP2], TMP4.cvt16());
+          break;
+        case 4:
+          mov(TMP4.cvt32(), dword [TMP3]);
+          mov(dword [TMP2], TMP4.cvt32());
+          break;
+        case 8:
+          mov(TMP4, qword [TMP3]);
+          mov(qword [TMP2], TMP4);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+
+    if (Direction == 1) {
+      // Incrementing pointers
+      add(TMP2, Size);
+      add(TMP3, Size);
+    }
+    else {
+      // Decrementing pointers
+      sub(TMP2, Size);
+      sub(TMP3, Size);
+    }
+
+    // Decrement counter by one
+    sub(TMP1, 1);
+
+    jmp(AgainInternal);
+    L(DoneInternal);
+
+    // Pointer math using source pointers and length.
+    mov(TMP3, Length);
+    switch (Size) {
+      case 1:
+        break;
+      case 2:
+        shl(TMP3, 1);
+        break;
+      case 4:
+        shl(TMP3, 2);
+        break;
+      case 8:
+        shl(TMP3, 3);
+        break;
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+        break;
+    }
+
+    // Needs to use temporaries just in case of overwrite
+    mov(TMP1, MemRegDest);
+    mov(TMP2, MemRegSrc);
+
+    mov(Dst.first, TMP1);
+    mov(Dst.second, TMP2);
+
+    if (Direction == 1) {
+      // Incrementing pointers
+      add(Dst.first, TMP3);
+      add(Dst.second, TMP3);
+
+      jmp(Done);
+      L(BackwardImpl);
+    }
+    else {
+      // Decrementing pointers
+      sub(Dst.first, TMP3);
+      sub(Dst.second, TMP3);
+    }
+  }
+
+  L(Done);
 }
 
 DEF_OP(CacheLineClear) {
@@ -681,7 +1066,19 @@ DEF_OP(CacheLineClear) {
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
 
-  clflush(ptr [MemReg]);
+  if (Op->Serialize) {
+    clflush(ptr [MemReg]);
+  }
+  else {
+    clflushopt(ptr [MemReg]);
+  }
+}
+
+DEF_OP(CacheLineClean) {
+  auto Op = IROp->C<IR::IROp_CacheLineClean>();
+
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
+  clwb(ptr [MemReg]);
 }
 
 DEF_OP(CacheLineZero) {
@@ -706,8 +1103,8 @@ void X86JITCore::RegisterMemoryHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(LOADCONTEXT,         LoadContext);
   REGISTER_OP(STORECONTEXT,        StoreContext);
-  REGISTER_OP(LOADREGISTER,        Unhandled); // SRA specific, not supported on this backend
-  REGISTER_OP(STOREREGISTER,       Unhandled);
+  REGISTER_OP(LOADREGISTER,        LoadRegister);
+  REGISTER_OP(STOREREGISTER,       StoreRegister);
   REGISTER_OP(LOADCONTEXTINDEXED,  LoadContextIndexed);
   REGISTER_OP(STORECONTEXTINDEXED, StoreContextIndexed);
   REGISTER_OP(SPILLREGISTER,       SpillRegister);
@@ -718,9 +1115,12 @@ void X86JITCore::RegisterMemoryHandlers() {
   REGISTER_OP(STOREMEM,            StoreMem);
   REGISTER_OP(LOADMEMTSO,          LoadMem);
   REGISTER_OP(STOREMEMTSO,         StoreMem);
-  REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
-  REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
+  REGISTER_OP(VLOADVECTORMASKED,   VLoadVectorMasked);
+  REGISTER_OP(VSTOREVECTORMASKED,  VStoreVectorMasked);
+  REGISTER_OP(MEMSET,              MemSet);
+  REGISTER_OP(MEMCPY,              MemCpy);
   REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
+  REGISTER_OP(CACHELINECLEAN,      CacheLineClean);
   REGISTER_OP(CACHELINEZERO,       CacheLineZero);
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp

@@ -6,6 +6,7 @@ $end_info$
 
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "FEXCore/Debug/InternalThreadState.h"
 
@@ -16,7 +17,6 @@ $end_info$
 #include <array>
 #include <stddef.h>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
@@ -24,7 +24,7 @@ namespace FEXCore::CPU {
 DEF_OP(GuestOpcode) {
   auto Op = IROp->C<IR::IROp_GuestOpcode>();
   // metadata
-  DebugData->GuestOpcodes.push_back({Op->GuestEntryOffset, getCurr<uint8_t*>() - GuestEntry});
+  DebugData->GuestOpcodes.push_back({Op->GuestEntryOffset, getCurr<uint8_t*>() - CodeData.BlockBegin});
 }
 
 DEF_OP(Fence) {
@@ -43,6 +43,7 @@ DEF_OP(Fence) {
   }
 }
 
+#ifndef _WIN32
 DEF_OP(Break) {
   auto Op = IROp->C<IR::IROp_Break>();
 
@@ -50,11 +51,19 @@ DEF_OP(Break) {
     add(rsp, SpillSlots * MaxSpillSlotSize);
   }
 
-  mov(byte [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.FaultToTopAndGeneratedException)], 1);
-  mov(byte [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.Signal)], Op->Reason.Signal);
-  mov(dword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.TrapNo)], Op->Reason.TrapNumber);
-  mov(dword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.err_code)], Op->Reason.ErrorRegister);
-  mov(dword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.si_code)], Op->Reason.si_code);
+  Core::CpuStateFrame::SynchronousFaultDataStruct State = {
+    .FaultToTopAndGeneratedException = 1,
+    .Signal = Op->Reason.Signal,
+    .TrapNo = Op->Reason.TrapNumber,
+    .si_code = Op->Reason.si_code,
+    .err_code = Op->Reason.ErrorRegister,
+  };
+
+  uint64_t Constant{};
+  memcpy(&Constant, &State, sizeof(State));
+
+  mov(TMP1, Constant);
+  mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData)], TMP1);
 
   switch (Op->Reason.Signal) {
   case SIGILL:
@@ -71,6 +80,11 @@ DEF_OP(Break) {
     break;
   }
 }
+#else
+DEF_OP(Break) {
+  ERROR_AND_DIE_FMT("Unsupported");
+}
+#endif
 
 DEF_OP(GetRoundingMode) {
   auto Dst = GetDst<RA_32>(Node);

External/FEXCore/Source/Interface/Core/JIT/x86_64/MoveOps.cpp

@@ -5,7 +5,7 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/IR/IR.h>
 

External/FEXCore/Source/Interface/Core/LookupCache.cpp

@@ -11,11 +11,15 @@ $end_info$
 #include "Interface/Context/Context.h"
 #include "Interface/Core/LookupCache.h"
 
-#include <sys/mman.h>
-
 namespace FEXCore {
-LookupCache::LookupCache(FEXCore::Context::Context *CTX)
-  : ctx {CTX} {
+LookupCache::LookupCache(FEXCore::Context::ContextImpl *CTX)
+  : BlockLinks_mbr { fextl::pmr::get_default_resource() }
+  , ctx {CTX} {
+
+  TotalCacheSize = ctx->Config.VirtualMemSize / 4096 * 8 + CODE_SIZE + L1_SIZE;
+  BlockLinks_pma = fextl::make_unique<std::pmr::polymorphic_allocator<std::byte>>(&BlockLinks_mbr);
+  // Setup our PMR map.
+  BlockLinks = BlockLinks_pma->new_object<BlockLinksMapType>();
 
   // Block cache ends up looking like this
   // PageMemoryMap[VirtualMemoryRegion >> 12]
@@ -29,46 +33,46 @@ LookupCache::LookupCache(FEXCore::Context::Context *CTX)
   // Allocate a region of memory that we can use to back our block pointers
   // We need one pointer per page of virtual memory
   // At 64GB of virtual memory this will allocate 128MB of virtual memory space
-  PagePointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, ctx->Config.VirtualMemSize / 4096 * 8, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  PagePointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::VirtualAlloc(TotalCacheSize));
 
   // Allocate our memory backing our pages
   // We need 32KB per guest page (One pointer per byte)
   // XXX: We can drop down to 16KB if we store 4byte offsets from the code base
   // We currently limit to 128MB of real memory for caching for the total cache size.
   // Can end up being inefficient if we compile a small number of blocks per page
-  PageMemory = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, CODE_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  PageMemory = PagePointer + ctx->Config.VirtualMemSize / 4096 * 8;
   LOGMAN_THROW_AA_FMT(PageMemory != -1ULL, "Failed to allocate page memory");
 
   // L1 Cache
-  L1Pointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, L1_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  L1Pointer = PageMemory + CODE_SIZE;
   LOGMAN_THROW_AA_FMT(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
 
   VirtualMemSize = ctx->Config.VirtualMemSize;
 }
 
 LookupCache::~LookupCache() {
-  FEXCore::Allocator::munmap(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8);
-  FEXCore::Allocator::munmap(reinterpret_cast<void*>(PageMemory), CODE_SIZE);
-  FEXCore::Allocator::munmap(reinterpret_cast<void*>(L1Pointer), L1_SIZE);
+  const size_t TotalCacheSize = ctx->Config.VirtualMemSize / 4096 * 8 + CODE_SIZE + L1_SIZE;
+  FEXCore::Allocator::VirtualFree(reinterpret_cast<void*>(PagePointer), TotalCacheSize);
+
+  // No need to free BlockLinks map.
+  // These will get freed when their memory allocators are deallocated.
 }
 
 void LookupCache::ClearL2Cache() {
   std::lock_guard<std::recursive_mutex> lk(WriteLock);
   // Clear out the page memory
-  madvise(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8, MADV_DONTNEED);
-  madvise(reinterpret_cast<void*>(PageMemory), CODE_SIZE, MADV_DONTNEED);
+  // PagePointer and PageMemory are sequential with each other. Clear both at once.
+  FEXCore::Allocator::VirtualDontNeed(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8 + CODE_SIZE);
   AllocateOffset = 0;
 }
 
 void LookupCache::ClearCache() {
   std::lock_guard<std::recursive_mutex> lk(WriteLock);
 
-  // Clear L1
-  madvise(reinterpret_cast<void*>(L1Pointer), L1_SIZE, MADV_DONTNEED);
-  // Clear L2
-  ClearL2Cache();
-  // All code is gone, remove links
-  BlockLinks.clear();
+  // Clear L1 and L2 by clearing the full cache.
+  FEXCore::Allocator::VirtualDontNeed(reinterpret_cast<void*>(PagePointer), TotalCacheSize);
+  // Allocate a new pointer from the BlockLinks pma again.
+  BlockLinks = BlockLinks_pma->new_object<BlockLinksMapType>();
   // All code is gone, clear the block list
   BlockList.clear();
 }

External/FEXCore/Source/Interface/Core/LookupCache.h

@@ -1,28 +1,28 @@
 #pragma once
+#include "Interface/Context/Context.h"
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/memory_resource.h>
+#include <FEXCore/fextl/robin_map.h>
+#include <FEXCore/fextl/vector.h>
+#include <FEXCore/fextl/memory_resource.h>
 
 #include <cstdint>
 #include <functional>
-#include <map>
 #include <stddef.h>
 #include <utility>
-#include <vector>
 #include <mutex>
 
 namespace FEXCore {
-namespace Context {
-  struct Context;
-}
 
 class LookupCache {
 public:
-
-  struct LookupCacheEntry { 
+  struct LookupCacheEntry {
     uintptr_t HostCode;
     uintptr_t GuestCode;
   };
 
-  LookupCache(FEXCore::Context::Context *CTX);
+  LookupCache(FEXCore::Context::ContextImpl *CTX);
   ~LookupCache();
 
   uintptr_t FindBlock(uint64_t Address) {
@@ -54,7 +54,7 @@ public:
         return L1Entry.HostCode;
       }
     }
-    
+
     // Try L3
     auto HostCode = BlockList.find(Address);
 
@@ -62,18 +62,18 @@ public:
       CacheBlockMapping(Address, HostCode->second);
       return HostCode->second;
     }
-      
+
     // Failed to find
     return 0;
   }
 
-  std::map<uint64_t, std::vector<uint64_t>> CodePages;
+  fextl::map<uint64_t, fextl::vector<uint64_t>> CodePages;
 
   // Appends Block {Address} to CodePages [Start, Start + Length)
   // Returns true if new pages are marked as containing code
   bool AddBlockExecutableRange(uint64_t Address, uint64_t Start, uint64_t Length) {
     std::lock_guard<std::recursive_mutex> lk(WriteLock);
-    
+
     bool rv = false;
 
     for (auto CurrentPage = Start >> 12, EndPage = (Start + Length -1) >> 12; CurrentPage <= EndPage; CurrentPage++) {
@@ -88,7 +88,7 @@ public:
   // Adds to Guest -> Host code mapping
   void AddBlockMapping(uint64_t Address, void *HostCode) {
     std::lock_guard<std::recursive_mutex> lk(WriteLock);
-    
+
     [[maybe_unused]] auto Inserted = BlockList.emplace(Address, (uintptr_t)HostCode).second;
     LOGMAN_THROW_AA_FMT(Inserted, "Duplicate block mapping added");
 
@@ -104,9 +104,9 @@ public:
     std::lock_guard<std::recursive_mutex> lk(WriteLock);
 
     // Sever any links to this block
-    auto lower = BlockLinks.lower_bound({Address, 0});
-    auto upper = BlockLinks.upper_bound({Address, UINTPTR_MAX});
-    for (auto it = lower; it != upper; it = BlockLinks.erase(it)) {
+    auto lower = BlockLinks->lower_bound({Address, 0});
+    auto upper = BlockLinks->upper_bound({Address, UINTPTR_MAX});
+    for (auto it = lower; it != upper; it = BlockLinks->erase(it)) {
       it->second();
     }
 
@@ -144,7 +144,7 @@ public:
   void AddBlockLink(uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker) {
     std::lock_guard<std::recursive_mutex> lk(WriteLock);
 
-    BlockLinks.insert({{GuestDestination, HostLink}, delinker});
+    BlockLinks->insert({{GuestDestination, HostLink}, delinker});
   }
 
   void ClearCache();
@@ -158,7 +158,7 @@ public:
   constexpr static size_t L1_ENTRIES_MASK = L1_ENTRIES - 1;
 
   // This needs to be taken before reads or writes to L2, L3, CodePages, Thread::DebugStore,
-  // and before writes to L1. Concurrent access from a thread that this LookupCache doesn't belong to 
+  // and before writes to L1. Concurrent access from a thread that this LookupCache doesn't belong to
   // may only happen during cross thread invalidation (::Erase).
   // All other operations must be done from the owning thread.
   // Some care is taken so that L1 lookups can be done without locks, and even tearing is unlikely to lead to a crash.
@@ -167,9 +167,7 @@ public:
   std::recursive_mutex WriteLock;
 
 private:
-  void CacheBlockMapping(uint64_t Address, uintptr_t HostCode) { 
-    std::lock_guard<std::recursive_mutex> lk(WriteLock);
-
+  void CacheBlockMapping(uint64_t Address, uintptr_t HostCode) {
     // Do L1
     auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
     L1Entry.GuestCode = Address;
@@ -237,9 +235,20 @@ private:
     }
   };
 
+  // Use a monotonic buffer resource to allocate both the std::pmr::map and its members.
+  // This allows us to quickly clear the block link map by clearing the monotonic allocator.
+  // If we had allocated the block link map without the MBR, then clearing the map would require slowly
+  // walking each block member and destructing objects.
+  //
+  // This makes `BlockLinks` look like a raw pointer that could memory leak, but since it is backed by the MBR, it won't.
+  std::pmr::monotonic_buffer_resource BlockLinks_mbr;
+  using BlockLinksMapType = std::pmr::map<BlockLinkTag, std::function<void()>>;
+  fextl::unique_ptr<std::pmr::polymorphic_allocator<std::byte>> BlockLinks_pma;
+  BlockLinksMapType *BlockLinks;
 
-  std::map<BlockLinkTag, std::function<void()>> BlockLinks;
-  std::map<uint64_t, uint64_t> BlockList;
+  fextl::robin_map<uint64_t, uint64_t> BlockList;
+
+  size_t TotalCacheSize;
 
   constexpr static size_t CODE_SIZE = 128 * 1024 * 1024;
   constexpr static size_t SIZE_PER_PAGE = 4096 * sizeof(LookupCacheEntry);
@@ -247,7 +256,7 @@ private:
 
   size_t AllocateOffset {};
 
-  FEXCore::Context::Context *ctx;
+  FEXCore::Context::ContextImpl *ctx;
   uint64_t VirtualMemSize{};
 };
 }

External/FEXCore/Source/Interface/Core/ObjectCache/CodeObjectSerializationConfig.h

@@ -1,12 +1,16 @@
 #pragma once
 
+#include <FEXCore/Utils/CompilerDefs.h>
+
 #include <cstdint>
 
 namespace FEXCore::CodeSerialize {
   // If any of the config options mismatch on load then the cache won't be used
   // Any of these will result in codegen changes
-  struct CodeObjectSerializationConfig {
-		// Cookie in the header of the file, isn't part of the config hash
+  struct
+  FEX_PACKED
+  CodeObjectSerializationConfig {
+    // Cookie in the header of the file, isn't part of the config hash
     uint64_t Cookie{};
 
     // Instructions per block configuration
@@ -16,41 +20,45 @@ namespace FEXCore::CodeSerialize {
     unsigned Arch : 4;
 
     // Multiblock enabled
-    bool MultiBlock : 1;
+    unsigned MultiBlock : 1;
+
+    // Hardware TSO enabled
+    unsigned HardwareTSOEnabled : 1;
 
     // TSO enabled
-    bool TSOEnabled : 1;
+    unsigned TSOEnabled : 1;
 
     // ABI local flag unsafe optimization
-    bool ABILocalFlags : 1;
+    unsigned ABILocalFlags : 1;
 
     // ABI no PF unsafe optimization
-    bool ABINoPF : 1;
+    unsigned ABINoPF : 1;
 
     // Static register allocation enabled
-    bool SRA : 1;
+    unsigned SRA : 1;
 
     // Paranoid TSO mode enabled
-    bool ParanoidTSO : 1;
+    unsigned ParanoidTSO : 1;
 
     // Guest code execution mode (We don't support live mode switch)
-    bool Is64BitMode : 1;
+    unsigned Is64BitMode : 1;
 
     // SMC checks style
     unsigned SMCChecks : 2;
 
     // x87 reduced precision
-    bool x87ReducedPrecision : 1;
+    unsigned x87ReducedPrecision : 1;
 
     // Padding to remove uninitialized data warning from asan
     // Shows remaining amount of bits available for config
-    unsigned _Pad : 18;
+    unsigned _Pad : 17;
 
     bool operator==(CodeObjectSerializationConfig const &other) const {
       return Cookie == other.Cookie &&
         MaxInstPerBlock == other.MaxInstPerBlock &&
         Arch == other.Arch &&
         MultiBlock == other.MultiBlock &&
+        HardwareTSOEnabled == other.HardwareTSOEnabled &&
         TSOEnabled == other.TSOEnabled &&
         ABILocalFlags == other.ABILocalFlags &&
         ABINoPF == other.ABINoPF &&
@@ -67,6 +75,7 @@ namespace FEXCore::CodeSerialize {
       Hash <<= 32; Hash |= other.MaxInstPerBlock;
       Hash <<= 1;  Hash |= other.Arch;
       Hash <<= 1;  Hash |= other.MultiBlock;
+      Hash <<= 1;  Hash |= other.HardwareTSOEnabled;
       Hash <<= 1;  Hash |= other.TSOEnabled;
       Hash <<= 1;  Hash |= other.ABILocalFlags;
       Hash <<= 1;  Hash |= other.ABINoPF;
@@ -79,6 +88,6 @@ namespace FEXCore::CodeSerialize {
     }
   };
 
-	static_assert(sizeof(CodeObjectSerializationConfig) == 16, "Size changed");
+  static_assert(sizeof(CodeObjectSerializationConfig) == 16, "Size changed");
   static_assert((sizeof(CodeObjectSerializationConfig) - sizeof(uint64_t)) == 8, "Config size exceeded 64its. Need to change how the hash is generated!");
 }

External/FEXCore/Source/Interface/Core/ObjectCache/JobHandling.cpp

@@ -2,25 +2,24 @@
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
 
 #include <FEXCore/Config/Config.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXHeaderUtils/Filesystem.h>
 
 #include <fcntl.h>
-#include <filesystem>
-#include <memory>
-#include <string>
-#include <sys/uio.h>
-#include <sys/mman.h>
 #include <xxhash.h>
 
 namespace FEXCore::CodeSerialize {
-  void AsyncJobHandler::AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const std::string &filename) {
+  void AsyncJobHandler::AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const fextl::string &filename) {
+#ifndef _WIN32
     // This function adds a named region *JOB* to our named region handler
     // This needs to be as fast as possible to keep out of the way of the JIT
 
-    auto BaseFilename = std::filesystem::path(filename).filename().string();
+    const fextl::string BaseFilename = FHU::Filesystem::GetFilename(filename);
 
     if (!BaseFilename.empty()) {
       // Create a new entry that once set up will be put in to our section object map
-      auto Entry = std::make_unique<CodeRegionEntry>(
+      auto Entry = fextl::make_unique<CodeRegionEntry>(
         Base,
         Size,
         Offset,
@@ -77,12 +76,14 @@ namespace FEXCore::CodeSerialize {
       // Tell the async thread that it has work to do
       CodeObjectCacheService->NotifyWork();
     }
+#endif
   }
 
   void AsyncJobHandler::AsyncRemoveNamedRegionJob(uintptr_t Base, uintptr_t Size) {
+#ifndef _WIN32
     // Removing a named region through the job system
     // We need to find the entry that we are deleting first
-    std::unique_ptr<CodeRegionEntry> EntryPointer;
+    fextl::unique_ptr<CodeRegionEntry> EntryPointer;
     {
       std::unique_lock lk {CodeObjectCacheService->GetEntryMapMutex()};
 
@@ -119,9 +120,10 @@ namespace FEXCore::CodeSerialize {
       // Tell the async thread that it has work to do
       CodeObjectCacheService->NotifyWork();
     }
+#endif
   }
 
-  void AsyncJobHandler::AsyncAddSerializationJob(std::unique_ptr<SerializationJobData> Data) {
+  void AsyncJobHandler::AsyncAddSerializationJob(fextl::unique_ptr<SerializationJobData> Data) {
     // XXX: Actually add serialization job
   }
 }

External/FEXCore/Source/Interface/Core/ObjectCache/NamedRegionObjectHandler.cpp

@@ -1,10 +1,12 @@
 #include "Interface/Context/Context.h"
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
 
-#include <FEXCore/Config/Config.h>
+
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
 
 namespace FEXCore::CodeSerialize {
-  NamedRegionObjectHandler::NamedRegionObjectHandler(FEXCore::Context::Context *ctx) {
+  NamedRegionObjectHandler::NamedRegionObjectHandler(FEXCore::Context::ContextImpl *ctx) {
     DefaultSerializationConfig.Cookie = CODE_COOKIE;
 
     // Initialize the Arch from CPUID
@@ -23,14 +25,14 @@ namespace FEXCore::CodeSerialize {
     DefaultSerializationConfig.x87ReducedPrecision = ctx->Config.x87ReducedPrecision;
   }
 
-  void NamedRegionObjectHandler::AddNamedRegionObject(CodeRegionMapType::iterator Entry, const std::string &base_filename, const std::string &filename, bool Executable) {
+  void NamedRegionObjectHandler::AddNamedRegionObject(CodeRegionMapType::iterator Entry, const fextl::string &base_filename, const fextl::string &filename, bool Executable) {
     // XXX: Add named region objects
 
     // XXX: Until entry loading is complete just claim it is loaded
     Entry->second->NamedJobRefCountMutex.unlock();
   }
 
-  void NamedRegionObjectHandler::RemoveNamedRegionObject(uintptr_t Base, uintptr_t Size, std::unique_ptr<CodeRegionEntry> Entry) {
+  void NamedRegionObjectHandler::RemoveNamedRegionObject(uintptr_t Base, uintptr_t Size, fextl::unique_ptr<CodeRegionEntry> Entry) {
     // XXX: Remove named region objects
 
     // XXX: Until entry loading is complete just claim it is loaded
@@ -40,7 +42,7 @@ namespace FEXCore::CodeSerialize {
   void NamedRegionObjectHandler::HandleNamedRegionObjectJobs() {
     // Walk through all of our jobs sequentially until the work queue is empty
     while (NamedWorkQueueJobs.load()) {
-      std::unique_ptr<AsyncJobHandler::NamedRegionWorkItem> WorkItem;
+      fextl::unique_ptr<AsyncJobHandler::NamedRegionWorkItem> WorkItem;
 
       {
         // Lock the work queue mutex for a short moment and grab an item from the list

External/FEXCore/Source/Interface/Core/ObjectCache/ObjectCacheService.cpp

@@ -1,8 +1,8 @@
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
 
 #include <FEXCore/Config/Config.h>
-
-#include <memory>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/Utils/Threads.h>
 
 namespace {
   static void* ThreadHandler(void *Arg) {
@@ -13,7 +13,7 @@ namespace {
 }
 
 namespace FEXCore::CodeSerialize {
-  CodeObjectSerializeService::CodeObjectSerializeService(FEXCore::Context::Context *ctx)
+  CodeObjectSerializeService::CodeObjectSerializeService(FEXCore::Context::ContextImpl *ctx)
     : CTX {ctx}
     , AsyncHandler { &NamedRegionHandler , this }
     , NamedRegionHandler { ctx } {
@@ -38,13 +38,13 @@ namespace FEXCore::CodeSerialize {
 
   void CodeObjectSerializeService::Initialize() {
     // Add a canary so we don't crash on empty map iterator handling
-    auto it = AddressToEntryMap.insert_or_assign(~0ULL, std::make_unique<CodeRegionEntry>());
-		UnrelocatedAddressToEntryMap.insert_or_assign(~0ULL, it.first->second.get());
+    auto it = AddressToEntryMap.insert_or_assign(~0ULL, fextl::make_unique<CodeRegionEntry>());
+    UnrelocatedAddressToEntryMap.insert_or_assign(~0ULL, it.first->second.get());
 
-		uint64_t OldMask = FEXCore::Threads::SetSignalMask(~0ULL);
-		WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
+    uint64_t OldMask = FEXCore::Threads::SetSignalMask(~0ULL);
+    WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
     FEXCore::Threads::SetSignalMask(OldMask);
-	}
+  }
 
   void CodeObjectSerializeService::DoCodeRegionClosure(uint64_t Base, CodeRegionEntry *it) {
     if (Base == ~0ULL) {
@@ -61,8 +61,7 @@ namespace FEXCore::CodeSerialize {
 
   void CodeObjectSerializeService::ExecutionThread() {
     // Set our thread name so we can see its relation
-    char ThreadName[16] = "ObjectCodeSeri\0";
-    pthread_setname_np(pthread_self(), ThreadName);
+    FEXCore::Threads::SetThreadName("ObjectCodeSeri\0");
     while (WorkerThreadShuttingDown.load() != true) {
       // Wait for work
       WorkAvailable.Wait();
@@ -81,5 +80,5 @@ namespace FEXCore::CodeSerialize {
     // Safely clear our maps now
     AddressToEntryMap.clear();
     UnrelocatedAddressToEntryMap.clear();
-	}
+  }
 }